Servez vous

LIRM M

ON

TP

ELL

IER

Embedded Flash Memories Overviewsand Failures Analysis

Olivier GINEZ - PhD Student

LIRM Montpellier/ ATMEL S.A.S Rousset

MEET – Week 25

Atmel Confidential2

LIRM MO

NT

PE

LLIE

R

• Flash Memories Introduction Technology Architectures Basic Building Blocks

• Flash Failure Mechanisms Hard Defects from Electrical View Hard Defects from Process View Dynamic Faults Resistive Shorts Disturbances and Soft Error

• Thesis Objectives

OUTLINE

Atmel Confidential3

LIRM MO

NT

PE

LLIE

R

• Non Volatile Memories Types:

ROM, EPROM, EEPROM and Flash (Electrically Erasable and Programmable)

• Flash Characteristics:

++ Non Volatile Behaviour (Store Data without Supply)

+ High Density (particularly Flash NAND)+ Low Power Consumption+ Low Cost per Bit (area, process, design)+ Read Access Time- Reliability, Endurance and Retention-- Low Programming Time

Flash Memories:Introduction (1)

Atmel Confidential4

LIRM MO

NT

PE

LLIE

R

• No Standard Different Approaches according to each Company

• Floating Gate Concept Flotox / Etox : Tunnelling through oxide to conducting gate Mnos / Sonos : Trap e- within insulating silicon nitride

• Write / Erase Mechanism Tunnelling Effect: “Fowler-Nordheim” HEI: “Hot Electron Injection”

Flash Memories:Technology (1)

Atmel Confidential5

LIRM MO

NT

PE

LLIE

R

ETOX Cell with FN Tunnelling Program and Erase

|QFG| >> 0|QFG| = 0

VT adjusted by the charge in the floating gateCell can be programmed in an analog way

ITunnel = * E²ox * exp (-/Eox)


Atmel Confidential6

LIRM MO

NT

PE

LLIE

R

BN+

Select Gate (WL)

Control Gate

GND

BLVM 0 V

VMVMVM

0VBL

Control Gate

Select Gate

(WL)

GNDTunnelling Effect

ATMEL Embedded Flash

Core-Cell

MODE Select Gate Control Gate BL

WRITE 1 (erased) VM VM 0

WRITE 0 (written) VM 0 VM

VM : High Voltage to program (~14 to 17V)


Atmel Confidential7

LIRM MO

NT

PE

LLIE

R

BN+

Select Gate (WL)

Control Gate

GND

BLVsense

Vdd1V

BL

Control Gate

Select Gate

(WL)

GND

ATMEL Embedded Flash

Core-Cell

MODE Select Gate Control Gate BL

READ Vdd Vsense 1v

Vsense : Read Voltage 1v

It’s a Current Sensing !!

Vsense

1V

Vdd

Erased : Vthigh +2v => Icell= 0Written : Vtlow -0.6v => Icell 0

Icell


Atmel Confidential8

LIRM MO

NT

PE

LLIE

R

• NOR Architecture : Storage until 256Mbits Random speed up access

• NAND Architecture: Growing faster than NOR memories market Use for mass storage up to 1Gbits

Serial Structure

Parallel StructureBL0 BL1

WL0

WL1

BL0 BL1

WL0

WLn-1

SG0

SG1

nmax => 32

Flash Memories:Architecture (1)

Atmel Confidential9

LIRM MO

NT

PE

LLIE

RFlash Memories:Architecture (2)

NAND NOR (ETOX)

Density 512 Mbits 128 Mbits

Read Access Time 50ns serial

25s random

70ns parallel

25ns burst

Write Delay 200s/512bytes 4.1ms/512bytes

8s/byte

Erase Delay 8ms/64Kbytes 700ms/64Kbytes

Write + Delay 33.6ms/64Kbytes 1.22s/64Kbytes

Random Read Slow

Program Fast

Random Read Fast

Program Slow

Atmel Confidential10

LIRM MO

NT

PE

LLIE

RFlash Memories:Architecture (3)

2T eFLOTOX

(ATMEL)

1T1MJT eMRAM

(SPINTEC)

Technology m 0.13 0.13

Cell size m² 0.27 0.8

Cell size F² 16 47.3

Write Speed 2ms/page <10ns/bit

Read Speed 25ns 25-40ns

Dynamic Power 10- 30mW >100mW

Stand By Current (A) 20-30 <1

FLASH versus MRAM


LIRM MO

NT

PE

LLIE

RFlash Memories:Basic Building Blocks (1)


LIRM MO

NT

PE

LLIE

RFlash Memories:Basic Building Blocks (2)


LIRM MO

NT

PE

LLIE

RFlash Failure Mechanisms:Hard Defects from Electrical View (1)

WLi

WLi+1

Vss

Vss

WLi+2

2

1

3

4

3

1

Example of 2*3 bits Flash Memory Array

Defect Types: Effect:

1- Contact Open(On the Bit Line)

Dual Bit at a logical ‘1’ (Not accessed)

2- Metal 1 Bridge(Between BLi / BLi+1)

Same state on bits of 2 adjacent Bit Lines

3- Contact Source Open Not able to read some cell’sstate (Read as stuck at 1’)

4- Poly1 Short Dual or Multiple Bit

BLj BLj+1


LIRM MO

NT

PE

LLIE

RFlash Failure Mechanisms:Hard Defects from Process View (1)

BN+

Select Gate (WL)

Control Gate

N+N+ 3 3

2

1

Cross Section of FLOTOX Core-Cell

Defect Type: Effect:

1- Tunnel Window Too thick – No Program EffectToo thin – No Retention≈ +Δtox (Å) - Bad Margin

≈ - Δtox (Å) - Bad Retention

2- ONO Short(Interpoly Oxide)

No Charges RetentionSingle bit Failed

3- Junction Leakage N+ => Drop of HV

BN+ => Drop of HV


LIRM MO

NT

PE

LLIE

RFlash Failure Mechanisms:Dynamic Faults (1)

WL0

BL0 BL2 BL3BL1

VrefPoly2

Via on Strap Word Lines Opened :Access Time IncreasingRead Delay Fault (RDFs)

Straps to reduce resistive

effects


LIRM MO

NT

PE

LLIE

RFlash Failure Mechanisms:Resistive Shorts (1)

• Poly2 (Word Line) -> Metal1 (Bit Line)

WLi

WLi+1

Vss

Vrefi

Vrefi+1

BLjBLj+1

(i,j)

(i+1,j)

(i,j+1)

(i+1,j+1)

Targeted cells

Defect 1 during Erasing WLi Drop of HV and Bad Vt value on (i;j)

21

43

Defect 2 during Writing cell(i,;j) VBLj+1 switch from HZ to HV (+14v)

Same Analysis for Poly2 (Word Line) / Poly2 (Sense gate) !


LIRM MO

NT

PE

LLIE

RFlash Failure Mechanisms:Disturb and Soft Error (1)

* Programming Disturb

BLj (HZ) BLj+1

Not selected cellTarget Cell

WLi ≈ 14v

0v

C1

C2

12volts

Capacitive Coupling BLj / BLj+1

VBLj = 12v * [C1 / (C1 + C2)] Some measures have shown VBLj= 4v

• Soft Programming of cell(i;j) !!! (remember ITunnel equation)• Cell(i;j) logical state switching from ‘0’ to ‘1’ My Functional Model is ‘BCPD’ (Bit Line Coupling Programming Disturb)


LIRM MO

NT

PE

LLIE

RFlash Failure Mechanisms:Disturb and Soft Error (2)

* Reading Disturb

0v

BLj

Vss

1.8v

Vbl ≈ 1v

Target Cell (a,j)

0v

0.7v

Ileak

HZ +Vin

Gnd

1

3 4

2

0

1

Ileakage 0

I=0

To Sense

Crosstalk Perturbation between 2 WL

Subthreshold leakage

Vgs = 0.1v Ids1 = 10*Ids0

Important ILeakage on the unselected cells with Vtlow

Mask of Data to Read

NPSF (Neighborhood Pattern Sensitive Fault)


LIRM MO

NT

PE

LLIE

R

RAM Functional Faults:

- Cells Stuck - RD/WR line Stuck- CE line Stuck - Data Line Stuck or Open- Pattern Sensitive - Wrong or Multiple Access- Crosstalk on Data lines - Address Line Stuck or Open

Simple Faults Models:

AFs / TFs / SAFs / SOFs / DRFs / BFs

Coupling Faults Models:

CFin / CFid / CFst / CFdst / NPSFs

March Test Strategy

Thesis Objectives:Flash versus RAM Testing (1)


LIRM MO

NT

PE

LLIE

R

Flash Failure Mechanisms Erase Mode by Sector Programming Time is Longer March Strategy not suitable

RAM Testing not Directly Applicable !!



LIRM MO

NT

PE

LLIE

R

• Most of March are for Bit Oriented Memories: Nowadays not suitable !

Industrial Realities:

Memories are Word Oriented (16/32/64…)

• March Tests for Word Oriented Memories

Modify Bit Oriented March Algorithms:• w0 becomes wDand w1 becomes w/D

• r0 becomes rDand r1 becomes r/D

(with d = data background to apply on B bits Words)

« March tests for word-oriented memories »

A.J. van de Goor – Delft University of Technology / Netherlands



LIRM MO

NT

PE

LLIE

R

• Inter-word faults Hard fixed data background :

01010101 / 10101010

• Intra-word faults Testing between cells in the same word

Example for CF disturb : NbD = 3 + 3*log2 B with NbD the number of different data backgrounds

and B the number of bits contained in 1 word


A.J. van de Goor – Delft University of Technology / Netherlands



LIRM MO

NT

PE

LLIE

R

Application to a Flash 64K * 32bits

– To optimize testing time we consider:

1 page = 1 word 64*32 = 2048bits

– D = 3 + 3*11 = 36 ( data backgrounds for the CFdst )

– Flash writing:1.Load

2.Auto-Erase

3.Functional Write-Word

Testing time = 1024*36*4ms = 147.5 sec just for the CF dst intra-word testing !

(1st order, Reading time is neglected )

4 ms/page



LIRM MO

NT

PE

LLIE

R

Memory Architecture

Possible and Realistic Fault List

Constraint linked to the Memory

New Methodologies for Flash Testing

• NAND or NOR

• E2PROM or FLASH

• NB Cells/Sector

• Collect All Possible Faults

• Fault Occurrence Probability

• RAM like

• Disturb Faults

• Write per Page

• Read per Word

• Programming Time

• Optimized Algorithms

• BIST and BISD

Exhaustive Fault Analysis

Thesis Objectives


LIRM MO

NT

PE

LLIE

R


A.J. van de Goor – Delft University of Technology - Netherlands

«Crosstalk in Deep Submicron DRAMs »

Z. Yang, S. Mourad / Santa Clara University - USA / IEEE MTDT00 San Jose - USA

« Flash Memory: Technology-Driven Test »

J. Pineda de Gyvez, R. Beurze / Philips Eindhoven - Netherlands / ETW02 Corfu - Greece

« Diagonal Test and Diagnostic Schemes for Flash Memories »

S-K Chiu, J-C Yeh, C-T Huang, C-W Wu / LARC / NTHU - Taiwan

« RAMSES-FT: A fault simulator for Flash Memory Testing and Diagnostics »

S-K Chiu, J-C Yeh, C-T Huang, C-W Wu / LARC / NTHU - Taiwan

« Nonvolatile memory disturbs due to gate & junction leakage currents »

J.E. Park12, J. Shields3, D.K. Schroder2 / Solid-State Electronics 2002

1IBM - USA / 2Arizona State University - USA / 3Microchip Technology - USA

« EEPROM Memory: Threshold Voltage Built In Self Diagnosis »

H. Aziza12, J.M Portal1, D. Née2 / IEEE ITC 2003

1L2MP Polytech’Marseille - France / 2ST-Microelectronics Rousset - France

Literature


LIRM MO

NT

PE

LLIE

R

« Semiconductor Memories: Technology, Testing and Reliability »

A-K.Sharma / IEEE Press, Piscataway, 1997

« RAMSES-FT: A fault simulator for Flash Memory Testing and Diagnostics »

S-K Chiu, J-C Yeh, C-T Huang, C-W Wu / LARC / National Tsing Hua University

« Embedded EEPROM memories performance optimization »

C. Papaix / ATMEL Rousset, France / LIRMM Montpellier / PhD Thesis 2002

Literature

Servez vous

Documents

Transcript of Servez vous