SERppt

6
Trends in the ASIC Marketplace  A Third Party View of Soft Errors Source: Semico Research “Gate Arrays Wane While Standard Cells Soar: ASIC Market Evolution Continues” Report: SC103-02 June 2002

Transcript of SERppt

8/8/2019 SERppt

http://slidepdf.com/reader/full/serppt 1/6

8/8/2019 SERppt

http://slidepdf.com/reader/full/serppt 2/6

 © 2002 Actel Confidential and Proprietary 2October 2002Soft Errors

Trends in t he ASIC Mark et p lac e

In a recent study, Semico Research identified 8key trends in the ASIC Marketplace:

! Trend # 1: Product Life Cycles Shrinking, Increasing Design Times

! Trend # 2: The Quality of IP is Improving

! Trend # 3: Complex Analog / Mixed Signal IP Becoming Available

! Trend # 4: Rapid Growth of Non-Recurring Engineering Charges

! Trend # 5: Increased Co-Dependency of Design Efforts

! Trend # 6: Silicon Foundries Implement SoC Initiatives

! Trend # 7: The SoC Market is Growing

! Trend # 8: Soft Error Rates A Growing Concern

8/8/2019 SERppt

http://slidepdf.com/reader/full/serppt 3/6

 © 2002 Actel Confidential and Proprietary 3October 2002Soft Errors

Trend #8 Sof t Error Rat es*

" “As the feature size of semiconductors continues to decrease

...they become more susceptible to hits from Alpha particles and

thus experience increased soft error rates”

" “This trend has not been that noticeable until the industry

reached the 0.13µm process node”

" “As speed increases and silicon area and voltage decrease the

performance continues to increase. Unfortunately, the System

SER is increasing right along with global performance”

" “Several companies such as IBM, MoSys and iRoC

Technologies are bringing the issue to the attention of

designers” * Source: Semico Research 6/02

8/8/2019 SERppt

http://slidepdf.com/reader/full/serppt 4/6 © 2002 Actel Confidential and Proprietary 4October 2002Soft Errors

Syst em Sof t Error Rat e Trends

Soft Error Rate Trends inVery Dense & Ultra DenseSemiconductor Memory

1

10

100

1000

10000

0.25 um 0.18 um 0.13 um 0.09 um 0.05 um

System SER

Source: Semico Research 6/02

Very Dense < 0.18µm

Ultra Dense < 0.09µm

   S  y  s   t  e  m

    F   I   T   S

   (   N  o  n   L   i  n  e  a  r   S  c  a   l  e   )

8/8/2019 SERppt

http://slidepdf.com/reader/full/serppt 5/6 © 2002 Actel Confidential and Proprietary 5October 2002Soft Errors

SER Im pac t by Mark et Segm ent

0 .1

1 .0

10

100

1000

10000

Networking

Comput ing

Telecom

W ireless

PC Peripherals

P C

Critical Applications

(Space, Autom otive,

Sm art Card)

0 .35u m 0.25 um 0.20 u m 0.15um 0 .10u m 0.05 um0.30um

1997

1999

2001

2003

2005

2008

2012

Soft Error Rate Forecast

Soft Error R ate Extracted from

AM D, Inte l, CompaqSource:iRoCTechnologies

Semico ResearchCorp June 2002

   N  o  r  m  a   l   i  z

  e   d   F   I   T   R  a   t  e

8/8/2019 SERppt

http://slidepdf.com/reader/full/serppt 6/6 © 2002 Actel Confidential and Proprietary 6October 2002Soft Errors

Soft Error Rat e Sum m ary

" Soft errors are a real problem today!

" SER problem getting worse with shrinks in geometry

" There is a growing awareness of this issue in themainstream commercial marketplace – this is not just a

“space market problem”

" The need to mitigate SER will affect designers invirtually every market segment

" Actel products offer immunity to Configuration softerrors because an SRAM element is not used toprogram the device configuration