Sense Amplifier for SRAM

SoC Lab

Sense Amplifier for SRAM

Professor : Der-Chen Huang

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Outline

• SRAM Structure• Sense Amplifier Introduction

– Voltage-mode– Current-mode

• Traditional Voltage-Mode Sense Amplifier• Current-Mode Sense Amplifier

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Elementary SRAM Structure

Memory Cell Array

Pre-charge Circuit

Select Circuit

Sense Amplifier

Write Circuit

Output B

uffer

Row

Decoder

Colum

nD

ecoder

Address R

egister

Address

Data_Out

Input Register

Data_In

OE

R/W

Ysel

SAen

IEWL

ReadWrite

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SRAM 6T Cell

• SRAM 6T Cell structure

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SRAM 6T Cell

• Read operation– 1st step

• BL & BL = 1• Word line = 1

– 2nd step• BL = 0

X=0 Y=1

=1=1

=1

=0

___

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SRAM 6T Cell

• Write operation

(a) Before write

X=0 Y=1

(b) After write

=0=1

=1

=0=1

X=1 Y=0

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Sensing Amplifier Design Objective and Classification

• Design Objective[3]– Minimum sense delay– Required amplification– Minimum power consumption– Restricted layout area– High reliability and tolerance

• Classification[1][3]

Circuit Types Operation Mode

Differential Voltage-mode

Nondifferential Current-mode

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Bit-line Model[1]

MemoryCell

Bit-lineload

Bit-line

RC-line

Vdd

To Sense Amplifier

RB

R R R R

C C C C RL io

Vo

Ii

Memory Cell Model

Bit-line RC Model Sense Amplifier Model

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Bit-line Model

• Ii is the output current of the driving source, i.e. memory cell.• RB is the output resistance of the bit-line load in parallel with the drain

resistance of the access transistor, which is the output device of the memory cell.

• The infinite RC ladder structure represents the interconnect line. The total resistance and capacitance of the line is given by RT and CT .

• The output of the line is terminated by resistor RL .

RB

R R R R

C C C C RL io

Vo

Ii

Memory Cell Model


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Bit-line Model

• RC delay

RB

R R R R

C C C C RL io

Vo

Ii

Memory Cell Model


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TB L

T T LB T

B T L B T L

RR RR C Rt R CR R R R R R

δ •

⎛ ⎞+ +⎜ ⎟ ⎛ ⎞= • +⎜ ⎟ ⎜ ⎟+ + + +⎝ ⎠⎜ ⎟⎝ ⎠

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Delay for Voltage-Mode

• For voltage-mode signals, RL is infinite and the output signal is the open-circuit voltage Vo .

• RC delay

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TB L

T T LB T

B T L B T L


δ •

⎛ ⎞+ +⎜ ⎟ ⎛ ⎞= • +⎜ ⎟ ⎜ ⎟+ + + +⎝ ⎠⎜ ⎟⎝ ⎠

∞

∞

∞

∞

212T T B

vT

R C RtR

δ ⎛ ⎞= • +⎜ ⎟⎝ ⎠

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Delay for Current-Mode

• For current-mode signals, RL is ideally zero and the output signal is the short-circuit current io .

• RC delay

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TB L

T T LB T

B T L B T L


δ •

⎛ ⎞+ +⎜ ⎟ ⎛ ⎞= • +⎜ ⎟ ⎜ ⎟+ + + +⎝ ⎠⎜ ⎟⎝ ⎠

0

0

0

0

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TB

T Ti

B T

RRR CtR R

δ

⎛ ⎞+⎜ ⎟= •⎜ ⎟+⎜ ⎟

⎝ ⎠

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Example

• Eample from [1], when– RB = 2500Ω– RT=250Ω– CT=2pf。

• Voltage-mode– δtv = 5.25ns

• Current-mode– δti = 0.235ns

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Traditional Voltage-mode Sense Amplifier

• Traditional Difference Amplifier[3]

• Full Complementary Positive-Feedback Sense Amplifier[2][3]

• Enhanced Positive Feedback Sense Amplifier [4]

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Traditional Difference Amplifier

1==0

1=

SE = 1 , Sense mode

SE = 0 , Standby mode

Current mirrorMP1 & MP2 have

the same Vgs

0

IMP1 IMP2' 2

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1 ( )2

gs tMP nMP

WI k V VL

⎛ ⎞= −⎜ ⎟⎝ ⎠

' 22

2

1 ( )2

gs tMP nMP

WI k V VL

⎛ ⎞= −⎜ ⎟⎝ ⎠

2 2

1

1

MP MP

MP

MP

WI L

WIL

⎛ ⎞⎜ ⎟⎝ ⎠=⎛ ⎞⎜ ⎟⎝ ⎠

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Full Complementary Positive Feedback Sense Amplifier

SE = 1 , Sense mode


1= =0

SE = 1 , Sense mode


BL BL__

( 1)

( ) (0)

gmR tRCto oV V e−

= i

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Enhanced Positive Feedback Sense Amplifier

SE = 1 , Sense mode


1 0

Decouple device: avoid the effect of the bit-line

capacitance

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Current-mode Sense Amplifier

• Clamped Bit-Line Sense Amplifier[5][6]

• Simple Four Transistor Sense Amplifier[1]• Hybrid Current Sense Amplifier[8][9]• New Hybrid Current Sense Amplifier[10]• Modified CSA[11]

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Current-mode Sense AmplifierClamped Bit-Line Sense Amplifier

Φ PRE = 1 , Pre-charge

Φ SA = 1 , Sense

The” ΦPRE” signal drives high to turn on M7 & M8, which works to

equalize the output node to the same voltage level.

I1↓I2↑

M5 & M6 are biased in the linear region and provide a low-impedance clamp between the bit line and the ground.

Vgs1↑ Vgs2↓

0 1

Positive Feedback Circuit

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• Advantages– The input nodes of the sense amplifier are low-impedance current

sensitive nodes, the voltage swing of the highly capacitance bit lines change small.

– The output nodes of the sense amplifier are no longer loaded with the bit-line capacitance and the sense amplifier is able to respond very rapidly.

– M1 ~ M4 works as a cross-coupled latch, its positive feedback effect can improve the driving ability of output nodes. Even the small input difference can be detected and the output can drive to full supply swing.

Clamped Bit-Line Sense Amplifier

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I+i I+i

I Oi I+i

ic icV1

V1+

+ +

+-

-

-

-

i+ic I+i+ic

V2

V2

V1 +V2V1 +V2

Simple Four Transistor Sense Amplifier

The gate-source voltage of T1 will be equal to that of T3 , since their currents are equal, their size are equal, and both transistors are in

saturation.

The gate-source voltage of T2 will be equal to that of T4 , since their currents are equal, their size are equal, and both transistors are in

saturation.

At the begin, Ysel arepulled down to gnd.

Because DL near to ground level, T1~T4 will work in saturation region.

△I

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• Advantages– In many cases it can fit in the column pitch, avoiding the need for

column-select devices, thus again reducing propagation delay.

– There exists a virtual short circuit across the bit lines, therefore the potential of the bit lines will be equal independent of the current distribution.

– The sensing delay is unaffected by the bit-line capacitance since no differential capacitor discharging is required to sense the cell data.

– Discharge current ic from the bit-line capacitors, effectively pre-charging the sense amplifier.

Simple Four Transistor Sense Amplifier

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Current-mode Sense AmplifierSimple Four Transistor Sense Amplifier

0 1

I1↑

I2↓

Current mirrorI3

I4

Because I1 > I2 , so I3 > I4

Ysel = 0 , Sense mode

Ysel = 1 , Standby mode

Current Conveyor

I5

I6

I5 = I4 + I6Because

current mirror effect, I3 > I4 ,

so I5 > I4 .

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Current-mode Sense AmplifierHybrid Current Sense Amplifier

Current Conveyor

Biased in the linear region and provide a low-impedanc.

Positive Feedback Circuit0 1

I1↑

I2↓

Vgs3↓ Vgs4↑

01

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Current-mode Sense AmplifierNew Hybrid Current Sense Amplifier

Current Conveyor

CBLSA

Overcome the pattern-dependent problem of the conventional current conveyor.In conventional current conveyor, after each read operation, the nodes RXP and RXN get floated and there will exist a residual differential voltage between them. The pattern-dependent problem occurs when the same logic value is sequentially read out several times from the same column.

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Current-mode Sense AmplifierS.M. Wang’s Sense Amplifier

Biased in the linear region and provide a low-impedance.

In standby state, pull the bit- lines close to the ground level

Standby stateSEN = 0SENB = 1

N7 & N8 are turned off to avoid DC current flows in the sense amplifier.N3 & N4 are turned on to pull down the drains of the N5 & N6 to low-level.

Sensing stateSEN = 1SENB = 0

Positive Feedback Circuit

0 1

I1↑

I2↓

Vgs5↓ Vgs6↑

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Reference[1] E. Sccvinck, P. J. van Beers, and H. Ontrop, “Current-Mode Techniques for High-

Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAMs,” IEEE Journal of Solid-State Circuits Vol.26 No.4 pp.525-536 April 1991.

[2] T. P. Haraszti, “High Performance CMOS Sense Amplifiers,” United States Patent No. 4,169,233, Sep. 1979.

[3] Tegze P. Haraszti, “CMOS Memory Circuits”, Kluwer Academic Publishers, 2000.[4] V.Kristovski and Y. L. Pogrbeny, “New Sense Amplifier for Small-Swing CMOS

Logic Circuit,” IEEE Trans, On Circuit and Systems, vol. 47, p.p. 573~576, June 2000.

[5] Blalock, T.N. and Jaeger, R.C.,”A High-speed Clamped Bit-line Current-mode Sense Amplifier”, IEEE J. Solid-State Circuits, vol. 26, no. 4, pp542-548, April 1991.

[6] Blalock, T.N. and Jaeger, R.C., “A subnanosecond clamped-bit-line sense amplifier for 1T dynamic RAMs”, Proceedings of VLSI Technology, Systems, and Applications, pp82-86, May 1991.

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Reference (cont.)

[7] Chrisanthopoulos, A., Moisiadis, Y., Tsiatouhas, Y. and Arapoyanni, A., “Comparative study of different current mode sense amplifiers in submicron CMOS technology”, IEE Pro. Circuits, Devices and Systems, vol. 149, no. 3, pp154-158, June 2002.

[8] P.Y. Chee, P.C. Liu, L. Siek, “A high-speed current-mode sense-amplifier for CMOS SRAM's“, Proceedings of 35th Midwest Symposium on Circuit and System, vol. 1, pp620-622, Aug. 1992.

[9] P.Y. Chee, P.C. Liu, L. Siek, “High-speed hybrid current-mode sense amplifier for CMOS SRAMs”, ELECTRONICS LETTERS, vol. 28, no. 9, April 1992.

[10] Jinn-Shyan Wang, Hong-Yu Lee, “A new current-mode sense amplifier for low- voltage low-power SRAM design”, Eleventh Annual IEEE International Proceeding of ASIC, pp.163-167, Sep. 1998.

[11] S.M. Wang and C. Y. Wu, “Full current-mode techniques for high-speed CMOS SRAMs”, IEEE International Symposium on Circuit and Systems, vol. 4, pp.IV580- IV582, May 2002.

Sense Amplifier for SRAM

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