Semiconductor Process Reliability...Semiconductor processing always yield a distribution of...

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Semiconductor Process Reliability

SVTW 2012Esko Mikkola, Ph.D. & Andrew Levy


IC Failure Modes Affecting Reliability

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Via/metallization failure mechanismsElectro migrationStress migration

Transistor failure mechanismsTime-dependent dielectric breakdown (TDDB)Hot carrier degradationNBTI and PBTI


IC Failure Modes Affecting Reliability

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Failure Mode Physics System Effect

NBTI (PMOS) / PBTI (NMOS)

• Negative Vt shift• Slower speed

• Timing Faults in Processors• Resettable – but increasing severity over time

TDDB

Soft Breakdown:• Slower speed• Weakened gate oxide• Increased leakage current

• Increased ESD Vulnerability• Non‐resettable timing faults

Hard Breakdown/Punch‐through • Catastrophic Short

Hot Carrier (NMOS)

• Positive Vt shift• Change in sub‐threshold swing

• Increased Off‐state power• Increased current draw• Decreased data retention time in DRAM

Metal Migration(Stress migration, electromigration)

• Higher resistance in Via connections

• Open circuits

• Catastrophic Open

Presenter

Presentation Notes

NBTI in PMOS shown to be a problem for .25u. NMOS PBTI problem in newest CMOS processes, with HiK metal gate. 45nm & down. Cause time delays in digital circuits, offsets in analog circuits. Both anneal fast if temperature and bias removed. TDDB: modern processes – 3 problems – SILC (stress induced leakage current), soft breakdown (partial oxide breakdown, often anneals partially), hard breakdown – causes short through oxide. Could have several (different) soft breakdowns. Soft breakdown may not precede hard breakdown. Hot carrier – long been a problem – since 60s. Problems with slow switching digital, analog with DC bias. Similar to NBTI, but doesn’t anneal as fast as NBTI. Worse problem at low temps. Accelerated carriers – drain to source. SM / EM: AKA stress-induced voiding. High temp makes it worse. High current density too. Al -> Cu because of EM. But now reaching limit of Cu.


Electromigration – Stress Migration

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ElectromigrationTransport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms. Known for more than 100 years, but became of practical interest with the advent of Semiconductor technologiesEffects are occurring primarily at the boundaries and material interfacesCu is intrinsically less sensitive to EM than Al but scaling and increasing current densities are pushing the limits

Stress MigrationResults from tensile stress due TCE mismatch of materialsStress relaxation over time through diffusion of vacancies leads to the formation of voids

Presenter

Presentation Notes

The higher the temperature, the worse it is. Stress migration: TCE mismatch & also from stress from CMP.


Via/Metallization Failure Mechanisms

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Presenter

Presentation Notes

65nm process. Different metal options. Many places where via problem can arise. Hard to make test structure to catch all the sensitivities. Via structures can be quite complex - intermetal oxides. Low-K is quite sensitive to breakdown.


Electromigration (physical mechanism)

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Electromigration (temperature dependency)

Reported data from fast Wafer Level Reliability (fWLR) tests shows that every 50 °C increase in the stress temperature will reduce the electromigration testing time by one order of magnitude.

Ki‐Don Lee, et al., “VIA PROCESSING EFFECTS ON ELECTROMIGRATION IN 65 NM TECHNOLOGY”, 44th Annual International Reliability Physics Symposium, San Jose, 2006.

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Presenter

Presentation Notes

Accelerated stress testing with temperature.


Transistor Failure Mechanisms

MOS transistor

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Presenter

Presentation Notes

Most degradation effects are due to trapped charge close to the Si substrate / gate dielectric interface.


Transistor Failure Mechanisms

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Presenter

Presentation Notes

Scaling. 9nm MOSFET (in 10 years)– a few atoms. 32nm single trap can cause a big VT shift. Channel length modulation – short channel effect. Channel pinches off near drain. Strong vertical electrical field. DIBL – drain induced barrier lowering. Velocity saturation – Saturation current – not as high as calculated by basic CMOS equations. Mobility degradation – caused by stresses. Newest processes need more advanced models. Small transistors – no more 90 degree angles.


Time Dependent Dielectric Breakdown

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Failure mechanism in MOSFETs, when the gate oxide breaks down as a result of long-time application of relatively low electric field (as opposite to immediate breakdown, which is caused by strong electric field). The breakdown is caused by formation of a conducting path through the gate oxide to substrate due to electron tunnelling current, when MOSFETs are operated close to or beyond their specified operating voltages.


Time‐Dependent Dielectric Breakdown (TDDB)

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TDDB influenced by:Smaller GeometryMore TunnelingThinner Oxides (Tox)Substrate Injection (NMOS)

Effects: Increased NoiseIncreased PowerSwitching characteristicsEventual wear-out and failure

Presenter

Presentation Notes

Leakage causes increase in power SILC – first thing that happens – stress-induced leakage current – increases noise & power


TDDB (types of breakdown)

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TDDB (types of breakdown)

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Presenter

Presentation Notes

Different kinds of behavior Bottom left – SILC first, then soft breakdowns, eventually hard breakdowns. Upper right - #5 – no hard breakdown. #3 directly to hard breakdown. Upper left – Fowler-Nordheim tunneling. Soft breakdowns may or may not anneal.


TDDB (DC stress vs. AC stress)

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Presenter

Presentation Notes

DC stress – SILC before hard BD. AC stress – directly to hard BD. Could be process dependent. (Old graphics – but problems persist / recur cyclically. Make some things better, other things get worse.)


Hot Carrier Injection (HCI) Degradation

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A phenomenon in which an electron or a hole gains sufficient kinetic energy to overcome a potential barrier necessary to break an interface state.

To become “hot” and enter the conduction band of SiO2, an electron must gain a kinetic energy of 3.3 eV. For holes, the valence band offset in this case dictates they must have a kinetic energy of 4.6 eV. The term "hot electron" comes from the effective temperature term used when modelling carrier density and does not refer to the actual temperature of anything. High temperatures caused by the effect are unrelated to the phrase "hot electron effect".

Carrier is injected from channel into gate dielectricEffects include heating of the device and increased leakage current

Heating is caused by hot electrons giving off their excess energy as phonons.

Presenter

Presentation Notes

Carrier accelerated in the electric field = source to drain, heat other particles, collisions, carriers trapped in oxide. Increased substrate current – good indicating of carrier injection. Lattice vibrations at higher temperatures – probability of getting to high energy (source to drain) is lowered. Thus problem is worse at lower temperatures.


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Hot Carrier Degradation

Presenter

Presentation Notes

Graphical representation of slide #15



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Presenter

Presentation Notes

On-current degradation, vt shift, sub-threshold swing degradation – all caused by hot carrier. Nit – positive charge at interface Not – positive charge at bulk


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Presenter

Presentation Notes

HCI degradation effect on individual circuit parameters. Transconductance (gm) is worst case.



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Presenter

Presentation Notes

HCI @ TSMC 65nm: transistors wear out at .2 years if dc bias, > 10 years at ac bias.


NBTI and PBTI

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Negative bias temperature instability (NBTI) is a key reliability issue in MOSFETs. Of immediate concern for pMOS→ operate almost always with negative gate-to-source voltage

The very same mechanism affects also nMOS when biased in the accumulation regime (PBTI)

NBTI manifests as An increase in threshold voltageA decrease in drain current and transconductanceThe degradation has logarithmic dependence on time

Two kinds of trap contribute to NBTI:Interface traps→ cannot be recovered over a reasonable time of operation - permanent traps→ similar to the ones resulting from HCI→ In case of NBTI, the electric field breaks Si-H bonds located at the SiO2 interface. H is

released and migrates in the substrate. The remaining dangling bond Si- (Pb center) contribute to the threshold voltage degradation.

Pre-existing traps located in the bulk of the dielectric (and supposedly nitrogen related), are filled with holes coming from the PMOS channel. Those traps can be emptied when the stress voltage is removed. This Vth degradation can be recovered over time. (Annealing effect)


NBTI and PBTI

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NBTI and PBTI (SiO2 gate)

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Presenter

Presentation Notes

NBTI is much worse for PMOS than PBTI for NMOS. Hi-K though NBTI & PBTI are probably close to each other.


NBTI and PBTI (high‐k gate)

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NBTI and PBTI (SiO2 vs. high‐k)

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Presenter

Presentation Notes

Difference between hi-k and conventional MOS transistors. NBTI: seem to have problems in both cases. PBTI: only hi-k transistors seem to have problems.


NBTI and PBTI (relaxation)

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Presenter

Presentation Notes

Need to sense degradation quite quickly. Annealing begins right away. Yellow curve shows 1s measurement, slower than 30us curve.


NBTI and PBTI (relaxation)

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Presenter

Presentation Notes

PBTI relaxes but not that much.


NBTI and PBTI (DC vs. AC stress)

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Presenter

Presentation Notes

Difference for different duty cycles Delta threshold voltage much higher when stressed for longer. Stress in linear region. Even 99% (on right) is different than 100% high.


Mitigation: Process Data

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Semiconductor processing always yield a distribution of parameter values

Minimum geometries have larger fluctuations

Smaller feature size & lower voltages increase the impact of variation of transistor properties on chip performance and yield

Foundry-supplied Process Design Kit (PDK) may not give sufficiently accurate data for critical design parameters

Presenter

Presentation Notes

(Would like to have distribution of process degradation on this slide but we don’t have it…)


Mitigation: Addressing Nanoscale Reliability Issues

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Use Additional Design MarginIncreased power consumptionImpacts overall circuit performance

Collect Accurate Process informationLifetime Reliability Monitoring

Real-time operating embedded sensorsActual State of Health for critical pathsEarly warning of impending failure


ProChek™

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Semiconductor

Reliability

Characterization

System


Characteristics of ProChek

• Targets bulk CMOS, SOI, SiGe reliability concerns•NBTI / PBTI, TDDB, HC, EM, SM

• Test Coupon•As little as 1 * 1mm chip area•MPW for lower cost•32 – 1024 devices can be tested in parallel for maximum throughput•On‐chip per transistor heaters to 325 °C, greatly reducing test time•Synthesizable (except for on‐chip heaters) to speed deployment

• Bench‐top Tester•Fully programmable test conditions cover DC and AC stress cases•Portable and compact•ATE not needed

• Host Controller•Easy‐to‐use software GUI•Rich suite of built‐in reliability test templates•Data processing capabilities

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Sentinel Silicon™

Die‐Level

Prognostic

Solutions and

Applications


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Calibrated Prognostic Distance

Stress/Accelerate:

T1 = 99% failure in canary

T2 = 1% failure in host

Prognostic Distance = T2 – T1


Questions?

Ridgetop Group Inc.

Andrew LevyDirector, Semiconductor & Precision

Instruments [email protected] x115 (office)503-320-5466 (mobile)

3580 West Ina RoadTucson, AZ 85741

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Esko Mikkola, Ph.D.Senior Principal [email protected] x141 (office)

mailto:[email protected]

mailto:[email protected]

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