Semiconductor Memories 2

CHAPTER 1

INTRODUCTION TO ADVANCEDSEMICONDUCTOR MEMORIES

1.1. SEMICONDUCTOR MEMORIES OVERVIEW

The goal of Advanced Semiconductor Memories is to complement the materialalready covered in Semiconductor Memories. The earlier book covered the fol-lowing topics: random access memory technologies (SRAMs and DRAMs) andtheir application to specific architectures; nonvolatile technologies such as theread-only memories (ROMs), programmable read-only memories (PROMs),and erasable PROMs in both ultraviolet erasable (UVPROM) and electricallyerasable (EEPROM) versions; memory fault modeling and testing; memorydesign for testability and fault tolerance; semiconductor memory reliability;semiconductor memories radiation effects; advanced memory technologies; andhigh-density memory packaging technologies [1]. This section provides ageneral overview of the semiconductor memories topics that are covered inSemiconductor Memories.

In the last three decades of semiconductor memories’ phenomenal growth,the DRAMs have been the largest volume volatile memory produced for useas main computer memories because of their high density and low cost per bitadvantage. SRAM densities have generally lagged a generation behind theDRAM. However, the SRAMs offer low-power consumption and high-per-formance features, which makes them practical alternatives to the DRAMs.Nowadays, a vast majority of SRAMs are being fabricated in the NMOS andCMOS technologies (and a combination of two technologies, also referred toas the mixed-MOS) for commodity SRAMs.

1

Figure 1.1 Semiconductor memory market as a percentage of the total IC market [2].

In 1995, semiconductor memories accounted for 42%of the total IC market,but following 1995’s strong growth, memory prices collapsed for the next threeyears. In 1998, memory devices represented only 21% of the total IC market.During the 1990s, semiconductor memory sales averaged approximately 30%of total IC sales. It is forecasted that the memory portion of total IC sales willgradually increase through year 2005. Figure 1.1 shows the semiconductormemory market as a percentage of the total IC market [2].

In high-density and high-speed applications, various combinations of bipo-lar and MOS technologies are being used. In addition to MOS and bipolarmemories, referred to as the ‘‘bulk silicon’’ technologies, silicon-on-insulator(SOI) isolation technologies have been developed for improved radiationhardness.

SRAM density and performance are usually enhanced by scaling down thedevice geometries. Advanced SRAM designs and architectures for 4 to 16-Mbchips with submicron feature sizes have been developed and currently availableas commodity chips. Application-specific memory designs include first-in-first-out (FIFO) buffer memory, in which the data are transferred in and outserially. The dual-port RAMs allow two independent devices to have simulta-neous read and write access to the same memory. The content addressablememories (CAMs) are designed and used both as the embedded modules on

2 INTRODUCTION TO ADVANCED SEMICONDUCTOR MEMORIES

larger VLSI chips, and as stand-alone memory for specific system applications.A major improvement in DRAM evolution has been the switch from

three-transistor (3T) designs to one-transistor (1T) cell design, enabling pro-duction of 4- to 16-Mb density chips that use advanced 3-D trench capacitorand stacked capacitor cell structure. Currently, 64-Mb to 1-Gb DRAM chipsare in production, and multigigabit density chips are being developed. Thetechnical advances in multimegabit DRAMs have resulted in greater demandfor application-specific products such as the pseudostatic DRAM (PSRAM),which uses dynamic storage cells but contains all refresh logic on-chip thatenables it to function similarly to an SRAM. Video DRAMs (VDRAMs) havebeen produced for use as the multiport graphic buffers. Some other examplesof high-speed DRAM innovative architectures are synchronous DRAMs(SDRAMs), cache DRAMs (CDRAMs), and Rambus�� DRAMs (RDRAMs).

Nonvolatile memories (NVMs) have also experienced tremendous growthsince the introduction in 1970 of a floating polysilicon gate-based erasableprogram read-only memory (EPROM), in which hot electrons are injected intothe floating gate and removed either by ultraviolet internal photoemissionor by Fowler—Nordheim tunneling. The EPROMs (also referred to as theUVEPROMs) are erased by removing them from the target system andexposing them to ultraviolet light. An alternative to EPROM (or UVEPROM)has been the development of electrically erasable PROMs (EEPROMs), whichoffer in-circuit programming flexibility. Several variations of this technologyinclude metal—nitride—oxide—semiconductor (MNOS), silicon—oxide—nitride—oxide—semiconductor (SONOS), floating gate tunneling oxide (FLOTOX),and textured polysilicon. The FLOTOX is most commonly used EEPROMtechnology. An interesting NVM architecture is the nonvolatile SRAM, acombination of EEPROM and SRAM in which each SRAM has a correspond-ing ‘‘shadow’’ EEPROM cell.

Flash memories based on EPROM or EEPROM technologies are devicesfor which contents of all memory array cells can be erased simultaneously,unlike the EEPROMs that have select transistors incorporated in each cell toallow for the individual byte erasure. Therefore, the flash memories can bemade roughly two or three times smaller than the floating gate EEPROM cells.Flash memories are available in 8- to 512-Mb densities as production devices,and even higher densities in development.

DRAMs are currently (and predicted to be in the future) the largest memorysegment in terms of dollar sales. After DRAMs the SRAMs and flash marketsrepresent the next two largest memory segments. In year 2000, the flashmemory market surpassed the SRAM market and became the second-largestmemory market segment. Both DRAM and flash market shares are expectedto continue growing through 2005, although flash memory at a much fasterpace. The remaining memory segments are predicted to remain stable.

SEMICONDUCTOR MEMORIES OVERVIEW 3

Figure 1.2a shows a comparison of different MOS technologies market shareprojected to year 2005 [2]. It is predicted that in year 2005, the DRAMs willaccount for just 60% of the memory market, whereas flash memory sales isforecast to account for 29% of the total memory market. Figure 2.2b showspercentages for each MOS memory technology market for the year 2000 andpredicted values for the year 2005.

Semiconductor Memories reviewed various memory failure modes and mech-anisms, fault modeling, and electrical testing [1]. A most commonly used faultmodel is the single-stuck-at fault (SSF), which is also referred to as the classicalstandard fault model. However, many other fault models have also beendeveloped for transition faults (TFs), address faults (AFs), bridging faults(BFs), coupling faults (CFs), pattern-sensitive faults (PSFs), and the dynamic(or delay) faults. A large percentage of physical faults occurring in the ICs canbe considered as the bridging faults (BFs), consisting of shorts between the twoor more cells or lines. Another important category of faults that can cause theRAM cell to function erroneously is the coupling or PSFs.

In general, the memory electrical testing consists of the dc and ac parametrictests and functional tests. For RAMs, various functional test algorithms havebeen developed for which the test time is a function of the number of memorybits (n) and range in complexity from O(n) to O(n�). The selection of aparticular set of test patterns for a given RAM is influenced by the type offailure modes to be detected, memory bit density that influences the test time,and the memory automated test equipment (ATE) availability.

Advanced megabit memory architectures are being designed with specialtest features to reduce the test time by the use of multibit test (MBT), line modetest (LMT), and built-in self-test (BIST). Application-specific memories such asthe FIFOs, video RAMs, synchronous static and dynamic RAMs, and double-buffered memories (DBMs) have complex timing requirements and multiplesetup modes that require a suitable mix of sophisticated test hardware, designfor testability (DFT), and BIST approach.

In general, the memory testability is a function of variables such as circuitcomplexity and design methodology. Therefore, the DFT techniques, RAMand ROM BIST architectures, memory error detection and correction(EDAC), and the memory fault tolerance are important design considerations.Structured design techniques are based upon the concept of providing uniformdesign to increase controllability and observability. The commonly usedmethodologies include the level-sensitive scan design (LSSD), scan path,scan/set logic, random access scan, and the boundary scan testing (BST). TheRAM BIST implementation strategies include the use of algorithmic testsequence (ATS), the 13-N March algorithms with a data-retention test, afault-syndrome-based strategy for detecting the PSFs, and built-in logic blockobservation (BILBO) technique. For the embedded memories, various DFT


Figure 1.2 (a) Comparison of different MOS memory technologies market share. (b) Percentagesfor each MOS memory technology market for year 2000 and predicted values for year 2005 [2].

and BIST techniques have been developed such as the scan-path-based flag-scan register (FLSR) and the random-pattern-based circular self-test path(CSTP). Advanced BIST architectures have been implemented to allow paralleltesting with on-chip test circuits. The current generation megabit memorychips include spare row and columns (redundancies) in the memory array to


compensate for the fault cells. In addtion, to improve the memory chip yield,techniques such as built-in self-diagnosis (BISD) and built-in self-repair (BISR)are used.

The errors in semiconductor memories can be broadly categorized as thehard failures caused permanent physical damage to the device and soft errorscaused by alpha particles or the ionizing dose radiation environments. Themost commonly used error-correcting codes (ECC) that are used to correcthard and soft errors are the single-error correction and double-error detection(SEC-DED) codes, also referred to as the Hamming Codes. MultimegabitDRAM chips have been developed that use redundant word and bit lines inconjunction with ECC to produce optimized fault tolerance effect. To recoverfrom the soft errors (transient effects), memory scrubbing techniques are oftenused, which are based upon the probabilistic or deterministic models. Thesetechniques can be used to calculate the reliability rate R(t) and mean time tofailure (MTTF) of the memory system.

Semiconductor Memories reviewed general reliability issues for semiconduc-tor devices such as the memories, RAM failure modes and mechanisms,nonvolatile memory reliability, reliability modeling and failure rate prediction,design for reliability, and reliability test structures [1]. The general reliabilityissues pertaining to semiconductor devices in bipolar and MOS technologiesare applicable to memories also. In addition, there are special reliability issuesand failure modes, which are of special concern for the RAMs. These issuesinclude gate oxide reliability defects, hot-carrier degradation, the DRAMcapacitor charge-storage and data-retention properties, and DRAM soft-errorfailures. The memory gate dielectric integrity and reliability are affected by allprocesses involved in the gate oxide growth.

The reduced MOS transistor geometries from scaling of the memory deviceshas made them more susceptible to hot-carrier degradation effects. Nonvolatilememories, just like volatile memories, are also susceptible to some specificfailure mechanisms. In the floating gate technologies such as the EPROM andEEPROMs, data retention characteristics and number of write/erase cycleswithout degradation (endurance) are the most critical reliability concerns.

Reliability failure modeling is the key to the failure rate prediction, and thereare many statistical distributions that are used to model various reliabilityparameters. The method of accelerated stress aging for semiconductor devicessuch as memories is commonly used to ensure long-term reliability. Anapproach commonly used by the memory manufacturers in conjunction withthe end-of-line product testing has been the use of reliability test structures andprocess (or yield) monitors incorporated at the wafer level and ‘‘drop-in’’ testsites on the chip. The purpose of reliability testing is to quantify the expectedfailure of a device at various points in its life cycle.


The space radiation environment poses a certain radiation risk to allelectronic components on earth-orbiting satellites and the planetary missionspacecrafts. The cumulative effect of ionization damage from charged particlespresent in the natural space environment, such as the electrons and protons onsemiconductor memories, can be significant. Ionizing radiation damage causeschanges in memory circuit parameters such as standby power supply currents,I/O voltage threshold levels and leakage currents, critical path delays, andtiming specification degradations. The single-event phenomenon (SEP) in thememories is caused by high-energy particles such as those present in the cosmicrays passing through the device to cause (a) single-event upsets (SEUs) or softerrors and (b) single-event latchup (SEL), which may result in hard errors. Theimpact of SEU on the memories, because of their shrinking dimensions andincreasing densities, has become a significant reliability concern. The non-volatile MOS memories are also subject to radiation degradation effects.

The memory circuits can be designed for total dose radiation hardness byusing optimized processes (e.g., hardened gate oxides and field oxides) andgood design practices. The bulk CMOS memories have been hardened to SEUby using an appropriate combination of processes and design techniques.Radiation sensitivity of unhardened memory devices can vary from lot to lot;and for space applications, radiation testing is required to characterize the lotradiation tolerance. Semiconductor Memories discussed the following topics indetail: radiation-hardening techniques, radiation-hardening design issues, radi-ation testing, radiation dosimetry, wafer level testing, and test structures [1].

Advanced semiconductor memories technologies include ferroelectric RAMs(FRAMs or FeRAMs), magnetoresistive RAMs (MRAMs), analog memories,and quantum-mechanical switch memories. These technologies were brieflyreviewed in Semiconductor Memories.

The increasing requirements for denser memories have led to furthercompaction of standard packaging approach to hybrid manufacturing tech-niques and multichip modules (MCMs). For the assembly of MCMs, variousinterconnect technologies have been developed such as the wire-bonding, tapeautomated bonding (TAB), flip-chip bonding, and high-density interconnect(HDI). An extension of 2-D planar technology has been the 3-D concept, inwhich the memory chips are mounted vertically prior to the attachment of asuitable interconnect. The 3-D approach can provide higher packaging den-sities because of (a) reduction in the substrate size, module weight, and volume,(b) lower line capacitance and drive requirements, and (c) reduced signalpropagation delay times. Semiconductor Memories reviewed commonly usedmemory packages, memory hybrids and 2-D MCMs, memory stacks and 3-DMCMs, memory MCM testing and reliability issues, memory cards, andhigh-density memory packaging future directions [1].


1.2. ADVANCED SEMICONDUCTOR MEMORY DEVELOPMENTS

This book, Advanced Semiconductor Memories, reviews in detail future ad-vances in SRAMs, high-performance DRAMs, application-specific DRAMdesigns and architectures, nonvolatile memory technologies, embedded mem-ory designs and applications, and future gigabit-to-terabit memory directions.These advanced developments are briefly summarized in this section.

Advanced SRAM technology developments are reviewed in Chapter 2.SRAMs are currently available for both asynchronous and synchronousdesigns in a wide variety of speeds and architectures. However, synchronousdesigns are preferred and use one or more external clock signals to control theSRAM operations, and they result in improved timing controls. This allows thereduction of the device access times and cycle times to match the clock cyclesof the fastest PC and RISC processors available. The synchronous SRAM(SSRAM) data buses are usually flow-through or pipelined. In the communi-cation networks, SRAMs are being used as data buffers between the input andoutput ports, and they are also being used as high-speed lookup tablescontaining addresses and other information to route data stream from the datasource to destination.

SRAM speed has been enhanced by scaling down the device geometries, aswell as by improvement in processes and circuit design techniques for theoptimization of chip architecture. For low-voltage SRAMs, the designers areusing various techniques to minimize the power consumption. Fast SRAMshave applications in cache memory system designs. Some examples of high-performance SRAM architectures are described, such as the flow-throughSSRAMs, zero bus turnaround (ZBT��) SRAMs, No Turnaround RandomAccess Memory (NtRAM��) pipelined, quad-data-rate (QDR) SRAMs anddouble-data-rate (DDR) SRAMs.

BiCMOS technology is more important in applications that require com-patibility with high-performance microprocessor clock speeds. However, Bi-CMOS process is more complex because of the additional steps required,compared to a standard CMOS process. The silicon-on-insulator (SOI) tech-nology in SRAM applications offers significant performance advantages due tothe reduction in device junction capacitance. The major advantages of the SOItechnology include latchup free operation and improved soft-error rate (SER)performance. SOI technology SRAMs are finding applications in criticalmilitary and space applications with high total dose radiation and transientsurvivability requirements (see Semiconductor Memories, Chapter 7).

The basic SRAM performance can often be improved by the addition ofsome extra logic control circuitry to provide specialty SRAMs. For example,in systems with multiple processors or devices requiring simultaneous access tothe SRAM, multiport memories can be used. An extension of this concept is


first-in-first-out (FIFO) memories available in various configurations for theuse as buffers for multiprocessors and serial communication networks. Aspecialty device is content addressable memory (CAM) that can output anaddress (or addresses) when data are presented to certain inputs. Design andarchitecture examples of three types of specialty memories are presented:multiport RAMs, FIFOs, and CAMs.

Semiconductor Memories provided an introduction to the DRAM technol-ogy evolution, as well as technology developments in advanced architectures[1]. Chapter 3 (High-Performance Dynamic Random Access Memories) in thepresent book provides a detailed overview of further DRAM technologyadvances, scaling issues, and future trends. The new-generation DRAMs usevarious refresh schemes, as well as provide several modes for accessing data inthe storage cells. For scaling to 64-Mb and higher densities, it is necessary toincrease the cell’s storage capacity by using 3-D cell structures, along withtrench or stacked capacitors. Enhanced DRAM (EDRAM) can be used toreplace standard, slow full-page mode (FPM) or EDO DRAM for some higherperformance applications that require large amounts of very fast memory.

Extended-Data-Out (EDO) DRAMs have the advantage over conventionalFPM memory is that it allows for a shorter page mode cycle time (or fasterdata rate) while accessing data within a single page in memory. An example of64-Mb EDO DRAM available from Infineon Technologies is discussed.Single-data-rate synchronous DRAMs (SDRAMs) and synchronous graphicRAMs (SGRAMs) use the same basic memory cell and the same word-linedrivers as the EDO DRAMs. However, their performance is limited by theinterface requirements. Therefore, the double-data-rate (DDR) SDRAM/SGRAM were introduced as an architectural enhancement by incorporatingseveral major features. An example of architecture and functional operationsof a commercially available 256-Mb SDRAM from Micron Technology ispresented.

The enhanced SDRAM (ESDRAM) is an evolutionary modification to theJEDEC standard for 16-Mb SDRAM, which incorporates changes to astandard DRAM to reduce latency, increase the bandwidth, and allow forconcurrent operations to the same bank. An example of 16-Mb ESDRAMfrom Enhanced Memory Systems, Inc., is discussed. Cache DRAM (CDRAM)introduced by Mitsubishi Corporation is an SDRAM with an on-chip cache inthe form of a separate SRAM array integrated with the DRAM array.However, in CDRAM (unlike the EDRAM), the SRAM and DRAM oper-ations can be separately controlled. An example of 16-Mb CDRAM fromMitsubishi Corporation is provided.

The virtual channel memory (VCM) memory core technology was develop-ed by NEC Incorporated, to improve the memory data throughput efficiencyand targeted for multiple users, multitasking, and interleaved access environ-

ADVANCED SEMICONDUCTOR MEMORY DEVELOPMENTS 9

ment. Another example of advanced memory architecture is a 64-Mb fast-cycleRAM (FCRAM) that involves basic changes in the DRAM core concept byoperating the memory like a synchronous SRAM using the dynamic core.Another example of 256-Mb DRAM architecture is given that provides up to�32-bit-wide organization and uses an exchangeable, hierarchical data linescheme to minimize the number of sense amplifier circuits.

Major gigabit DRAM scaling issues are discussed, using several examples of1-Gb SDRAM cells and architectures that have been recently developed.In gigabit DRAM scaling, one of the major issues is the reduction of arraypower consumption without degrading the operating margin of the memorydevice and other characteristics. Multivalued and multilevel RAMs(MLDRAMs) schemes have been proposed, in which the amount of voltageplaced across the capacitor is varied to represent the multiple states. If thenumber of states in a single memory cell is doubled, then the storage capacityof the memory cell can be doubled. Some of the proposed MLDRAM designsare reviewed, including a 4-Gb DRAM with multilevel storage memory cellsthat utilize data storage at four levels, where each level corresponds to a 2-bitdata storage in a single memory cell. This approach can reduce the effectivecell size by 50%.

SOI DRAMs are under development for which the major advantagesinclude a superior SER, better static data retention time characteristics, andpotential for higher integration density than the bulk-Si-based DRAMs. Anoverview of various isolation processes used for SOI and feature comparison ofthe bulk-Si, partially depleted (PD) and fully depleted (FD) SOI transistors isprovided.

The technical advances in multimegabit DRAMs have resulted in greaterdemand for memory designs incorporating specialized performance require-ments for applications, such as the high-end desktops/workstations, PC ser-vers/mainframes, 3-D graphics, network routers and switches. Some earlierexamples of these application specific DRAMs, such as the pseudostaticDRAMs (PSRAMs), or virtual static DRAMs (VSRAMs) were discussed inSemiconductor Memories [1]. Chapter 4 in the present book describes latestdevelopments in application specific memory architectures and designs in moredetails, such as the Video RAMs, SGRAMs, DDR SGRAMs, Rambus��Technology, Synchronous Link DRAMs (SLDRAMs), and 3-D RAMs.

The video RAM (VRAM) was developed to increase the bandwidth of rastergraphics display frame buffers. An example of the architecture of a 4-MbVRAM is provided. A further improvement was SGRAMs that are very similarto the SDRAMs, except that they have several additional functions to improvetheir effectiveness in graphic systems design. Examples of a 64-Mb DDRSGRAM from Fujitsu Semiconductor, and a 256-Mb fast-cycle RAM(FCRAM��) are provided.


Figure 1.3 A flow chart of various types of some commonly used high speed RAMs.

Direct RDRAM is a high-speed memory for graphic applications and offersdouble the word width of the original RDRAM, offering storage capabilities of64/72 Mb, 128/144 Mb, and 256/288 Mb. Concurrent RDRAMs perform twobank operations simultaneously, to allow high transfer rates using interleavedtransactions. These memories can operate at speeds of 600 MHz, achievingdata transfer speeds of 1.2 Gbytes/s. Various Rambus technologies andarchitectures including command sets, protocol formats, and functional blocksare discussed. SLDRAM is a new memory interface specification developedthrough the cooperative efforts of leading semiconductor memory manufac-turers with a goal to meet the high data bandwidth requirements of emergingprocessor architectures, as described in IEEE Standard P1596.4. An exampleof a very-high-speed, packet-oriented, pipelined, 4-Mb�18 synchronousSLDRAM available from Micron Technology, Inc., is provided.

Mitsubishi Corporation pioneered the introduction of a family of 3-D RAMfor high-performance 3-D graphics hardware. The architecture and variousfunctional blocks of this 3-D RAM family are discussed. Currently, in applica-tion-specific, high-performance memory designs, the competing technologiesare SDRAM, DDRSDRAM, Rambus DRAM, and SLDRAMs. An overviewof various memory system design considerations, such as the peak bandwidthperformance comparison, granularity, and latency, is provided.

Figure 1.3 provides a flow chart of various types of some commonly usedRAMs.


Nonvolatile memories (NVMs) are characterized by their ability to retainthe stored data even with the device power off for indefinite periods of time, ascompared to the volatile memories (such as the SRAMs and DRAMs) that losethe stored information under these conditions. Some examples of the NVMsare ROMs, PROMs, EPROMs, and EEPROMs designs and technologies.Special memories are also available such as nonvolatile random access memory(NOVRAM) or shadow RAM configurations that combine on the same chip,a SRAM array, and a backup EEPROM array of equal bits. In recent years,an area of interest in advanced nonvolatile memories has been the developmentof thin-film ferroelectric (FE) technology to build ferroelectric RAMs (FRAMs)as substitutes for the NOVRAMs, These NVM technologies were brieflydiscussed in Semiconductor Memories, Chapter 3 [1].

Serial EEPROMs are considered low-cost solution for the applications thatdo not require the high capability or short access times of traditional NORand NAND type of architectures. The flash memory architecture has splitalong two main paths: traditional random access devices based on the NORdesigns and byte-serial devices based on the NAND/AND architectures thathave closer resemblance to the solid-state disk drives. Each of these approachesis suited for different applications, and finding wider usage throughout theindustry. Chapter 4 of the present book provides a detailed overview of theEPROM/EEPROM and FRAM (or FeRAM) technology developments andarchitectures.

In the growth of multipurpose flash memory market, the demands for alldensities of flash are rising simultaneously, including that of low-density flashdevices. In general, the flash memory technology can be divided into two broadcategories: (a) NOR-based flash targeted toward the program code/datastorage applications and (b) NAND-based flash ideal for mass storage appli-cations. The NAND-based flash memories of 256-Mb and higher densities arealready in mass production, with 512-Mb and higher densities also beingtargeted by the suppliers. The NOR-type flash memories are available withtypical access times of 35 ns for 1-Mb memory devices and 45 ns for 128-Mbcapacities. The latest approach to provide high storage densities in flashmemories is the use of multilevel cell (MLC) charge storage per cell techniques.

The EPROM/EEPROM technology is based on the charge storage indiscrete trapping centers of an appropriate dielectric layer, or on a completelyelectrically isolated gate referred to as the ‘‘floating-gate’’ device. The floating-gate cell theory and operations, along with charge transport mechanisms suchas the channel hot electron (CHE) injection and Fowler—Nordheim tunneling,are presented.

The EPROM cell developments over last two decades include T-cell, X-cell,staggered virtual ground array (SVG) array cell, alternate metal ground(AMG) array cell, and so on. The EEPROM/flash memory cell arrays include


various NOR cell structures and NAND flash cells. An EEPROM technologythat was developed earlier is the metal—nitride—oxide—silicon (MNOS) and(poly)silicon—oxide—nitride—oxide—semiconductor (SONOS), and floating-gate tunnel oxide (FLOTOX) cells that were briefly discussed in SemiconductorMemories [1].

Chapter 5 in the present book reviews the latest developments in EEP-ROM/flash cells and array structures. Four major flash architectures arereviewed: NOR, NAND, DINOR, and AND along with representative mem-ory devices currently available from vendors, such as a 32-Mb simultaneousread/write NOR-based flash memory from Advanced Microdevices, Inc.(AMD), 32-Mb dual-plane flash memory from Intel Corp., 256-Mb Ultra-NAND flash memory from Samsung, Inc., and 16-Mb DINOR flash memoryfrom Mitsubishi, Inc. The new developments include a proposed 3.3-V, 16-Mbnonvolatile memory using NAND flash architecture, which has operationvirtually identical to that of a DRAM.

The latest development in flash memory is the concept of multilevel (ML)that refers to the storage of more than one bit per cell, in order to increase thedevice density and reduce the cost per bit. In principle, the ML concept can becoupled with various types of memory architectures, such as the NOR andNAND to implement a 2-bit/cell scheme. However, there are several MLprogramming, sensing, and reliability issues that need to be addressed in eachof these architectures. An example of this approach is Intel’s multilevelNOR-based architecture, which is currently capable of storing two bits permemory cell but may be scalable to three bits per cell. An overview of Intel’s3-V StrataFlash NOR-based memory, a proposed multilevel 64-Mb NANDflash memory design, a 512-Mb NAND flash memory from Toshiba Corp., anda 256-Mb multilevel cell AND flash memory from Hitachi Corp. is provided.

Semiconductor Memories reviewed general reliability issues such as the gateoxide breakdown, electromigration, hot-carrier degradation, metallization cor-rosion, and so on, which are generic among various semiconductor technolo-gies [1]. However, there are a number of failure modes and mechanisms thatare specific to the EPROM/EEPROMs such as data-retention characteristicsand the number of write/erase cycles without degradation (endurance), whichare critical reliability concerns. The major issues concerning yield and reliabil-ity of flash memories are flash overerase, program/read disturbs, program/readendurance, flash data retention failures, and flash hot carrier reliability effects.

In general, the reliability of MLMs is more critical than that of theconventional two-level logic (1 bit/cell) because of the requirements for a largerthreshold (V

�) window (to keep adequate spacing among the stored levels)

and/or reduced spacing between the adjacent levels (to limit the increase in V�

window). Chapter 5 in the present book reviews the major reliability and yieldissues for flash memories.


FRAM is a RAM-based device that uses the ferroelectric (FE) effect as thecharge storage mechanism, based on the ability of material to store anelectrical polarization in the absence of an applied electric field; that is, aferroelectric memory stores data within a crystalline structure. In FRAM, thememory readout is a destructive operation, and therefore each read access isaccompanied by a precharge operation that restores the memory state. A writeoperation is very similar to a read operation and requires no system overhead.Some of the most widely used FE materials are PZT (PbZr

�Ti

��O

�) and SBT

(SrBi�Ta

�O

�).

An example of the FRAM is 256-Kb device that uses a two-transistor,two-capacitor (2T2C) memory cell design from Ramtron Corp. The newdevelopments include one-transistor, one-capacitor (1T1C) memory cell designsuitable for 1-Mb and higher-density designs. A proposed DRAM-like FeRAMcell array, referred to as the depletion FeRAM (DeFeRAM), and a 4-MbFRAM with 1T1C cell design are discussed. A new chain FRAM (CFRAM)architecture has been proposed, which can realize 4F� size memory cell andrandom access; and when 16 cells are connected in series, the chip size can bereduced to 63% to that of a conventional FRAM.

Metal— ferroelectric semiconductor (MFS) devices that are considered can-didates for high-density NVM applications are based on the principle thatinformation can be stored as a polarization direction rather than as a chargeon a capacitor. Ferroelectric films used as memory storage elements havesignificant reliability concerns, such as the aging/fatigue effects, thermal stabil-ity, effects of electric fields, and so on. These are briefly reviewed in Chapter 5.

As the processor performance has increased from several hundred mega-hertz to 1 GHz and beyond, idle wait time in relatively slower DRAMshas increased, leading to a memory-processor performance gap. The fastestgrowing trend in advanced semiconductor memory is the embedded mem-ories designs and applications. Memory technology for embedded memoryhas a wide variation, ranging from small blocks of ROMs, hundreds ofkilobytes for the cache RAMs, high density (several megabits) of DRAMs, andsmall to medium density nonvolatile memory blocks of EEPROMs and flashmemories. Embedded SRAM is one of the most frequently used memoryembedded in logic chips. Chapter 6 discusses embedded memory designs andapplications.

Currently, the two major approaches for embedded memories developmentare fabricating memory in a logic-based process versus fabricating logic in aDRAM-based process technology. A recent trend driving the integration ofDRAM into logic chips is the need to reduce power by eliminating the needfor off-chip drivers and improving performance. Another advantage is noisereduction. A key advantage of the embedded memory approach is the higherpackaging density and board space savings, which is a desirable feature for


applications such as the notebook computers and portable communicationdevices. The relative tradeoffs between the two approaches have spawnedarguments regarding which technology should be preferred over the other.

In a PC system, the major goal of using a cache memory is to increase theDRAM subsystem performance by reducing the latency and increasing band-width. Cache memory design tradeoffs are reviewed, and an example of cachearchitecture implementation for a popular TI DSP is provided.

The demand for embedded memories is on the rise in current generation ofultra-large-scale integration (ULSI) and system-on-chip (SOC) level designsthat require large amounts of SRAM, multiport RAM, DRAM, ROM, andEEPROM flash memories. Examples of some of the advanced SRAM macrosare provided, such as one-transistor (1T) and four-transistor (4T) cell designs.In general, an ASIC with embedded memory will provide better systemperformance and a smaller part count as compared to a design that usesexternal memory.

An example of early embedded DRAM development is Toshiba’sdRAMASIC process, based on two approaches, one of which utilizes one-transistor, one-capacitor (1T1C) architecture for providing high-density em-bedded DRAMs, and the other based on three-transistor cell that providescapability for implementation of low-density embedded DRAMs. CompiledDRAM macros of various densities, speeds, databus widths, dual-port con-figurations, and other features implemented in a merged DRAM/logic processare available from various companies. The latest developments include a1-GHz eDRAM macro cell to serve large-capacity, on-chip L2 cache memoryfor gigahertz-level SOC designs.

The embedding of DRAMs in a logic technology requires some additionalsteps to the standard logic process flow. Two examples of merged logicprocessor—DRAM architectures are discussed in detail: (1) Mitsubishi MR32/D, a 32-bit RISC processor with DSP functions that uses 2 MB of DRAM plus4 KB of cache SRAM on the same die and (2) a multimedia-oriented RISCprocessor that has a high-data-rate system and uses a concurrent RDRAMcontroller in a superscalar architecture.

The alternative approach of DRAM technology with embedded logicarchitecture is mainly utilized by companies such as Mitsubishi, Samsung,Toshiba, and Infineon Technologies, which have DRAM manufacturing heri-tage and add some masking steps to include logic in their DRAM processes.Multimedia accelerators that require high data transfer rates between the framebuffers and the data processing units utilize embedded DRAM-logic approach.An example of Oki Electric Company’s multimedia accelerator, which inte-grates the MPEG-1 video/audio decoder, the 2-D graphic user interface (GUI)engine, and a RAMDAC (135-MHz, true color digital/analog converter), isprovided.


The University of California, Berkeley, approach for intelligent RAM(IRAM) supports designing the processor in a memory process, which hasseveral advantages as well as disadvantages that are discussed. Anotherapproach that has been proposed to implement processor-in-memory architec-ture is computational RAM (C ·RAM) with a goal to make an effective use ofinternal memory bandwidth by pitch-matching simple process elements tomemory columns. C·RAM can function either as a conventional memory chipor as a single-instruction stream, multiple-instruction data stream (SIMD)computer.

The most popular examples of embedded flash memory devices are PLDs,FPGAs, DSPs, and microcontrollers. The embedded system designers prefer touse flash-based processors, which can be quickly programmed before transfer-ring their code to a more cost-effective ROM-based chip for high volumeproduction. The use of embedded flash and EEPROM technologies in micro-controllers available from various suppliers is discussed.

There is a growing need worldwide for small, inexpensive, rugged, and easilytransportable forms of nonvolatile data storage. Flash card technology meetsthose requirements, and the use of flash cards is expected to grow exponentiallyover the next decade. Various flash card technologies are reviewed, such as theAdvanced Technology Attachment (ATA), CompactFlash�� Cards, Multi-Media Cards, and single-chip flash disk.

1.3. FUTURE MEMORY DIRECTIONS

Chapter 7 discusses mostly volatile and nonvolatile memory technologies thatare in research and development, along with their future directions and potentialfor gigabit-to-terabit scaling. An example is magnetoresistive RAMs (MRAMs)that are nonvolatile magnetic storage devices based on the principle that amaterial’s magnetoresistance will change due to the presence of magnetic field.TheMRAM technology has some attractive features such as the nondestructivereadout (NDRO), high radiation tolerance, higher write/erase endurancecompared to the FRAMs, and virtually unlimited power-off capabilities. EarlierMRAMs were based on the anisotropic magnetoresistance (AMR) effect, whichhas allowed realization of smaller elements with largerM-R effect and, therefore,a higher output signal. Some companies such as Honeywell, NonvolatileElectronics, Inc. (NVE), have demonstratedworkingMRAMchips ranging from64-Kb to 256-Kb densities. Many other companies such as Motorola, IBM,InfineonTechnologies,Toshiba, and so on, are also actively developingMRAMs.

The resonant tunneling diode (RTD) consists of an emitter region andcollector region, and a double tunnel barrier structure, which contains aquantum well. Both tunnel diodes and RTDs exploit negative differential


resistance (NDR) characteristics of quantum-mechanical resonant tunnelingcurrents. RTDs are of interest for use in multistate and compact memory, aswell as in tunneling-based SRAM (TSRAM) cell designs and applications. Afully decoded 1-Kbit TSRAM prototype with DRAM-type high-speed signal-to-noise ratio sensing circuitry has been designed. An RTD-based senseamplifier circuit called a quantum MOS (QMOS) has been proposed thatshows a good noise immunity and 20% faster sensing time as compared to theconventional CMOS design sense amplifier. RTDs based on III—V compoundmaterials can achieve high peak current densities and appear to be the mostlikely candidates for advanced TSRAM designs and applications.

In single-electron devices, the operating principle relies on the Coulombrepulsive force between electrons. These devices are expected to operate evenat very small physical dimensions (atomic scale), making ultra-large-scaleintegration possible. Another potential advantage is ultra-low-power oper-ation, because the device uses a very small number of electrons to performbasic operation. The majority of research in single-electron devices has beendone at very low temperature, because room temperature operation requiresvery large Coulomb energy, accomplished only with sub-10-nm structures,which imposes lithographic limitations.

Single-electron phenomena have also been observed at room temperature,and demonstration has included the concept of the floating-dot memory cell,in which nano-Si particles can replace the floating gate of the memory device.However, many major challenges need to be overcome before the commercialproduction of single-electron memory becomes feasible. Various single-electronmemory configurations are under development, such as the SET flip-flop,electron-trap memory, SET ring memory, random background charge-inde-pendent memory, and single/multiple island memories.

In a nanocrystal memory, the charge storage in a distributed floating gateoffers several attractive characteristics such as the faster write times, operationat lower power than those for the EEPROMs, and better endurance charac-teristics than that for the flash EEPROMs. A 128-Mb single-electron memoryprototype chip has been developed by Hitachi Central Laboratory, Japan,using the Coulomb blockade effect based on the electron repulsion within anultrathin layer of polycrystalline material.

The phase change memory technology stores information using structuralphase changes in certain thin film alloys that typically utilize one or moreelements from column VI of the periodic table (e.g., germanium and anti-monium). These phase change alloys are referred to as the chalcogenidematerials. The phase change technology uses a thermally activated, rapid,reversible change in the structure of an alloy to store the data. Semiconductormemory elements using chalcogenide materials have been fabricated as tech-nology demonstrators. Air Force Research Laboratories (AFRL) is funding

FUTURE MEMORY DIRECTIONS 17

development for a 64-Kb memory cell array as a characterization test chip,with plans for future migration to higher densities.

A new area of research is protonic nonvolatile memories that are based onthe observation that hydrogen ions (protons) can be used as the primarycarriers of information in a silicon—silicon oxide—silicon (Si—SiO

�-Si) device,

creating a memory function. Several patents have been granted based on thismemory function concept.

Chapter 7, Section 7.7 provides a few examples of the following new memorytechnology developments:

· A proposed novel thyristor-based SRAM cell, called T-RAM, which hasa cell area less than one-tenth the area of a conventional SRAM cell. Itcan provide DRAM densities, while the potential for speed is comparableto current generation of SRAMs.

· An integrated content addressable read-only memory (CAROM) datastorage system that uses data compression algorithm, which promisesCD-ROM density, in an arbitrarily shaped data package without movingparts. A company, Autosophy, Inc., is planning to etch these arrays on foil,similar to active LCD production, which could result in foldable deviceswith hundreds of megabyte capacity that can fit in PC cards or othersmall cartridges.

· Work (by IBM Research Group in Zurich, Switzerland) on developmentof a prototype called Millipede, which can store an amazing amount ofdata (e.g., 500 Gb/in.�) as microscopic indentations on a flat polymersurface. This technology is similar to the operation of a phonographicstylus and is derived from the atomic force microscopy.

· Holographic data storage that is considered a promising technology forachieving random access volumetric storage, offering orders of magnitudegreater density than the surface storage. A unique advantage of holo-graphic memories from the space applications perspective is their inherentradiation hardness. A holographic random access memory (HRAM)design has been proposed that can lead to the implementation of compactand inexpensive modules that can be used to construct large read—writememories. The greatest challenge for HRAM development is to improveits slow recording rate by several orders of magnitude.

REFERENCES

1. Ashok K. Sharma, Semiconductor Memories: Technology, Testing and Reliability,IEEE Press, New York, 1997.

2. B. McClean, B. Matas, and T. Yancey, The McClean Report: 2001 Edition, ICInsights, 2001.


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