Semiconductor Device Reliability

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Semiconductor Device Reliability Semiconductor Device Reliability

Transcript of Semiconductor Device Reliability

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Semiconductor Device Reliability Semiconductor Device Reliability

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NATO ASI Series Advanced Science Institutes Series

A Series presenting the results of activities sponsored by the NA TO Science Committee, which aims at the dissemination of advanced scientific and technological knowledge, with a view to strengthening links between scientific communities.

The Series is published by an international board of publishers in conjunction with the NATO Scientific Affairs Division

A Life Sciences B Physics

C Mathematical and Physical Sciences

o Behavioural and Social Sciences E Applied Sciences

F Computer and Systems Sciences G Ecological Sciences H Cell Biology

Series E: Applied Sciences - Vol. 175

Plenum Publishing Corporation London and New York

Kluwer Academic Publishers Dordrecht, Boston and London

Springer-Verlag Berlin, Heidelberg, New York, London, Paris and Tokyo

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Semiconductor Device Reliability edited by

A. Christou Surface Physics Branch, Naval Research Laboratory, Washington, D.C., U.S.A.

and

B. A. Unger Bell Communications Research, Red Bank, N.J., U.S.A.

Kluwer Academic Publishers

Dordrecht / Boston / London

Published in cooperation with NATO Scientific Affairs Division

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Proceedings of the NATO Advanced Research Workshop on Semiconductor Device Reliability Heraklio, Crete, Greece June 4-9, 1989

Library of Congress Cataloging In Publication Data NATO Advanced Research Workshop on Semiconductor Device

Reliability (1989 : Herakleion, Greece) Semiconductor device reliability.

(NATO ASI series. Series E: Applied sciences ; vol. 175)

"Published in cooperation with NATO Scientific Affairs Division."

1. Semiconductors--Reliability--Congress. I. Christou A. II. Unger, B. A. III. Title. IV. Series: NATO A.'SI series. Series E, Applied sciences no. 175. TK7871.85.N3758 1989 621.381'52 89-24589

ISBN-13: 978-94-010-7620-3 e-ISBN-13: 978-94-009-2482-6 DOl: 10.1007/978-94-009-2482-6

Published by Kluwer Academic Publishers, P.O. Box 17, 3300 AA Dordrecht, The Netherlands.

Kluwer Academic Publishers incorporates the publishing programmes of D. Reidel, Martinus Nijhoff, Dr W. Junk and MTP Press.

Sold and distributed in the U.S.A. and Canada by Kluwer Academic Publishers, 101 Philip Drive, Norwell, MA 02061, U.S.A.

In all other countries, sold and distributed by Kluwer Academic Publishers Group, P.O. Box 322,3300 AH Dordrecht, The Netherlands.

Printed on acid-free paper

All Rights Reserved © 1990 by Kluwer Academic Publishers Softcover reprint of the hardcover 1 st edition 1990

No part of the material protected by this copyright notice may be reproduced or utilized in any form or by any means, electronic or mechanical, including photo­copying, recording or by any information storage and retrieval system, without written permission from the copyright owner.

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TABLE OF CONTENTS

PREFACE

CHAPTER I. RELIABILITY TESTING

1.1 The Influence of Temperature and Use Conditions on the Degradation of LED Parameters

1.2

1.3

1.4

1.5

R. Goarin. J.P. Defars. M. Robinet. P. Durand and B. Bauduin (CNET. France)

An Historical Perspective of GaAs MESFET Reliability Work at Plessey

James Turner and R Conlon (plessey Research Caswell Ltd .• U.K.)

Screening and Bum-In: Application to Optoelectronic Device Selection for High-Reliability S280 Optical Submarine Repeaters

M. Gucguen. J.L. Boussois. J.L. Goudlard and S. Sauvage (Alcatel CIT. France)

Assuring the Reliability of Lasers Intended for the Uncontrolled Environment

J.L. Spcncer (Bellcore. U.S.A.)

Component Bum-In: The Changing Attitude F. Jensen (The Engineering Academy of Denmark)

CHAPTER II. RELIABILITY MODELS AND FAILURE MECHANISMS

2.1

2.2

2.3

2.4

Statistical Models for Device Reliability; An Overview J. M¢1toft (The Engineering Academy of Denmark)

Computer-Aided Analysis of Integrated Circuit Reliability P. Mauri (SGS-Thomson Microelectronics. Italy)

Reliability Asscssment of CMOS ASIC Designs M.S. Davies (University of Leeds. U.K.) and P.D.T. O'Connor (Britisch Aerospace DynamiCS Group, U.K.)

Models Used in Undersea Fibre Optic Systems Reliability Prediction

RH. Murphy (STC Submarine Systems. U.K.)

CHAPTER III. FAILURE ANALYSIS

3.l. Failure Analysis: The Challenge RG. Taylor and I.A. Hughes (British Telecom, U.K.)

29

43

75

97

107

127

137

147

161

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3.2

3.3

3.4

3.5

3.6

Gate Metallisation Systems for High Reliability GaAs MESFET Transistors

D.V. Morgan (College of Cardiff, U.K.) and J. Wood (University of York, U.K.)

Reliability Limitations of Metal Electrodes on GaAs H.L. Hartnagel (Institut fur Hochfrequenztechnik, F.R.G.)

Failure Mechanisms of GaAs MESFETs and Low-Noise HEMTs

F. Magistrali (Telettra S.p.A., Italy), C. Tedesco and E. Zanoni (Univcrsita' di Padova, Italy)

Metal Contact Degradation on III-V Compound Semiconductors G. Kiriakidis (Research Center of Crete/FORTH, Greece) W.T. Anderson (Navel Research Laboratory, U.S.A.) z. Hatzopoulos, C. Michelakis (Research Center of Crete/ FORTH, Greece) and D.V. Morgan (University of Wales, College of Cardiff, U.K.)

Nuclear Methods in the Characterization of Semiconductor Reliability

J.C. Soares (Centro de Ffsica Nuclear da Universidade de Lisboa, Portugal)

CHAPTER IV. OPTO-ELECTRONIC RELIABILITY (I)

4.1

4.2

4.3

4.4

A Review of the Reliability of III-V Opto-electronic Components S.P. Sim (British Telecom Research Laboratories, U.K.)

Considerations on the Degradation of DFB Lasers T. Ikegami, M. Fukuda and M. Suzuki (NTT Opto-electronics Laboratories, Japan)

InP-Based 4 x4 Optical Switch Package Qualification and Reliability

K. Mizuishi, T. Kato, H. Inoue and H. Ishida (Hitachi Ltd., Japan)

Modelling the Effects of Degradation on the Spectral Stability of Distributed Feedback Lasers

A.R. Goodwin, J.E.A. Whiteaway (STC Technology Ltd., U.K.) and R.H. Murphy (STC Submarine Systems Ltd., U.K.)

177

197

211

269

291

301

321

329

343

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CHAPTER V. OPTO-ELECTRONIC RELIABILITY (II)

5.1

5.2

5.3

5.4

Optoelectronic Component Reliability and Failure Analysis P. Montangero (CSELT, Italy)

Temperature Cycling Tests of Laser Modules P. Su and B.A. Unger (Bellcore, U.S.A.)

An Experimental and Theoretical Investigation of Degradation in Semiconductor Lasers Resulting from Electrostatic Discharge

L.F. Dechiaro, C.D. Brick-Rodriguez and R.G. Chemelli (Bell Communications Research, U.S.A.) J.W. Krupsky (South Central Bell, U.S.A.)

Reliability Testing of Planar InGaAs Avalanche Photodiodes M. Kobayashi and T. Kaneda (Fujitsu Ltd., Japan)

CHAPTER VI. COMPOUND SEMICONDUCTOR RELIABILITY

6.1

6.2.

6.3

6.4

6.5

Status of Compound Semiconductor Device Reliability W.T. Anderson and A. Christou (Naval Research Laboratory, U.S.A.)

Investigation into Molecular Beam Epitaxy-Grown FETs andHEMTs

S. Mottet and J.M. Dumas (Centre National d'Etudes des Telecomunications, France)

Reliability of GaAs MESFETs B. Ricco (University of Bologna, Italy), F. Fantini (S.S.S.U.P.S. Anna, Italy), F. Magistrali and P. Brambila (Teletlra Spa, Italy)

Hydrogen Effects on Reliability of GaAs MMICs W.O. Camp, Jr., R. Lasater, V. Genova and R. Hume (IBM Systems Integration Division, U.S.A.)

Temperature Distribution on GaAs MESFETs: Thennal Modeling and Experimental Results

G. Clerico Titinet and P.M. Scalafiolli (CSELT, Italy)

CHAPTER VII. HIGH-SPEED CIRCUIT RELIABILITY

7.1 High Speed IC Reliability: Concerns and Advances A.A. Iliadis (EO.R.T.H./University of Maryland, U.S.A.)

vii

353

363

379

413

423

439

455

471

479

491

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7.2

7.3

7.4

7.5

Reliability of short channel silicon SOl VLSI Devices and Circuits

D.E. Ioannou (University of Maryland, U.S.A.)

Special Reliability Issues and Radiation Effects of High Speed ICs

G.I. Papaioannou (University of Athens, Greece)

Reliability of High Speed HEMT Integrated Circuits and Multi-2DEG Structures

A. Christou (Foundation of Research and Technology­Hellas, Greece)

AlGaAs as a Dielectric on GaAs for Digital IC'S: Problems and Solutions

W.T. Masselink (IBM T.J. Watson Research Center, U.S.A.)

APPENDIX A. RELIABILITY STRESS SCREENING F. Jensen (Leader), W.E. Camp, R. Murphy and R. Goarin

507

517

545

557

569

APPENDIX B. LIFETIME EXTRAPOLATION AND STANDARDIZATION OF TESTS 571 A. Christou (Leader), J. Mfi)ltoft, P.D.T. O'Connor, W.T. Anderson and P. Mauri

INDEX 573

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PREFACE

This publication is a compilation of papers presented at the Semiconductor Device Reliabi­lity Workshop sponsored by the NATO International Scientific Exchange Program. The Workshop was held in Crete, Greece from June 4 to June 9, 1989. The objective of the Workshop was to review and to further explore advances in the field of semiconductor reliability through invited paper presentations and discussions. The technical emphasis was on quality assurance and reliability of optoelectronic and high speed semiconductor devices.

The primary support for the meeting was provided by the Scientific Affairs Division of NATO. We are indebted to NATO for their support and to Dr. Craig Sinclair, who admin­isters this program.

The chapters of this book follow the format and order of the sessions of the meeting. Thirty-six papers were presented and discussed during the five-day Workshop. In addi­tion, two panel sessions were held, with audience participation, where the particularly controversial topics of bum-in and reliability modeling and prediction methods were dis­cussed. A brief review of these sessions is presented in this book.

The success of any conference, but particularly one with a small attendance, depends not only on the technical content and preparation of each paper and presentation, but also on the willingness of each participant to share and socialize data and experiences and to contribute to the technical discussions. In this regard, the Semiconductor Device Reliability Workshop was a stellar example with each participant contributing freely and profession­ally and presenting papers of considerable merit. The co-directors wish to acknowledge this and thank the attendees for contributing to a splendid week of technical exchange.

It is also a pleasure to acknowledge the Organizing Committee consisting of Professor J. Mf/lltoft, Dr. G. Kiriakidis and the co-directors. This Committee planned the Workshop: set the format, the program, and the activities of the Workshop. We are also indebted to Dr. G. Kiriakidis for taking care of all the conference and attendee hotel arrangements as well as handling all the operational details during the meeting. He was ably assisted at the meeting by Ms. Lia Papadoulau and Ms. Georgia Papadaki. We also acknowledge the secretarial help of Mrs. Mary Daley, who did a splendid job of maintaining order during the planning phase of the meeting and assisting in the preparation of this publication.

And finally a word about the conference. Reliability and quality have become buzz words in our society. The Japanese emphasis on R&Q and demonstrated performance in this area, with the attendant economic benefits, have raised the importance of reliability and quality in all areas of technology. R&Q attributes have become an important part of any sales program, commanding considerable emphasis in sales literature. Indeed, we believe that, in general, product R&Q has improved, even as the products, particularly electronic products, have become more complex. This conference focused on the R&Q of devices to be incorporated in the next generation of electronic and communications products. It was one of the few platforms solely dedicated to the discussion of R&Q of optoelectronic and GaAs circuitry. R&Q emphasis on new emerging technologies at meetings such as this will help to continue this trend toward improved reliability and quality of the next generation of solid state electronics.

Dr. A. Christou Dr. B.A. Unger

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THE INFLUENCE OF TEMPERATURE AND USE CONDITIONS ON THE DEGRADATION OF LED PARAMETERS

R. GOARIN, J.P. DEFARS, M. ROBINET, P. DURAND, B. BAUDUIN C.N.E.T. Departement lABjIFEjCOD BP40 22300 Lannion France

ABSTRACT. This paper is intended to illustrate the quality and reliability of optoelectronic devices. Limited exemples to LED indicate how laboratory tests can be used for preparing component specifications.

The usefulness of burn-in and screening procedures is indicated based on real experience. The importance of technology and manufacturer is presented. The quality and reliability of devices based on failure analysis are often more related to external causes than due to intrinsic reliability of the semiconductor.

1. Introduction

A long experience has been obtained on LED components tested in CNET laboratories showing the contribution of temperature and current on the degradation of optical power. A good correlation between the variations at different conditions has been observed. The Paper gives the results of the evolution of diodes over more than 3 years duration. Those results were very useful to decide on the choice of components for the broadband network installed by FRANCE TELECOM. Several ten thousands of LEDs are now under operation corresponding to excellent reliability results compared to results obtained from lasers.

The observation of individual variations for devices from different manufacturers can be used to evaluate the degradation and extrapolate the behaviour for a long term duration. A position concerning burn-in and screening can be derived, showing that no general philosophy or strategy can be the rule, due to improvement of technology and based on different failure mechanisms.

Investigation on available components and also previous experience on the evolution of optocouplers was a good base to undertake laboratory tests.

The development in France of optical broadband network using optical fibers at a reasonnable cost was only possible if cheap and reliable optical components were available which was not the case in the Biarritz experience.

Due to the fact that a subscriber uses less than 1 kilometer of optical fiber, LED for emission was the best solution combined with multimode fibers. In order to share the fiber using wavelength

A. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 1-28. © 1990 Kluwer Academic Publishers.

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multiplexers two values of length 850 nm and 1300 nm were choosen. The first subscribers are installed with a 850 nm diode, then when the number of subscribers exceeds the number of available fibers the second length is necessary.

The cost for those new subscribers is based on the fact that the same fiber is used allowing an extra cost for the multiplexer and the 1300 nm LED more expensive than the 850 nm. It was also necessary to make evaluation on those components.

Depending on the position of the subscriber and the length of needed fiber, the power through the LED is adjusted and so the intended life. The system budget was based on the worst case evaluation so that any subscriber even at a distance of 1 Km should be in a confortable position.

2. Components for the 850 nm window

A. For the length 850 nm a GaAIAs/GaAs diode, double heterostructure, Burrus structure with active region on the solder side was tested. The lens is attached on the top of the die with silicone glue. After a wafer selection all diodes are screened after 100 ·C burn-in during 21 days at 100 mAo Those devices are encapsulated in a hermetic package with a glass window without pigtail and integrated in an active duplexer(bidirectional integrated coupler) by combination of LED, PIN and optical connector.

The structure is described in figure 1

n , , , '.

n .... ---

n (MAI .... (s.)

Figure 1

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B. Another type of double heterostructure using a dome diode was investigated due to the high optical power available. (fig. 2)

Figure 2

C. A third type of double heterostructure, buried localisation layer, mounted junction side up was tested without lens on the die. (fig. 3)

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D. A single heterostructure diode, buried localisation layer, mounted junction side up was also tested.

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2.1. LABORATORY TESTS

The two main parameters interferring with reliability are temperature and current conditions.

Temperature and related activation energies is commonly used to accelerate degradation, that is why 4 values were chosen 20, 70,100 and 125° C (ambiant temperature).

Two sets of diodes were put on test at 50 mA or 100 mA (aging conditions). Measurements at typical use condition (100 mA) and low current condition (2 mA) were made on each device in order to reveal more sensible variations.

Based on thermal resistance it is possible to know the junction temperature which corresponds to an increase of temperature of 22° C at 50 mA and 45° C at 100 mA for instance for the first manufacturer.

2.2. RESULTS

Measurements on each device during the test were performed on different batches having specific test conditions based on a combination of temperature and aging current. The main parameter for those devices is the radiant power measured from time to time at room temperature using an integrater sphere.

Two categories of presentation have been used:

- the variation of optical power with time for each individual device (the dotted lines are measurements for a current of 2 mA, the full lines at 100 mA),

- for an individual diode and at the measurement times, the variation of optical power with forward current and voltage and also reverse characteristics.

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It can be seen from the curves that both temperature and direct aging current have an effect on the degradation of the radiant power. The evolution is gradual, showing a more sensitive drift on measurements at low current level (2 rnA) compared to typical current (100 rnA).

For the same aging current 100 rnA the degradation is accelerated by temperature (see fig. 5, 6, 7) and at a fixed temperature 100°C the degradation is accelerated by the aging current, seen by comparison between fig 7 and 8.

For the same junction temperature the degradation is higher for a higher aging current by comparison between fig 7 and 9 (same junction temperature 145°C).

From the individual variation we can see that a group degradation is observed plus some devices having a higher degradation detectable after an aging time which can be greater than several thousand hours. This indicates the effectiveness of a burn-in for screening purpose, the most sensitive parameter beeing the measure of radiation power at 2 rnA.

An "acceleration factor" of about 10 on aging time gives a good correlation between observation of radiant power drift measured at low current at time T compared to the drift on normal use conditions at time 10xT.

When considering the results observed on the diodes from the manufacturer A more details can be seen on the degradation through observation of other parameters (fig 10) on individual diodes.

As an example iP = f(Vf) do not indicate any variation while iP = f(If) and If = f(Vf) indicate a non radiative current increase due to active interface defects affecting more the characteristics at low current level (fig. 11). The same amplified phenomena can be observed on diodes submitted to higher temperature stresses (lOO°C compared to 20°C) (fig. 12). This is the mechanism affecting the global population.

A failure analysis (see photos) was made on those diodes having an erratic behaviour. It can be observed that corrosion under the lens explains the degradation of parameters. The same analysis made on "better" diodes shows the start of the same phenomena. The analysis of the silicone glue used to attach the lens revealed that acetic anhydrid is present in the case of diodes and dissapears with aging time.

The failure mechanism seems to come from acetic acid in the silicone glue used during the process of manufacturing.

The same kind of aging test was conducted on another manufacturer B giving quite stable variations for several thousands hours at "normal" use conditions (SO rnA, 20°C) (fig 13).

At higher temperature (70°C) (fig. 14) for the same aging current the variations show more disturbances due to high stress temperatures, even if 70°C is not so high compared to 100°C and 125°C for the first manufacturer. The activation energy for those diodes is higher. The influence of current is put on evidence on fig. 15 to be compared to fig 13.

A remark can be made at this step. If a standard has to be prepared in order to evaluate the behaviour of the diodes and a possible qualification through accelerated test, the habit (rule, fashion ... ) used in many standards is to choice a 125°C test (why 125°C ? because it is often found in standards and reciprocally !!)

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The choice for the best manufacturer based on accelerated test should certainly be A even if at "normal" temperature 20·C the behaviours of A and B are quite similar.

Observation of aged devices indicated a degradation due to well known phenomena for those devices which is the dark line defect affecting the efficiency of diodes. (see photos).

The variation between A and B is due to different failure mechanisms corresponding to different physical origin. A conclusion at this step is that we cannot use the same accelerated conditions (temperature and aging current) to predict the real behaviour in use conditions. Another manufacturer C was tested at 100 rnA aging current and two different temperatures 70°C and 125°C. Compared to the manufacturer A for the same test condition those diodes look more stable, and the influence of temperature is less (fig. 17 compared to fig. 16). Even at this high stress (100 rnA - 125°C) the variations are lower than observed on manufacturer B (see fig. 14).

In fact different batches from different wafers were put on test and we can see a significant variation from one (fig 16) to the other (fig. 18) corresponding to the same test conditions.

That means, even for a technology and a manufacturer, that the wafer selection is important. The quality level for a manufacturer will be related to his criteria used to decide about the rejection of a wafer if a portion of diodes taken as a sample will exceed a specific requirement on the power drift during a burn-in test. Observation on diodes from this manufacturer showed some dark lines on the die, but without affecting the optical power. (see photos)

The photo technology D was also tested at different conditions. In order to reveal the influence of the lens, tests on components with or without lens were conducted at different test conditions.

Without lens, the influence of current at normal temperature cannot be detected. The "improving" of diodes is the same. Only one failure (catastrophic failure) occured after 2 thousands hours, the reaction would be to prove the influence of current on reliability, it is better not to reach this step.

The non influence of the lens is seen by comparison between fig. 19 and fig. 21 corresponding to the same aging conditions. On this manufacturer we can see a good stabilisation of optical power with or without lens in opposition to the first manufacturer where the main cause of degradation was due not directly to the lens but due to the glue used to attach the lens. Is it to conclude that the reliability is dependent more on the glue than on the semiconductor?

It seems when comparing fig. 21 and fig 22 that temperature has some influence on the behaviour of diodes. Problems we had on those diodes are in fact not detectable on curves, those diodes were rejected for bad encapsulation!

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B

- 00

Papl.,. 100000 H

..... --- /

------ .... ~ ..... , ~ ---........ ~-- .. --- ........ --..-:.. ....... ~ ...

---\

\ \

\ \

\ \

100 H

Fig. 18

\ \

... \

\ " .....

• I • "I 1000 H

--- \ \ \

'" "'\",- .. , B

I • • III ..

10000 H

MANUF.C

17

.100000 H

I I • I I III

.100000 H

Page 27: Semiconductor Device Reliability
Page 28: Semiconductor Device Reliability

19

100 MA - 25 C

%P ~ 100 mol.

XP" 211l4 _______ -o

OX

X 26

o 27

+ 28

-50 XV 29

.. 30

Y 31

@ 32

8 33

-100

100 H 1000 H 10000 H 100000 H

Fig. 21 MANUF. D with lens

100 Mol. - 70 C

X 42

o 43

+ 44

-50 S V 45 - 5

If 46

Y 47

iii 48

B 49

.100 H 1000 H :lOOOO H .100000 H

Fig. 22 MANUF. D with lens

Page 29: Semiconductor Device Reliability

20

3. Components for the 1300 nm window

The technology for different tested eomponents is quite similar, double heterostructure on InP, active region on the solder side. (fig. 23)

Au-O.-NI I I , Inp su~str.t n

Inp I n

np • Au

L..AII...I

Figure 23

RESULTS

Four manufacturers were tested.

For the manufacturer A, for quite severe conditions, we can see that the optical power is quite stable, even if important variations of the power measured at low current (2 rnA) indicate a possible degradation in the future (see figure 24). The measurement at low current is an amplification of what can be expected for high current, with an acceleration factor higher than observed on 850 nm diode (manufacturer A). Another test was also eonducted at less severe conditions (fig. 25) indicating a more stable optical power at 100 rnA and by the same way the influence of stress eonditions. But the erratic behaviour of diodes measured at 2 rnA make difficult any extrapolation nicely seen on fig. 24. Details on a specific diode can be seen on fig. 26.

The failure mechanism which was revealed is gold electrodiffusion and accumulation in the active region. (see photos)

For the manufacturer B we have also stable optical power (see fig. 27).

The influence of temperature (fig. 28 to compare to fig. 27) is not very important. It can be noticed than failures occur after a very long duration (more than one year), which indicate the limitation of burn-in possibilities (or the beginning of wear out !)

At 4500 hours a sudden variation (- 20 %) of optical power was observed. The failure was due to the glue used to mount the die in the case. (see photos)

In fact this glue caused a short circuit on the device causing this failure which was recovered by eliminating the extra glue. This is again, a failure which has nothing to do directly with the structure of the diode.

Page 30: Semiconductor Device Reliability

OS

"p il 100 mA

li:P II 2 mA

x

a 10

+ 11

-50 S V 12

If 17

y

iii

8

\ \

JOO H

, \ I

200 HA - 100 C I I I I I

JOOO H

Fig. 24 MANUF.A

\ 100 MA - 70 C \

%P il 100 mA \

"P!! 2 lilA \,~---, "\ "

OS

X 50

a 51

+ 52

-50 SV 53

If 54

y

8

- 00

JOO H JOOO H

Fig. 25 MANUF.A

21

- 6

JOOOO H JOOOOO H

- 5

JOOOO H JOOOOO H

Page 31: Semiconductor Device Reliability

22

p p

UI till

tul

Vf If

.5V tV !.!IV tOUA

If Vr Ir

tOO

10 uA

SuA

100

No 17 I 200 MA - 100 C

X o H • !IOOO H 0 50 H B 8000 H

Vf + 200 H * 10000 H V 700 H S 12000 H M 1000 H ~

SV UV ~ y 2000 H H

Fig. 26 : MANUF. A

Page 32: Semiconductor Device Reliability

23

MANUF.A

Page 33: Semiconductor Device Reliability

24

Page 34: Semiconductor Device Reliability

25

MANUF.B

Page 35: Semiconductor Device Reliability

26

For the manufacturer C we can see a very stable power on the fig. 29.

For the manufacturer D even if the variations are more important, (fig. 30) they stay in a range giving good expectation for the future, even if the time duration for those devices do not reach experience already accumulated on 850 nm diodes. Some diodes from this manufacturer were put on test without lens (fig. 31) in order to try to characterize the semiconductor itself (intrinsic reliability).

In general the behaviour of 1300 nm diodes compared to 850 nm seems better and we can expect to have better reliability results.

When the costs will reduce (due to quantities) they will be well adaptated to our broadband networks.

4. Conclusion

A general conclusion is that... it is impossible to have general conclusion on requirements to be put in a general specification.

The same accelerated conditions cannot be applied to different components, due to different activation energies and due to different mechanisms of degradation.

For a specific component (technology and manufacture) an accelerated test can be a way to select good wafers. The burn-in can be useful to reject abnormal components but it can be costly due to the fact that a long duration is often needed to reveal the weak components (sometimes several thousand hours).

The goal of laboratory tests is to evaluate the quality and reliability of components (not to produce nice curves obtained from mathematics), to reveal the weak point(s) in a technology and to find the basis for improvement.

The need for burn-in has to be based on the behaviour of a manufacturing process for a specific manufacturer. The efficiency of such a burn-in is determined on real experience, it can be costly and needs a long time to reveal weak components.

Variations from lot to lot, from a manufacturer to another make that a permanent view on the quality is necessary. General extrapolation is hazardous as well as reliability predictions based on accelerated laboratory test.

Experience and investigation can give the possibility for a user to make the best choice.

Acknowledgements

Those results are only a part of all experience accumulated in CNET on LED. Preparing aging positions, measuring devices and interpretation of results as well as failure analysis required the assistance from more people than referred in the author list. Thanks have also to given to J. MARTRET, M. OLLIVIER, M. DONTENWILLE, C. BOIS ROBERT, C. PATRAC, D. RIVIERE ... and those manufacturers who provided the facility to have a better knowledge of technology and so help in the interpretation of degradation mechanisms.

Page 36: Semiconductor Device Reliability

27

70e - 100mA

XP II 100 mA

XP Il 2 m4

o ~ - eC-", o J

x 1

0 2

+ 3

-50 ~ V 4 - 50

.. 5

Y

II 7

8 8

Pap ".,. 100000 H 100 H 1000 H 10000 H 100000 H

Fig. 29 MANUF. C

BOmA - 70e

~P II 100 rnA

o ~ o ~

X 309

o 315

+ 414

-50 X V 419 .... - 50 ....

.... .. 420 y

Y 11

III 12

8

-100

Papl.,. 100000 H 100 H 1000 H 10000 H 100000 H

Fig. 30 MANUF. D

Page 37: Semiconductor Device Reliability

28

o ~

SP II 100 mA

SP II 2 mA

X 104

o 109

+ 112

-50 )\ V 206

-100

IE 211

Y 312

II 301

B 311

80 mA - 70 aC

100 H 1000 H 10000 H 100000 H

Fig. 31 MANUF. D

Page 38: Semiconductor Device Reliability

AN HISTORICAL PERSPECTIVE OF GaAs MESFET RELIABILITY WORK AT PLESSEY

James Turner and Rodney Conlon Plessey Research Caswell Limited, Allen Clark Research Centre, Caswell, Towcester, Northants. England.

ABSTRACT. Gallium Arsenide MESFET fabrication technology has become more and more sophisticated and this has led to a marked improvement in device reliability. This paper charts the progress of MESFET life tests at Plessey Research Caswell Limited and shows how by adopting new fabrication techniques the MTTF of the device has been improved by four orders of magnitude.

L INTRODUCTION

This paper reviews some of the life test programmes carried out at Plessey Research since 1975 and shows how the results of the tests nave influenced the meta11isations and geometries used by Plessey for both ohmic and rectifying contacts to small signal and high power GaAs MESFETs.

The life testing programmes reviewed here are representative of many performed at Plessey:

(a) Small signal 1.0 micron gate length MESFETs (1975) (b) Power 1.0 micron gate length MESFETs (1978) (c) Electron beam processed 0.3 micron gate length MESFETs (1984) (d) Ion implanted 0.7 micron gate length MESFETs (1988).

2. SMALL SIGNAL 1.0 MICRON GATE LENGTH MESFETs (1975)

In this programme a number of X-band devices with two different ohmic metallisation systems were stress tested:

(1) indium/gold/germanium (In/Au/Ge); (2) nickel/gold/germanium (Ni/Au/Ge).

The devices had a passivation layer of silicon monoxide covering the channel area and parts of the drain and source contacts.

The tests performed included reverse biasing of the gate diode at an elevated ambient temperature, thermal cycling from -65 to +15QoC, AC modulation of the drain current by application of gate volts to

29

.1. Christou and B. A. Unger (eds.), Semiconductor Device Reliabilily, 29-42. <l 1990 Kluwer Academic Publishers.

Page 39: Semiconductor Device Reliability

30

• turn the device on and off, and high-temperature DC and RF tests. The major failure mode identified was ohmic contact migration.

Metal migration, the current induced transport of material, appears to have been first correctly identified as a potential cause of failures in microcircui t interconnection around 1965 [I]. Since then there has been a lot of work done on identi fying the causes of migration and evaluating preventive measures. Without question, at some elevated temperature metal migration effects can be observed in all semiconductor devices - what is important is to determine the conditions under which this occurs in the GaAs MESFET. These results show that metal migration does indeed occur but only noticeably at channel temperatures around 250°C and so does not represent a serious hazard to high reliability usage.

In order to accelerate the migration and shorten the time to failure, the GaAs MESFETs were subjected to DC biasing at an ambient temperature of 200°C (i.e. approximately 250°C junction temperature). The devices were run at +5V drain bias with the gate grounded, giving a current density of about 105 A/cm 2 . Under these conditions migra­tion effects were observed on all devices tested within 1000 h. Following the initial observation of metal migration, further experi­ments were carried out to assess the effect of contact shape on the time to failure.

Figure 1 DEPLETION AND ACCUMULATION OF In/Au/Ge CONTACT MATERIAL AFTER TEMPERATURE STRESSING

With In/Au/Ge ohmic contacts the combination of time, temperature, and current caused material to accumulate at the edge of the source contact adjacent to the etched channel, and to deplete the drain contact at a similar place. Fig. 1, with the source on the right and drain on the left, illustrates this effect. Microprobe analysis confirmed that the accumulated material was that of the ohmic contact. It is not believed, though, that the material crosses the gate region,

Page 40: Semiconductor Device Reliability

31

but that it moves across the contact from t.he source bond wire towards the edge of the source contact, and from the edge of the drain contact to the drain bond wire. This direction of material transport is the same as that of electron flow, and thus agrees with present explana­tions of migration [2]. Nodules of mate rial have been seen on the drain bond wire which were not present when the devices were put on test (Fig. 2).

(a) (b)

Figure 2 ACCUMULATION OF OHMIC CONTACT ALLOY ON BOND WIRE TO GaAs MESFET

lal Initial state of bond wire

IbI Nodule formation after life test

For the Nil Au/Ge system the primary effect under high temperature stress was the "balling" of the metallisation causing increased contact resistance. Heime et a1 [3] observed a similar effect when alloying the contact, but found that evaporation of a thin nickel layer on top of the Au/Ge before alloying could reduce the balling. In the devices tested there was no evidence of balling after alloying; this only appeared after high temperature testing. The increased contact resistance during the life test n!duced the drain current and transconductance and led to a general deterioration in microwave performance.

2.1. Effect of ohmic contact shape

Three ohmic contact shapes were examined - T-shaped, triangular and rectangular - to evaluate their effect on the time to failure. It was found that the accumulation rate, depletion rate, and the positions of accumulation and depletion were all affected by contact shape. Thermal profiling with a nematic liquid crystal [4] showed that these differences were caused by localised hot spots due to current crowding in the contact. The positions of these hot spots were also affected by the "heat-sinking" effect of the bonds. The migration rate was slowest for the rectangular and fastest for the T-shaped contact.

Page 41: Semiconductor Device Reliability

32

Migration occurred mainly at the narrow ends of the T-shaped contacts, at the apex of the triangular contacts, and was distributed evenly along the edge of the rectangular contacts.

2.2. Conclusions and Recommendations

In small-signal GaAs MESFETs produced at this time the dominant failure mode was metal migration of the ohmic contact. Reduction of this high temperature effect can be accomplished in several ways. The current densi ty can be reduced by making the metallisation thicker, but due to limits imposed by the float-off process used to define the metal areas, plating up of the contacts is necessary to achieve maxi­mum effect. The contact shape, also influences the migration. Rectangular contacts give the most uniform distribution of current and therefore are the most promising. As the migration is dependent on surface temperature, improvements in mounting techniques to reduce the thermal impedance could aiso give improvements in reliability. To obtain the optimum noise performance from the GaAs MESFET, it is necessary to bias them at low drain currents. This is beneficial to the device lifetime as it reduces both the current density and channel temperature.

These life test resul ts on small-signal MESFETs with In/ Au/Ge ohmic contacts gave a room temperature mean time to failure in excess of 107 h. This compares with the only other published data for GaAs MESFETs at the time of 106 h [S]. This MTTF is in excess of that required for most high reliability applications; devices fabricated in this way have already undergone successful qualification for space flight use [6].

These recommendations were implemented by Plessey and all devices in the following life test programmes incorporated.

(a) Rectangular contacts with rounded corners. (b) Plated up source and drain contact areas to a thickness of 3

microns. (c) Improved thermal impedance.

3. POWER MESFETs WITH 1.0 MICRON GATE LENGTH (1978)

In this programme both step stress and constant temperature stress life tests were carried out on 84 devices biased at a drain source vol tage of 9V wi th drain currents ranging from 100-200 rnA and at ambient temperatures between 130°C and 18Soc. In the tests the devices had In/Au/Ge ohmic contacts and an aluminium gate electrode. The effect of gold and aluminium bond wires to the gate bond pad were investigated. Using a nematic liquid crystal technique the channel temperature of the devices under test was set at 4SoC above ambient by controlling the drain current of each transistor. The tests were conducted in a dry nitrogen environment but the devices were not passivated.

Page 42: Semiconductor Device Reliability

33

3.1. Constant Stress Tests

Three batches of gold gate wired devices and two batches of Al gate wired devices each containing twelve transistors were mounted in alumina microstrip test fixtures and were constant stress tested at 9V under the temperature conditions shown in Table 1.

In all cases the devices failed due to a greater than 10% reduc­tion in transconductance caused by the formation of voids in one or more of the gate 'fingers'. The presence of the voids prevented that section of the channel current from -being modulated by the applied gate voltage. A secondary effect was that of drain ohmic contact migration but this was relatively minor and is believed to have had no effect on the DC degradation observed. The gate voids observed are shown in Figure 3.

Figure 3 GATE VOIDS FORMED DURING LIFE TESTING

Prior to the commencement of the tests it was expected that the devices with gold wire bonds to the gate would fail much more quickly due to the enhancing effect of gold/aluminium intermetallic alloy formation at the bond Wire/gate metallisation interface. This proved not to be the case and Arrhenius plots of the failures gives MTTFs of 105 and 2 x 105 at 65°C channel temperature for gold and aluminium bonded devices respectively. Independent measurements of gate current on similar devices showed that values as high as 300~ could be reached for the highest temperature constant stress test. This corresponds to a current density of 8 x 10 3 A cm- 2 in the 0.3 micron thick, '1 micron long gate metallisation. This current is sufficiently high to cause 'straightforward' electromigration of the gate metalli­sation. Examination of the grain structure of the aluminium gate metal showed it to be particularly small and therefore more prone to

Page 43: Semiconductor Device Reliability

34

electromigration effects. The activation energy for the voiding process was determined from Arrhenius plots to be 0.67 eV.

3.2. Conclusions and recommendations

This series of tests left many questions unanswered such as;

(a) the extent to which electromigration is enhanced by the gold concentration in the Au/AI interaction.

(b) the distance over which the Au/AI interaction can influence electromigration of AI.

(c) the effect of GaAs substrates, grain structure and geometry on the electromigration of AI.

It also prompted Plessey to modify its gate metallurgy and to incor­porate a silicon nitride dielectric passivation layer in the channel region of the FET. The combination of these two modifications led to a greatly reduced gate leakage current. These changes were incorpora­ted in the life tests reported in the following section (section 4).

4. ELECTRON BEAM 0.3 MICRON GATE LENGTH MESFETs (1984)

In this test small signal devices with gate lengths of 0.3 micron were mounted in microstrip test fixtures and subjected to elevated tempera­ture life tests. During the test both DC and RF performance was monitored. The devices had titanium/aluminium gate metallisation and In/Au/Ge ohmic contacts. The ohmic contact areas had additional gold based metallisation in order to locally reduce the current density in the ohmic contacts to minimise the susceptibility to metal migration. As in previous tests some samples had aluminium bond wires to the gate, others gold wires. Tests were carried out at junction tempera­tures of 165°C, 192°C and 220°C and, apart from one device (out of a total of 30) which showed some sign of metal migration of the ohmic contact, there was no visible sign of failure. In these tests failure was defined as a 10% change in DC characteristics or a 1 dB change in noise figure or gain at 14 GHz.

There was no apparent correlation between changes in DC current and RF insertion gain, 15211 but there is a strong correlation between changes in transconductance particularly at high gate bias (close to pinch off) and 15211. It was therefore concluded that the observed changes in both DC and RF performance were due to a change in the electrical parameters of the channel. This change in channel properties was examined further by examining the change in transcon­ductance at zero gate volts and close to pinch off. The results indicate a greater change at zero vol ts than at large negative gate voltages perhaps indicating a general degradation at the surface (Figure 4).

From these tests an activation energy of 1.0 eV was deduced leading to an MTTF of 3.5 x 105 hrs at 70°C.

Page 44: Semiconductor Device Reliability

iii 0

..c: E E ., " c: 5 " :::I .., c: 0

" .. c: ~ ~

40 Start of life test

35

After 1143 hrs

30

25

20

15

10

5

OL-~~~-L-L-L~~~

- 1.8 - 1.4 - 1.0 - 0.6 - 0.2 0 Gate Voltage (volts)

Figure 4 VARIATION OF TRANSCONDUCTANCE WITH GATE VOLTAGE BEFORE AND AFTER LIFE TEST

4.1. Conclusions and recommendations

35

Whilst there was no obvious difference in life between the aluminium and gold gate wire bonded devices it was realised that the practice of using aluminium for gates and gold for source and drain bonding was not cost effective and could eventually lead to reliability problems. For the life tests described in Section '5 the gate metallisation was changed to Ti/Pt/Au, a metallisation system used by Plessey in its MMIC process since 1982. All of the other previously recommended geometry and process changes were also incorporated into the life tested devices.

5. ION IMPLANTED DEVICES (1988)

The latest set of life test data has heen obtained as part of the ESPRIT 1270 programme. In these tests devices with Ti/Pt/Au gates and In/Au/Ge ohmic contact fabricated in the Plessey GaAs IC Foundry were subjected to temperature accelerated tests at 220°C and 250°C ambient under DC bias. The devices tested were part of the process control monitor chip and had gate lengths of 1 and 5 microns.

Page 45: Semiconductor Device Reliability

36

40

o

CI) CI) c 80

.5 Q>

'" c 60 «I ~

" "# 40

0

1000

-. -------. 220°C

2000 Time (hrsl

3000

51!m MESFET

4000

-·~2200C

11!m MESFET

0---______ 0 250°C

1000 2000 Time (hrsl

3000 4000

Figure 5 VARIATION OF lOSS FOR 51!m AND 11!m ION IMPLANTED MESFET DURING ACCELERATED LIFE TESTING AT 220 DC

The general trend in these characteristics for both l~m and 5~m

devices was of decreasing current with time being most pronounced for the shorter gate length devices. These changes were confirmed by the periodic measurement of all devices at room temperature. For both the 250°C and 220°C tests the mean change in I DSS has been plotted in Figure 5. Accompanying these changes were reductions in pinch off voltage and drain-gate breakdown voltage. Only small changes in contact resistance were observed for both tests (see Figure 6) although there was a greater change at the higher temperature as might De expecteu.

Page 46: Semiconductor Device Reliability

50

u 40 a: .E

30 G> c:n c: 20 ca o 250°C .c: ... _220°C

~ 10 • 0

2000 3000 4000 Time (hrs)

Figure 6 VARIATION OF CONTACT RESISTANCE DURING ACCELERATED LIFE TESTING AT 220 DC AND 250°C

37

Although detailed failure analysis has not yet been carried out on degraded devices, other workers have attributed such parameter changes to gate metal interdiffusion (gate-sinking) causing shrinkage of the effective channel thickness.

Referring to Figure 5 and applying a failure criterion of 20% reduction in I DSS then from the 220°C test the mean time to failure is approximately 4000 hours for both the l~m and 5~m device. Assuming an acti vation energy of 1. 6 eV, a value generally accepted for the above failure mechanism, results in a predicted median lifetime of 1 x 107 hours at 150°C operating temperature or 5 K 109 hours at 100°C.

5.1. Channel Temperature Estimation

The above reliability testing was carried out with the baseplate temperature controlled to 220°C or 250"C. To evaluate the true channel temperature under such conditions and establish the detailed temperature distribution over the MESFET surface, a small programme of work has been undertaken with the University of Birmingham, UK. Based on a combination of infra-red thermal imaging and numerical simulation, the channel temperature of the l~m and 5~m test FETs has been estimated. An example of the surface temperature distribution for the 250°C baseplate condition is seen in Figure 7 which predicts a peak channel temperature of 289°C for the l~m FET and 274°C for the 5~m device. These therefore are the true channel temperatures applicable for the life test described above.

Page 47: Semiconductor Device Reliability

38

290

280

270

290

280

270

XV axes in millimetres

Z axes temperature °c

Figure 7 SURFACE TEMPERATURE SIMULATION WITH 250°C BASE

6. SUMMARY

This paper has followed the progress of a number of Plessey reliability programmes since 1975. It has shown how detailed failure analysis has led to a continual improvement in life expectancy of the transistors by removing the obvious short comings in geometry and process technology exposed by the life tests.

Table 2 summarises all these results and shows how the MTTF of the Plessey device has been increased by 3.5 orders of magnitude since the testing began in 1975. Table 3 shows the technology changes that improved device lifetime.

Progress has been such that gate voiding and ohmic contact migra­tion are now no longer major failure modes but that device life is limited by degradation of the electrical properties in the channel. Failure analysis on the recently tested ion implanted devices coupled with the fabrication of special test structures could well help to suggest ways of reduc Lng this ef fec t thereby further improving the reliability of the GaAs MESFET.

7. ACKNOWLEDGEMENTS

This paper is a compilation of the efforts of many Plessey workers over the past 14 years and the authors would like to acknowledge the help gained from reviewing their past reports and published papers. Support for the reliability programmes came from a number of sources -the European Space Agency, the Procurement Executive Ministry of Defence (Directorate of Components, Valves and Devices), the sponsor-

Page 48: Semiconductor Device Reliability

39

ship and technical direction of INTELSAT and the European Commission (ESPRIT 1270). The support of the Plessey Company pIc is also acknow­ledged.

8. REFERENCES

l. Blech, I.A. et aI, R.A.D.C., Griffiss A.F.B., NY, Tech. Rept. TR-66-31 (Dec. 1965).

2. Black, J. R., "'Electromigrat.ion - A brief survey and some recent results"' IEEE Trans. ED, Vol. ED-16, pp.338-347, 1969.

3. Heime, K. et aI, Solid State Electronics, Vol. 17, 835-847, 1974.

4. Stephens, C.E. and Sinnadurai, E.N., Journal of Physics E: Scientific Instruments, Vol. 7, 1974.

5. Wireless World, June 1975, p.271. 6. James, D.S. et aI, Proceedings of 19"75 European Microwave Conf-,

Montreux Switzerland. 7. Roesch, W.J. and Peters, M.F., Proceedings of the GaAs IC

Symposium, p.27-30, 1987.

Page 49: Semiconductor Device Reliability

t;

TABL

E 1;

L

ife

test

tem

per

atu

res

for

Ple

ssey

1

.0 m

icro

n

pow

er

MES

FETs

Tes

t A

mbi

ent

Tem

p.

Ch

ann

el

Tem

p.

Ch

ann

el

Tem

p.

i (0

C)

Ris

e T

(O

C)

T

(OC

)

Au

gate

w

ires

T1

15

0 ±

3

45

195

±

3 I

T2

140

±

3 45

18

5 ±

3

T3

117

±

3 40

15

7 ±

3

Al

gate

w

ires

T4

20

0 ±

3

45

245

±

3 T5

17

0 ±

3

55

225

±

3 --

----

---

--

Page 50: Semiconductor Device Reliability

TABL

E 2:

P

rin

cip

al

fail

ure

m

odes

an

d M

TTFs

o

f P

less

ey

MES

FETs

Gat

e le

ng

th A

cti

vati

on

en

erg

y M

TTF

at

150°

C

Dev

ices

T

este

d

of

fail

ure

m

ode

chan

nel

te

mp

. P

rin

cip

al

Fail

ure

Mod

e D

ate

(mic

ron

s)

(eV

) (h

rs)

Sm

all

sig

nal

dev

ice

1.0

1

.0

2 x

103

Ohm

ic

co

nta

ct

mig

rati

on

19

75

(Ple

ssey

)

Pow

er

dev

ice

1.0

0

.67

4

x 10

3 V

oid

s in

gate

met

al

1978

(P

less

ey

)

E-b

eam

d

evic

e 0

.3

1.0

3

x 1

04

Cha

nges

in

ch

ann

el

(Ple

ssey

) p

aram

eter

s 19

84

Pow

er

dev

ice

1.0

1

.0

5 x

104

Cha

nges

in

ch

ann

el

(Ple

ssey

) p

aram

eter

s 19

86

Sm

all

sig

nal

ion

0

.7

1.6

1

x 10

7 C

hang

es

in

chan

nel

im

pla

nte

d

dev

ice

par

amet

ers

1988

(P

less

ey

)

Sm

all

sig

nal

ion

1

.0

1.6

1

x 10

7 C

hang

e in

ch

ann

el

imp

lan

ted

d

ev

ice

par

amet

ers

-(T

riq

uin

t -

[7 ]

) 'g

ate

si

nk

ing

' 19

87

-_

.-

;t

Page 51: Semiconductor Device Reliability

i!3

TABL

E 3:

Su

mm

ary

of

tech

no

log

ies

use

d

in P

less

ey M

ESFE

T li

fe te

sts

MES

FETs

te

sted

G

ate

len

gth

O

hmic

G

ate

Pass

ivati

on

Co

nta

ct

MTT

F at

ISO

°C

(mic

ron

s)

meta

llis

ati

on

meta

llis

ati

on

die

lectr

ic

ov

erl

ay

s ch

ann

el

tem

p (h

rs)

Sm

all

sig

nal

dev

ices

1.0

In

/Au

/Ge

Al

No

No

2 x

103

Pow

er

dev

ice

1.0

In

/Au

/Ge

Al

No

Yes

4

x 10

3

E-b

eam

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Page 52: Semiconductor Device Reliability

Screening and burn-in: application to optoelectronic device selection for high-reliability S 280 optical submarine repeaters

M. GUEGUEN, J. L. SOUSSOIS, J. L. GOUDARD and D. SAUVAGE Alcatel CIT, Centre de Villarceaux, Route de Vil/ejust-Nozay BP 6, 91620 LA VILLE-OU-BOIS, FRANCE

After reiterating the reliability objectives of such equipment in a special link such as EMOS and the respective allowances made for transmit and receive components, and a overview of the consolidated reliability data obtained on these components, the emphasis will be put on the resulting selection procedures that have been chosen after an optimisation and validation phase. The practical application of these procedures in supplies for the EMOS link shall be described in particular detail.

In conclusion, even if a few uncertainties remain with regard to demonstration, the ATe reliability assurance programme for submarine optoelectronic components shows that these sensitive components satisfy the reliability requirements of the ori~linal Submarcom S 280 system.

43

A. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 43-73. © 1990 Kluwer Academic Publishers.

Page 53: Semiconductor Device Reliability

44

I. Introduction

The rapid commercial success of optical fibre submarine systems with links already brought into seIVice such as Alcatel Submarcom S 280 French mainland-Corsica III, Rome-Sardinia and TAT 8, has called for a special effort at every level during the development stage to meet the stringent reliability objectives that are required.

After reiterating the reliability objectives of such equipment as the future EMOS link that is in the manufacturing stage and the respective allowances made for the various components such as optoelectronic devices, we shall present the reliability data obtained on these particular components. This will enable us to consolidate reliability objectives that are, moreover, associated with the concept of complete qUality. On the basis of a number oftests conducted for their final qualification, the emphasis will be put on the resulting selection procedures that have been chosen. These procedures were defined using basic principles and pretested methods to select components used in analogue submarine equipment. Modifications were made to them in orderto take into account the special character of each component. The particular example of transmit components, laser diode emitter and receive components, PIN photodiode is illustrated, paying particular attention to the consistency of the total quality assurance system implemented right up to the final selection of the submersible components.

Needless to say, the selection procedures that have been chosen are the result of continuous optimization, validation, field experiments throughout the component manufacturing, inspection and utilization cycle.

The practical application of the procedures involves: • Process quality assurance with line inspection to control the crucial technological stages • The finished product quality assurance corresponding to the final selection destructive tests in order to verify the reliability level measured during qualification • Unitary selection to eliminate marginal parts using non-reliability, nonconfonnity and non­homogeneity criteria for each testable, sensitive basic component and fibred finished product that is specially developed for the EMOS contract.

II. Reminder of reliability objectives

The reliability requirement for a submarine optical system is generally a minimum lifetime during which a mean number of ship repairs is allowed due to component failures (this number is based upon a mathematical prediction). The link parameters that have a crucial influence on reliability perfonnance are the number of repeaters and the mean temperature.

From a reliability standpoint, S 280 repeater components can be classified into the following groups: • Components where the failure mechanism leads to a log nonnal distribution of the lifetime (estimators are mean time MTTF and standard deviation 0). In this group only the laser behaviour is predicted. • A group showing a constant failure rate behaviour (exponential law) which includes the photode­tectors, integrated circuits, SAW filters and the other passive components. • The switching devices for redundancy operation where we have to consider the probability of non­operation.

Page 54: Semiconductor Device Reliability

45

2.1 EMOS SYSTEM

2.1.1 Brief description The EMOS system is a submarine cable system linking Palenno (Italy) with Lechaina (Greece), Mannaris (Turkey) and Tel Aviv (Israel). The system includes three subsystems, each consisting of one fibre pair providing 2 x 139 264 kbit/s digital line sections: • One subsystem between Palenno and Lechaina • One subsystem between Palenno and Mannaris • One subsystem between Palenno and Tel Aviv

This configuration is shown in the diagram below (Figure 1). The geographical length of the submerged plant is approximately 2760 km.

Marmaris

Lechaina

Palermo

BU1

Key

D Cable station

Branching [!J unit Figure 1 - Schematic diagram of the EMOS-1 system

The EMOS 1 system is made with the Alcatel Submarcom S 280 system. It includes 46 repeaters as follows: • 12 repeaters housing three double regenerators (3S) • 13 repeaters housing two double regenerators (2S) ·21 repeaters housing one double regenerator (1S) and two branching units with a passive transmission path.

Each double regenerator is defined as the equipment required for signal regeneration in both transmission directions of a fibre pair and for its supervision.

The mean temperatures associated with each type of repeater are 32.2 °C (3S), 26.3 °C (2S) and 20.4 °C (IS) respectively.

Page 55: Semiconductor Device Reliability

46

2.1.2 EMOS system reliability objectives Reliability requirements for the EMOS system are as follows: • The system lifetime shall be at least 25 years • During this period, reliability shall be such that the expected number of mean ship repairs due to system component failures shall not be more than three.

In order to meet reliability requirements for EMOS, the MTBF of each double regenerator shall be greater than 700 years, meaning a FIT value ofless than 165 FITs.

Compared with a terrestrial system consisting of two single regenerators for example, this objective figure is more than fifty times greater, highlighting the reliability effort being made for this type of application.

2.2 RELIABILITY OBJECTIVES FOR EACH TYPE OF COMPONENT

In order to assign a separate reliability budget to each type of component, components are classified in the following categories: • Laser diodes • Transmitter packages • Optoelectronic receivers • "Critical" integrated circuits • SA W filters • Optical switches and dc motors • All other "critical" components such as resistors, capacitors or protection devices "Critical" components are those for which a failure causes a hard transmission fault if no redundancy is provided.

The failure of one supervisory device does not impair the operation of the whole line supervisory system for the other regenerators. Moreover, in this case fault location redundancy is provided by loopback and laser switchover operations. Supervisory devices are therefore not considered as critical components, though they have the same reliability level.

We shall reserve our comments to active optoelectronic component allocations. The allocations for the other categories will be summarized in Table I on the following page showing the reasonable objectives given to various components.

Laser diodes For this type of component, wear out phenomena are considered more frequent than random failures. These ageing mechanisms are temperature accelerable which has made it possible to characterize the component and establish basic data on lifetime duration. Results already obtained from tests carried out during characterization have enabled us to use the following values for the EMOS link that were standardized at 20°C, considered as a reasonable objective and obtained after component selection: • Mortality law: log normal distribution • Median lifetime MTTF (at 20°C/5 mW): 7.6 x 1()6 hours • Standard deviation a: 1.35 This results in 30 FITs in 25 years. • Activation energy: 0.9 eV

Page 56: Semiconductor Device Reliability

Components

Transmitter

package

Optical receiver

Integrated circuit

SAW filter

Switching device

Passive components

Approximate number per double regenerator

2

2

17

2

2

300

Table 1 • Component reliability objectives

47

Kind of failure distribution

Reliability obJectives

Log normal M = 7.6 x 106 hrs (20°C)

Exponential

Exponential

Exponential

ExpClne nti al

a = 1.35 (30 FITs in 25 years at 20°C)

10 FITs

1 FIT

0.63 FITs

5 FITs

Non-operating probability

Exponential

Exponential

10 FITs (common part not duplicated)

0.015 FITs

Page 57: Semiconductor Device Reliability

48

Transmitter package In addition to contributions derived from the reliability of the laser alone, experience already obtained leads us to say that two types of failure can be encountered in an optical transmitter package: • Rogue failures comprising standard sudden failures well known in semiconductors and failures' specific to the optical output such as fibre breakage and sudden misaligmnent between the fibre and the laser . • Gradual failure mechanisms associated with a gradual change in coupling efficiency. They can be treated as a drift failure mode that can be compared with the mode characterizing the laser wear out. However, according to the gradual change law with time and temperature, which exhibits a marked sublinearity, individual long-term ageing is expected in order to carry out very accurate selection and to eliminate all parts which show a drift incompatible with the allocated margin. We have therefore considered it reasonable only to use rogue failures to characterize the reliability of the emitter module with an allocation objective of 10 FITs.

Optoelectronic receiver In view of the highly reliable planar technology used with the receiver that closely resembles the silicon planar technology used in our analogue submarine transistors, we are very confident about having a similar rogue failure rate of less than 1 FIT. The tests that have been carried out and the results obtained showing that this hypothesis is valid are described below.

Optical switch The reliability figure must be estimated on the basis oftest results.

An operating test has been conducted on a representative 60 sample lot showing a 0.5 dB mean insertion loss without any loss variation above 0.05 dB after 200 operations. This corresponds to 1.2 x 104 operations without failure and a subsequent probability of non-operation of less than 10-4.

A fibre breakage phenomenon similar to the one in the optical transmitter can be encountered. Therefore a random failure rate of 10 FITs is allocated to the switch.

Applying these figures to EMOS repeaters fitted with a duplicated laser transmitter package, one mean ship repair is estimated for the submerged plant. This value is consistent with the contract and is on average three times better than the objective and consequently reveals the potential reliability margin taken on the link even if it is customary, without being contractual, to use the upper confidence level of 90% (see Figure 2).

III. Consolidated reliability data obtained with optoelectronic components

3.1 iNTRODUCTION

This data results from successive characterization and qualification tests carried out on these components since 1984 and that today are being completed with final product certification.

The test programme consists of short robustness tests (step stress technique) and long lifetime tests (isothermal tests) for characterization and standardized tests for qualification. This programme has been conducted for the two types of optoelectronic components in the following way using the

Page 58: Semiconductor Device Reliability

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Page 59: Semiconductor Device Reliability

50

separate technological variable method and by testing the finished component: • Studying the crystal, basic active component on test vehicle, submount support or in a hermetic package representative of the final configuration and enabling accelerated tests. This is the case with PIN IIJJV photodiode crystal (KDOl), the Ge 800 Ilm monitoring photodiode (ceramic on Kovar support transferred to a T08 package) and lasersubmount (Cu) using nitrogen chamber for reliability tests. • Studying the various assembly supports and techniques for a total quality plan analysing the materials and processes and validating every point of their construction and implementation. Moreover, this plan has made it possible to fix the sequence of manufacturing operations and to implement inspection and tests and a quality assurance process. • Studying the finished fibred component: - The laser emitter module subassembly comprising the laser on submount (BH 1.3 Ilm on Cu/ln), the monitoring photodiode on its ceramic/Kovar support and the metallized fibre for the direct coupling function with the laser (front holding point) and the optical output with regard to the package (rear holding point in the fibre feed-through tube and output pigtail structure). - The receiver module corresponding to the assembly of the detector in a hermetic KDOI package and the fibre soldered in its fibre holder, itself a testable item.

The purpose here is notto describe all the different test stages oTto provide detailed results and failure mechanisms encountered, but rather to provide a synthesis of basic reliability data that has been extracted and that have made it possible to position the reliability level obtained for these two sensitive components in relation to the objectives set.

Moreover, this basic data resulting from accelerated tests has been consolidated by the results of practical experience acquired when producing components used in commercial links that are or will soon be in service and whose budget will also be given.

3.2 EMITTER MODULE

3.2.1 Requirements The EMOS 1 system requires a pigtailed source including a laser diode capable of delivering an optical signal from an electrical modulation of its operating drive current at 280 Mbit/s, the specifications for the laser source and the pigtail being summarized in Figure 3.

3.2.2 Choice of technology The laser and pigtailed transmitter have already been described in detail [ref 1].

By way of a reminder, the laser diode is an InGaAsP/lnP buried heterostructure (BH), the monitoring photodetector a large germanium photodiode (800 Jlffi dia.) used in photovoltaic mode and the fibre pigtail a tapered and metallized single-mode fibre.

The BH laser has a very suitable structure for submarine systems and offers the following major advantages: • Its highly directive optical beam enables high coupling cfficiency • Thanks to a low threshold current, it operates on low electrical power and at high temperatures These characteristics have the following advantages in terms of reliability: - In normal operating conditions, the temperature is low and the associated lifetime is high

Page 60: Semiconductor Device Reliability

Characteristics

Laser source Wavelength in the full temperature range

Linear output power Half spectral width at one sigma Threshold current in the temperature range Optical noise level

Operating temperature range

Pigtailed laser Mean optical power Bias current for maximum output power allocated by the system design Modulation current Photodiode current at maximum output power Dark current for monitoring diode Output power variation within the temperature range 10 to 40·C at constant photodiode current Reliability allocation: Wear out failure rate (log normal distribution)

Random failure rate (exponential law)

Figure 3 • Laser source and pigtail requirements

Specifications

1310±20 nm

> S mW (laser) < 1.2 nm <SOmA < 30 dB up to 296 MHz and 20 dB above 10/40 ·C

>-0.7dBm

<90 mA' <30mA > 250 IlA <151J.A

Q< 10%

MTTF (20 ·C, 5 mW) s7.6106 h 30 FITs after 25 years

0= 1.35

A.b: 10 FITs

51

• Including the threshold current drift allocation for ageing (50% drift) and the modulation current at maximum optical output power.

Page 61: Semiconductor Device Reliability

52

-For screening, tests can be perfonned at high temperatures that increase the confidence level insofar as weeding out marginal and flawed parts is concerned • The BH laser chip can be soldered "p side up" preventing all catastrophic failure modes due to possible whisker growth

3.2.3 Consolidated emitter reliability data

a) Wear out failure contribution Two drift failure mechanisms that can be modelled and predicted and that can be classified as wear out failures, have been identified and characterized as follows: • Gradual degradation of the laser chip only evident through the increase in polarization current required for a given power on the front side • Gradual change in coupling efficiency characterizing the laser coupled to the glass fibre at the output of the package It shall be seen that with ageing, many thousands of testing hours are required in order to extrapolate in time and to distinguish between extrapolatable drifts and transient and measurement errors. Moreover, it can be noted that the monitoring photodetector did not show up any defects representative of wear out mechanisms. The latter have a negligible contribution since with a pessimistic activation energy of 0.6 e V, a nonnallog distribution with a high standard deviation «J = 2) and zero faults during reverse bias type tests at 125 °Cf}. V carried out on 60 parts during 5000 hours, the instantaneous failure rate after 25 years would be < 0.1 FIT (20°C).

Laser evolution data First lifetests have been perfonned on about 340 laser chips on submount of which 95 were screened according to the standard procedure (reference DI: "autoselection" level) and 245 were raw and unscreened and realized at the beginning of 1984 when the characterization stage started. They consist oftwo long-tenn isothennal tests (30°C and 60°C) at constant optical power output (3 m W). The main results obtained from data after a time lapse of 22000 operating hours ('" 2.4 years) are given in the table in Figure 4.

The table shows the main characteristics of log-nonnal distributions of lifetimes obtained for two ageing temperatures and three groups of lasers classified in several sub-populations compiled in December 1986. The lifetime is defined as the time when the drive current for each laser is increased to 1.5 times its initial value.

We may recall that the law describing the degradation kinetics in its useful part in relation to the wear out mechanism is of the tm type where m (med) = 0.7, ie. between 0.5 (favourable case) and 1.5.

Experimental results lead us to the following conclusions: • The minimum value obtained of 0.9 e V is taken as the activation energy value • A relation is established for the influence of power at least up to levels of 8 m W. A conservative factor of 0.8 has been used when going from 3 to 5 m W (useful power level).

The projected MTTF (mean time to failure) associated with an end of life criterion .-'11 .... /1_ of 50% at 20°C (standard temperature) and 5 m W of power are given in the same table in Figure 4 (last three columns). The accumulated failure rate corresponding to the various populations selected are shown in Figure 5. This figure clearly shows the effect of the screening severity level on the failure rate

Page 62: Semiconductor Device Reliability

Results Lifetest temperature Sub-population Batch

& type of lasers definition size Median time for MTTF

."" Standard 3mW dnlatlon

Name variation (hours)

Component hours (hour.)

60 DC All 130 7.510 3 2 5.510 4 A1

unscreenoo 6 Lasers with more 104 1.610 4 1.2 3.310 4

210 than 1600 hours A2

30 DC All 113 2 10 5 2.6 5.810 6 B1

unscreened 6 lasers with more 75 7.510 5 2.910 6 3.410 than 4.310 4 hours B2 1.65

All 95 3.210 4 5

01 2 2.310

60 DC 84 4 1.910 5 screened Levell 02 5.410 1.6

72 h1150 mAl80DC 74 , 5

& P (60 DC) over 4 mW Level 2 03 7.610 1.45 2.110

Level 3 80 6.810 ' 1.5 2.110 5 0'

6 58 1.0510 5 2.6 10 5 2.510 Level 4 05 1.35

Figure 4 • Laser lIfetest results

A (FITs)

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53

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(hours)

4 10 6 1120 5.410 5

2.410 6 530 1.1510 6

1.910 7 920 6.510 5

9.510 6 370 2.410 6

7 6 1.710 480 2.310

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30 6

7.610

III LASERS D 1 • LASERS D2 a LASERS D3 o LASERS D4

• LASERS D5

108 Time (h)

Figure 5 • Laser failure rate at 20 °C corresponding to different selection levels

Page 63: Semiconductor Device Reliability

54

Type of laser

Unscreened

Screened (72 hl150 mAl80 °C P max (60°C) > 4 mW)

Llfetest temperature

Figure 6 - Laser lifetests and sub-population definitions

Sub-population definition

A1 - P max (60°C) > 3 mW

A2 - P max (60°C) > 3 mW + lifetime> 1600 h

81 - P max (30°C) > 5 mW

81 - P max (30°C) > 5 mW + lifetime> 4.3104 h

01 - all

02 - .!lIth (150 mAl72 hl80 0c) < 20 mA P max (60°C) > 5 mW

.!ll/If (168 hl60 °C/3 mW) < 2%

03 - .!lIth (150 mAl72 h/80 0c) < 20 mA P max (60°C) > 7 mW

.!ll/If (168 hl60 °C/3 mW) < 2%

04 - Lllth (150 mAl72 h/80 °C) < 20 mA P max (60°C) > 5 mW

.!llf Ilf (336 h/60 °C/3 mW) < 2%

05 - .!lIth (150 mAl72 h/80 °C) < 5 mA Pmax (60°C) > 7 mW

.!ll/If (336 h/60°C/3 mW) < 2%

versus time at 20°C for the various populations defined according to the specific criteria (Fig.6).

The following two scenarios have been chosen for comparison insofar as they correspond to the reliability objectives of two specific links, and have been used for the tests consolidating the initial results given in Table 2.

Page 64: Semiconductor Device Reliability

Median (20°C, 5 mW) = 5.5 x 106 hours

(1 = 1.45

I ~ 90 FITs in 25 years

I ~ MTTF = 1.6 x 107 hours , or A. (25 years) = 0.9% ~ (accumulated failure rate)

Median (20°C, 5 mW) = 7.6 x 106 hours

(1 = 1.35

~ 30 FITs in 25 years ~ MTTF = 1.84 x 107 hours or A. (25 years) = 0.3% (accumulated failure rate)

Table 2 - Initial test results

Selection level D3 "TAT 8"

dlth (80 °Cf150 mN72 h) < 15 rnA dl/I, (3 mWf60 °Cf168 h) < 2%

Ith < 50 rnA (20°C) P max (60°C) > 5 mW

Selection level D5 (level 4) "EMOS"

dlth (80 °Cf150 mN72 h) < 5 rnA dl/I, (3 mWf60 °Cf336 h) < 2%

Ith < 50 rnA (20°C) P max (60°C) > 7 mW

55

It can be underlined that the first level of selection corresponding to the ageing test in mode 150 mAl 80 °Cn2 h can be used to position lasers nOimally in the ageing mode associated with the wear out mechanism (after a certain drift effect on the wafers associated with the saturation of the leakage channels). These initial results have already becn confirmed (see Figure 7): • During the laser qualification stage on 38 parts (from four wafers) • For laser quality assurance tests performed on 84 lasers from 21 wafers during commercial selection of TAT 8/Sardinia-Sicily • On the lasers in a lot of 48 emitter modules allocated to test 50 °C/3 m W with a predetermined D3-type laser selection level and totalling 12000 testing hours to date

These results can be compared with those of a similar D3-type laser population which proves that emitter module integration does not modify the distribution noted on the laser.

The selection procedure to be used for EMOS with a laser selection even more severe than a strict D3 and completed by an emitter module laser ageing of2500 hours at 40 °C (equivalent to 600 hours at 60°C) enables us to be more or less compatible with the equivalent selection reference D5 and to confirm the reliability figures allocated to the laser wear out mechanism.

Coupling evolution data The long-term tests on emitter modules have also had the purpose of determining changes in transmitter power in conditions close to those encountered with real usage (rear side adjustment) in order to predict their system lifetime. Determining a change law for the front side power on the basis of accelerated tests comes up against several difficulties: • A change is caused by several different factors that may develop independently or even compensate

Page 65: Semiconductor Device Reliability

56

Test Noot Laser Results parts tested selection level Median time to failure

at test temperature

Laser characterization 74 03 7.610' h (I = 1.45

60 °C/3 mW/20 000 h 58 05 1.0510'h (I = 1.35

Laser qualification 60 °C/3 mW/12 000 h

38 03 810' h (I =1.1

Laser quality assurance 60 °C/3 mW/5 000 h 42 03 (32 parts) 8.6 10' h (03 parts only)

(1=1.4

80°C 1150 mA 15000 h 42 2.610'h (I = 1.8

Laser module qualification 48 03 2.810' h (I = 1.6 50°C 13 mW 112000 h (-10' h 60°C)

Figure 7 - Confirmed laser reliability data

themselves as follows: - Laser/fibre coupling (adaptation and stability of optical accesses) - Laser front side/rear side ratio - Coupling with rear side photodetector - Photodetector sensitivity The first of these is generally considered to be more important and crucial . • Front coupling changes are caused by microdisplacement (some hundredths of A) of the fibre in front of the transmission field of the laser .

. It may be noted that it is not easy to identify the exact Origin of the fibre displacement: creep and assembly stress relaxation are typical causes. This makes modelling all the more complex from the physical point of view. AnotJrr point is that the three dimensional nature of the problem and the shape of the transmission field of the laser show that there is no straightforward relation between the apparent displacement of the fibre with regard tho lhe laser and the reSUlting coupling variation. The same fibre displacement may lead to either a drop, an increase or even an appllrent stability in coupling depending on the initial position of the fibre. It shall be noted that technologicillly our emitter .corresponds experimentally to positive drifts which poses a problem when applying the system end ofHfe criterion normally associated with a 35% drop in the transmitter power. It should be mentioned that an arbitrary decision was made to fix the same end oflife cri terion of 35 % for both positive and negative drifts which is an unfavourable situation.

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57

• The order of magnitude of the drifts observed remains low'" 5% for the test at 30°C that to date has accumulated more than 20000 hours. All these considerations lead us to the conclusion that a too complex. unusable model should be avoided. Analysing coupling changes over long durations (> 10' hours) and at temperatures between 30 and 50°C has made it possible to show the following: • That most parts demonstrated positive coupling changes • That the coupling drift can reasonably be modelled with a change law in relation to time tD where n median = 0.35 over the model validation period between 1000 and 20000 hours. This law provides good confirmation of the considerable sublinear effect expected for coupling changes. • That the activation energy for the lifetime (and not for related physical phenomena) is 1 e V between the two test temperatures. This model with t" is confirmed by the analysis of drifts during qualification on 48 emitter modules each having to date more than 12000 ageing hours at 50°C/3 m W (see Figure 8). In these observation conditions. the coupling changes related to a drift mechanism with a log normal distribution for defects on the criterion of a maximum of one drift of35% by extrapolation using the model, lead us to the following results: • Median (50°C) = 1.7 x lOs hours • a = 1.2 (max value)

Figure 8 " Typical coupling evolution during long IIfetest

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58

The selection principle chosen aims, for a subsequent operating (ageing) duration, for an individual guarantee for each part to satisfy the objective of 35% maximum drift over 25 years at the average repeater operating temperature. This principle will be described in section IV.

b) Random failure contribution The statistical analysis of random failures requires, to have a sufficient confidence level, tests of a large number of components over significant testing periods so that the maximum component hours is accumulated in the face of an objective that is all too often inaccessible.

In order to bypass this difficulty, the strategy to adapt is related to the concept of complete quality that has already been the subject of a publication [ref 2) and to which we shall return.

An estimation of the importance of random failures can, however, be made using an accumulated number of component hours during various tests and also using selection tests on all the commer­cially manufactured equipment to date. At this stage we are in the process of selecting the emitters for EMOS and have accumulated a total for this type of component of 1.8 x 107 component hours at 20°C with zero faults (see Figure 9). This leads to a failure rate of 56 FITs.

Of course, this is not sufficient to prove failure rates as low as 10 FITs, for example. However, it is on the basis of such tests with equivalent volume that we have always successfully included new components in submerged repeaters in the past.

Ageing Device hours Acceleration Effective temperature factor* device hours

75°C 8 10' 43 3.4 106

65°C 6.4 10' 23 1.5 106

50°C 106 9.1 9.3 106

40°C 8 105 4.6 2.1 106

30°C 8 105 2.2 2 106

Figure 9 - Laser package device: hour summary

• Ea = 0.6 eV Total: 1.8 107 h.c: zero faults

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59

[n any case, we consider that these results have to be completed by continuous long duration tests as we have already done with previous technology.

Therefore in order to increase our confidence level continuously with a view to eliminate specific random failures completely, we have intensified the process quality assurance, the precap inspec­tions, the severity of the mechanical screening tests and the duration of ageing to 2500 hours/40 °C for EMOS selection.

3.3 PHOTODETECTOR

3.3.1 Requirements The photodetectors must detect very faint optical pulses at a wavelength of 1.3 J.l.m and a bit rate of 280 Mbit/s and convert them into electrical pulses. The association of the photodetector and its amplifier constitutes the receiver which performs the optical-to-electrical conversion.

The main characteristics of the photodetector are designed to ensure the required level of perform­ance for the receiver (see Figure 10).

3.3.2 Technological description The back illuminated planar PIN InGaAs/lnP structure coupled to a fibre pigtail (single-mode fibre) in a hermetic KDOI package, has been chosen. This technology has already been described in detail I ref 1].

Parameter

Responsivity Rise and fall time Leakage current CapaCitance Breakdown voltage Forward voltage Noise voltage

Receiver failure rate

Figure 10· Photodetector requirements

Specifications

S > 0.7 AIW < 1 ns

< 70 nA (6 V) < 0.6 pF (0.25 pF chip)

> 30 V < 0.65 V (1 mAl

< 500 nV-,J Hz (300 Hz - 10 V)

< 1 FIT

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60

3.3.3 Consolidated photodlode reliability data Crystal The crystal characterization stage has not shown any wear out degradation mechanism (log normal distribution, for example) or any modelable drift so that there is no activation energy [ref 4). As the failure rate connected with the wear out mechanism has to be calculated from a description of failure distribution by a log normal law , in the absence of this type of failure we shall admit in the worst case that they are likely to be distributed according to such a law with a minimum median lifetime of 8000 testing hours at 200 °e (less than 50% at 8000 hours) and a standard deviation of 1.2, which is a reasonable value for a selected population.

With a pessimistic activation energy of 0.6 eV compared with the 1.2 eV announced by AT&T, for example, this leads to an instantaneous failure rate over 25 years of 0.01 FITs (median lifetime at 20 °e equal to 7 x 107 hours). The wear out mechanisms, therefore, have a negligible effect during the useful life of the component.

It has been possible to confirm these results by the final qualification programme on the detectors on submount carried out on 200 parts spread over several test groups. Reliability was calculated on the basis of results obtained during an HTRB test (high temperature reverse bias) covering 80 parts of which 40 had already been burnt in that revealed seven defects (of which six on non-selected parts).

It can be noted that the distribution of these seven defects cannot be satisfactorily interpreted using a log normal law that leads to the presence of aberrations and unrealistic values for the standard deviation (0 = 3.8). On the other hand, it can be described satisfactorily by a Weibulllaw whose parameters are as follows (with median ranks approximated):

"" = 2.5 x lOS hours "~= 0.6 The value of ~ indicates that we are going through a phase where the failure rate is decreasing with time (infant mortality period). By using an activation energy ofO.6 e V, the failure rate after selection should be 0.22% for a service life of 25 years at 20 °e, giving an average instantaneous failure rate of 11 FITs. Taking only the burnt in parts, this rate is reduced to about 3 FITs.

However, it will benotcd thatthe description of the phenomenon as given above is a pessimistic case since this description only considers serious defects such as short circuits that are eliminated during bum in or ageing. In fact parts of reduced reliability can be eliminated by selection process based on parametric criteria and distribution (parameters and drifts), especially on high Idnk and low frequency noise en parameters before and after bum in.

In order to describe crystal reliability completely, the random failures should be added to this failure rate connected with "infant mortality defects".

The total number of component hours at 200 °e is 6 x lOs hours without random failure. With an activation energy of 0.6 e V, this gives an instantaneous failure rate of 0.5 FITs at 90% confidence level.

Accumulating "infant mortality defects", wear out failures and random failures, the maximum failure rate over 25 years for selected parts is 3 FITs for crystal. The apparent efficiency of selection

Page 70: Semiconductor Device Reliability

61

and doubts concerning the nature of at least some defects that might be connected with electrostatic discharge, make it reasonable to suppose that this rate is lower than the one indicated, all the more as the activation energy value used corresponds to the worst case envisaged by AT&T (the most probable being 1.1 eV).

Fibred detector Tests on fibred single-mode photodiodes have shown that behaviour during selection is very satisfactory on the whole with average displacements ofless than 2 or 3 !!lIl (analysis made on parts deliberately fibred at the edge of the plateau).

The standard reference qualification tests: thermal shocks (- 40/+ 90°C - 100 cycles) have shown that they can cause displacements likely to attain + 10 !!lIl. The reverse bias tests at 80°C are likely to cause a displacement of less than 5 J.Lm with a phenomenon of stability after 500 hours of ageing.

This behaviour is a priori associated with microdisplacements of the same nature as that observed on the multimode fibred photodiodes but with a far greater dfect on single-mode parts insofar as this variation on a marginal part positioned at the limit with regard to the plateau causes a more sensitive variation of about 25% for 5 !!lIl.

'This has led to the fabrication process being optimized in order to guarantee that the fibre is centred on the active zone during fibre coupling operations. This gives important margins (> ± 20 J.Lm) for acceptable microdisplacements without losing sensitivity. This operation that forms part of the complete quality programme, constitutes the key to the success of our components; by taking the selection procedure to 1000 hours at 50°C for ageing of the detector with fibre coupling any residual risk of abnormal components should be detected.

3.4 COMPLETE RELIABILITY CONCEPT

Except for the mean time to failure of the lasers which can be determined, other failure rate objectives as defined in previous sections, will require an excessive amount of components to be reasonably proved. Fortunately, reliability requirements can be reached thanks to a reliability assurance programme based upon a general philosophy called compkte reliability which has been successfully implemented with submarine components over the last twenty years in analogue systems. The concept of complete reliability aims at minimizing drastically the risks of failure. The main principles which have provided the guidelines for our assurance strategy and programmes are as follows: • To manufacture all critical key components so as to keep all reliability aspects under tight control within the company (in particular optoelectronic devices and ICs) • To know all extreme operating conditions (electrical, optical, mechanical and environmental) so as to determine the required level of ruggedness for each device • To use the best technological process so as to reach an intrinsic lifetime (the lifetime which depends only on the norm:iI wear out mechanisms) compatible with the required failure rate • To set up monitoring procedures including all quality control methods to be applied throughout the manufacturing cycle so as to make certain that each step has been processed according to specified conditions • To apply selection procedures including all teSts and measurements so as to be sure that each lot reaches the expected robustness while poor or marginal parts are detected and rejected

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62

• To staff and maintain good manufacturing and quality control teams with personnel having the qualification level required and the dedication to work well

The last part of our report puts particular emphasis on selection procedures for optoelectronic components that have been largely justified in the presentation of consolidated reliability data that has just been carried out.

IV Selection procedures for EMOS link

4.1 INTRODUCTION

The general selection methodology for optoelectronic devices as well as all active components in the S 280 system follow our complete reliability principles and the experience acquired with discrete submarine bipolar transistors that to date have exceeded 1.2 billion operating hours without one failure.

The selection methods are also based upon the fundamental notion of a homogenous lot. The statistical calculations of parameters and drifts measured during tests provide a powerful tool to monitor and compare the quality oflots and to detect any marginal and flawed parts in a lot. In the semiconductor industry it is common practice to consider that all parts issued from the same wafer have the highest degree of homogeneity.

For each kind of component the procedure includes the selection of the wafer by sampling and the individual selection of units in the lot by screening and ageing (including bum in).

Wafer selection consists of high stress tests applied to a few good electro-optical and electrical parts selected at random on the wafer. These tests characterize the quality of the wafer and provide significant results on robustness margins and spreads for the parts located on the wafer. When the results follow the normal trend as identified during the qualification step, the wafer is accepted. This also gives conclusive proof that all steps in wafer processing have been properly controlled.

After acceptation of the wafer, the dice are visually inspected and assembled. Priorto capping, visual inspection of the chips is performed and then they are subjected to screening and ageing for individual selection.

Screening tests are designed to avoid damage to the normal part but with enough severity to weed out marginal or potentially weak parts. After these tests, all the units are subjected to a long ageing test so as to verify the stability of parts which operate in conditions very similar to the normal ones.

All measurements and calculations of parameter drifts which are made during screening and ageing are logged into a computer system. Each aged component is individually approved or rejected under the control of a commission composed of several representatives from ATe and the P1T administration.

Of course, according to the general philosophy, the selection procedures should be tailored to the specific nature of each device and the associated manufacturing process.

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63

The application of the optical emitter and receiver shall now be given.

4.2 EMITIER SELECTION

For components included in the transmitter and for the transmitter itself, the test sequences are organized according to the following general considerations: • The laser package must be regarded as an optoelectronic subunit rather than a laser diode, a monitoring photodiode and a single-mode fibre. The laser and the photodiode cannot be submitted together in the laser package to an efficient test sequence for selection because the two devices cannot withstand the same stress level. Before assembly therefore, each component must be subjected to its own selection. For the laser package, it is also required that appropriate test sequences and selection procedures are applied, because all operational parameters depend on the mutual coupling and interaction of different internal components. The notion of homogenous laser package lots loses much of its interest, the lot meaning only an assembly period. • Because of the poor heat resistance of the fibre assembly, the pigtailed devices cannot be subjected to high temperature tests. For such devices, sampling and screening tests at temperatures higher than 70°C will be performed with devices on submount. After assembling the pigtail, the devices will be submitted to a second test file at lower temperature in preparation for the final selection.

4.2.1 Laser on submount selection The selection procedure for lasers on submount is given in Figure 11.

The principles of unitary selection are mainly encountered in the bum in and ageing stages: • Conformity in terms of parameters with the definition of the D5 population (reliability aspect) and the definition of the product for the application in question (functional aspect). • Elimination of parts that are statistically marginal in parameters and drifts at each stage of the procedure, in compliance with the general principles described above (verification of the principle of homogeneity of acceptance tested populations) (see Figure 12) • Elimination of parts showing Significant drifts in operating current during on-the-site monitoring at 60 °C(3 m Wand not conforming with the strict criteria chosen for the amplitude for the D5 population backed up the slope (m exponent) criterion when it is accessible, that would lead to a lifetime extrapolation not in accordance with the objective of the test.

This procedure truncates the log normal lifetime distribution resulting from normal wear out failure mode and leads to a selection level being guaranteed that is at least equal to that of the D5 reference population whose lifetime characteristics (MTTF and a estimators) are verified to be compatible

with the reliability objective by quality assurance procedures (> 4000 hours testing at 60 °C/3 m W).

4.2.2 Monitoring photodiode The selection procedure is given in Figure 13. Individual selection of diodes is based on conformity with functional specifications, in addition to selection on the basis of the parameters' distribution curves (I .... k, V 1<' etc) and the drifts associated with each step in the procedure. Selection lots are taken from wafers whose behaviour during wafer selection (on quality assurance destructive tests) is comparable with that observed during qualification.

4.2.3 Optical head Once selected, both elementary devices are then assembled in the pigtailed housing. The laser

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64

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Figure 11 - Laser on submount selection procedure: EMOS application

Page 74: Semiconductor Device Reliability

99.9 99.8

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Page 75: Semiconductor Device Reliability

66

Wafer selection

Rejection on yield

Group 2 Storage 250°C 168 h (5 specimens) or 200 °C/336 h

Rejection

Reference batch (15 specimens min.)

Assembly in TO 39 package with window

Electro-optical characterisation

Group 1 Temperature step stress (Step 15 h,"'T = 25°C, 125°C to 275°C) VR: 2 V (I max = 20 mAl (10 specimens) Wafer acceptance

Figure 13 - Monitoring photodiode selection procedure: EMOS application

Wafer from production process

40-pattern test

Electrical probe sorting

Visual inspection

Subassembly (on alumina and Kovar support)

Assembly in TO 8 package Optical test

Adhesion test Kovar/alumina

Electro-optical measurements NOO

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Electro-optical measurements N01

Ageing 168 h/100 °C

Electro-optical measurements N02 Final visual inspection Final selection

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67

package is sealed under dry nitrogen after the application of a strict degassing procedure. Before sealing, a very meticulous precap inspection is carried out under customer quality assurance control.

The final product selection procedure is given in Figure 14. The sequence aims at achieving the following: • Weeding out potential standard and specific rogue failures • Prestabilising the component parts for coupling purposes • Verifying the wear out mechanisms related to the laser and coupling so that the drift behaviour and lifetime extrapolations comply with objectives. This stage makes use in particular of the on-the-site monitoring results for the operating current and the coupled power over 2500 hours at 40°C.

Unitary selection criteria are based on the following: • The eKamination of the distributions of the parameters and drifts at each measurement level during the procedure (distributions of a lot given as representative of an assembly and "historical" accumulated distribution period) with the systematic elimination of non-distribution parts. • The conformity with the product's functional specifications (technical specification limits) • Verifying the tolerable drift criteria for on-the-site drifts on the basis of the amplitudes statistically authorized by evaluation models and extrapolations with a view to guarantee the reliability objective.

From a practical viewpoint as far as coupling is concerned for example, selection is performed by marking the maximum amplitude reached and the slope acquired at the end of selection in accordance with the to model already described. The extrapolation obtained that is supposed to guarantee the service life (25 years) takes into account the temperature of the test and the temperature associated with utilization (1 to 3 systems) (see Figure 15).

It can be recalled that in view of the positive increase obse:rved on most parts under test this method is considered as "conservative".

4.3 PHOTODETECTOR SELECTION

Figures 16, 17 and 18 describe the selection procedures applied to EMOS.

The selection procedures are based upon the following: • A wafer selection that guarantees the mean reliability objective • A crystal on submount selection for high temperature tests during bum in (5 hours/200 °C/20 V) and ageing (125 °C/168 hours/20 V) designed to trap the drift mechanisms inherent in the electrical performance of the crystal (S .... ' V",) and random failure mechanisms (through thermo-mechanical tests). • Selection of fibred detector for the purposes of testing fibre/photodiode coupling. The nature of this selection should enable efficient stabilisation of the component.

Part processing by homogenous lot (lot/wafer) can be used for selection on the criterion of homogeneity of parameters and drifts, especially with the electrical aspects for the crystal and sensitivity for the detector with fibre coupling.

It should be noted with the last point that the intermediate test measurement at 500 hours during 1000 hour/50°C ageing reduces the importance of the sensitivity measurement uncertainty (± 2%).

Page 77: Semiconductor Device Reliability

68

laser module Key assembly

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Electro-optical measurements level 04

Final selection acceptance Figure 14· Laser module

selection procedure: EMOS application

Page 78: Semiconductor Device Reliability

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Page 79: Semiconductor Device Reliability

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Figure 16· InGaAs/inP PIN detector selection procedure: S 280 1.3 Jlm crystal selection (EMOS application)

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Page 80: Semiconductor Device Reliability

Figure 17· InGaAs/lnP PIN detector selection procedure: S 280 1.3 J..LII1 head selection (EMOS application)

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71

Page 81: Semiconductor Device Reliability

72

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Figure 18 - InGaAs/inP photodlode: batch by batch assembly quality assurance

Page 82: Semiconductor Device Reliability

73

V Conclusions

All the reliability results presented in this paper and the quality assurance and unitary selection procedures implemented authorize us to say that in-house ATC optoelectronic components are designed to satisfy submarine link reliability requirements.

The EMOS S 280 link that is being manufactured will represent with its 46 repeaters the longest optical fibre link in the Mediterranean.

While recognizing certain limitations regarding demonstration in particular of the concept of the confidence level of statistical risk or the impact that the presence of weak activation energy degradation (Ea < 0.6 e V) might have on overall reliability, selection by homogenous lot criteria and the applied complete reliability concept overcome these difficulties.

Indeed these are the conditions in which Akatel Submarcom has succeeded to lead the world of submarine optical fibre transmission with more than twenty years experience.

Bibliography

[ref 1] Bzrowwski H., Lemonde J. L., Fourrier J. Y., Giron P., (18 - 21 February 1986), 'International Conference on Optical Fiber Submarine Telecommunication Systems', SUboptic 1986, Paris, 199 - 205. [ref 2] Pestie J. P., Franco P., Gobin F., Durand P., 'International Conference on Optical Fiber Submarine Telecommunication Systems', Suboptic 1986, Paris, 173 - 180. [ref 3] Pes tie J. P., 'Reliability assessments and selection procedures of semiconductor components for EMOS 1 link', EMOS contract, 1987. [ref 4] 'Fiabili\t des photodetecteurs PIN InGaAs/lnP planar pour liaisons saus-marines sur fibre optique', Cinquieme colloque international de fiabilite et de maintenabilite, Biarritz, 1986.

Page 83: Semiconductor Device Reliability

ASSURING THE RELIABILITY OF LASERS INTENDED FOR THE UNCONTROLLED ENVIRONMENT

JAMES L. SPENCER Bellcore, Fiber Optic Electronics District 331 Newman Springs Road Red Bank, New Jersey 07701-7040 United States of America

ABSTRACT. This paper examines various reliability issues that impact the use of semicon­ductor lasers in an uncontrolled environment (versus a controlled environment) and how these issues should influence component reliability assurance strategies. The paper first discusses the calculation of acceleration factors for thermal aging in an uncontrolled environment. Qualification issues are then reviewed. Finally, the potential conflict between laser reliability, as assured through testing and screening, and final cost is considered.

1. Introduction

In the next few years, use of semiconductor lasers in uncontrolled environments will reach a turning point. Telecommunications applications, which have been some of the primary driving forces in the advancement of laser performance and reliability I , could see explosive growth if fiber in the network is extended to subscribers' homes and offices.2 However, this means that typical applications will diverge in important ways with respect to operating environment.

1.1 OPERATING ENVIRONMENTS

Until now, most telecommunications applications of fiber optics have been dominated by sys­tems used to transmit telephone conversations and/or data between telephone company central offices. Lasers for this specific application were designed for "high performance" (i.e., high relia­bility, high bit rates, maximum repeater spacing, etc.). A relatively high cost per laser was acceptable for the relatively low volume of lasers required for network equipment. The correla­tion between high performance (including reliability) and relatively high device cost under­scored the difficulty in producing such lasers. Yet, the operating environment in this applica­tion was fairly benign; while not controlled to the same extent as a computer room, the

1. The commercial success of compact disc players is directly linked with another aspect of laser technology ~ the development of low-cost packaged lasers. In general, those lasers are not advertised as having the same performance or reliability as lasers used today in telecommunica.tions.

2. Local area networks (LANs), which might be implemented using fiber optics, are owned by individuals or businesses; as such, they are not considered part of the telecommunications network in the context used here.

75

A. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 75-96. © 1990 Kluwer Academic Publishers.

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temperature limits in central offices seldom exceeded a specified range of 4' C to 38' C. Today, though, fiber optic systems are also being deployed for transmission between the

central office and remote terminals or nodes. The additional, final step toward an all-fiber telecommunications network is being explored by telephone companies with trials of "fiber to the home" (FTTH). In both of these applications, the operating environment is essentially uncontrolled and encompasses a wide range of possible temperatures.

In an outdoor environment, cabinets or other fixtures are used to house the electronics and optical sources/receivers of a fiber optic system. Many factors affect the temperatures within such housings:

• geographic location and climate

• housing design (ventilation, color, shape)

• specific location of the housing (exposed or shaded)

• power dissipation of the electronics inside the housing.

In cold areas of the continental United States, temperatures can go below -40' C. If the housing has forced ventilation or the system power dissipation is low, the ambient temperature inside the housing can approach these same low temperatures. Conversely, temperatures in many places in the United States can exceed 45' C. With low solar loading, low power dissipa­tion and adequate ventilation (i.e., forced air using fans), the ambient temperature inside the housing can still easily reach 50' C. The ambient temperature could climb further to ~65' C under conditions of maximum solar loading, high power dissipation or reduced/inadequate ven­tilation (e.g., no fans or fan failure).

For typical fiber optic systems designed for central offices, the actual air temperature near devices (within the equipment) is typically about 5-15' C higher than the ambient room tem­perature. This results in a maximum device operating temperature of 50' C for a controlled environment, assuming a maximum system ambient temperature of 38' C plus a 12' Crise between the inside and outside of the system. However, the temperature rise inside equipment is often higher in systems designed for applications other than central offices. These include underground, controlled environmental vaults (CEVs) and most outdoor cabinets and fixtures above ground. In such applications, space is usually limited and there are more electronic com­ponents per unit volume. Consequently, a 20' C internal temperature rise must be assumed. Worst case conditions for uncontrolled environments, therefore, involve system ambients of ~65 • C and device operating temperatures as high as 85' C. Table 1 summarizes these results.

Table 1. Operating Environments for Typical Applications

ENVIRONMENT "AMBIENT" "DEVICE"

TEMPERATURE TEMPERATURE

Central Office 4' C to 38' C 4' C to 50' C

CEV 4' C to 38' C 4' C to 58' C

Outside Cabinet -40 • C to 50 • C -40' C to 70' C (fans and low power)

Other Outside Fixtures -40 • C to 65 • C -40 • C to 85 • C (higher power or no fans)

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[~ote that, with the exception of the central office and CEV environments!lj, the numbers in Table 1 are preliminary; nevertheless, some equipment suppliers are designing and marketing systems consistent with such temperatures.]

1.2 COMMON LASER MODULE DESIGNS

As indicated by the title and preceding discussion, the focus of this paper is laser reliability in uncontrolled environments. Most reliability issues associated with the laser diode itself do not differ substantially for uncontrolled versus controlled environments. One important exception is the calculation of acceleration factors for predicting reliability from endurance test results. Section 2 addresses that subject.

Most problems, as encountered in endurance testing, relate to the design and assembly of the laser package or "module" (as it is called here). Some of those problems are examined in Section 3. First, though, it is important to review a few basics about laser modules.

1.2.1 Hermetic Rectangular Package. One of the most common laser module designs is a her­metic, rectangular package. Such laser modules are typically about 1 cm by 2'h cm by 1 cm in size, with various available lead configurations (dual in-line, single in-line, butterfly, and oth­ers). Hermeticity is required to prevent degradation of the exposed laser diode, which can occur in the presence of moisture. Figure 1 shows a generalized schematic of a common design. In addition to the laser diode (attached to a heat sink on a small mounting fixture), a laser module typically contains some or all of the following component parts:

• a monitor photodiode

- for monitoring the rear-facet light output from the laser diode

• an optical isolator

- for eliminating optical reflections that could affect laser performance

• a thermoelectric cooler or "TEC"

- for maintaining (within specified limits and conditions) a constant laser temperature

• a temperature sensor

- for use in conjunction with the TEC

• miscellaneous hybrid circuitry

- for operating the laser

• optical lenses

- for optical coupling with the laser diode's front-facet light output

• optical fiber

for coupling the laser diode's front-facet light out of the module; alternatively, there might be a lens arrangement that interfaces directly with an opt­ical connector on the exterior of the module.

1.2.2 Two-Piece Cylindrical Module. Another common laser module design is a two-piece cylindrical package.i2j As shown in Figure 2, this module consists of a hermetic package (or "can") for the laser diode and a separate, nonhermetic second stage assembly. Light is passed through a window at the front of the diode package and coupled to optical fiber using lens( es)

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in the second stage of the module. If the diode package does not contain a monitor photodiode, a rear window is usually provided for attaching a separate photodiode in its own package. The overall design of the cylindrical module does not usually provide space for a TEO or any circui­try.

1.2.9 Low-Gost Module. Several companies are working on the development of commercial, low-cost packages that could meet the performance and reliability needs of telecommunications applications. Some companies are also exploring the use of low-cost laser packaging already established for compact disc applications.l3j One possible low-cost design is shown in Figure 3. Similar to the two-piece cylindrical module design described above, this design does not include a TEO.

2. Acceleration Factors

An important use of results from endurance tests, such as elevated temperature life tests, is the calculation of the laser's predicted reliability. Although interpretation problems exist because different calculation procedures are often used[4j, predictions based on elevated temperature life tests can usually be derived for laser diodes.

The discussion below deals specifically with the thermal aging of the laser diode. These failure rate calculations do not account for temperature cycling failures, which are often associ­ated with the laser sub mount assembly (including wire bonds) or the laser module assembly. In particular, the calculations do not consider reliability problems resulting from any instability of the laser/fiber alignment. [Sections 2.3 and 3.2.3 have more on the difficulties of predicting failure rates for laser modules and the meaning of temperature cycle tests, respectively.]

2.1 ARRHENIUS RELATIONSHIP

In an elevated temperature life test, a value for the predicted reliability is usually calculated for the specified test conditions (i.e., the elevated temperature). This value is translated to actual operating conditions (or any other temperature) based on empirical acceleration factors. Typically, these factors are modeled by the Arrhenius relationship:

where

ML[Tzl [Ea(l 1)] ML[Tll = exp k;; r; - r;

ML [Tl is the median life at a given temperature,

E. is the activation energy (in eV),

kB is Boltzmann's constant (in eV/K), and

T 1 and T z are the temperatures (in Kelvin, K).

(1)

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This calculation is straightforward for a controlled environment. In such cases, a nominal operating temperature dominates any small fluctuations. Thus, T 1 is the (elevated) test tem­perature and T 2 is a given nominal operating temperature. The activation energy is empiri­cally derived from performing the life test at several different temperatures.

2.2 FAILURE RATE PREDICTIONS FOR UNCONTROLLED ENVIRONMENTS

Calculating the predicted failure rate of laser diodes is much more complicated for uncontrolled environments. Lasers in uncontrolled environments are subject to wide daily temperature vari­ations as well as seasonal changes. The exponential nature of the Arrhenius relationship and the inverse temperature dependence mean that using an "average" temperature is not a valid approach.

Careful modeling of temperature variations versus geographic locations is necessary. From such work, it is likely that a few reference cases will be identified. These reference cases or models should account for typical conditions as well as worst case conditions (for both environ­mental factors and equipment/housing characteristics) from which exceptions could be noted.

A hypothetical example is described below; it results from numerous assumptions and quali­tative approximations. It is described here only to demonstrate the complexity in building a model (some of its assumptions are arbitrary). It includ(,s the following considerations:

A. The daily variation in system ambient temperature (i.e., f, T ) is 25 0 C in the summer but only 10 0 C in the winter. sa

B. The daily variation in system ambient temperatur,~ is described by an asymmetric function for which:

1. the temperature increases rapidly during the morning hours;

2. the temperature asymptotically approaches II maximum in mid-afternoon;

3. the temperature drops off rapidly in late afternoon;

4. the temperature gradually reaches a minimum during the night.

C. The device operating temperature varies from a 10 0 C rise over system ambient at night to a 20 0 C rise during the day.

D. The maximum device operating temperature in the summer is 75 0 C.

E. The minimum device operating temperature in th(, winter is 0 0 C.

F. A TEC, if used, provides maximum heating of f, T=65 0 C and cooling of f, T=35 0 C (giving a range for the laser temperature of 25 0 C to 40 0 C).

G. The seasonal variation in (average) temperature is sinusoidal.

H. The life test results are assumed to be for an elevated temperature of 70 0 C.

If detailed calculations are not performed according to a model (such as this one), serious mistakes can be made about "obvious" conclusions. For example, a common misconception is that the high temperatures of an uncontrolled environment have an overwhelming impact on the reliability predictions. Closer inspection, though, reveals almost the opposite. Because Equation 1 is a function of the inverse temperature, the reliability predictions actually depend more on lower temperatures. For example, the Arrhenius relationship gives a factor of 0.121 in the median life calculated at 50 0 C (323 K) versus 25 0 C (298 K), assuming Ea = 0.7 eV. The predicted life at 0 0 C (273 K), though, is 12.1 times longer than the median life at 25 0 C.

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Multiplying the two results together (i.e., assuming that the device is subject to equal times at 50' 0 and 0 0 0) gives an overall improvement of 1.47x with respect to the expected median life at a constant 25 0 0.3

Of course, a TEO is often included in the laser module to maintain a "constant" operating temperature for the laser diode. A TEO usually has no difficulty in maintaining, for example, a constant 25 0 0 temperature for ambients down to _40 0 O. However, many TEOs are limited in cooling to a b. T of 30-40 0 0. This limit is exceeded in the worst case conditions of Table 1 if a laser operating temperature of 25 0 0 is desired. Under those conditions the laser temperature can still reach 45-55 0 0 (this effect must also be included in models used to calculate the predicted failure rate).

The use of a TEO, therefore, might decrease the expected median life of the laser diode by canceling the apparent benefits of the colder temperatures on laser aging. TEOs are used for other reasons, though. In many applications, the fiber optic system might not be able to tolerate drift or changes in laser wavelength or spectral width. Some lasers experience a "roll­ofI" or apparent saturation effect in light output versus drive current at temperatures above ~70 0 O. Other lasers might be sufficiently linear in operation even at 85 0 0, but the additional drive current required for a specified light output level at high temperatures might be a prob­lem for the system.

Bellcore has found that some lasers are also subject to splitting of their optical spectra into two distinct mode groups for small changes in temperature. Figure 4 shows this for a change of less than 1 0 o. Such behavior could have a serious impact on system bit error ratio (BER) and other performance parameters. The manufacturer has not been able to estimate the fraction of the total population of lasers with this problem. Although the exact cause of this phenomenon has not been determined conclusively, it seems likely that the wide temperature variations in an uncontrolled environment (if a TEO is not used) should increase the probability of experiencing this problem.

2.3 OTHER ISSUES

The discussion on reliability predictions up to this point has dealt with ways to handle failure rate predictions for single components, such as laser diodes. At the module level, many other difficulties are encountered in attempts to predict laser reliability. First, the various com­ponents contained in the module have different acceleration factors for a given temperature; when elevated temperature life tests are performed on laser modules, it is therefore difficult to translate the results to other temperatures. Even if this problem can be overcome, appropriate electrical stresses might not be applied to individual components (contained in the laser module) during module life tests because of limited electrical access to the components' leads. Another basic question involves the TEO. Assuming the module contains a TEO, some com­ponents will be at reduced temperatures if the TEO is operating; if the TEO is not operated, laser/TEO/module interactions will not be stressed.

All of the discussions above deal almost exclusively with elevated temperature life tests of laser diodes (although they also apply to laser diode burn-in). In the following sections, tem­perature cycle endurance tests and temperature cycle screens are an important topic for laser modules. Reliability predictions from such tests are even more difficult. There is no generally

3. However, it must be pointed out again that this result only allects the th.rmal aging of the laser diode; temperature cycling in a.n uncontrolled environment is .generally expected to accelerate other failure mechanisms (such as loss of laser/fiber alignment or fiber breaks inside the laser module) that will dominate laser diode aging ellects.

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accepted method for converting temperature cycle results to reliability predictions for other (more "normal") operating conditions. Much of the work in this area by laser manufacturers and equipment suppliers has not been published. It is not clear if the results of these specific investigations can be extrapolated to general cases. For example, Bellcore subject matter experts are not convinced that the results for a two-piece cylindrical module design can be used for a rectangular design.

3. Design and Qualification Issues

A comprehensive review of the design and qualification issues that are important for laser applications in an uncontrolled environment are lengthy lsi and fall beyond the scope of this paper. Instead, a representative sample of the reliability concerns that relate to laser module design are briefly discussed below. Qualification practices to identify these problems are then considered.

3.1 POTENTIAL RELIABILITY PROBLEMS

Some of the laser module design and assembly issues that are especially important for long­term reliability in an uncontrolled environment include:

• thermal impedance between the laser and TEO (and/or module case),

• coupling of light from the laser to the fiber pigtail,

• correlation between the light measured at the end of the fiber pigtail and the light measured by the monitor photo diode (i.e., "front-to-rear tracking ratio"),4

• TEO operation,

• hermetic seal failure.

Each of these issues is addressed below.

3.1.1 Thermal Impedance. As shown in Figure 5, there are several interfaces between the laser and the thermoelectric cooler in a typical laser module design - laser diode to heat sink, heat sink to submount fixture, submount to TEO (or module case, if no TEO is used). The solder or epoxy at each of these interfaces must provide good thermal conductivity as well as mechanical attachment. In an uncontrolled environment, high system ambient temperatures can raise the laser operating temperature above the manufacturer's design limits unless the thermal path allows efficient dissipation of heat by the laser diode. Poor solder wetting of interface surfaces or voids in epoxies significantly increase the thermal impedance.

3.1.2 Laser/Fiber Coupling. Long-term stability of the optical coupling between the laser diode and the module's fiber pigtail (or connector if a pigtail is not used) is perhaps the most important reliability issue for uncontrolled environments. Most laser module designs, which use single-mode fiber pigtails in common telecommunications applications, can tolerate only ~ 1 pm or less transverse movement in the laser/fiber alignment.

4. Laser·to-fiber coupling (the preceding listed item) contributes to the overall front·to-rear tracking, of course. The two items are treated separately to emphasize different aspects of the overall reliability issue.

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Table 2. Laser /Fiber Alignment Tolerances

COUPLING METHOD OFFSET TOLERANCE [in pm]

Lens 1 Lens 2 Fiber

Tapered Hemispherical- - - 0.7 Ended Fiber

Plano-Convex 0.7 2.6

GRIN-Rod Lens -

Confocal, Two Lenses 0.7 2.6 2.6

Confocal Combination 0.7 6.0 6.0

Lenses

Table 2 lists the alignment tolerances measured by Mitomi et a1. 16/ for various coupling schemes (the numbers represent the maximum transverse movement for which excess loss is no greater than 1 dB). For the case of the simple tapered fiber, only a 0.7 pm movement of the fiber (with respect to the laser diode) can be tolerated after assembly in its optimum position. Confocal coupling methods allow larger movement tolerances for some optical elements, although the first lens is still limited to 0.7 pm shifts.

In addition to different schemes for coupling the light output, there are also different means for locking the lenses and fiber into place. The three basic techniques include epoxy attach, solder attach and laser spot welding (see Figure 6). Each has its own advantages and disad­vantages with respect to implementation and reliability. A primary concern is preventing any movement as the epoxy cures or the solder hardens. Over the long term, epoxy can degrade (due to high temperatures or the presence of moisture) and solder can "creep," either of which could result in fiber or laser movement. [Note that even when spot welding is used, some epox­ies or solders are often still required to attach the laser diode to the heat sink or to lock the fiber pigtail in a ferrule.]

3.1.3 Tracking Error. A critical assumption in the design of fiber optic systems involves the correlation between the light emitted from the laser's front facet (as measured at the end of the fiber pigtail) and the light emitted from the laser's rear facet (as measured by the monitor photodiode). The front-to-rear tracking ratio should be a linear relationship for the system to provide "known" amounts of light through the fiber to the receiver. Deviations from a linear relationship are called "tracking errors."

In an uncontrolled environment, the tracking error can change significantly with ambient temperature (even if a TEC is used). This effect results from movement of the monitor photo­diode, lenses or fiber with respect to the laser diode. The amount of movement depends on the overall module design, including the mismatch in the thermal coefficient of expansion (TCE) of different materials and the method of locking fiber alignment.

Cassidyl7/ has investigated an important aspect of this. His work measured the variation in front-to-rear tracking of laser light output for changes in the (longitudinal) distance between the laser diode and the end of the fiber pigtail. Several different laser structures were studied, including planar gain-guided InGaAsP lasers, index-guided InGaAsP lasers and quasi-index­guided InGaAsP lasers. The dependence on the type of fiber was also examined. Cassidy reported a 5-10% variation in the detected power between the front (as measured at the far end of the pigtail) and the rear (as measured by the monitor photodiode) of the laser.

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Figure 7 shows the results for one combination of laser diode structure and fiber type (the solid curve is the coupled fiber output and the dotted curve is the power detected by the moni­tor photodiode). As seen in the figure, Cassidy found:

• The detected rear-facet and front-facet outputs vary sinusoidally as a function of laser /fiber distance.

• The magnitude of the variation in rear-facet output is higher for laser drive currents closer to the threshold current.

• The magnitude of the variation in coupled front-facet output goes to zero with increas­ing drive current up to a "crossover" value; beyond that value, the magnitude of the variations increase again.

• The variations of the front and rear outputs are in phase at low drive currents and change to 180 0 out of phase for currents above the crossover value.

Cassidy theorized that reflections from the near end of the fiber pigtail re-enter the laser diode where they interact coherently with light in the structure's active area.

If all laser modules are subject to these effects, it appears very possible that temperature changes in an uncontrolled environment could provide enough laser/fiber movement to produce tracking errors on the order of the 5% measured by Cassidy. Laser manufacturers should examine ways to minimize the problem. In addition, system designers need to account for this problem in their considerations.

8.1.4 Thermoelectric Gooier. Up to this time, most fiber optic systems designed for an uncon­trolled environment incorporate a TEC to maintain a near-constant laser operating tempera­ture. A stable operating temperature is necessary to prevent degradation in system perfor­mance due to drift in laser wavelength, shift in threshold current, nonlinear light output as a function of drive current (at high temperatures), etc. A stable operating temperature also simplifies reliability predictions. Figure 8 shows an example cross section of a TEC. TECs tend to fail due to:

• diffusion of material away from the solder joints,

• diffusion of metal impurities into the bismuth telluride (BiTe) elements,

• mechanical stresses applied to the TEC, especially in the shear direction.

These mechanisms can also produce gradual degradation in TEC performance before catas­trophic failure. Symptoms include a decrease in cooling/heating capacity, an increase in current to maintain a desired temperature, and/or a change in TEC voltage. Any of these symptoms, as well as actual TEC failure, could impact system performance in an uncontrolled environment.

3.1.5 Hermeticity. For the rectangular module design described earlier, hermetic seals exist where the module lid, the electrical leads and the ferrule are attached to the module case. Moisture can enter the module if any of these hermetic seals fail. This can threaten long-term reliability through degradation of the exposed laser diode or any epoxies used in the module. Hybrid circuits, if included in the module, might be subject to corrosion. In addition, there is the likelihood that moisture will condense if the TEC/laser temperature is below the dew point.5 These threats are clearly more serious in uncontrolled environments. As a result,

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module hermeticity is considered a necessity, in spite of cost, until further progress is achieved on these associated reliability problems.

3.2 LASER MODULE QUALIFICATION

Full qualification of a laser module should include l81 :

• module characterization,

• mechanical tests,

• endurance tests,

• other special tests.

Again, it is beyond the scope of this paper to cover these topics comprehensively. Instead, only a few specific tests that address the examples of the reliability issues discussed above will be reviewed here.

3.2.1 Character£zat£on Tests. Many characterization tests exist, but the two pertinent ones here are thermal impedance measurements and tracking error measurements. Based on discus­sions over the last five years, Bellcore has found that some laser manufacturers have overlooked thermal impedance measurements. Attention to this (after the manufacturer's design phase for the laser) is critical in applications for the uncontrolled environment. In particular, samples used in qualification should be representative of normal production; the usual variations in solder or epoxy coverage should be included in the characterization.

An example of tracking error for a laser module designed for uncontrolled environments is shown in Figure 9. Clearly, there is no way to predict how front-to-rear tracking will change as a function of temperature. In this case, the total error between the low and high tempera­ture limits is about 1.3 dB (a factor of about 1.35). It is important that the tracking error lies well within design guidelines if this measurement is not performed on all lasers at final testing.6

3.2.2 Elevated Temperature L£/e Test. Although elevated temperature life tests are performed on the laser diode as a subassembly (before packaging), it is still important to run a life test on the completed module. This life test demonstrates the reliability of the assembled module with all the various component parts working interactively. It provides necessary supporting infor­mation for all the other measurements and tests. With respect to the reliability issues dis­cussed in this paper, an elevated temperature life test does provide additional information on:

• thermal impedance

problems at the interface between the TEC and the laser heat sink or the module case could lead to higher laser operating temperatures or TEC thermal runaway

• laser/fiber coupling

constant elevated temperature can identify potential epoxy degradation or solder creep (temperature cycling produces different stresses, although the failure mode

5. This actually happened in the United States when an equipment supplier used a nonhermetic laser module. Even though the systems were in telephone central offices, moisture condensed on the laser facets, causing fluctuations in laser output (and associated jumps in BER) that varied by time of day.

6. Bellcore TA-TSY-000468 does call for tracking error measurements on all lasers, but as discussed later in Section 4, this might not be possible for high volume, low cost lasers.

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might appear to be the same)

• tracking error

- tracking error can change due to shifts in laser/fiber coupling or laser/monitor align­ment, reflections from the lenses or fiber, degradation of the laser diode, and degra­dation of the monitor photodiode

• thermoelectric cooler

- damage to the TEC due to inherent problems in the assembly process, for example, might not be found without this test

• hermeticity

elevated temperature life tests could accelerate different failure mechanisms than thermal shock, some of which might lead to hermeticity failures; for example, the lid attach might be more susceptible to degradation and failure at high temperatures than form the mechanical stress of cycling

8.2.3 Temperature Cycle Endurance Test. The temperature cycle endurance test provides cru­cial information on the mechanical stability of the laser/fiber alignment. It can also identify hermeticity problems under certain circumstances? For eentral office applications, the Bellcore criteria call for at least 100 cycles (with the laser unpowered) between -40' C and +70' C. It is recommended that this test be extended to 500 cycles for information purposes. Two com­panies, for example, reported problems only after 200-300 cycles.

For uncontrolled environments, preliminary Bellcore criteria\S\ call for 500 cycles between -40' C and +85' C (these criteria are under additional review at this time). The higher upper limit is necessary to cover the worst case conditions discussed in this paper. The increased number of cycles reflect the long-term reliability desired in spite of the hostile environment.

Temperature cycling tests performed in Bellcore's Reliability Laboratory have identified several serious potential reliability problems.l9\ Problems found from tests on various manufac­turers' laser modules included fiber pigtail breaks inside the laser module, in the ferrule, just beyond the ferrule outside the module package, along the fiber pigtail, or even in the connector at the end of the pigtail. Associated with some of these breaks are cracks in solder at the point where the pigtail exits the module; such cracks can lead to failures of the module hermet­icity. Other problems, such as TEC degradation, can also be found in temperature cycling tests.

A final note is that the temperature cycling test must be performed with the optical con­nector on the pigtail. Many laser manufacturers in the past have left the connector off during temperature cycle tests (possibly to lower the cost invested in the laser modules). It is clear from experiments performed by Bellcore, though, that problems can go undetected without the connector assembled onto the fiber pigtail. This is believed to relate to shrinking of the fiber jacketing; without the connector to lock the end of the pigtail, stress can be relieved. Conse­quently, this can leave problems to be detected later as field failures.

7. Bellcore TA-TSY-000468 includes a thermal shoek test for assessing the hermHicity of laser modules.

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3.3 TEC QUALIFICATION

Even though it is important to qualify the completed laser module, it is also important for all component parts of the module to be individually qualified (logically, the component qualifications should take place before the module-level qualification). Thus, the TEC as a separate part needs to be characterized and subjected to various tests, including endurance tests.

Based on discussions with TEC manufacturers, Bellcore has identified three endurance tests that should be performed as part of the qualification of TECs. These tests are high tempera­ture storage, temperature cycling and power cycling.

• High temperature storage provides information on potential diffusion problems associ­ated with operation of the TEC. The test should be performed at the TEC's maximum­rated storage temperature for a minimum of 2,000 hours.

• Temperature cycling investigates the mechanical strength of the TEC with respect to stresses generated by external conditions. The test should extend for at least 500 cycles (-40' C to +85' C).

• Power cycling addresses the reliability of the TEC with respect to internal stresses (i.e., stresses occurring as a result of normal operation). It also provides important additional information on potential diffusion problems. The test should be performed with the TEC's "hot side" at 60' C or higher; the TEC should be cycled on and off for a minimum of 20,000 cycles (using a suggested duty cycle of 1.5 minutes on and 4.5 minutes off). When powered "on" in the test, the TEC should be operated at maximum-rated ~T (i.e., maximum-rated current).

For each test, appropriate pass/fail criteria need to be specified. These criteria should include, as one reason for rejection, a reduction in cooling capacity below the TEC's specified rating (at a given current) when measured under load.

An example of TEC deterioration following temperature cycling is shown in Figure 10. Lengthwise cracking and splitting of a BiTe element are clearly seen. Such problems can be difficult to detect electrically (before catastrophic failure of the TEC). Thus, failure analysis after life tests is important even if the devices still appear good.

It is a concern to Bellcore that TEC qualification has not received adequate attention by many equipment suppliers. The TEC manufacturers, of course, have developed specific tests and test conditions for their own qualification purposes. In the absence of industry standards (as with lasers), present TEC qualification practices vary considerably.

4. Screening Issues

Qualification testing, which was discussed in relation to specific reliability issues in the preced­ing section, is intended to ensure that lasers meet (the manufacturer's or customer's) specifications and to demonstrate long-term reliability. Other controls are necessary to assure quality and reliability on a lot-by-Iot basis.

4.1 TRADITIONAL LOT-TO-LOT CONTROLS

Traditionally, lot-to-Iot controls include 100% electrical and optical testing, plus environmental screening. Bellcore criteria l81 call for measurement of the following parameters for every laser

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module:

• optical spectrum

- wavelength

- spectral width

• light-current curve

- threshold current

- optical power (at a specified drive current)

- L-I linearity (including dL/dl to detect "kinks")

• monitor operation

- photocurrent (at a specified optical input power)

- photodiode dark current

• TEC operation

- current

- voltage

• component alignment

coupling efficiency

front-to-rear tracking

87

Two environmental screens are called out by Bellcore criterial81 • Laser modules intended for a controlled environment should be subjected to 5-20 temperature cycles (_40 0 C to +70 0 C). In addition to burn-in of the laser diode (and other component parts, as necessary), the completed laser module should be subjected to a 96-hour burn-in at 70 0 C under automatic power control (APC).

4.2 EXPANSION OF SCREENING CONDITIONS

It would seem natural to expand the lot controls for lasers to be used in uncontrolled environ­ments, even if the costs might be slightly increased. For example, the optical measurements should address temperature effects in addition to the traditional key parameters. Likewise, the temperature cycle and burn-in screens should be modified to reflect the possibility of 85 0 C operating temperatures. Many laser manufacturers are not anxious to adopt such proposals, although there is some movement in that direction. However, stringent lot controls are extremely important for some systems in uncontrolled environments. Remote nodes in the dis­tribution feeder portion of the telecommunications network, for example, might consist of a digital carrier system that handles a (relatively) high concentration of lines or channels over a single fiber. A failure of this type of system could result in loss of service for several hundred to several thousand customers; this is a more serious situation than failure of a system in the sub­scriber loop, in which service might be lost for only one to four customers.

In applications, though, low-cost lasers are clearly desired. To achieve laser prices in the range of 50-100 dollars (down from 1988 unit prices in the range of 500-5,000 dollars) several manufacturers argue that lot controls must be reduced in scope. Some manufacturers suggest that no more than one or two key parameters can be measured on a 100% basis. Certain parameters would be reduced to sample measurements; many parameters would simply be

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omitted (except possibly in periodic reliability monitor tests). Similarly, several manufacturers want to eliminate or reduce screening for lasers, both at the sub mount stage and for the com­pleted module.8

4.3 RELIABILITY VS. COST TRADE-OFFS

Clearly, the trade-off between reliability and cost is a central issue for applications such as "fiber to the home" (FTTH). Low-cost lasers are essential to the success of FTTH. Yet, tele­phone subscribers do not want less reliable telephone service. The cost to the telephone com­panies for maintenance (i.e., dispatch of personnel to replace failed lasers) in FTTH is another factor in this dilemma.9 Thus, "cost" must be considered in the context of total life-cycle cost rather than just initial cost.

There are no simple solutions or easy conclusions, as one might have guessed. Bellcore is studying the reliability objectives for FTTH and how they affect the reliability typically needed for the laser. It is hoped that these findings can then be translated into minimum lot control procedures.

AB a preliminary view, it appears that measurement of certain parameters could be optional for specific applications. Measurement of the remaining required parameters might be adequate on a sample basis (after establishing that the distribution of each parameter has sufficient margin with respect to the manufacturer's or customer's specified limits). Minimum screening practices might also be subject to modification. For the laser diode, ACC (automatic current control) burn-in should be performed but APC burn-in could be deferred to module burn-in.1O The APC burn-in of the laser submount and/or laser module might be sufficient on a sample basis. However, a temperature cycle screen should still be performed on a 100% basis.

Comments have been requested from industry on Bellcore's preliminary views of reliability assurance practices for lasers designed to operate in uncontrolled environments. Technical dis­cussions have also been initiated with several laser manufacturers and equipment suppliers on this topic. Bellcore expects to provide additional details, based on these discussions and other feedback, later in 1989.

5. Summary

Operation of lasers in an uncontrolled environment requires reliable performance for device temperatures that can range from _40 0 C to +85 0 C. Daily and seasonal variations within this temperature range add another level of complexity to reliability predictions, which are difficult at best.

Obviously, many reliability problems can be magnified under these hostile conditions. Some

8. Alternatives to these reduced lot controls, such as simplified assembly of laser modules or increased integration of functions in a transmitter module, are under investigation by many laser manuracturers and equipment suppliers.

9. In the United States, the Federal Communications Commission (FCC) has not ruled at the time of this writing whether the optical network interface (ONI), including the laser and detector, is part of the telecommunications network or if the ONI is owned by the subscriber.

10. Bellcore TA-TSY-0004B8 calls for a two-step (ACC and APC) burn-in of the laser diode, which is independent of the laser module burn-in. Elimination of APC burn-in for laser diodes must be carefully considered by manufacturers, though, because it could add to the total cost if much additional drop~out was experienced in laser module burn-in (after the expense of module assembly).

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of the reliability issues include:

• thermal impedance of the laser subassembly,

• optical coupling between the laser and fiber pigtail,

• front-to-rear tracking ratio,

• TEC reliability,

• laser module hermeticity.

Qualification practices that address these reliability issues include specific characterization measurements, elevated temperature life tests and temperature cycle endurance tests for laser modules. In addition, endurance tests for TECs should be performed.

A controversial area that must be settled as soon as possible involves appropriate lot con­trols. Because of the severe conditions that can occur in uncontrolled environments, there is reason for expanding current practices (which have slowly evolved for lasers designed for con­trolled environments). In FTTH and similar applications, however, even the current level of lot controls might not be supported when lower laser costs are a driving factor. Laser manufactur­ers and telecommunications equipment suppliers must identify the highest reliability that can be achieved for "low-cost" lasers. Bellcore and the telephone companies need to establish the minimum reliability required for lasers in specific applications like FTTH. If the two efforts do not show a match between desired and predicted reliability for a given cost, trade-offs will have to be explored.

6. Acknowledgements

A number of people at Bellcore have contributed directly or indirectly toward the material presented in this paper. Special appreciation is extended to R. G. Chemelli, R. S. Koelbl, P. Su and B. A. Unger.

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REFERENCES

1. Bellcore Technical Reference TR-EOP-000063, 'Network Equipment-Building System (NEBS) Generic Equipment Requirements,' Issue 3, March 1988.

2. Saruwatari, M., 'Laser Diode Module for Single-Mode Optical Fiber,' in Optical Devices and Fibers - 198-4, North-Holland (New York, 1984).

3. Reith, L. A., P. W. Shumate and Y. Koga, 'Laser Coupling to Single-Mode Fibre Using Graded-Index Lenses and Compact Disk 1.3 pm Laser Package,' in Electron. Lett., Vol. 22 (1986), pp. 836-838.

4. Spencer, James L., 'Calculating Laser Diode Reliability,' in Conference Record Volume Iof the 1988 IEEE Global Telecommunications Conference and Exhibition (GLOBECOM '88), IEEE Cat. No. 88CH2535-3.

5. Bellcore Special Report SR-TSY-001369, 'Introduction to Reliability of Laser Diodes and Modules,' Issue 1, May 1989.

6. Mitomi, Osamu, et aI., 'Highly Reliable Optical Components,' in Rev. Elect. Comm. Lab., Vol. 33 (l985), pp. 977-984.

7. Cassidy, Daniel T., 'Front/Back Tracking in InGaAsP Diode Laser Transmitter Modules,' in J. Lightwave Tech., Vol. LT-6 (1988), pp. 1395-1398.

8. Bellcore Technical Advisory TA-TSY-000468, 'Reliability Assurance Practices for Optoelec­tronic Devices,' Issue 2 (July 1988).

9. Su, P., and B. A. Unger, 'Temperature Cycling Tests of Laser Modules,' presented at Semi­conductor Device Reliability - Advanced Research Workshop II, sponsored by the NATO International Scientific Exchange Program, at Heraklio, Crete, Greece, June 4-9, 1989.

Several Bellcore documents are referenced in this paper. Technical Advisories (TAs) describe Bellcore's preliminary view of generic requirements. To obtain TAs, write to:

Bellcore Document Registrar 445 South Street - Room 21125 Morristown, NJ 07960-1910 United States of America

To obtain other Bellcore documents (such as Technical References and Special Reports), con­tact:

Bellcore Customer Service 60 New England Avenue - Room IB252 Piscataway, NJ 08854-4196 United States of America Telephone: (201) 699-5800

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91

Hermetic Sealed Package Rear Facet Monitor

Ferrule Fiber Lock

Lenses LD

DO\> B Temperature

r---------------------~~ensor

Cooler Circuitry

Figure 1. Typical Laser Module Design

SPHERICAL LENS

SAPPHIRE WINDOW

'GRIN' ROD LENS

Figure 2. Two-Piece Cylindrical Module

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92 rCD LASER

~

CONNECTOR J

Figure 3. Low-Cost Laser Package

30.0

T .., 15°C

Ac = 1325.0 nm L'>Arms = 1.24 nm

1300.00 1306.3 1312.5 1318.8 1325.0

WAVELENGTH (nm)

-

-

-

-

I

T "'14°C

Ac = 1321.6 nm L'> Arms = 4.8 nm

I 1I..L..I..I1 U-IJU ~ 1300.0 1306.3 1312.5 1318.8 1325.0

WAVELENGTH (nm)

Figure 4. Change in Laser Spectral Width With Temperature

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ACTIVE REGION ......... ..:;;;..----r"'~

Epoxy

COPPER BLOCK

,

Figure 5. Typical Laser Diode Submount

Solder

Figure 6. Photograph of Laser Modules With Different Fiber Locking Techniques

93

Welding

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94

bias = 30.2 rnA

-.~ "C a.. CI) Co • ~ 0 bias = 20.5 mA • - -('II -- -- --- .. - -- -• • •• • ::l • - • -Co - -::l 0 - •• - . .. •• - - - • .c - - - • • • C)

::::i •• • CI) • • >

'';:: ~ bias = 18.5 mA - -CI) a: .. - -- --- • • -- • - • • -

- •• • • - • •

Relative Position (- 0.43 )lm per div)

Figure 7. Front-to-Rear Tracking Versus Fiber Position (Solid curve = coupled front facet output; Dotted curve = rear facet output detected by monitor)

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Example LEAD WIRE

BiTe -5~=nFlm==jji:......,."....-_=_--_ ELEMENT

CERAMIC

Figure 8. Thermoelectric Cooler Cross Section

+1 EXAMPLE

o~------------~~~------~----~

-1 -40 -10 20 50 80

TEMPERATURE rC]

Figure 9. Front-to-Rear Tracking Error

95

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96

Figure 10. Magnified Photograph of Degraded Thermoelectric Cooler

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COMPONENT BURN-IN: THE CHANGING ATTITUDE

FINN JENSEN The Engineering Academy of Denmark DK-2800 Lyngby Denmark

AB STRAcr. This paper addresses some of the changing attitudes to component burn-in that have become evident over the past ten years. On the one hand many equipment manufacturers now no longer request burn-in of semiconductor components due to the overall improved quality and reliability of components available from most vendors. Also, many have become aware of the inherent dangers of inducing damage in otherwise healthy components in the burn-in area. On the other hand, when burn-in is deemed necessary, such as on many state-of-the-art devices, many manufacturers now make an effort to monitor for failures during the bum-in in order to plan the most effective burn-in durations. A technique for evaluating which failure patterns can be dealt with effectively in a week of burn-in is outlined in the final section of the paper.

1. Introduction

In a recent discussion with a major independent test-house in Europe it evolved that the mainstay of their business, the high-volume semiconductor component burn-in, was rapidly slipping away. This change has come about because the equipment manufacturers, Le. the test-house customers, have realised that they might have been mis-spending their money by requiring bum-in on mature semiconductor components. This change, then, is a direct result of the ongoing efforts of the component vendors to enhance the quality and reliability of their products. Using corrective action techniques on their production lines the component manufacturers have over the years reduced the number of inherent defects or flaws that are the root causes of the early-life, freak failures.

97

A. Christou and B. A. Unger (eris.), Semiconductor Device Reliability, 97-106. © 1990 Kluwer Academic Publishers.

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2. Freak failures and mature technologies

It is useful to dwell a little on the nature of component failures and what we actually are trying to accomplish by component burn-in.

In general, the purpose of component bum-in is to eliminate weak. components that have a high risk of failing during early life under normal operatings conditions. These component failures are called freak. failures.

The weaknesses come in many forms, but they are nearly always caused by inherent flaws or defects, i. e. some kind of in-built "damage" in a very broad sense. The flaw might be mechanical, such as a weak. wire bond, a cracked chip, or a flawed metal1isation line. It might also be of a physical or chemical nature such as the presence of contaminating ions at or near the chip surface.

One recently advanced hypothesis [1] suggests that all failures in components working under a fixed set of operating and environmental conditions are due to wearout. Wearout describes the deterioration of component strength that takes place when a component is subjected to a constant or time changing load. The terms wearout and deterioration are used synonymously. In a "perfect" component, utilized within its capabilities as regards current, voltage, and temperature, failures will not occur. It is the presence of imperfections, or flaws, in a "practical" component that will lead to failure under normal operating conditions. It becomes reasonable to suggest that the wearout or deterioration of component strength is the result of flaw growth. It then becomes a question of degree, i. e. flaw size and growth rate, whether the failure will be in early or late life.

The concept of component failures being due to a wearout process not only for end-of-life failures but also for early and mid-life failures has also previously been mentioned in the literature [2]. [3]. [4], [5], [6], [7].

The ideas suggested above might eventually lead to a better understanding of why component lifetime patterns actually look as they do. Although we recognise that component technologies and component failure mechanisms best should be treated individually, it is nevertheless enlightening sometimes to discuss a broader picture such as the one illustrated by Figure 1 [8].

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~OO

"'--..

I~ ~ LONG-TERM ;EAR~?r

1\/:\ " ~ ~ I \ Ix" r--... ~ ~ \.

250

'200

ISO

\ ""- '---. "'-" tOO

~' """ LA'rE Ft::;-

~ ~ so ~

'\ 25

to to~ 104 10' TIME HOURS

Fig,1. Possible median lives of classes of failure with a tri-modal distribution superimposed at 125 <>C, [8].

......

to'

99

This illustration shows the basic lifetime performance for ICs in general as a function of junction temperature, We need not at this point worry about the validity or otherwise of the Arrhenius equation (the two slopes illustrated correspond to activation energies of O.4eV and 1.0eV respectively),

The main reason for showing this picture is to illustrate that ICs often show three "lumps" of failure over their lifespan: the early freaks (often called "infant mortality"), the late freaks, and the long-term wearout,

The early freak failures are often caused by quite severe mechanical type damage as might occur in the bonding and encapsulation of the device, They should of course be eliminated by process control at the vendor's plant, and, indeed, recent experience would seem to indicate that these ~ freaks do not exist with reputable component vendors working with a well established production line,

The late freaks are a bit more elusive, Their failure pattern would indicate that they occur far out in time, For example, the median life suggested by Figure 1 at 12SoC is about 5000 hours, If you go down to, say, 500 C the median life is around 4 '106 hours or more than 400 years! If the picture therefore really shows the status of

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failures in mature technologies, the late freak: problem is virtually non-existant in most practical applications. Also, a "standard" bum-in at 12SoC lasting for 168 hours will just not catch up even with the lowermost tail of the late freak: population.

All-in-all, the consensus as regardS burn-in of mature technology components from reputable vendors is: don't do it. it is just not effective!

But, some OEM's argue, we have been using burn-in for many years on many of our Ies and we always fail a number of these components in a standard bum-in, so it must be doing some good. The comment to this kind of statement is, of course, that yes, it may be doing some gOOd, but only if you are buying really poor quality components with an early freak: population. More likely, the situation will be such that the burn-in process itself is generating severe weaknesses that fail components early. Unger, [9] gives an excellent account of the inherent dangers of component bum-in on mature devices.

A 1988 study by the ESSER parts committee (Environmental Stress Screening of Electronic Hardware) in the U.S. addressed the usefulness of component reb urn-in [10]. especially of military rcs. I quote from the summary in the report:

"The participating OEMs retemperature cycled more than 70.000 devices ... ~ were due mainly to handling damage and electrical overstress. This study does not support retemperature cycling of military Ies, although retemperature cycling of large die Ies may be beneficial" .

The report goes on to say in its final summary:

"Results of the parts committee report show that most devices are defect free, and that supplier/OEM teams can systematically resolve correlation and quality issues. Supplier and OEM commitment and alliances are the key to successful implementation of long term quality and reliability improvement, leading to a ship-to-stock program. "

These findings correlate well with various studies performed by the IC manufacturers themselves [11].

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3. State-of-the-art devices

The burn-in situation can be quite different when we turn to state-of-the-art devices, VLSI, etc. Going towards sub micron technologies invariably brings back some of the earlier difficulties in manufacturing flaw-free devices [12]. However, if burn-in is being considered then it needs to be considered carefully. By this is meant that as much information as possible must be sought on the inherent failure mechanisms and lifetime patterns of the freak failures that need to be eliminated (the early freaks). The word "inherent" should be stressed, as we do not wish to make some of the same mistakes cited above for the mature technologies by letting the burn-in process itself induce fatal damage in the components.

The time-to-failure pattern in the chosen burn-in environment should be evaluated carefully by monitorini the performance during burn-in as closely as possible. Of course, it is impossible to perform continuous monitoring of all functions of a device, but a basic testing for "sign-of-life" is strongly recommended [13]. Fortunately, with some of the burn-in chambers that have been developed over recent years (Kineticon, Scantest) this requirement is not as utopic as it would have seemed ten years ago.

The next section gives an example of how to use the so-called sequential burn-in technique [14] to find out if it is possible with any degree of effectiveness to eliminate an early freak population within an allotted one week of burn-in.

4. Sequential burn-in

The sequential burn-in technique is a burn-in process (steady-state temperature or temperature cycling) that uses a "waiting period" or failure-free period as a stopping rule [14]. A batch of components is loaded into the burn-in chamber at time zero (see Figure 2) and their performance is monitored. At some point a pre-computed failure-free period is detected and at this point the bum-in is stopped and the components are taken out of the chamber. Using the technique you are able to state at a certain statistical confidence level that there are, say, no defective components (i. e. freaks) left in the batch.

We will use the mathematics of the technique to compute a set of curves that will allow us to evaluate how well we can perform burn-in, allotting for example a total of one week (168 hours) to the process. What kind of freak failure patterns can we expect to eliminate within this time period?

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102

~ Total burn-in time T;a -I

I 1 t t • ~ ~ t t=O Failures Failure-free period TW

Fig. 2. Illustration of burn-in using a failure-free period. TW' as a stopping rule.

The input information necessary to use the sequential bum-in technique is a knowledge of the failure pattern of the early failure population. i. e. the early freaks. The pattern will often be described by a Weibull distribution. but the following example will assume that the early freak population. PC%. is exponential. that is the Weibull shape parameter is beta=1. An underlying assumption of the technique is that the early freak population is well separated from the next part of the lifetime pattern (the late freaks or the main. long-term wearout population).

The necessary computations follow the techniques of [14] using the tables of the book "in reverse". Figure 3 shows an example of a chart that can be generated in this manner. You allow yourself one week expected total burn-in time. Ta. you wish to

state with 90% confidence that there are no early freaks left in the batch at the end of the burn-in. For a given batch size and early failure percentage. PC' the chart tells that your requirements can be fulfilled only if the MTTF of the freak population is less than the value shown on the bottom scale.

An example: Your batch size for bum-in is 1000. You expect 0.5% early freaks (5000 ppm). Only if the freak failures have an MTTF less than 38 hours (as read off Figure 3) can you expect to eliminate them all within. one week of burn-in.

Results such as this should at least make you think seriously about the effectiveness of a short-term burn-in. The early freak population has to be very early indeed if you are to stand a chance of eliminating the freaks using the bum-in times and temperatures commonly favoured in industry still. that is typically 24-168 hour at temperatures in the range 125-155 degrees centigrade.

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1Gr---------------------------------------~

3ATCH SIZE

O.'5~

5000

0.1 ~------------------------------~~~--~

24 25 30

MTTF OF LARLY' FREAKS

I , , I I I I I I I I 13~

HOuRS

Fig. 3. Chart showing which early freak populations can be eliminated with 90% confidence in an expected one week of burn-in.

\03

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5. Conclusions

What, then, are the changing attitudes?

First: The continuing improvement in component quality and reliability has more or less rendered traditional component bum-in superfluous, at least as far as mature technology devices are concerned. The situation is different for the evolving technologies. However, only if there is clear evidence of inherent weaknesses that may lead to early freak failures should component level burn-in be considered. There is always the danger of subjecting devices to unwanted, and harmful, stresses during handling and testing in a bum-in process.

Secondly: More and more companies have come to realize that only by monitoring the failure development during a bum-in can they hope to evaluate the effectiveness of the screen. A strong recommendation is to always monitor burn-in (go/no-go, sign-of-life). The failure patterns generated should be used to tailor the bum-in to the particular products.

6. References

1. Jensen, F., "Component Failures Based on Flaw Distributions". Proceedings Annual Reliability and Maintainability Symposium, pp.91-95, Atlanta, Georgia, 1989.

2. Pitetti, R.C., "Electromigration of TiPdAu Conductors". Proceedings of the 10th Annual Reliability Physics, pp.171-174. 1972.

3. Mead. P.H., "Reliability Growth of Electronic Equipment". Microelectronics and Reliability, Vol. 14. pp.439-443. 1975.

4. Nash, F.R. et.al., "Selection of a Laser Reliability Assurance Strategy for a Long-life Application", AT&T Technical Journal, Vol. 64, No.3, pp.671-675. March 1985.

5. Gerling,W., "Factors Contributing to Early Life Reliability". NATO Advanced Research Workshop on Semiconductor Device Reliability, Helsing0r, Denmark. 1985.

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6. Intel, "Component Quality/Reliability Handbook", Intel Corporation, 1986.

7. Wong, K.L. and Lindstrom, D.L., "Off the Bath-tub onto the Roller-coaster Curve". Proceedings Annual Reliability and Maintainability Symposium, pp.356-363,1988.

8. Peck, D.S. and Trapp, O.D., "Accelerated Testing Handbook". Technology Associates, 1981.

9. Unger, B.A., "Early Life Failures". Quality and Reliability Engineering International, VolA, No.1, pp.27-34. 1988.

10. Institute of Environmental Sciences, "Integrated Circuit Screening Report". November 1988.

11. Naumchik. P., "Burn-in of Integrated Circuits ... Required or Not?". Signetics Report,1988.

12. Woods, M., "Reliability in MOS Integrated Circuits". NATO Advanced Research Workshop on Semiconductor Reliability, HelsingIZIr, Denmark, 1985.

13. Parsons, R., "Semiconductor Device Burn-in. is there a Future?" Quality and Reliability Engineering International, Vol.2, NoA, pp.255-258, 1986.

14. Jensen. F. and Petersen. N., "Burn-in: An Engineering Approach to the Design and Analysis of Bum-in Procedures". John Wiley and Sons Ltd .• Chichester, England. 1982.

105

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BIOGRAPHY

Finn Jensen is a g-aduate of the Technical University of Denmark, where he received his Ph.D. in electronics engineering. Dr. Jensen spent four years working in industry before becoming an independent reliability consultant in 1974. In addition to his private consulting practice, Dr. Jensen has for many years held a part-time research position with the Engineering Academy of Denmark, heading government-sponsored projects on burn-in, reliability indicators, field-failure studies, and lifetime properties of electronic components.

Finn Jensen has since 1981 presented reliability seminars for the George Washington University Continuing Engineering Education Program in the United States and in Europe. He is chief editor of the journal Quality and Reliability Engineering International published by John Wiley and Sons , and has co-authored two books on reliability. He is at present gathering material for a new book on electronics reliability screening.

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STATISTICAL MODELS FOR DEVICE RELIABILITY; AN OVERVIEW

J. 110LTOFT The Engineering Academy of Denmark [)epartment of Electronic ami Elect.rical Engineering Akademivej, Building 451 DK-2800 Lyngby Denmark

ABSTRACT. In reliability engineering it is necfCss;uy to ,,':ombine physiccll causal models with statistielll models. The classical statistical model is tile constant hazard rat.e model. \"hich has proven in many cases to \lr> too simple. A decreasing hazard rate is often observed and t.his may be modelled in several ways. Furthermore as t.he submicron t.echnology is emerging w'earout phenomena may be observed. ThE sit uat ion j s further complicated when more than one failure meehan'isms are acUng Silllll1i,a­

r.eously. And finally a device may by defined in several ways dppenrtf'llt c,n the viel,point taken. This paper present·s nw defini tinns of ;1 rieY1c(-' and ',~Olllpa1:es and disc1lsses several statistical models to b~ applied. These models enccmpass single as well as Ilmltipl" failure Ilwchanism cases. The models :u·e i.llustrated hy examples.

1. INTRODUCTION

Failu:res in devices are only of interest. if t.hey occur :,r are expectp,] to occm' in equipment under use conditions. This simple statement is often overlooked ,,;hen the reliability of dc·vices an' und"r ,:(,nsidel'''' ation. A part.i.cular good example is the use of l'eliahilit.y st.ress screening (RSS) either at the device or at the system level. R~;" lIlelY be necessary. but if the design of the stress conditioning is not focusing ')!l the failure mechanisms 1 ikely to develop under field condi t ions thp system reliability may not be improved even if a lot of fai],rres are ,hserved under the RSS!! Ihis is the reason \\ihy in so !l1d.ny cases getlPral ievice !{SS' s done by t he device manufacturel apparently have no f'ff pct .

Thf> statement abcAE; is quite nature}] for equipment OlanufactUters ,,1 though they may not be aI,'are of it.. For d device llIanufdctUl'eJ the ;tatement is true as well. but the devices are used 'ill so many eli ff"l'pnt applications t.hat. the statement becomes more distant. Quit.e ofter. it' is unfortunately regarded as academic. IIm,ever, this should not be the ':Clse if reliability problems are to be solved.

107

A. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 107-125. © 1990 Kluwer Academic Publishers.

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In consequence any reliability model for a device must describe the failure development of the device under field conditions. This means that an adequate model must include not just the inherent flaws in the device but also the induced flaws and eventually a wrong or partly wrong application of the device.

Furthermore device failures may be caused not only by "catastrophi­cal" events but by degradation in functional performance as well.

A model or a set of models that covers the field failure develop­ments of devices and take into account all contributors to the failure development is a necessary prerequisite for solving reliability problems.

This paper outlines and discusses the capability to describe the field failure development of some of the available statistical device reliability models. The emphasis will be laid on the model.s developed within the last decade.

2. CONCEPTS AND DEFINITIONS

2.1 "Devices" and "sockets".

A lot of confusion is caused by differences in the understanding of what is included in the term "device". In some cases a device is defined as the item delivered by the device manufacturer. In othp.r cases the inter­connections to the surrounding components are included as ,,,ell.

As mentioned in the introduction the starting point must be the field conditions. After a system has failed in the field it is repaired by l'eplacement of the device that has caused the failure. The repair includes the inter"connections of the device as well. If for example the system failure is caused by an integrated circuit and the interconnec­tion technology is soldering of the Ie leads onto a printed ci rcuit the replacement of the Ie cannot be performed without the unsoldering of the "defect" Ie and the soldering in of the replacement Ie.

Furthermore -still from a field failure point of view- the devices have been t.hrough the system assembly process since they left the device manufacturer. During this process they have been handled as ,,'ell as interconnected. Both are capable of inducing flaws which later in t.he field may develop into a failure in the device. The interconnecting joints themselves may be flawed which may leael to a replacement of the device.

Finally the application of a device differs from system to system and within a system. This influences the field failure deve.1opment. and has to be taken into account as well.

Therefore from a field failure paint of view

a "device" consists of a body, its leads and its interconnection joi~ the surrounding circuit and it is located to a specific ,pOSi­tion in a system type.

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The quotation marks are introduced in order to separate this (ex­panded) definition from the traditional definition limited to encompass the component body and its leads. In the following the difference between the quotated and the plain term is to be observed.

This very stringent definition may be loosened dependent on the purpose of analysis to be carried out. If for example a device type is used in several positions in a system the outcome of an analysis inc lud­:mg all these positions will be an average reliability for the "device".

From a "device" point of view a component position is a nonrepail'ed item, because the faulty "device" after the repair no longer exists.

However, from a systems point of view the component position still ioxists. but in a repaired state. This calls for another name for the <;omponent position as well. The name used in the liter:ature is "socket", although a socket may not exist. A "socket" is the simplest form for a repaired item.

The present "device" defini.tion seems to exclude the possibility of attributing a reliability measure to a particular device type, because the device may be used in a vadety of differ:ent designs and because it may he interconnect.ed equally many different ways.

Fortunately this is not the case. On the contrary it may be poss­ible to describe the inherent reliability of a component, because models oased on this definition may lead to methods of analysis by which the "noise" in t.erms of assembly and application relat.e(i effect.s is screened lway leaving the inhel'ent device reliabili ty open for assessment.

2.2 "Device" reliability concept.s. 1)

The concept of "device" reliabilit.y is clearly expressed in t.he defini­tion:

The ability of the "device" to perform a requit'ed function under' stated conditions for a stated period of time.

The three key phrases are underlined and are equally important. This definition leads to the tradit.ional probabilist.ic measure of

"device" reliability

( 1 )

which says that the reliability is the probability, p, of having an act.ual lifetime (L act) great.er than the st.ated period of time L. The word "lifetime" means t.hat the "device" under consideration performs the required function under stated conditions.

1) O'Connor [1]; M¢1toft [2]

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I'he lifetime t OLC' of a "device" can be both shorter and longer than

T. Having a specific "device" in our hands, we cannot tell how long Tact

would be for that particular "device". This means that the lifetime is a stochastic variable which has an associated probability distribution that may be characterized by one or more parameters. One of the purposes of a reliability analysis is to estimate these parameters and their dependancies on the failure causes.

Probability distributions are usually expressed in terms of the cumulative distribution function c.d.f. or the probability density func­tion p.d.f.-In the present case we have the c.d-:-f. for the lifetime­expressed as

F(T) = PCT,,,,! ~ T)

This st.ates the probability of having a lifetime shorter than or equal to the stated period of time. As a "device" either performs its function or not, we have

Fer) = 1 - ReT.)

because the total probability cannot exceed one. The corresponding p.d.f. is

JCT) = d F(T) dT

While the p.d.f. is seldom used, a further measure that is often used in reliability technology is the hazard or failure rate function

NT) hCT)=~

RCT)

The failure rate h(T) expresses the conditional probability such that:

hCr)' dT is the probability that the "device"

will fail in the coming time interval de given that it has survived the stated period of time T.

(2)

(3)

(4)

(5)

For small values of T where R(T) is close to unity, the p.d.L and

the hazard rate function are almost identical. As R Ct) decreases \"i th time hCT) and J(T) differ more and more (except if they both have zero as limiting value).

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1\1

In recent years the cwnulative hazard function

f"<

H(T,) = ! h(T,)dT, Jo

(6)

has been used more and more. This is because the data for reliability analysis of electronic "devices" are characterized by few failures com­pared with the (large) number of survivors. This makes hazard plotting easier than c.d.f. plotting without losing the ability td extract distribution parameters.

When dealing with probability distributions it is common to deal with at least two measures, the mean or average value ~ and the standard deviation 0 or variance 0 2 . 1 )

Using the formulas for the first moment about the origin and the second moment about the mean we get

~- i T,f(T)dT, .10

(7)

(8)

in which we have substituted minus infinity with zero as the lO\ver inte­gration limit because the lifetime cannot be negative.

The standard deviation is simply the square root of the variance. In reliability engineering the mean value is often known as the

mean time t.o failure or MTIT. However, no othtn' measure has lean to so many misconceptions. so the author prefers not to use the term MTTf a.nd will stick to ~ instead.

2.3 "Socket" reliability concepts.

As mentioned in section 2.1 a "socket" is the simplest repaired system that exists. However, t.he important feature compared with a "device" is that it is repaired when a failure occurs. This means that a "socket" experience:. a series of events namely failures ann repairs. In between these events are periods of operation and peri.ods of rest.

It. is common to regard the periods of :::est as periods when' fa; lure mechanisms do not develop. This may not be true and dormant failure development. is under investigation at present.

However, for the majority of cases the failure mechanism develop­ment under rest is so much slower t.han under operational conditions that it is acceptable to disregard the rest periods in the analysis.

The result of this discussion is that a "socket" experiences a series of events (failures) separated by operational time at Il'hich the "device" is "at. risk".

1) l!iller and Freund [3)

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112

When a failure occurs the faulty "device" is completely substituted by a new "device" taken from the same population as the old one. In other words the "socket" is "as good as new" after a repair in contra­diction to its mother system. This situation is termed as a renewal process and is well described by the renewal theory.2)

Although it is outside the scope of this paper it shall be men­tioned that a system can be desribed by a superimposed renewal process in which the system is regarded straightforward as the sum of its "sockets". Recently the theory of superimposed renewal processes has been successfully transformed into practical use by Jensen et. al. (l (89) [5].

According to the renewal theory a suitable reliability measure for a "socket" is the mean number of failures 2> (m) of the "socket" as a function of the operational time (t). Furthermore the renewal theo!"), yields the expression

met) = Iss' t ... d.;. E(t) (9)

in which Iss is the time independent failure intensity in the steady

state (late) period, d is a time independent constant and Eet) is a time dependent term that characterises the transient (early) period of the failure development.

The steady state failure intensity [ss is related to the "device" reliability by

1 I =­

s. 11

The constant d is related to the "device" reliability by

(10)

(11 )

The last term has in most cases a rather complicated relation to the reliability of the "device". However, fortunately its limiting value for increasing values of t is always zero, that is

limE(t) = a (12) t->~

Another reliability measure for a "socket" is the failure intensity let) which simply is the derivative of met) with respect to t.

1) Cox [4 j 2) It would be lore correct to use the term "renewal', but in the present context" failure" is

acceptable because the replacements are repairs as concequences of failures.

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113

Jet) = dm(t) = I + dE(t) dt s, dt ( 13)

From this equation and equation 9 it is seen that for increasing values of operational time the failure intensity for a "socket" approaches a constant value equal to the steady state failure intensity. Furthermore these equations show that the met) function approaches a straight line which has the slope Iss and intersects the met) axis in d. This line is called the steady state asymptote.

The failure intensity of a "socket" is often mixed up with the failure rate of the "device" in the "socket". This is because the two measures become identical when the lifetime of the "device" follows an exponential dist.ribution, which is often (wrongly) assumed. However, as it seen from the discussion above the failure intensity of a "socket" becomes constant regardless of the time dependancy of the "device" fail­ure rate function!!!

3. STATISTICAL MODELS FOR SINGLE FAILURE MECHANISM CASES

3.1 The general model.

Some of the most often used (and abused) statistical models are based on the assumption that the lifetimes obey the two parameter Weibull dis­tribution function.

The models can be divided into three cathegories: The decreasing hazard rate case. the (classical) constant hazard rate case and the increasing hazard rate case.

Common for the models are as well that they are valid in principle if one and only one failure mechanism is acting in the "device". This condition is often overlooked when the models are appli.ed.

For the two parameter Weibull distribution we have

FCT)= l-exp( -(::y) \ ,11, , (14)

13 (1:)13-r h(1:)=~' ~ (15)

. \~

H(T)=(~) (16)

( 17)

Page 122: Semiconductor Device Reliability

114

( 18)

in h'hlch f3 is the shape parameter (or the Weibull slope) and 11 is the characteristic lifetime.

3.2 The constant hazard rate case.

This is the classical model on \"hich for example ~llL-HDBK-217 predic­tions are based.

As f3 is equal to one the formulas (4) to (18) become very simple. Thus we get a constant hazard rate

1 h("c)=-=A

'1

introducing the symbol'" to describe this case,

( 19)

For the other " device" measures we get. the follo\1iing well knohil formulas

F(c)= l-exp(->--. t) (20)

H(-C)=A-C (21 )

1 Il=-

.~ (22)

In this case we have d= ° as well as E(l)= 0, which means that the "socket" reliability simply is described by the straight line through origin

mCt) = At (23)

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"DEVICE" "SOCKET"

FCT) [~~Weibull)

63.2

10

0.1 T] 1m:

10~ 10 5 10 6 10 7

h(T) [FIT) I(t) [FIT)

300 300

200 200

100 100

0 0

0 10'10 6 20'10' T

0 10'10' 20'10' t

HCT) m( t)

3 3

2 2

o~--------r---------r-~ 20'10 6 t o 10'10 6

T

figure 1. The reliability functions for a constant hazard rate case with A.=200FIT (n=5·10ohours). The failure intensity function ,":"ld the renewal function are identical with respectively the hazard rate function and the cumulative hazard rate function.

115

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116

An example with "- = 200FIF) (11 = 5· lO"hours ) appears in figure 1. As illustrated by the example the "device" and "socket" reliability graphs are identical and no distinction has to be made. This is the reason why in so many cases the failure rate concept has been used for a repaired system instead of the failure intensity concept implicitly assuming a constant failure rate even if it is not the case.

The terms MTTF and MTBF 2 ) are normally used in conjunction with the constant hazard rate case. They are simply the reciprocals of respect­ively the (constant) hazard rate and the (constant) failure intensity. As these are equal the MTTF and the MTBF are equal as well.

In the constant hazard rate case the failures occur completely ran­dom in time. This may happen when good "devices" are subjected to random overload either because of an unexpected load profile, mishandling by the users and/or poor design.

A constant hazard rate is seldom observed, because most designs are good and rather robust for overloads. Normally the random failures are very few and overshadowed by failures due to other causes.

3.3 The decreasing hazard rate case.

"Early" failures haunt the electronic industry. A good design may be swamped by failures due to flaws in the "devices". The flaws may be inherent or induced. Inherent flaws are created before system assembly. Induced flaws are created during and after the assembling process.

Not all "devices" are flawed. Usually the p"robabili ty of having a flaw in a "device" is below 1%. Therefore a repair after a failure caused by a flaw is not likely to introduce another flaw. For this rea­son a decreasing hazard rate model could be a proper description.

The Weibull distribution offers a model for the decreasing hazard rate case. As seen from equation 15 a beta value lower than 1 gives an ever decreasing hazard rate because the exponent becomes negative.

Given the values of f3 and n the "device" reliability functions are calculated easily via equation 14, 15 and 16.

The "socket" reliability functions are very difficult to calculate. This is because no simple mathematical expression is available for the transient part of the m(t) function. However, the asymptote and hence the steady state failure intensity are easily calculated by application of equation 10. 17 and 18. The complete functions can be visualized by simulation as shall be demonstrated below ..

An example with [3=0.7 and Tj=5·10 6 hours (the same value as in the constant hazard rate case) appears in figure 2.

The example illustrates how important in this case it is to distin­guish between the "device" and "socket" reliability. While the failure rate is ever decreasing the failure intensity becomes constant. In this case the steady state failure intensity is 158 FIT (which is amazingly close to the 200 FIT in the constant hazard rate case).

1) 1 PIT : 1 failure per billion hours 2) Mean Time To Failure and Kean Time Between Failure

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117

"DEVICE" "SOCKET"

F (-r) [%Weibull]

63.2

10

0.1 InT 10' 10 5 10 6 1110 7

hh) [FIT ] let) [FIT]

300 300

~ 200 200

100 100

0 0 0 10-10· 20 -1 0 G

T 0 10-10· 20 -1 o· t

H(T) met)

3 3

2 2

T t

Figure 2. The reliability functions for a decreasing hazard rate case with f3 = 0.7 and 11 = 5· 106hours. The failure intensity function and the renewal function are not identical with respectively the hazard rate function and the cumulative hazard rate function.

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118

The cumulative hazard graph and the met) graph are seen to be dif­ferent as well. While the former gradually approaches a horizontal line the latter approaches the asymptote

m(t)= 158.[0-9 .[ ... 0.57 (24)

As it is seen in figure 2 this model implies that the hazard rate and the failure intensity are infinite at time zero. This seems rather theoretical from an engineering point of view. Furthermore it is doubt­ful whether the shape parameter [3 can be linked to some physical Pl'OP­

erties of a failure mechanism. Therefore this model is not particular good to describe real life decreasing hazard rate cases.

3.4 The increasing hazard rate case.

Another type of failure mechanisms are characterized as "wear-Qut" because the associated hazard rates increase with time. This type of failure mechanisms should not cause failures within the llseful life period of an equipment.

However, if an increasing hazard rate failure mechanism is present, the Weibull distribution may offer a model in this case as \,'ell.

A beta value above 1 means an increasing hazard !'flte, sef> f>quat.ioll 15, and the full description of t.he "device" I'eliability is given nncE" the values of ~ and ~ are known.

As in the previous case the "socket" reliability is more difficult to calculate. The asymptote is easy to calculate using equation 10, 17 and 18, but. as above the transient period is left to be visualized by simulation.

An example with f3 = 3 and II = 5· lObhours (the same value as in the two cases above) appears in figure 3.

Again it is seen how important it is to distinguish between the "device" and "socket" reliability. After a few oscillations the failure intensity stabilizes at 224 FIT while the hazard rate continues to increase. The m(t)-graph quickly reaches the asymptote

m(t)=224·1O- 9 ·t-0.43 (25)

while the cumulative hazard function continues to increase with a faster and faster rate. It is worth noticing that the failure intensity again is rather close to the value from the corresponding constant hazard rate case above.

As seen in equation 2S the value of d is negative. This is in gen­eral characteristical for increasing hazard rate cases. Fc}}' decreasi ng hazard rate cases the value of d is always positive.

Page 127: Semiconductor Device Reliability

119

"DEVICE" "SOCKET"

F (T) n.Weibull]

63.2

10

0.1 lnT 10' 10 5

h(T) [FIT] I(t) [FIT]

300 300

200

100 100

0 0 0 10'10 6 20'10 6 T 0 10'10 6 20'10 s

t

H(T) m(t)

3 3

2 2

O~~------r--------'--~

o 10'10 6 20'106 T

O~~------r-------~~"t

Figure 3. The reliability functions for an inereasing hazard rate case with 13=3 and 1l=5·10 6 hours. The failure intensity function and the renewal function are not i.dentical with respectively the hazard rate function and the cumulative hazard rate function.

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120

In contradiction to the Weibull decreasing hazard rate model for the flaw related failures this Weibull model for increasing hazard rates are more succesful in describing "wear-out" related single failure mech­anism cases. However, there is not established any relation between the actual values of shape parameters and the physical nature of "wear-out" failure mechanisms.

3.5 The "flaw" model.

In recent years it has been suggested that all failures are caused by flaws which may be inherent and/or induced. The flaws may have different sizes which should explain the differences in lifetimes.>')

As failures in "devices" are observed to appear in lumps over the time 2 ) a first approximation to a flaw model would be to assume that the flaws could be separated into two groups: Major flaws causing failures early in life and minor flaws causing failures late in life. If the proportion of "devices" with major flaws is called p then the proportion of "devices" with minor flaws will be (l-p). The lifetimes of "devices" with major flaws are described by the c.d.f. FICe). For "devices" with

minor flaws we have similarly the c.d.f F 2(t). This model could be named the "bimodal flaw" model because the

resulting distribution function will be bimodal as follows

fC't) = pf I (e) + (1 - p)f 2C't)

(26)

(27)

(28)

The hazard rate function, the cumulative hazard function and the variance are more complicated to calculate and often it has to be done numerically using the basic equations 5, 6 and 8 respectively.

3.6 The decreasing hazard rate case and the "bimodal flaw" model.

As mentioned in section 3.3 a unimodal Weibull distribution function with f3 < 1 is not a good model. The "bimodal flaw" model offers a more realistic approximation by assuming the two c.d.f. 's to be exponential distribution functions with different values of ~.3)

1) Wong [6] 2) Jensen and Petersen 171 3) Jensen, Kj!rqaard, M¢ltoft and Rimestad [5]

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121

In this case we have

F(T,) = p( 1 - expO,,] T,))+ (1 - p)( 1- exp(A,21:) (29)

(30)

(31 )

A,tA,2 .. 1"=(1 )A, A, ::'PA,j+A,2 -p ]+p 2

(32)

(33)

The approximations are valid for A,] » A, 2 and p « 1 which is often the case.

By these formulas it is possible to sketch the reliability func­tions, which is done in figure 4.

As illustrated by figure 4 the hazard rate is decreasing to a con­stant level (which could be zero if A,2 = 0 ), but in this model it starts from a finite value, which is much more realistic.

Furthermore the m(t)-graph reaches rapidly the steady state which corresponds with observations.

Finally figure 4 illustrates the corresponding S-shaped c.d.f. on the Weibull paper which corresponds with real life observations as well.

Although the exponentially bimodal approximation seems reasonable it is quit.e possible to refine t.he "bimodal flaw" model by using general Weibull approximations for the two distribution functions. 1)

11 Jensen and Petersen [7 J

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122

"DEVICE" "SOCKET"

F(T) [Weibull]

~--------------------------~ lnT

o~------------------~-o T

I(t)

O~----------------~-t o

m(t)

t

Figure 4. The reliability functions for a decreasing hazard rate case based on the "bimodal flaw" model in which the two subpopulations have different exponentially distributed lifetimes. The failure intensity function and the renewal function are not identical with respectively t.he hazard rate function and the cwnulative hazard rate function.

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123

.3.7 Estimation of ~ and a word of warning.

fhe mean lifetime ~ is easy to estimate. By counting the total number of failures r and the related accumulated time "at risk" T for the "de­vices" or "sockets" under observation we get

- T u=­. r

This is in accordance with the standard textbook procedure for estimation of mean values: The observed values of the variable are summed up and divided by the sum of the number of observations. i)

(34)

The estimation yields in reality the steady state (constant) fail­ure intensity for the "socket" (see equation 10) and not a constant .tailure rate for the "device" except in the (rare) cases where the hazard rate function is independent of time (the constant hazard rate case) .

This fact is very often forgotten!! And that is one of the main reasons for misbeliefs in reliability engineering, because the misuse of the estimates have resulted in mismatch between reliability predictions and observations.

4. STATISTICAL MODELS FOR MULTIPLE FAILURE MECHANISMS CASES

In a "device" normally more than one failure mechanisms ar,' in oper­ation. rhey are all "competing" to be the "winner" that makes the "de­\-ice" to fail. This situation is similar to a syst.em in \l7hich the many "devices" are in "competit.ion". Therefore the reliability series oldel for system analysis can be applied for "devices" with "competing" fail­ure mechanisms.

This model is refered to as the competing risk model. 2 ) The model yields the formula

< F(T)= 1- IT(l-F,(I:)) (35)

I,~ i

in which k is the number of failure mechanisms in the "device" and F! (I:) is the c.d.f. for the i'th failure mechanism which may be any distribu­tion in a unimodal, bimodal or multimodal form.

Application of the basic equations in section 2.2 and 2.3 renders it po::.cible to arrive at reliabili ty graphs of the types illustrated in the preceeding chapter. :;:he calculations may be cumbersome in some cases. but it is attainable in part~"ular with the help of the powerful calculators and PC's available nowadays.

1) Mlller and Freund [3], O'Connor [1] 2) M¢ltoft [2] and Jensen [S]

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124

Recently dr. Finn Jensen has demonstrated the applicability of the model extensively in [8] and the reader is recommended to read this important paper.

5. DEGRADATION MODELS

It is often seen that a failure is not catastrophic but due to parameter degradation. However, the reliability society seems not to deal seri­ously with this problem. Degradation models for specific devices are presented and applied from time to time, but very few general models are presented.

Two general models are available, but they have not been proven to be valid by experiments and must for the time being be deemed speculat­ive although they seem quite reasonable.

The Bosch model [9J may be regarded as the one extreme in which the degradation function of a parameter is determined by the initial value of this parameter. Probability measures comes in, because the initial parameter value is not known but given by its distribution function.

The M¢ltoft model [10] may be regarded as the other extreme in which ther are no statistical correlation between an initial parameter value and its drift function.

As mentioned have neither of the models been verified. However, the subject of degradation is too important to be left. over and more work ought to be done.

6. CONCLUSION

An overview of the present status on statistical reliability models has been given.

It is pointed out how important it is to distinguish between a device, a "device" in which the interconnect.ion is included and a "socket" which is the position where the device is mounted and which include repairs.

Furthermore it is stressed that the widely used method for estima­tion of a failure rate for a device is inadequate and leads to wrong conclusions.

Suitable models for single and multiple failure mechanism cases are quoted and discussed. In combination the models seem quite adequate for a description of the observed failure patterns.

Finally it is pointed out t.hat. degradation modelling is a subject. that should be developed in the future.

REFERENCES

1. O'Connor, Patrick D. T. (1985) Practical Reliability Engineering, John Wiley & Sons Ltd.

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125

2. M¢ltoft, J. (1987) 'Statistical Analysis of Data from Electronic Component Lifetests', Active and Passive Electronic Components Vol. 12 pp. 259-279

3. Miller, 1. and Freund, J. E. (1977) Probab:ility and Statistics for Engineers, Prentice-Hall Inc.

4. Cox. D. R. (1962) Renewal Theory, Methuen & Co.

5. Jensen, F., Kjrergaard, C., M¢ltoft, J. and Rimestad, L. (1989) Field Failures, The Engineering Academy of Denmark - Electrical and Electronic Engineering.

6. Wong, K. L. (1981) 'Unified Field (failure) Theory - Demise of the Bathtub Curve', Proceeding Annual Reliability and Maintainab:ilit.y Symposium pp. 402-407, IEEE

7. Jensen, F. and Petersen. N. E. (1982) "Burn-in" An Engineering Approach to t.he Design and Analysis of Burn-in Procedures, John Wiley & Sons Ltd.

8. Jensen, F (1989) 'Component Failures Based on Flaw Distributions', Proceedings Annual Reliability and Maintainabilit.y Symposium pp. 91-95

9. Bosch, G. (1979) 'Model for Failure Rate Curves'. Microelectronics and Reliability, Vol. 19 pp. 371-375

10. M¢ltoft, J. (1980) 'The Failure Rate Function Estimat.ed from Para­met.er Drift. Measurements', Microelect.ronics and Reliabilit.y, Vol. 20 pp. 787- 801

Page 134: Semiconductor Device Reliability

COMPUTER-AIDED ANALYSIS OF INTEGRATED CIRCUIT RELIABILITY

P.MAURI SGS- THOMSON Microelectronics MMD Reliability Laboratory Via Tolomeo 1 20010 Cornaredo (Milano) Italy

ABSTRACT. A computer system which assists engineers in reliability evaluation of integrated

circuits in development is described. A key feature of the computer system is the collection of quantitative data, such as failure times and electrical parameter measurements, and qualitative

data, such as failure descriptions. Quantitative data are analysed by means of "traditional" methods,

e g. statistics, while failure data are stored and analysed using approaches coming from artificial

intelligence applications. The use of computer tools eases data management, enriches data analysis

and suggests the exploration of new reliability evaluation methods.

1 Introduction

The reliability evaluation of Integrated Circuits in development (both bipolar and MOS) exploits a large amount of data that the engineers analyse by using several kinds of cogni­t ive and methodological tools. For instance the implementation of reliability tests requires knowledge of electronics and physics and information about device features and field op­erating conditions, the interpretation of test results is performed by means of statistical methods, the analysis of failed devices is performed by means of electronic and physical models integrated with expertise and skill.

To support data management and to improve the analysis and evaluation processes a computer system has been designed following the key idea of grouping, in the system ar­chitecture, software procedures that use some of the several approaches involved in the reliability evaluation and formalize them by means of different techniques.

The role of the system is not only to assist the present activities but also to support the exploration and the implementation of new models and methods.

2 The system architecture

As described above the architecture of the computer system was conceived to store quan­titative and qualitative data and to analyse them with procedures corning from methods often applied, e.g. statistics, or new approach such as qualitative and quantitative simula­tion.

There are two main activities the computer can assist: reliability evaluation and failure

127

A. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 127-136. © 1990 Kluwer Academic Publishers.

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128

analysis. These activities have different goals and exploit partially different cognitive processes

continuously exchanging a large amount of information. Hence the whole system, as shown in figure 1, is partitioned in two modules oriented towards the two different goals: the Diagnosis Assistant for failure analysis activities and the Reliability Assistant for re­liability evaluation.

Diagnosis Assistant

Reliability Assistant

Figure 1. The overall design of the computer system.

The Diagnosis Assistant, which is at an advanced design phase, is described in [4]. This paper details the Reliability Assistant that is already employed in production. In the Reliability Assistant, sketched in figure 2, data and procedures are partitioned

in the following main modules:

• Data Base Maintenance to manage input/output of quantitative and qualitative data about devices, reliability test conditions and results. The test results are failure times, electric parameter measurements and qualitative descriptions of failure modes and mechanisms in the form of causal chains.

• Statistical analysis to analyse quantitative data, i.e. failure times and parameter measurements. Most procedures are designed to study electrical parameter drifts that describe the functional behaviour and the degradation trends of the devices during the stress test.

• Failure data analysis to search for regularities in the events of causal chains. This microscopic and causal knowledge can integrate the macroscopic results of statistics and help in failure analysis activity. The logical structure of the failure data base and the analysis procedures are influenced by methods coming from artificial intelligence applications.

• Reliability models to evaluate and forecast integrated circuit reliability by using stored data, knowledge and results of analysis modules.

The modules of the computer system are connected to the "outside" and to one another by an interface. The open architecture of the system allows a continuous updating and enrichment not only of data but also of procedures. Data base maintenance and a set of statistical procedures are already everyday tools for reliability engineers, failure data anal­ysis is at an advanced prototyping stage and reliability modelling is in the design phase.

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Next sections detail the four modules of the system.

Maintenance and

Reporting

Statistical Analysis I

n t

Failure e r

Data f Analysis a

c e

l_

Synthesis and

Models

Figure 2. The architecture of the Reliability Assistant

3 Reliability data

The first step in the design of the computer system was the definition of types of data that are relevant for reliability evaluation and then the design of the logical structure of the data base [1] [2]. This stucture is mainly oriented towards reliability requirements in the perspective of the integration of a structural reliability modelling tool with process control. Figure 3 shows a simplified example of the data base structure.

Information on device features, such as die size, metallization, passivation glass etc. are stored in the module "I.e. sample". This data grid is used to describe a device in devel­opment submitted to reliability evaluation. Following reliability requirements the device description is strictly connected to the sampling used in stress tests and any change in attributes defines a new entity. In such a way the system can record a change of reliability results even between different lots.

The stress test operating conditions are described in term of setting variables such as voltage, temperature, time of cycling, etc. These variables changes according to type of test (figure 3 shows them for H.T.R.B).

On the contrary, the description of results is the same for all tests and encompasses times of failure, electric parameter results and descriptions of failed devices.

Readout times and failures are directly stored in the "Results" segment, that is linked with "Datalog" and "Failure analysis" data bases. "Datalog" contains electrical parameter results for every sample item at every control time. The data model records information on items, on measurements (name, unit, limits) and on results.

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130

I.C.sample

Code Date Plant Process Size Metal Passivation Package Dieattach Frame Bonding Molding

I

I I ,

Setting

H.T.R.B.

Code

Date

Engineer

I

Results

V-supply T-ambient T-junction Sample-size

Time Failures Datalog !Failure-anal.

Datalog I

Code I

I

Date

Test I Results

Name I Item Units I Test Limits Value

Figure 3. An example of the logical structure of the Reliability Data base.

Besides these quantitative results of reliability test the data base is conceived to store some qualitative result of failure analysis. The logical structure of the failure data base, shown in figure 4, follows the main features of final diagnosis assessment: ~ite of failure (Where), failure mode (How) in terms of electric parameter degradation and of physical damaging, failure mechanism (Why) and the device flaws which induced the failure (What).

All these segments of the data base contain an attribute called Judgement where the subjective evaluation of the expert, Le. the "degree of truth" of the stored sentence, is syn­thesized in the form of a score. The top segment links the failure description to reliability tests and to device features.

This logical structure was conceived as a simplification of the engineer's causal thinking: "vVhere", "How", "vVhy" and "What" can be viewed as rings of a causal chain that describe the results of a diagnosis activity performed by means of complex reasoning processes [6].

Figure 5 shows the representation of a failure description where the sentences are stored following the data base structure. Note, in particular, the "vVhy" segment can be repeted many times for a better explanation of a failure mechanism and it is possible to store "and" / "or" connectives.

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Failure Anal.:

Code

Item

Where How Why !

Site Description Description I Description Notes Notes

Judgement Judgement Judgement I

What

F eature

ction

udgement

A

J

Figure 4. The logical strucure of the Failure Data Ba.se.

I

Pad 4 :

WHERE

Open i I

Circuit HOW

Aluminum !

Corrosion HOW

Phosphoric I Acid Formation I

I WHY ~

~hosphorus Humidity !

III Penetration Passivation WHY

No package

Hermeticity ; WHY

Resin I Defects I

I I WHAT

Figure 5. A causal chain in failure description.

131

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The first module of the computer system was released for production use after the im­plementation of the user inteface. An easy human-machine interaction is a key feature of the system because data maintenance is performed directly by engineers who can not spend time on software management. The interface has a menu-driven structure and data maintenance is performed by means of input screen as shown in figure 6.

I GLL I fJ9/fJI/89 FAILURE A~LYSIS ISGS - THOMSOl~ I CASTELLETTO

F _A_ id : TRD2P13 ITEf1 : 21 LJHERE: t'ETAL !'EAR T22 PH r10DE: Key descr-' ipt ion ALUMINUM CORROSION

Not.es Score 5

1.IHY : l\e8 descriplion PHOSPHOR IC Ae ID FOR~IATIDN Notes

Score 4 ArlO/OR

D Where EH E lecl. How PH Ph\J51C.How WT WhaT

F4 EXIT F2 TOP F8 VALUE LIST

Figure 6. An example of input screen for Failure Analysis Data. The upper part of the screen displays data already stored (Internal code, Failed Item, Where, How). The middle part contains the description of the failure mechanism. The lower grid contains functional keys.

4 Statistical analysis

The procedures of the statistical analysis module are used for the interpretation of quanti­tative data, i.e. failure times and electric parameter measurements. Particularly for devices in development, failure times represent the least significant part of data, while parameter measurements have great importance because they describe in depth the functional be­haviour of devices over the stress test time.

For this reason most of the studies are devoted to the analysis of the parameter results. Univariate analysis and fitting techniques are applied to results selected by control time

and parameter type. Reliability engineers use them to test normality of distribution, to estimate statistical parameters and to explore non-normally distributed data.

To study trends over the control times the engineers can choose among several analysis methods: drawing the parameter drift for every item of the sample, plotting statistical parameter, like mean and standard deviation, or applying regression procedures.

Statistical analysis results can be helpful to reveal early signs of degradation process.

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Furthermore, threshold values for parameter drift can integrate the definition of "failure time" based only on catastrophic events [5].Figures 7 and 8 show some output of statistical programs.

OEVI CE NAME : WO 3 0

PlutAl1ETER : Re G ODBM lK

VAIUABLE=TlMEO

N MEAN STD DEV SKE'WNESS USS CIl

T :ME.AN=O SGN RANK NOM "= 0 D:NORMAL

QUANTILES (OEF=41

100% MAX 75% Ql 50% MED 25% Q1 0\ MIN

RANGE Ql-Q1 HODE

STEM LEAF -0 3 -0 6 -1 -1 865 -2 2211 -2 -3 32 -3 6 -4 430 -, 9988 -5 4433 -5 98875 -6 443220 -6 988888 -7 443310 -7 876 -8 41

-0.003 -0.051 -0.068

-0.0885 -0.12

0.117 0.0375 -0.068

-8 98777765 -9 4332200 -9 966

-10 2 -10 8665 -11 4 -11 07

--+- I

99% 95% 90% 10'

5% 1%

I

RELIABILITY TEST : SLT

UNIT: DB TESTING TE1-lP.

UNIVARIATE

MOMENTS

'77 -0.0674156

0.0275959 0.383065 0.407831 -40.934 -21.437 -1501.5

77 0.0767204

-0.003 -0.0159 -0.0218 -0.1026 -0.1086

-0.12

SUM \'KiTS SUH VARIANCE KURTOSIS CSS STD MEAN

PROB> ITI PROB> IS I

PROB>D

77 -5.191

.000761536 -0.399652 0.0578767

0.00314485 0.0001 0.0001

) .15

MULTIPLY STEM.LEAF BY 10"'·-02·

figure 7.Univariate analysis of a parameter results.

25 c

EXTREMES

LOWEST -0.12

-0.117 -0.114 -0.108 -0.106

HIGHEST -0.018 -0.016 -0.015 -0.006 -0.003

BQXPLOT

I I I I I I I I I I

+--+ I

I I .-~*

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\34

PARAMETER: RC G ODE UNIT: DB TIME (h): 2500

DIS !NT 15 1.11 14 ~~-

8.9 " ' 13 I "-/ \

11.8 12 I \ I ,

11 I \ fl.? I

III I , I \

9 , \ H.6 I ,

8 I , I \ 8.5 ? , , , \

6 I \ 11.4 I , 5 I \

I \ H.3 4 J , I \

3 J , 8.2 I ,

2 I , , I ... 11.1 , ... 1 , ..... fI

I "'-- ... - H.O

-tl. 13 -0.08 -0.03 0.02 fI.H?

X

Figure S.Fitting for non-normal distribution of a parameter values.

5 Failure data analysis

The analysis of qualitative results stored in the failure data base can help diagnosis activities and enrich reliability assessment, partially overcoming the limits of a reliability evaluation based only on statistics [3].

A set of procedures record regularities among the events of the cause-effect chain and uses them to build a knowledge base which the failure analyst can employ as support during the diagnosis.

For reliability evaluation, the failure data can be used as selection criteria: for instance, in failure rate estimation, the results can be grouped according to failure mode through stress tests. Moreover the statistical analysis of parameters that gives a "macroscopic" description of device behaviour can be confirmed and controlled by the results of the failure analysis that explores in a " microscopic" way the failure process.

6 Reliability modelling

The procedures of the "Synthesis and models" module could assist in the formulation of a total assessment. The project choice is to support the analysis with a set of computer tools implementing several reliability models and not to constrain the engineer to follow a predefined modelling path.

A goal is, for example, to support an "a posteriori" evaluation by aggregating data according to different criteria such as structural similarity or failure mechanism and then by analysing reliability results with a set of different models and methods. The interface

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selects the stored data by using criteria that are each time defined by the reliability engineer and the selected data can be analysed by means of well known methods, such as parameter models for failure times, or by means of new procedures wich take into account the results of statistical analysis of parameter values.

The possibility of exploring the history of I.e. performance can be helpful also for the preliminary reliability estimation of new devices on the basis of structural similarity.

7 Man-machine interactions

The procedures of the described system are everyday tools for reliability engineers. The major returns of the computer aid to reliability activities have been the following:

• the improvement of data management, in particular through the automatic transfer­ring of parameter results which saves time and avoids human errors in data entry

• the enrichment of data analysis by means of powerful computational tools

• the suggestion of new approaches for reliability evaluations

• the availability, in data and knowledge bases, of device history and expert know-how.

A long term interaction between the data analyst and the reliability engineer was nec­essary to achieve these results through the computer system development.This interaction was performed during all phases of the project, from early design steps to user training.

8 Conclusions

This paper describe the main features of a computer system designed to assist the reliability evaluations of integrated circuits in development (bipolar and MOS).

The computer system was conceived to store quantitative and qualitative data and to analyse them with procedures coming from methods often applied, e.g. statistics, or new approaches such as artificial intelligence.

The data management module and a set of analysis procedures already support engi­neer's activities, improving the data analysis and suggesting new evaluation approaches.

Work in progress is oriented towards a deeper analysis of electrical parameter measure­ments and a modelling of reliability performances which takes into account the several types of information and knowledge stored in the system.

9 Acknowledgements

My thanks to reliability laboratory engineers. Their knowledge and experience feed the computer system and their everyday activity is the best test for the computer tools.

My thanks also to Prof. Finn Jensen for his comments to an earlier version of the paper.

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136

References

[1] Blaha M.R., Premerlani W.J., and Rumbaugh J.E. (1988) Relational database design using an object-oriented methodology Communications of the ACM, 414-427, April 1988.

[2] Gillenson M.L. (1987) The duality of database structures and design techniques Com­munications of the ACM, 1056-1065, December 1987.

[3] Harris L.N. (1985) The rationale of reliability prediction Quality and Reliability Engi­neering International Vol.1, 77-83.

[4] Mauri P., Mussio P., and Piccoli 11. (1987) Design of an automatic system for failure analysis in integrated circuits Second Workshop on AI and Simulation- AAAI.

[5] Moltoft J .,(1980) The failure rate function estimated from parameter drift measure­ments Microelectronics Reliability, Vol.20, 787-802

[6] Yung-Choa Pan J., and Tenenbaum J.M. (1986)PIES: An Engineer's Do-It-Yourself Knowledge System for Interpretation of Parametric Test Data AI MAGAZINE, 62-69, Fall.

Page 144: Semiconductor Device Reliability

RELIABILITY ASSESSMENT OF CMOS ASIC DESIGNS

M. S. Davies Dept. of Electrical & Electronic Engineering University of Leeds Leeds LS29JTU.K

P.D.T. O'Connor British Aerospace Dynamics Group PO Box 19, Six Hills Way Stevenage SG18JU U.K

ABSTRACf. A methodology is presented which aims to improve CMOS ASIC reliability. It differs from conventional reliability assessment techniques as it is based on an understand­ing of CMOS failure effects at the circuit-level. The first step of this approach requires a yield and failure analysis programme of CMOS ASIC::S to be established. The programme results are then used to simulate the effects of CMOS failures at the circuit-level and evaluate test patterns. The final step uses this knowledge to provide guidelines for test pattern gen­eration and fault coverage comparisons.

1. Introduction

The reliability assessment of electronic system designs based on application specific integrated circuits (ASICs), in particular CMOS ASICs, has become an important issue. Conventional methods used in this type of assessment usually include stress analysis (thermal and electrical), reliability prediction, failure modes, effects and criticality analysis (FMECA), and testability analysis. These methods are restrictive when applied to designs which employ CMOS ASICs as the analyses are not all conducted below the pin level. This is undesirable as reliability, safety and testability concerns are critical at the circuit-level of the ASIC design.

The rapidly expanding CMOS ASIC market and technology advances have both contributed to the introduction of reliability risks. Risks arise as some ASIC manufacturers have been slow to adopt yield and failure analysis techniques to investigate CMOS failure mechanisms and failure modes pertinent to their manufacturing process. Little work has been carried out on determining the relative failure mode probabilities at the circuit-level.

Another risk arises due to the applicability of the stuck-at fault model often used in VLSI test pattern generation and fault simulation CAD packages. It has been shown that CMOS failure modes are inadequately modelled by the stuck-at fault model (1,2). This results in the non-optimisation of ASIC yield testing and reliability. Generated test patterns may not detect the presence of physical CMOS failures which cannot be modelled by the stuck-at fault model; consequently, faulty ASICs may be delivered to the customer. More effective test pattern generation approaches need to be developed to ensure the detection of likely CMOS failures. Due to the strong correlation between the fault coverage and the reliability of manufactured ASICs, the detection of non-stuck-at faults will effectively increase the

137

A. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 137-146. © 1990 Kluwer Academic Publishers.

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138

reliability of the shipped device and improve yield testing.

This paper describes the work undertaken to obtain a better understanding of CMOS ASIC reliability issues. Since the work is currently in progress, the paper describes developments to date and achievements expected in relation to reliability optimisation due to consideration of the effects of realistic failure modes. The work is presented as a structured methodology with its main emphasis being channeled towards the reliability improvement of CMOS ASICs. The approach is intended to be integrated with existing VLSI design CAD and can be tailored to a specific manufacturing process.

2. The Methodology

The methodology aims to improve the reliability of CMOS ASICs. The approach differs from that of reliability prediction as it attempts to reduce the likelihood of failures rather than obtaining a measurement of reliability. Also, it is based upon understanding the tech­nology and establishing yield and failure analysis programmes for data acquisition; whereas, reliability prediction often uses inaccurate data and models. The methodology can be divided into three steps.

2.1. YIELD AND FAILURE ANALYSIS DATA ACQUISITION - STEP ONE

The first step of the methodology involves setting up yield and failure analysis programmes to investigate failures on CMOS processed wafers, packaged devices and returned field failures. Such an analysis programme is underway using a British Aerospace CMOS ASIC design. The analysis work is being carried out by British Telecom Materials and Com­ponents Centre on CMOS ASIC processed wafers and packaged devices. The purpose of this programme is to investigate and identify the sources of the most likely CMOS ASIC failures and assign their relative likelihood of occurrence.

The motivation behind this step is attributable to the wide variations that exist between reported relative incidences of failures. These variations are understandable as failure mechanisms are dependent upon many variables e.g. environment, manufacturer, manufac­turing process, circuit complexity, test and quality control procedures. In order for reliability assessment and improvement approaches to be useful they both require recent, specific and accurate failure mode information.

2.2. CIRCUIT-LEVEL SIMULATION - STEP TWO

The second step of the methodology centres around circuit-level failure simulation and tes pattern evaluation of CMOS cells and sub-modules used in the ASIC design process (3,4,5). The evaluation is a necessary operation as it identifies if realistic CMOS failures can be detected by test patterns generated by a proposed algorithm.

Circuit-level fault simulation overcomes the inadequacy of the stuck-at fault model and the problems associated with CMOS fault representation at the gate-level. The results of step one identified likely and realistic CMOS failures which can be modelled and simulated at the circuit-level to enable the definition of CMOS fault types. Effective test patterns can be gen­erated for these cells to expose classical (stuck-at), nonclassical (non-stuck-at) and hard to detect failures.

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The simulations are achieved using SPICE and Pre-SPICE Insertion of Faults (PSIF). SPICE (Simulator Program with IC Emphasis) was developed by the University of Califor­nia, Berkeley (6). PSIF is a pre-processor module to SPICE that has been developed by the authors. This module automatically includes faults into SPICE CMOS circuit description files. Electrical element fault models for open and short circuit failure modes can be included into the SPICE circuit file of the CMOS cell under investigation. The open and short circuit fault models are resistive or capacitive in nature depending upon the failure mechanism and failure mode being modelled. Similarly, PSIF modifies SPICE level-3 MOS­FET model parameters in the circuit description file to enable SPICE to simulate the effects of MOSFET degradations (7). Care must be taken when modifying MOSFET parameters due to their interdependencies and correlations (8).

Short circuit (node-short), open circuit (line-open) and MOSFET degradations are the basic fault primitives considered by PSIF. A SPICE-like fault description language is used to include required faults at user definable positions within the circuit file. PSIF uses this file to modify the circuit topology, include the fault model and create a faulty circuit description file amenable for SPICE simulation. Then SPICE simulates the faulty circuit description file to show the effect of the fault introduced into the cell. Failure Modes Effects Analysis (FMEA) is executed on the SPICE results and FMEA are tables generated for each cell that is simulated. The tables contain information on the location and effects of the failure mechanisms and failure modes simulated for each cell. Together, PSIF, SPICE and FMEA form the second step. The interaction between step one and step two is show in figure 1.

TEST PAITERNS

YIELD ANALYSIS

COMPARE SPICE

FMEA TABLES

PARAMETER E>."TRACTlO:-'

FAILURE AMLYSIS

COMPARE

Figure 1. The interaction of step one and step two.

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140

Some researchers favour the switch-level representation of CMOS circuits for simulation purposes (9,10). Test patterns generated at this level give a much greater assurance that faulty circuits are correctly identified and rejected, hence increasing the reliability. By using PSIF and SPICE with a switch-level test pattern generator fault simulation and test pattern evaluation can be achieved. However, a major drawback is that SPICE simulations are com­putationally time consuming compared with less accurate switch-level and gate-level simula­tors.

2.3. STEP 1HREE

Step three of the methodology capitalises on the knowledge embodied in the FMEA tables to analyse the behaviour of more complex VLSI circuits. An ASIC design comprises of a number of interconnected standard cells. FMEA tables can be generated for each cell used in the ASIC design using the second step to provide information on likely fault effects. A fault list, which can be obtained from the tables, containing the relative likelihood of each fault can be passed to a test pattern generator to ensure that the most likely faults are tested for first and the least likely last. Studies can be made on the fault coverages of differently derived test pattern sets to ensure that the most realistic fault model is chosen for the partic­ular process under investigation (see figure 2).

This procedure of simulating the effects of realistic CMOS failure modes and provision of ranked fault list provides the knowledge needed for efficient test patterns to ensure the delivery of more reliable ASICs to the customer.

RANKED/ORDERED FAULT LIST

{ r- TEST PATTERN

GENERATOR i-

~ ~ ~ ~

NON-CLASSICAL CLASSICAL FAULTS FAULTS

{ { TRANSISTOR GATE LEVEL

LEVEL SIMULATOR SIMULATOR

~ FAULT COVERAGE ,.A-ASSESSMENT ~

Figure 2. Step Three.

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141

3. Results

The example results and problems encountered with implementing each step are presented in this section.

3.1. STEP ONE

At the time of writing this paper the British Telecom yield and failure analysis work, outlined in 2.1, was still in progress. For the purpose of this paper the failure mechanisms and failure modes in table 1, which are not specific to any manufacturer or process, will be used (11,12,13). The table identifies open circuit, short circuit and MOSFET degradations as being the most common failure modes. It only serves as an indication of the most likely sources of CMOS failures and it has been assumed that they have equal likelihood of occurrence, are catastrophic and unrecoverable, have a random distribution across the chip and are intrinsic rather than extrinsic in nature.

When the analysis work has been completed these assumptions will be reassessed and ques­tions such as:

1) Which failure mechanism causes a particular failure mode?

2) What is the probability of a failure mechanism causing a failure mode?

3) What is the relative probability of each identified failure modes?

will be answered. Also, results will provide insights for process improvements and design alterations which will help to build-in reliability.

Table 1. CMOS failure mechanisms and failure modes.

Failure Mechanism Type Failure Mode. Electromigration wear-out opens / shorts Corrosion random/wear-out opens/shorts Microcracks random opens Oxide defects infant/random shorts Contamination infant/wear-out degradations Contacts wear-out/infant shorts Implant defects infant/random degradations Silicon defects infant/random degradations Interconnect defects infant opens/shorts Soft errors random degradations Hot electrons wear-out degradations Slow trapping wear-out degradations Surface charge infant/wear-out shorts spreading Charge loss infant/random/ degradations

wear-out Photolithography infant/wear-out opens/shorts/ dependent degradations

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3.2. STEP TWO

The effects of likely failure modes in basic CMOS cells have been simulated using this step of the approach. Following each set of simulations FMEA was executed and FMEA tables were generated for each cell. Table 2 shows the faults that were simulated for a simple NAND gate (see circuit diagram in figure 3). Open and short circuit failure modes have been simulated. The correspondence between physical failures and logical faults was made in the table. Logical faults occurred at the inputs A or B, the output F, or the power line VDD•

A--_---1 4

--~---+---F

B-~~-----~ 1

3

Figure 3. NAND gate circuit diagram.

Short circuit failures between nodes results in the creation of extra conductive paths. This type of failure was modelled by including the parallel resistor electrical element fault model available in PSIF (typical value 1 0) Short circuit failures were simulated between the termi­nals of each MOSFET. However, there is a strong possibility of shorts between nodes at other positions in the circuit, e.g. electromigration between aluminium lines. Possible candi­dates for this type of fault have been simulated. Cell layout information is required to postu­late the likely positions for this type of short.

Open circuit failures result in the removal of conductive paths. These results were obtained using the series resistor model (typical value 1 MO). All the open circuit failures were simu­lated at the terminals of the MOSFET transistors. Any open circuits that occur in the aluminium lines of the cell would, effectively, be translated to a terminal of a MOSFET transistor in the circuit-level simulation.

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143

The results given in table 2 indicate the majority of failures in the NAND gate could be modelled as stuck-at (s-a-1/0) faults. However, gate-to-drain and shorts between two neigh-bouring nodes could not be modelled by the classical stuck-at fault model or by stuck-open type faults. Non-classical faults were introduced which caused a logical effect type fault. A gate-level model that represented the logical behaviour of the physical circuit would not be able to emulate this type of fault. The logical operation of the physical circuit had changed and a different gate-level model would be required. More accurate gate-level fault models have been proposed (1,4). However, some authors favour accurate circuit-level simulation of cells used in a constrained design methodology, with circuit partitioning, and use of a hierarchical fault simulator (14).

Table 2. CMOS NAND gate simulation results.

Source FET Logical Fault Fault Class Comment 1 Short Gate-Drain T3 B s-a-notB Nonclassical Logical Effect 2 Short Gate-Source T3 F s-a-1 Classical Stuck-at 3 Short Drain-Source T3 B s-a-1 Classical Stuck-at 4 Short Gate-Drain T1 Fs-a-A Nonclassical Logical Effect 5 Short Gate-Source T1 F s-a-1 Classical Stuck-at 6 Short Drain-Source T1 A s-a-1 Classical Stuck-at 7 Short Gate-Drain T4 F s-a-A Nonclassical Logical Effect 8 Short Gate-Source T4 No Effect 9 Short Drain-Source T4 F s-a-1 Classical Stuck-at 10 Short Gate-Drain T2 F s-a-B Nonclassical Logical Effect 11 Short Gate-Source T2 No Effect 12 Short Drain-Source T2 F s-a-1 Classical Stuck-at 13 Short Node 4-2 F s-a-A Nonclassical Logical Effect 14 Short Node 7-9 No Effect 15 Open Gate T3 F s-a-l Classical Stuck-at 16 Open Drain T3 F s-a-1 Classical Stuck-at 17 Open Source T3 F s-a-l Classical Stuck-at 18 Open Gate T1 F s-a-O Classical Stuck-at 19 Open Drain T1 F s-a-l Classical Stuck-at 20 Open Source T1 F s-a-l Classical Stuck-at 21 Open Gate T4 F s-a-O Classical Stuck-at 22 Open Drain T4 No Effect 23 Open Source T4 No Effect 24 Open Gate T2 F s-a-1 Classical Stuck-at 25 Open Drain T2 No Effect 26 Open Source T2 No Effect

The choice of model resistance for either the short or open circuit failure modes was critical. If the model resistance was too high for the short circuit parallel resistor model then inter­mediate or indeterminate (X) voltage levels (neither logic 1 or 0) appeared at the output of the gate. Effectively, the inclusion of the high resistance model simulated t?e ~ehav~our o~ a partially short circuit. Similarly, if the resistance was too low for the open CIrCUIt senes reSIS­tor model intermediate or indeterminate voltage levels appeared at the gate output. The inclusion of the low resistor model simulated a partially open circuit.

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The FMEA table for the CMOS NAND gate was generated from the results (see table 3). However, the same questions, which were asked in section 3.1, need to be answered to accu­rately complete the FMEA tables. For completeness speculative answers have been given in table 3.

Table 3. CMOS NAND Gate FMEA Table.

Component

n-type MOS FET T1

n-type MOS FET T3

p-type MOS FET T4

p-type MOS FET T2

Aluminium Lines Aluminium Lines

Failure Mode

Short Gate-Drain Short Gate-Source Short Drain-Source Open Gate Open Drain Open Source Short Gate-Drain Short Gate-Source Short Drain-Source Open Gate Open Drain Open Source Short Gate-Drain Short Gate-Source Short Drain-Source Open Gate Open Drain Open Source Short Gate-Drain Short Gate-Source Short Drain-Source Open Gate Open Drain Open Source Short Node 4-2 Short Node 9-7

Table 4. Test pattern evaluation.

Test A B Fault F13 Pattern Free A 1 0 1 1 B 0 1 1 0 C 1 1 0 1 D 0 0 1 X(1.5)

Possible Cause of Failure

oxide defects/ contacts/

interconnect electromigration/

microcracks/ corrosion

oxide defects/ contacts/

interconnect electromigration/

microcracks/ corrosion

oxide defects/ contacts/

interconnect electromigration/

microcracks/ corrosion

oxide defects/ contacts/

interconnect electromigration/

microcracks/ corrosion

Electromigration Electromigration

F14 FlO

1 0 X(3.8V) 1

0 X(3.9V) 1 X(1.5)

System Effects

F s-a-A F s-a-1 F s-a-1 F s-a-1 F s-a-1 F s-a-1

B s-a-notB F s-a-1 B s-a-1 F s-a-1 F s-a-1 F s-a-1 F s-a-A

No Effect F s-a-1 F s-a-O

No Effect No Effect F s-a-B

No Effect F s-a-1 F s-a-1

No Effect No Effect F s-a-A

No Effect

Fault Detected FlO F13 F13 F14

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145

Logical type effects and intermediate logical outputs have been identified as likely failure effects in CMOS circuits. The effectiveness of some test patterns applied to the NAND gate with realistic faults induded can be seen in table 4. The results confirm the inadequacy of the stuck-at fault model for modelling real CMOS failures. The generated FMEA tables form a knowledge base that can be referenced, modified, and expanded as more simulations are completed and when yield and failure analysis data becomes available.

3.3 STEP THREE

Step three of the methodology is currently being developed to automate the analysis of larger ASICs which have been designed with cells which have had FMEA tables generated. It is hoped that a future paper will present the results of the application of the methodology on an ASIC design, presenting results of the fault coverages of differently derived test patterns and with ranked fault lists. A recent publication indicated that some tests identified up to 12% of know faulty chips as being fault free (15). Faults occurred that were not able to be modelled at the gate-level. The final step of the methodology capitalises upon the knowledge embo­died within the FMEA tables to provide an ordered fault list to help generate effective test patterns and to enable fault coverage assessments to be made.

4. Conclusions

A structured methodology has been presented which can be used to investigate the effects of failures on CMOS cells or sub-circuits. This is achieved using relevant and applicable data at the circuit-level which avoids higher level abstractions. It attempts to overcome problems associated with the stuck-at fault model and provides a route for test pattern evaluation.

However, it has been recognised that FMEA, employed in step two, has two main drawbacks i.e. a lack of formal connection with any subsequent reliability analysis and the considerable amount of knowledge accumulated during a FMEA becomes superfluous and neglected after reliability analysis completion (15). The FMEA information forms a knowledge base that will be exploited by the last step to overcome the problems outlined above. This will enable the investigation of larger and complex ASIC circuits designed using standard cells, for which FMEA tables have been produced. Currently, more work is needed to help automate step three of the methodology to exploit the FMEA knowledge.

This methodology will aid the improvement of CMOS ASIC reliability via realistic failure simulation and effective test pattern generation of the CMOS cell building blocks of the design process and exploitation of the knowledge gained.

REFERENCES

1) Wadsack, R.L.,'Fault Modeling and Logic Simulators of CMOS and MOS Integrated Circuits', 1978, Bell Systems Technical Journal, Vol. 57, No. 2,1449.

2) Galiay, J., Crouzet Y., and Vergniault, M, 'Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability', 1980, IEEE Trans. on Computers, C-29, No. 6.

3) Abraham JA, and Shih, H., 'Testing of MOS VLSI Circuits', 1985, Proc. Int. Symp. on Circuits and Systems, 1297.

4) AI-Arian, SA, and Agrawal, D.P., 'Physical Failures and Fault Models of CMOS Cir­cuits', 1987, IEEE Trans. on Circuits and Systems, CAS-34, No.3, 269.

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5) Renovell, M., Gambon, G., and Auvergne, D., 'FSPICE: A tool for fault modelling in MOS circuits', 1985, INTEGRATION, the VLSI Journal, Vol. 3, 245.

6) Vladimirescu, A, and Lui, S., 'The Simulation of MOS Integrated Circuits Using SPICE2', 1980, Memo. No. UCB/ERL M80j7, University of California, Berkeley.

7) Burgess, N., Damper, R.I., Shaw S.1., and Wilkins, D.R.1, 'Faults and fault effects in NMOS circuits - Impact on design for testability', 1985, lEE Proc. Pt. G, Vol. 132, No. 3,82.

8) Gribben, A, Robertson, J.M., and Walton, AJ., 'Accurate Physical Parameter Extrac­tion for Small Geometry Devices', 1986, SEMI CON.

9) Shih, H., and Abraham, AJ., 'Transistor-level test generation for physical failures in CMOS circuits', 1986, Proc. IEEE 23rd Design Automation ConL

10) Agrawal, P., 'Test generation at switch-level', 1984, Proc. IEEE Int. Conf. in Computer Aided Design.

11) Fantini, F., 'Reliability Problems with VLSI', 1984, Microelectron Reliability, Vol. 24, No.2.

12) Edwards, D.G., 'Testing for MOS Integrated Circuit Failure Modes', 1984, Proc. IEEE Test ConL

13) Mangir, T.E., 'Sources of Failures and Yield Improvement for VLSI and Restructable Interconnects for RVLSI and WSI: Part I - Sources of Failures and Yield Improvement for VLSI', 1984, Proc. of the IEEE, 72, No.6, 690.

14) Rogers, W.A, and Abraham, J.A, 'CHIEFS: A concurrent hierarchical and extensible fault simulator', 1981, Proc. IEEE Test Conf.

15) Burgess,N, Damper, R.I., Totton, K.A, Shaw, S.J., 'Physical faults in MOS circuits and their coverage by different fault models', lEE Proc, Vol. 135,Pt. E, No.1, Jan. 1988.

16) Pages A, and Gondran, M., System Reliability - Evaluation and Prediction in Engineer­ing, North Oxford Academic, 1986.

Page 154: Semiconductor Device Reliability

MOOELS USED IN UNDERSEA FIBRE OPTIC SYSTEMS RELIABILITY PREDICTION

R H Murphy

STC Submar i ne Systems Christchurch Way

Greenwich LONDON

SE10 OAG UK

This paper describes some of the Models used for c~nent and system reliability prediction in the context of undersea optoelectronic regenerator modules. Practical results of the application

of these models are presented in conjunction with a discussion of their limitations and ongoing deve l opments.

I NTROOUCTI ON

Undersea fibre optic communications systems comprise extremely long lengths (up to 8000 i<ms) of single mode light guiding fibres paci<aged (as 1-4 fibre pairs) in strong cables. In order to

overcome the attenuating effects (ci rca 0.2 to 0.4 dB/km, according to wavelength) in these light

guides, optoelectronic regenerators in repeater housings intersperse the cables at 60 to 120 km intervals. Each repeater contains 2-8 regenerator modules and there can be more than of 1000 of

these modules in a typical long-haul system.

The function of each regenerator module is to receive, re-time and regenerate the long wavelength

infra-red light pulses in non-return to zero (NRZ) format, at data rates (currently) up to 560

Mbit/s. Such systems are capable of handl ing at least 7,500 simultaneous telephone channels per fibre pair (i .e. more than 30,000 channels per system). They also provide a medil.ll1 for wide-band

services such as very high speed data l inks, video/fast fax services, etc. and do not suffer from the transmission delay/echo problems endemic in satellite services.

As a di rect result of the need for long term maintained security of these fibre-optic systems,

together with the very high cost of recovery/repair and loss of revenue in the event of prolonged

unavailability, such systems are required to be ultra-reliable. In spite of the fact that they must employ rapidly advancing c~nent technology to handle the ever-increasing traffic capacity demands, a typical system must meet a rel iabi l ity specification of no more than 2 or 3 repeater replacements as a consequence of regenerator failure during a 25 year design life. In other

words, the cumulative hazard per regenerator for a long haul system must not exceed 0.2 to 0.3% (say 1 fai lure in 300 to 500 modules) per 25 years, which would be equivalent to 9 to 14 FITs

total average fai lure rate over this period if no redundancy of any form were employed. However, there are of necessity, 10-20 active c~nents (advanced ICs,optolectronic transmit and receive modules) and over 100 passive c~nents (thick film resistors and multilayer ceramir. capacitors plus Surface Acoustic Wave - SAil - Fi l ters) in each of these regenerator modules. Hence the best

147

A. Christou and B. A. Unger (eels.), Semiconductor Device Reliability, 147-160. © 1990 Kluwer Academic Publishers.

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anyone can demonstrate, and provide statistical evidence for to a 90 or 95% confidence level, as demanded by the system customers, is a 1 to 2% 25 year cUlUlative hazard (equivalent to 45-90 FITs) per regenerator_

Apart from electrical and optical power density stresses experienced by the components, the undersea envirorvnent is, of course, relatively benign, and there are several redundancy schemes that can be employed to overcome the mismatch between the required and currently demonstrated regenerator cUlUlative hazards enunerated above. Never-the-less, the ultimate requi rements in terms of the per component cUlUlative hazards (i .e. those for combined early-life and wear-out failures) remain more severe than those in any other sphere of professional electronic equipment dep l oyment •

COMPONENT ACCELERATED TESTING

The rel iabil ity growth progranmes for undersea communications system components [1] involve the following major tasks, which must be rigorously adhered to for "state-of-the-art" devices as they emerge from the development laboratories:

Ul tra-careful design and manufacture with a premium placed on individual device traceabil ity to homogeneous batches of materials and piece-parts.

Very severe device screening (burn- in, etc) to remove as much as possible of the potential early life failure population in the system and to identify batch-related defects so that complete batches of suspect components may be el iminated.

Accelerated (overstress) testing to predict the onset of major fai lure mechani sms and/or parameter drift beyond acceptable limits for system performance.

Long term operational life testing, often for periods up to 2 years under moderately accelerated test conditions, which is used in conjunction with the severe overstress tests to characterise the remaining early life failure population and confirm that the ultra-low design life fai lure rates are achievable in the system envirorvnent.

Several million unit-hours of accUlUlated life test experience on each of a wide variety of active and passive components, and many tens of thousands of repeater-years actual operating experience on analogue/early digital-optical repeaters have confirmed the short-comings of the classic bath­tub failure rate model for components and systems. This experience has led to strong concurrence with other authors [2,3] that, at least under the well controlled conditions of accelerated/ operating life tests and for the relatively benign envirorvnental conditions of undersea system operation, the classic random or constant failure rate of the bath-tub si~ly does not exist. Given ultra-careful component and regenerator manufacturing procedures, all fai lure rate distributions are, at most, bi-modal, and the corresponding cUlUlative distribution functions (Cdfs) are S-shaped, with a pronounced 'plateau' where the random-stress related portion should be. This is illustrated by the mixed Weibull plot shown in fig (1), which happens to be for a severely overstressed zener diode, but is representative of a wide variety of submerged repeater (SR) active and passive components subjected to accelerated life testing.

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The following points of c~rison with a schematic representation of a I"ixed lIeibull edf drawn

from a classic bath-tub curve (shown inset) are extremely relevant to the present discussion:

Fig 1 Zener diode Weibull Cdf @ 250°C.

%

50

10

1.0 50% I

/r>--~1

::~ 01 1'-1

Hours

0.1

,,' ". 0.01

ClassIc bathtub for comparison

10 10' Hours

The early life (rogue, or infant mortal ity) regime usually has a shape parameter (p) greater

than unity, and hence indicates an increasing fai lure rate, but a limited population at risk. \lithout the latter constraint, it would of course be impossible to screen-out these early life fai lures, but note that the widely held bel ief that screening is impossible unless the early life fai lure rate decreases with time, is obviously disproved_ The mixed \leibull Cdf does

have a transition from the early life regime to the plateau, but does not show a sustained decreasing fai lure rate portion_ This transition occurs in the region where the sub­

population of weak devices rapidly depletes to zero_ On the relatively few occasions where a decreasing early life fai lure rate has been observed, the transition has not been to a plateau, but di rectl y to the wear-out phase.

The constant fai lure rate regime, as stated above, is absent_ This obviates the necessity to

carry out the extremely dubious practice of applying stress-related acceleration factors (see below) to random fai lure rates (expressed in FITs) or to accumulated overstress life test experience (expressed in unit-hours)_ Only time, or more specifically median/characteristic

lives can be accelerated via overstress.

It is admitted that the wear-out regime, taken in isolation, more usually fits a log-normal

distribution than a \leibull Cdf. However, from many viewpoints, this is the least important part of the curve, because related acceleration factors are usually very much higher than those for early-life failures and hence extrapolation to use conditions produces median/ characteristic I ives of several thousands of years. The phi losophy adopted is that unless standard tests of significance [4] positively disqualify the \leibull representation for this regime, it may be employed without significant risk to system reliability predictions.

Amongst other things, this philosophy simplifies the mathematics for obtaining overall life

predictions.

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150

Another point to note when planning an accelerated l He test is that many components (eg les, Receive Modules) do not function correctly under severe overstress (e.g. high operating t~rature) conditions, and hence the stresses experienced are unlikely to be truely representative of use conditions. This sets a limit to the amount of stress that can be appl ied, and attempts should always be made to first explore the stress·time to failure relationship from a device function/failure physics viewpoint. This is conveniently done via step·stress experiments, which also serve, when performed on a representative sample per batch basis, to screen-out entire sub-standard batches. Rel iabi l ity programne managers are often criticised for wishing to see the occurence of fai lures on l He tests, and are seldom bel ieved when they state that tests producing failures yield more information, and often ~ optimistic reliability predictions, than those that produce zero fai lures. The reason for this apparent anomaly is that tests that produce fai lures are at optimised high stress levels and provide very relevant information on the ways in which components can fail; consequently information on believable acceleration factors. Those that produce zero fai lures provide (almost) zero relevant information, and worst-case acceleration f actors must be assumed.

Fig 2 - Translation of mixed Wei bull Cdt to lower temperature

% 250°C 100°C ~ 1.0eV

50 (AF = 7600)

10

1.0

0.1

0.01

10 102 103 104 105 106 107 108 109

Hours

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151

One major advantage of the mixed lIeibull edf representation of a high tenperature overstress

bimodal distribution is that separate acceleration factors may easily be applied to the early-life and wear-out regimes in isolation_ These acceleration factors are derived from the well known

Arrhenius relationship, which in decimal logarithmic 'form may be conveniently expressed as follows:-

log (A_F_) 5.04 Eac.M •••• ,_ (1)

IIhere: A.F. = Acceleration Factor t1/t2, the ratio of times to failure at the low and high tenperatures, respectively.

Ea = Activation Energy of relevant failure mechanism (eV)

c.M= M, - Ml. = 1000 ~

respectively.

1000 T1.

T1 & T2 being the low and hightenperatures (Kelvins)

This is equivalent to translating (in time) the characteristics of the two regimes, as shown

schematically in fig (2). Because the Ea for the wear-out regime is usually higher (circa 1.0

1.8 eV) than that for the early-life failure regime (circa 0.4 - 1.2 eV) this translation usually leaves only the early life regime at use condition (2-40·e Operating case temperature) in the time-frame relevant to system deployment (0-100 years). It might seem strange that early-life

regimes are projected to last, in many cases, for up to 100 years, but:

The term refers to the early-life of the component, not the system, and components which are projected to take several thousand years to wear out at normal tenperatures can, by definition from the bimodal nature of the characteristic, exhibit early life failures up to this time.

In conjunction with the postulated absence of random failures, it is inferred that the early

life failure population, although a finite proportion of the entire population, cannot be el iminated by a screen of shorter (equivalent) duration than the time it takes to reach the plateau, and at relatively low operating tenperatures this can easily extend beyond the design life of the system_

Accelerated life tests are, of course, usually censored in time, i.e. they are terminated before

the complete fai lure pattern of the sub-lot has been establ ished. Every effort should be made to ensure that they are not censored in accelerated time before the plateau is reached, and even in well-planned overstress evaluations, this often means leaving the devices on test well beyond the anticipated duration. If this is not possible, some information is lost concerning the

'contamination' of the main population by early life failures, but, since the shape parameter and

acceleration factor as derived from tests at two or more overstress temperatures are more important, this deficiency can be overcome by merely assuming the early life regime extends for 100 years (or any convenient time beyond system design life). Finally, it should be noted that all stresses, apart from the one varied by conducting overstress tests under several different conditions to evaluate acceleration factors, must remain constant and equal to those experienced

in the operating condition. This demands that devices should remain fully functional on overstress tests, and unless a more elaborate stress relationship (e.g. the Eyring Equation [4]) is employed, should be operated at the same electrical field strengths, current densities, etc. as

those experienced under use conditions_

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152

PARAMETRIC DEGRADATION

Some c~nents, such as Semiconductor Laser Diodes (LDs) and SAW Fil ters are limited by maximun operating temperatures and relatively low activation energies of predominant failure mechanisms to genuine acceleration factors in the range 2 to 16. This impl ies that years, or even decades of accelerated testing on a traditional attributes basis would be necessary before confidence could be firmly establ ished in meeting design lives of greater than 25 years. Other c~nents, such as Thick Fi lm Resistors, could feasibly be I ife tested at very high temperatures to obtain large acceleration factors, but it would be very difficul t to establ ish that the latter were relevant to attributes failures at normal operating temperatures.

Fortunately, these components have a tendency to exhibit 'graceful' degradation of major (system critical) parameters under moderately accelerated test conditions, and life prediction may be obtained by extremely accurate measurement, curve fitting and extrapolation of the degradation 'laws' for these parameters. More specifically, if D. is the percent or ppm degradation from the initial value (time zero) and A f is the amount of degradation that would cause system failure:

A degradation law, i.e. a relationship between f( A.) and f(t), that is applicable to individual devices and to population parameters (median, upper and lower x - percentiles) is necessary and sufficient to predict the time to individual device fai lure and the time to failure distribution of the population of devices, respectively.

If the degradation law conveniently includes a temperature acceleration factor based on, for example, the Arrhenius relationship, then translation from a higher operating temperature at which degradation is more pronounced, to a lower operating temperature (use condition) is possible_

Such degradation laws are generally empirical and extrapolation to A f naturally assumes the law will not change at any time after the last measurement point. Complex, e_g_ polynomial, laws are very sensitive to exact values of individual coefficients, and hence are of limited use in these circumstances. However, simple laws have been found to fit many observations of parametric degredation over the life test duration, or to progressively converge to the data as the I He tests continue indefinitely_

Table 1 lists a suite of laws that have found widespread application in SR c~nent reliability prediction. The most generally applicable is the first one listed, viz:-

-Ea n --

At Exp ( KT ) b. = (2)

where A and n are constants independent of temperature for the same device, or, to a fairly accurate approximation, for the same percentiles of two sample batches taken from a homogeneous population over a limited temperature range.

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Table 1 Models used for SR component life prediction

Model Application Ref.

Il = At" Exp,-~; Laser threshold/drive current, [5] SAW filter centre frequency, TF resistance.

Il = At" Laser threshold/drive current [6] @ constant temperature.

Il = A Log (1++) Alternative for laser [6] threshold/drive current & SAW filter centre frequency @ constant temperature.

Exp-[xo(1±a ,)]2 Laser power output [6] Il = 21 @ constant temperature.

Exp-[Xo(1± a 0)]

A,", T, XO, ao, a1, are fitting parameters.

153

When extrapolating drift measurements of a single device at a constant temperature to the amount of degradation that would cause system fai lure. the law reduces to:-

log b. --Z;:-f

n log _t_

tf

where tf is the time to system fai lure.

(3)

Al ternatively. when c~ring the resul ts at two temperatures. the law reduces to:-

5.04 Ea* AM (4)

where Ea* = Ea/n may be defined as the apparent activation energy. in direct c~rison with the Arrhenius relationship discussed above.

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154

Fig 3 SAW filter ageing characteristic

60 Irdl-ppm

40

A Ageing @ 85°C for 2000 hours followed by ageing eel', 40°C.

B Predicted ageing @ 40°C (scales reset to zero)

C Predicted ageing @ 20°C. Time to 30ppm £:: 20.2 years.

~ r1.~------~-----:-~~----------------

A

• B~ . ... " I

C

O~------~--------~--------~--____ ~ ______ ~ o 2000 4000 6000 8000 1000

Hours

Fig 4 - Thick film population ageing at three temperatures

~R -ppm Ro

I 90th percentile

Median

10th percentile

10 ~ ____________ ~ ____________ ~~ ______________ ~

10 Hours

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For LDs, correspond cases of

155

SAil filters and thick film resistors, n is usually less than 0.5, a value which would to a square root degradation law, but the relationship has been found to hold even for super·linear degradation (n>1). Figs (3) and (4) show, respectively, single device and

population fits at two terrperatures, and the first indicatE~s the relevant prediction for time to system fai lure. The method has great relevance to screening these specific components at moderately high terrperatures in relatively short times, and can be conbined with the mixed lIeibull model to yield conservative Cdfs for screened product to be deployed in systems. A disadvantage

is that different system-critical parameters tend to obey the same law, but with different

constants, or even different laws, as shown in the table. Hence it is important to consider all parameters that could cause degradation to system failure, and to make sure that all 'rogue'

devices (sporadic failures or units that do not fit the overall population trends) are screened out - even if the indications for these devices are initially favourable.

REDUNDANCY AT THE COMPONENT AND SUBSYSTEM LEVEL

In the early days of digital - optical SR systems, the L.D. Transmit Module was by far the least assured component from a reliability viewpoint. Not only was it known to have a well defined

wear-out fai lure mechanism in the form of a progressive threshold/drive current degradation at constant output power, but also since accelerated testing at terrperatures much above 70'c was known to be totally unrepresentative, it was considered that life predictions would be extremely difficult to obtain. Hence cold-standby laser redundancy with up to 3 spares per working LD was

proposed for these early systems_

However, as the methods of parametric degradation prediction were perfected, it gradually emerged

that the best 1.3 um LOs would have wear out Median lives of hundreds of years under normal use

conditions, and that 'rogue' devices or sporadic early-life failures were virtually unknown provided ul tra-careful assen"bly and surge/ESO protection procedures were observed.

Given that the LO was proving to be almost as rel iable as any other active component (e.g. the

receive module) in the regenerator, there remained the problem of how to demonstrate an overall regenerator 25 year cumulative hazard an order of magnitude lower than was feasible with relatively short term/economically viable life test programmes. One approach was to provide redundancy on a c"",,lete regenerator basis, but a major difficulty was that a suitable

mathematical model for the form of redundancy that could switch a traffic stream to a spare-l ine

and back onto its original path in order to bypass a fault:, did not exist. The straight binomial

n out of m path expansion was tried, but proved inadequate because the interest was not in

maintaining n good paths for one traffic stream, it was in maintaining n good paths for n distinct

and separately identifiable traffic streams. Moreover, an algorithm was needed that would allow

switching anywhere in the network prior to a fault, rather than in a single block containing a faul t, and subsequent restoration anywhere after the faul t; in effect an algorithm that would

cater for a nearly infinite nt.mber of paths.

Fortunately, the 'Matrix Method' [n was developed as just such an algorithm, and proved to be an extremely powerful tool for analysing the rel iabil ity of ladder networks with cross connections to provide alternative paths for signals in the event of failures. It is broadly applicable to all

systems with repeatered sections, but achieves maximum effectiveness in standby line redundant systems, since it offers the only way of reducing the complex rel iabil ity equations for such

systems to a tractable form.

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156

Fig Sa 1 block, 2/2, 1 R2T

Tx, H25 = 1%

~ Fig 5b Reliability characteristic

Probability (%j

100r.-------------------------~

A Probability of 2 paths available

B Probability of 1 path available

C Probability of zero paths available

50

o Ii::::... _________ -=::::::f 100 blocks

100 50

Number of blocks

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157

The Matrix Method is based on the Markov process of state propagation, but in spatial co-ordinates along a network, rather than in teqlOral co-ordinates as more widely used, for exa~le, in the analysis of ",-,lti-state networks with given repair times_ It deals with probability states of signal presence or absence, written in Matrix format:-

So = MN Si (5)

Where Si and So are, respectively, the input and output state vectors, M is the characteristic

Matrix, and N is the nurber of (identical) blocks in the system_ For ex~le, in fig (Sa), which represents one block of one direction of a two fibre pair' system with standby redundant transmit

sections, but no path switching between fibres, Si could be a 4 X 1 vector of the form 1,0,0,0, indicating (certain) signal presence on both inputs. M would be a 4 X 4 matrix whose elements

were a function of the cU"'-llative hazards indicated at the particular time horizon under consideration. So would then be a 4 X 1 probabi I ity vector determined only by the number of blocks in the system, as c~ted from equation (5). Fig (5b) shows how the elements of this output vector, representing the probabilities of both paths being available, only one path being avai lable (two identical curves superimposed) and zero paths being avai lable vary for system lengths of up to 100 blocks. The figure can be regarded as a 'snap-shot' of the system state at the time horizon (e.g. 25 years) for which the cU"'-llative hazards apply.

For systems with path switching between fibres, i.e. systems with dedicated spare lines, as shown in fig (6a), the algorithm is identical, but the calculation is somewhat more c~lex.

In this case for a 2 out of 3 standby I ine system with the block structure shown, the input vector

Si could be an 8 X 1 matrix 1,0,0,0,0,0,0,0 indicating (certain) signal presence on all three

inputs. M would be an 8 X 8 matrix, which in fact would be the product of four 8 X 8 matrices, two of which (Tx - Rx characteristic matrices) were identical. These matrices are quite difficult

to derive, since they involve the SI.lllS of disjoint terms of quite c~lex Boolean expressions, but, once derived, are available for all similar network architectures. So would then be an 8 X 1 probability vector with only the top 4 terms, representing all 3 signals or any two signal outputs, of interest_ Fig (6b) shows the probabi I ity of at least two paths being avai lable, versus the nurber of blocks in the system, to the time horizon of 25 years for which the

CU"'-Ilative Hazards are quoted.

When comparing figs (5) and (6), it should be remembered that the block structure of fig (6)

c~rises effectively two hal f repeaters in series, and in addition the block structure of fig (5)

includes a passive optical coupler with approximately 3_5dB of attenuation; hence for the same overall system length, approximately 100 fig (5) blocks would be equivalent to 45 fig (6) blocks.

The net result is that the standby line system has a very significantly better reliability, with the probability of at least two paths remaining available over the 25 year design life being

56.2%, as compared with 1.7% for the straight two fibre pair system with spared transmit sections.

With different values of the relative 25 year cU"'-llative hazards for the transmit and receive sections, the probabi I ity figures involved in the quantitative comparison would, of course, change, but for long haul (Trans-Atlantic or Pacific) systems at the present state of the art, standby line redundancy represents a cost-effective, technically superior solution. The merit is further emphasised if the entire reI iabil ity curves are c~ared (fig. [7]), rather than the

'snap-shots' of system states at the 25 year time horizon. Here it is seen that the reliabi I ity

of the standby line system is far superior during the first 10 years of system life.

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158

Fig 6a 1 block, 2/3, 1 Ri T

Tx + Rx, H25 = 3%

x / /

Fig 6b Reliability characteristic

PrObability (%J

1oor.---------------------------,

50

~ ~----

o -----------~50~------... 100

Number of blocks

A Probability of 3 paths available

B Probability of 2 paths available

C Probability of at least 2 paths available

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159

Fig 7

Comparison of reliability curves

A 100 blocks, IR2T configuration

B 45 blocks, 2 out of 3 standby line configuration

Probability of zero failures - %

100 __ --------------------~

50

oL---~~------~=-.. ~ 50 100 Years

CONCLUSION

A comprehensive set of models has been developed for component and system rel iabi l ity prediction in the context of undersea opto-electronic cOlllllJnications links. These models are not the only

ones that have proved of value, but are highl ights of the rel iabi l ity growth progranmes that have been, and are continuing to be, conducted, to ensure that such systems remain the most secure,

reliable and cost-effective short, medilMll and long-haul cOlllllJnications links for international telephone, video and high speed data traffic.

ACKNOWLEDGEMENTS

The author wishes to acknowledge helpful contributions to theoretical understanding and test data from Dr. E.R. Monks, STC Semiconductors, Dr. A.P. Janssen, STC Optical Device Systems, Dr. A. R.

Goodwin, & Dr. G. G. PulllMll, STC Technology Ltd, over many years of collaborati on on SR component and system rel iabi l ity growth progranmes.

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REFERENCES

[1] Murphy, R.H., 'ReI iabi I ity • Growth Progr8llllles for Undersea Conmunications Systems'. IEEE Tans. Reliabil ity, Vol R-32, No.3, August 1983.

[2] Moeltoft, J.'Behind the Bath Tub Curve; A New Model and its consequences'. Microelectronics &

Reliabil ity, Vol 23, No.3, 1983.

[3] Jensen, F. & Petersen, N.E. 'Burn-In' John Wiley & Sons Ltd., 1982.

[4] Reynolds, F.H. 'Accelerated - Test Procedures for Semi conductor Components'. 15th Annual Proceedings, Reliabi l ity Physics, 1977.

[5] Murphy, R.H. 'The Application of Degradation Models to Laser Diode Wear-out Life Prediction',

9th E.C.O.C, October 1983.

[6] Janssen, A.P. et al. 'High Rel iabil ity Lasers for Submarine Use'. Proc. Suboptic '86 Conf.

February 1986_

[7] Pullem, G.G. et al ' Reliability Analysis of a Multipath Switching Network'. Microelectronics

and Reliabil ity, Vol.28, No.4, 1988.

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FAILURE ANALYSIS: THE CHALLENGE

R. G. TAYLOR & J. A. HUGHES British Telecom Quality & Reliability Centre 310 Bordesley Green Birmingham, UK (21) 771 6021

ABSTRACT. Optoelectronic, VHSIC, ASIC & US[C devices are key components critical to system reliability and when failure occurs correct diagnosis together with expedient remedial action is essential (in certain applications, for example military or aerospace, failure cannot be tolerated). Consequently with the advances in these technologies, together with the wide variety of packaging formats used, innovative tools and techniques for failure analysis need developing.

The information obtained from field performance and the failure mechanisms involved form an important part in the total quality cycle. It is important to relate field failure mechanisms with those generated by reliability evaluation assessments and hence establish the value of such assessments. The escalating costs of electrical and environmental evaluation equipment, analytical equipment and just maintaining expertise can be prohibitive.

Long gone are the days when the failure analysis laboratory was merely a support service aligned to either an equipment user or manufacturer or component manufacturer. This paper looks at the technical, commercial and quality issues facing the user of components and particularly the role of the failure analyst. Focus is given to the part played in determining failure costs, appraisal costs and prevention costs, all inherent in minimising whole life cycle costs. The need to interface effectively and promptly with respective parts of organisations from equipment users and manufacturers, component manufacturers and component designers is recognised.

The paper is written from the perspective of a user of the failure analyst's services (viz the component evaluation engineer).

161

A. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 161-175. © 1990 Kluwer Academic Publishers.

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1. INTRODUCTION: TRADITIONAL FAILURE ANALYSIS

Almost without exception every major technological company whether it be an equipment manufacturer or an equipment user (eg PTTs) supports component approval/evaluation activities. The reasons are numerous and range from a need for incoming goods testing to component qualification which in some instances is literally verifying what their supplier had (or should have) done to maintain component expertise. Component manufacturers were very protective of proprietary information for obvious commercial reasons. Consequently little confidence could be gained by users from what appeared as unsubstantiated quality and reliability data. It can be argued that the existence of such component assessment activities has been instrumental in ensuring that reliable product is released from the manufacturers. For example, advances in non-hermetic packages of comparable reliability with hermetic packages has been a result of the pressures brought to bear by users and their ability to assess components supplied to them.

An integral part of all these component assessment activities is the failure analysis facility. For an equipment user failure analysis was essential in determining firstly whether the cause was application or component related and secondly to instigate prompt remedial action. Unfortunately in many instances added justification of a failure analysis facility was warranted because of confli·::t between the user and the component manufacturer ("it must be your fault"). This arose not only because of disagreement over causes of failure (hence the risk of liability) but also from unacceptable delays experienced before vendors responded. This could be excessive if the failure investigation had to be referred to manufacturers' worldwide headquarters and could have major commercial consequences to the user.

All failure analysis investigations follow a carefully controlled procedure to determine the cause of failure (1) and (2). This is important in order to avoid missing vital information. A typical procedural programme is shown in Table 1. This approach is ideally suited to "yesterday's" technologies since most causes of failure and quality related aspects could be readily identified at stages 9, 10 and 11. Figures 1 (corrosion), 2 (electrical overstress), 3 (electromigration) and 4 (ionic contamination) are representative of such failures. The approach can also be useful for some of the emerging technologies. Figures 5 and 6 show ESD damage on GaAs devices and Figures 7 and 8 illustrate quality related defects on laser modules. Scales of integration were such that non-destructive techniques such as Infra-red microscopy, EBIC, voltage contrast and liquid crystal, could without much difficulty, locate failure sites.

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However the major advances in semiconductor technologies resulting in sub-micron geometries, 3-D structures, BlCMOS, digi-lin, complex ASICs (application Specific ICs), USICs (User Specific lCs) and IU-V materials for both microelectronic. and optoelectronic applications present a whole new challenge. Figure 9 shows the scale of complexity found in a microprocessor device. The problems are e.xacerbated with the advances in packaging technologies; surface mount technology becoming prevalent and with it different reliability risks. Pin counts well in excess of 100 are also common place (Figure 10). These developments and the associated criticality to systems mean that reliability more than ever, must be assured and that risks to reliability should be identified and quantified at the outset and not discovered in the field. Whilst this may be vie\oied as idealistic the observed change in culture in the industry resulting in closer working relationships between component manufacturers, eqUipment manufacturers and users is instilling the confidence which was missing previously.

2 RELIABILITY PREDICTION AND TESTING: THE CULTURE

The predicted reliability of semiconductor eomponents has traditionally been calculated using the models from such sources as Military Standard 2l7E and British Telecom Handbook of Reliability Data (HRD4). These models have partly been based on theoretical considerations and partly based on field return data. HO\oiever, in neither case can the resultant prediction be relied upon with a great deal of confidence since the theoretical prediction is based on an historical model and the field return prediction is based on historical data. To illustrate this point recent field return data (3) on the reliability of 64K and 256K DRAMs would suggest a reliability of 10-12 FITs whereas Mil Std 217 predicts 74 FITs and HRD4 predicts 20 FITs.

The problem here is that the prediction sources have not been able to successfully keep abreast of the dramatic i.mprovement in quality and reliability of VLSI semiconductors although they have been more successful wi.th discrete devices and semiconductor devices with lesser integration. In short they do not cope with the modern concept of "Continuous Quality Improvement".

Another area where this quality improvement ethic is not catered for is the in the traditional methodology of reliability assurance of components. The well established reliability tests using typically (but not exclusively):-

* thermal overstress * moisture endurance * thermal shock or temperature cycle

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are well proven tests with a great deal of experimental data to back their validity. But, for practical reasons, it is only possible to subject a limited number of devices to these tests. For example, a typical thermal overstress test (4) uses a 1000 hour, 150 Deg C condition with a sample size of 77. This will give, at best, a predicted failure rate of 230 FITs at a 60% confidence level (based on HRD4 model and assuming zero failures). This is often unacceptable since in the case of multilayer chip capacitors (MLCCs), HRD4 predicts 0.3 FITs for these devices. For the equipment manufacturer to demonstrate an MLCC reliability to even 5 FITS (the acceptable level in the application) it is necessary to obtain a total of 3500000 test hours (ie 3500 devices for 1000 hours at 150 Deg C (based on the model in HRD4».

This demonstration was undertaken recently (5) (to 5 FITs) and this resulted in, initially, some screening of the devices to effect the required reliability level. The component vendor is now working to implement improvements which should render this screening unnecessary.

Nevertheless, this was a specific case and is certainly not the norm. Such extensive testing can only practically be undertaken on a small percentage of the component types used in an equipment design.

A further problem arises when one considers the cost of both the hardware and the software required to adequately electrically characterise a modern VLSI semiconductor component. It is becoming increasingly difficult for both the component manufacturer and the equipment manufacturer to make the necessary capital purchase of VLSI test equipment. These now require typically of the order of 250 test pins and a test frequency of up to 50 MHz particularly if testing of user or application specific devices is required.

In addition the cost of software for these testers is also becoming increasingly high. This becomes more apparent when it is noted that the majority of equipment manufacturers who characterise the components they purchase, write their own test vectors. This is because of problems with the inadequacy of "off the she If" software and also to ensure that the expertise gained from writing this software and the associated understanding of the device operation, is retained within the organisation. To write software internally becomes extremely costly and adds considerably to the initial capital cost of the equipment.

The total cost of ownership of a VLSI test capability is therefore high and becoming prohibitively so for most organisations.

For optoelectronic components (viz lasers from £700 to £5000), where few devices are used in each system, even the initial cost of purchasing the devices for evaluation becomes prohibitive.

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3 FAILURES IN SERVICE

Another question which is being increasingly asked is "do the traditional rethods of evaluation give the necessary assurance?"

There is evidence to show that approximately 25% of qualification exercises undertaken by equipIrent manufacturers result :Ln failure of the component to meet the test criteria (5). It is also quite clear that where such rigorous qualification is not undertaken considerably less than 25% of the component types fail in the quantities that these qualification exercises would suggest.

In addition, there have been three serl.ous cases of failure of eomponents in equipIrent supplied to British Telecom in the past two years which have passed the traditional qualification tests. There has been no question of the integrity of the qualification in these cases; the devices have failed dua to Irechanisms which have not been accelerated (or not been accelerated sufficiently) by the traditional Ire thods.

The first of these fallures resulted from oxide breakdown in a high voltage (63V) integrated circuit. The thermal overstress test under supply voltage bias at 125 Oeg C did not produce failures in the 2500 hours of the test. When problems in service caIre to light a short term solution, and one which is still be used, was to screen out weaker devices with latent oxide defects by a 125 Oeg C 48 hour burn-in but using an increased bias voltage of 70 Volts. The longer term solution of improving the oxide integrity by an improved process is still being sought.

The second problem was discovered when a power supply controller device proved to be particularly unreliable. The device failure resulted from the power-up, power-down sequence of the power supply unit during initial test and subsequently its commissioning phase. The device employed a silicon nitride passivation process. The interface of this layer and residual silicon dioxide present on the die surface prior to nitride deposition is a preferential site for charge trapping. The combination of this over a shallow junction zener diode led to instability of the reference voltage and eventual failure. Again a short term solution could be found by removing the passivation layer over the site of the zener diode or reverting back to a silicon dioxide (vapox) passivation. However, a well established accelerated life test does not yet exist to warn of such a problem in the future.

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The third, more recent component failure was identified as being caused byelectromigration. The tretallisation used in the wafer fabrication process was pure aluminium without a copper additive to reduce the incidence of electromigration. These were high speed, emitter coupled logic devices which, due to their relatively high power dissipation had a high junction temperature which exacerbated the electromigration effect. Again traditional life tests were carried out on the device at the qualification stage by both the component and equipment manufacturers but these were not sufficiently extended to detect this failure mode (characterised by its 0.3 eV activation energy).

The traditional accelerated life tests are therefore not only becoming less practical for reasons of cost and the necessary device hours requried in many cases, they are also not always effective at identifying potential problems. All of this points to a need to very critically re-assess traditional methods of VLSI semiconductor component quality and reliability assurance, particularly by a purchaser of these devices.

4 ACCELERATED LIFE TESTING

From evidence it can be shown that a question mark exists against the traditional Arrhenious approach to reliability assurance as applied to advancing semiconductor technologies. It is not intended to cast doubt against the validity of accelerated life testing using elevated temperature testing. In fact if it wasn't for these techniques, demonstration of reliability figures of the order of tens of FITS would never have been achievable. The placebo effect is also considered contributory. In other words for manufacturers to neet the acceptance criteria of high temperature reliability testing then an all round improvement in fabrication, processing and assembly was necessary.

However failure mechanisms have been described earlier which are not necessarily observed using temperature related testing. With technologies which are even more critical to system reliability then both alternative accelerated testing and reliability indicator testing are important. These tests must concentrate on worst case conditions. For example when evaluating the reliability of surface mount devices the component manufacturer must assess the reliability with respect to the various assembly conditions whether it be vapour phase, infra-red or double wave soldering. The onus is on the manufacturer to recomtrend which assembly technique is preferred and be able to demonstrate why. Likewise with high pin counts recommendations minimising crosstalk are essential. The current issue surrounding "ground bounce" on ACL (Advanced CMOS Logic) being a point in case. One manufacturer minimises ground spikes by centralising supply pins and positioning all input and output pins together, while other manufacturers have addressed the problem by re-designing output structures.

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Stresses induced in non-hermetic packages when large die are used, mixed technology circuitry where the small signal logic functions are incorporated on the same chip with high power driving circuitry, 4Mbit memories where geometries are reduced dramatically, present some of the challenges to the reliability engineer. In these circumstances the likelihood of locating failure sites is nigh on impossible unless the cause of failure is gross. New and enhanced failure site location techniques will need to be developed to rneet th~ demands of this emerging technology.

:) ENHANCED QUALlF ICATION TECHNIQUES

Because of the problems with both the cost of traditional component qualificEition programmes and the concern over their ability to predict whether the components will, or will not fail in service, a number of users of components are looking with enthusiasm for alternative or at least enhanced qualification techniques. Members of the STACK (6) organisation have identified classifications of component qualification philosophy which are now being used or considered for use by the members:-

* Shared Evaluation: Formal evaluation with the work undertaken by the equipment manufacturer or user and the results shared with the other STACK members.

* Joint Qualification: An evaluation based on formal testing work with the testing either shared between the STACK member and the component vendor or the work performed entirely by the vendor to an agreed test schedule.

* Risk Assessment: Identification of risks associated with components by audits of the component vendor's manufacturing sites to support vendors data.

* Use of Vendor Data: Device qualification based solely on vendors data.

It is not the intention here to discuss the merits of these approaches but is should be noted that with the exception of the first item which is the traditional method of qualification within the STACK membership, the trend is towards growing co-operation between the user and the vendor.

It is of concern that although this is a growing trend, there are few instances of truly close co-operation. Compare this relationship with that between the component manufacturer and his supplier. Many of the leading component manufacturers are introducing Statistical Process Control (SPC) techniques which are being extended to their raw mat,;!rial (including piece parts) suppliers. One company in particular is applying its "6 Sigma" approach (7) to its suppliers and the closeness of the

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relationship is demonstrated by the company giving training in SPC to its suppliers. In other cases the component manufacturer takes a controlling financial interest in the supplier to ensure the necessary control of the quality of these piece parts. SPC is therefore, and should not be confined to individual manufacturing links in the complete chain from component raw materials (including chemicals, silicon, lead frames etc) to the testing of a complete equipment or even a system.

Certain links have been forged between equipment manufacturers and component suppliers through parts per million schemes but these have tackled tester correlation issues and not reliability problems. The level of co-operation between the two parties is certainly not as high as that between the component vendor and his supplier. The only instance where the relationship is believed to be strong enough is in a vertically integrated structure where component manufacturing and equipment manufacturing is part of the one organisation.

6 PARAMETRIC VARIATION AND DRIFT

A concern with the use of vendor data which has restricted its acceptance is that of the presentation of results of component reliability testing in the form of attributes rather than variables. The most common format for these results is a table indicating few, if any failures over the duration of the test. Although this gives a measure of confidence this can be greatly enhanced if variables information is offered since one of the user's major concerns is the stability of the component. Indeed an understanding of parametric variation and drift also gives the user valuable information o~r and above confidence in reliability. Information about the parametric variations is particularly relevant to the equipment manufacturer when tolerancing his design and to the component engineer for establishing the equivalence of similar devices or devices from other manufacturers for second sourcing and maintenance purposes.

Again this issue relates to the use of SPC across the complete manufacturing cycle. Although the use of attributes data can be employed, most of the important experimental data used to understand more fully the variability in the process, and hence initiate improvement, is derived from variables data. Therefore to apply SPC across the complete manufacturing cycle requires the component vendor to provide data of this form.

This does have practical difficulties, particularly in the potential volume of data which would need to be generated. HOlolever, one component manufacturer has alrady indicated that final test data in parametric variable form will be made available with the supply of certain transistors (8). It should also be noted that the phrase "Statistical Product Monitoring" (9) has been coined to identify this particular concept of the value of parametric variation and drift information.

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7 THE FAILURE ANALYST AND THE FUTURE

As technologies have advanced and increased integration on silicon continues the roles of the respective component evaluation groups in both equipment manufacturers and end users organisations have also changed. Maintaining the practical facilities for both electrical characterisation and reliability evaluation is almost an impossible task requiring capital investment which is difficult to justify. Hence the emphasis has changed, the onus for reliability assurance still being with the vendor but being evaluated by the component user employing data supplied by the vendor. This has also meant a fundamental change in the role of the failure analyst. In fact few, if any, are engaged solely in failure analysis activities. Their responsibilities have developed such that their expertise enables them to address a wide range of activities throughout the life cycle of a component. Aspects now being covered are (10):

Technology Evaluations

the physical examination of new or evolved technologies to allow a greater understanding of the associated failure mechanisms and the relevance of conventional reliability assessments.

Technology Risk Assessments

the evaluation of the risks in relation to factors influenced by application or operating environments.

Package Evaluation Projection

ensures that there is no compromise to reliability or component function which results from new packaging technologies or materials.

Component Interfacing

consideration of the interaction of the component within the circuit configuration, relating back to the risk of poor service performance.

Validity of Evaluation Techniques

ensure that the conclusions drawn from new evaluation techniques are valid and accurate ie observed failure mechanism can be considered a realistic field reliability risk.

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Component Failure Rate

a correlat ion of the component failure rate and mechanisms as seen from fie ld performance, to the documentation commonly used in reliability performance prediction.

Using these techniques gives the failure analyst a vital part to play in the evaluat ion process and it is becoming increasingly important for him to be a key member of the component evaluation team.

It should be noted that one of the key elements of these new roles for the failure analyst is the technology evaluation. It is not anticipated that this would be undertaken in isolation. It is the technology evaluation aspect where the close relationship between the component manufacturer and his suppliers can be paralleled to that bet~en the equipment manufacturer and his component vendor.

Only through close relationships between these latter two parties can the problems identified in the case histories identified in Section 3 be resolved prior to causing failures in the field. To take the first case as an example, although work is still progressing to improve the process, collaboration between the equipment manufacturer and the component manufacturer has enabled controls on the oxide deposition to be tightened to a considerable extent. Further work is necessary before the screening procedure can be removed but this is being progressed jointly such that the processing knowledge of the component manufacturer and the application knowledge of the equipment manufacturer are producing improvements towards a satisfactory solution.

It could also be argued that the component manufacturer could have undertaken this corrective action without the assistance of the equipment manufacturer. However, this does isolate the component manufacturer from the expertise the component specialist in the equipment manufacturing environment can bring to the problem. This has been gained through his experience of problems associated with the application of devices, field service failures, and dealings with other component manufacturers.

The depth of liaison between the component and equipment manufacturers argued for here can however lead to certain difficulties. Problems with confidentiality are certain to be raised. It is envisaged that these may only be fully overcome by long term relationships being established between the two parties through scheme s suc h as "sh ip-to-stock" and t he "technology evaluation" discussed here. The way could then be paved for the necessary mutual trust for such schemes to be a success to be established.

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8 CONCLUSIONS

1. Component reliability must be assured and the risks to reliability from potential failure uechanisms identified and quantified at the outset and not discovered in the field.

2. Component reliability prediction sources have not been able to successfully keep abreast of the dramatic improvement in quality and reliability of VLSI semiconductors although they have been more successful with discrete devices and semiconductor devices with lesser integration. In short they do not cope with the modern concept of "Continuous Quality Improvement" '.

'L The traditional acce lerated life tests are not only becoming less practical for reasons of cost and the necessary device hours required in many cases. They are also not always effective at identifying potential causes of failure. All of this points to a need to very critically re-assess traditional methods of VLSI semiconductor component quality and reliability assurance, particularly by a purchaser of these devices.

4. The total cost of ownership of a VLSl tl~st capability is high and becoming prohibitively so for most organisations.

5. Failure uechanisms exist which are not necessarily observed using temperature related testing. With technologies which are even more system dependent then both alt,:rnat ive accelerated testing and reliability indicator testing are important.

6. Statistical Process Control, where used for component quality and reliability improvement, should cross the boundaries between each of the organisations in the chain from component raw materials to the te.,ting of a complete equipment or even a system. The only circumstance where the relationship is believed to be consistently strong enough at present is in a vertically integrated structure where component manufacturing and equipment design and manufacturing are part of the one organisation.

7. A concern with the use of vendor data for evaluating component reliability, which has restricted its acceptance, is that of the presentation of results of component reliability testing in the form of attributes rather than variables. An understanding of the parametric variations and drift gives the user valuable information over and above confidence in reliability.

8. The role of the failure analyst is changing. Few, if any, failure analysts are now engaged solely in failure analysis activities. Their responsibilities are developing such that their expertise is enabling them to address a wide range of activities throughout the life cycle of a component.

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REFERENCES

1. R. G. Taylor and C. E. Stephens "Microcircuit Failure Analysis" British Telecommunications Engineering 4, April 1985, 39.

2. B. P. Richards and P. K. Fother "Failure Analysis of Semiconductor Devices - Rationale, Methodology, and Practice" GEC Journal of Research 1, No 2, 74.

3. Minutes of the STACK Reliability Working Party, March 1989.

4. STACK Purchasing Specification S/OOOL

5. GPT Switching, Component Evaluation Programme.

6. STACK (Standard Computer Komponenten). An association of major users of components from both the computer and telecommunication environments.

7. Motorola presentation to the STACK, Test and Correlation Meeting, Paris, 19th April 1989.

8. British Telecom audit of Motorola Toulouse (1988).

9. IBM presentation to JEDEC Solid State Products Engineering Council, Myrtle Beach, US, September 1988.

10. C. E. Stephens discussion paper "STACK Failure Analysis Working Party", March 1989.

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1. Data Search

2. External visual

3. Electrical test

4. Bake and electrical test

5. X-Radiography

6. Hermeticity and internal atmosphere

7. Decapsulation

8. Electrical re-test

9. Internal visual examination

10. Non-destructive analysis

11. Destructive analysis

Interrogation of all previous FA investigations and other component inte lligence

Low power optical microscopy examination of all aspects of packaging

Identification of failure mode by verification of non-functionality or degradation

Unbiased baking followed by assessment of parameter or functional recovery -indicates charge storage or ionic contamination problems

Checking of internal connections and alignments, especially where decapsulation might have an effect

Assessment of hermeticity in cavity packages and internal atmosphere by residual gas analysis (RGA) to identify sealing environment

Exposure of internal aspects of the component by a variety of mechanical or chemical methods or preparation of plastic encapsulated samples for infra-red microscopy examination by backpolishing

Examination to ensure that decapsulation has not altered failure mode

High power optical microscopy to low energy e lec tron beam techniques

Thermal analysis, material analysis by energy or wavelength dispersive spectroscopy (EDS or WDS)

Bond pull and die shear, circuit node probing and circuit element isolation, section and stain, selective etching and so on

Table 1. A typical failure analysis procedural programme.

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Figure 1. An ea;ample of corrosion on a 4000 Series CMOS Device

Figure 3. An example of elect rom.igrat ion

Figure 1. An example of electrical overstress

Figure 4. An example of iiJnle contamination

Figures 5 and 6 ESD Damage on Ga As Devices

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Figure 7. Cracked solder joint beneath a PeltllH' cooler in a laser module (X7).

Figure 9. Example of a complex die used in a microprocessor device

Figure 8. Bond pad on an ELED device almost detached (Xl20)

Figure 10. Examples of growing complexit y of package styles avai lable

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GATE MET ALLISA nON SYSTEMS FOR HIGH

RELIABILITY GaAs MESFET TRANSISTORS

D.V. MORGAN School of Electrical, Electronic & Systems Engineering University of Wales College of . Cardiff

J. WOOD Department of Electronics, University of York, England

ABSTRACT

Driven by the need for high device reliability in MESFET power transistors operating at elevated temperatures, and more recently the development of self aligned gate structures, high stability contacts are being investigated in many laboratories. This paper will consider two classes of metallisations that have proved very prOmISIng. These include the refractory metals such as W, Ta and Ti together with the refractory silicides such as TaSix TiSix and WSix. The work carried out in this area will be reviewed and appraised. The basic interface has been characterised by the use of RBS and SIMS studies. More recent studies have been concerned with the use of these results in the fabrication and evaluation of transistor structures.

1. INTRODUCTION

One of the key components of a GaAs MESFET transistor is the Schottky barrier gate electrode. The rectifying Schottky barrier performs the same function in the MESFET as a p-n junction does in a conventional JFET. For the fabrication of high reliability devices the gate metallisation must exhibit the following characteristics.

i) The gate metal must exhibit a reasonably high barrier height and consequently, a low reverse leakage current. GaAs possesses a high surface state density, and the resulting free surface band bending ensures that most metals will form rectifying contacts to GaAs.

(ii) Good stability during operation. (iii) Good resistance to metallurgical reactions, oxidation and corrosion. (iv) Good mechanical adherance to GaAs (v) A low sheet resistivity, particularly where fine sub-micron gates are

involved. (vi) Reasonably ductile to allow wire bonding. In the case of the refractory

metals and silicides this inevitably m<:ans an overlayer of a ductile material such as gold.

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A. Chrislou and B. A. Unger (eds), Semiconductor Device Reliability, 177-196. © 1990 Kluwer Academic Publishers.

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(vii) Potential of selective etchability between metal and GaAs.

In general it is not possible to find anyone single metallisation that will satisfy all the above criteria and this has led to the development of multilayer metallisation systems [1]. Such systems are designed to provide a good interface Schottky barrier, stable against interdiffusion with the GaAs, a containment or barrier metal and finally a ductile metallisation system such as gold or a gold based alloy for the final layer to provide a good bonding interface which is highly stable against oxidation or corrosion.

In recent years, very severe demands have been made on the performance of GaAs field effect transistors in terms of output power and frequency of operation and this has led to the development of devices with good metal/semiconductor stability. In particular, application in high frequency analogue and high speed digital devices has led to the development of the so called self aligned gate structures [2]. In this technology, the region between the ohmic contacts (source and drain) and the gate are implanted with a high density of n-type dopants (n+) with the gate being used as the implantation mask to ensure that the n+ region extends right up to gate (i.e. self aligned). This procedure reduces the parasitic series resistance partly on account of the high doping and further because it reduces the surface depletion width in those regions between the source/drain metallisations and the gate.

The difficulty arising out of this process is the need to use gate metallisation systems that are stable up to the temperatures needed to anneal the implantated layer (i.e. '" 800 - 900°C). It is for this reason that the current work on high temperature gate metallisations is being carried out. It should be noted that although the ohmic contacts have to be deposited and alloyed with the gate in place this is not such a severe problem because the alloying temperatures are considerably lower (i.e. $ 450°C) than the implant activative temperature ($ 900°C).

2. REFRACTORY METAL SYSTEMS

The refractory metals, titanium tantalum, molybdenum, tungsten and near-noble metals, (platinum, palladium) are of interest in GaAs metallisation system for their high temperature stability in comparison with metals such as gold, silver and aluminium. Considerable early success was achieved with titanium and tungsten as stable gate m etalli sations. The thermal stability of these refractory and near-noble metals has been reviewed recently [1,3] to identify the effects of annealing temperature and time on the structure of the Schottky contact (Physical interdiffusion and electrical degradation). Most of these metallisation systems exhibit degradation at temperatures below 500°C. The one clear exception is W /GaAs.

W/GaAs

There is now strong evidence to suggest that the W /GaAs system is very stable and does not readily interdiffuse with GaAs. Tungsten forms two intermetallic compounds with arsenic, W2 As s and WAs 2 , but none with gallium. Among the common refractory gate metals, tungsten is unique in this

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respect. Furthermore, thermodynamic data suggests that the tungsten arsenides are not formed below JOOOoC [27].

A selection of the available published data [4,5,6,7,8] is reviewed in reference [3]. Some of this data corresponds to relatively long term heating (up to 2 hours) in a conventional furnace whilst others utilises transient annealing techniques. In all cases these correspond to conditions suitable for post implantation annealing and hence self aligned technology. Tungsten has proved to be stable at temperatures as high as 9000 C with conventional annealing whilst over lOOOoC has yielded stable contacts with transient optical annealing [22,23,27]. A frequently reported problem at the higher temperature annealing is that of metallisation peel-off owing to thermal expansion mismatch.

Ti-W/GaAs

A modification of the basic tungsten contact is the alloy Ti-W. This system is stable up to around 7000 C [8,9,10] but annealing above 7S00 C results in outdiffusion of gallium and/or arsenic together with indiffusion of titanium. Kohn (11] observes that sputter deposited films suffer a degradation in rectification due to defects in the GaAs created by the tungsten component during the sputtering process. Annealing the contact in the temperature range 400 - SOOoC removes this damage and intially reduced the reverse leakage. However, interdiffusion at the higher temperatures (> 750°C) and the consequential reduction in barrier height (figure 1) limits the use of the system for self aligned structures.

3. REFRACTORY METAL SILICIDES AND NITRIDES

To overcome the problems associated with peeling, corrosion and interdiffusion, refractory metals compounds such as WSix' TiWSix' TaSix' WN x' etc. are generaJly employed to improve the adhesion and thermal stability. The main disadvantage with such materials from a device point of view is the high sheet resistivity compared with the pure metal. These compounds are deposited using sputtering techniques, using either: (a) A hot-pressed compound target of the correct composition, although these

are not favoured as there is evidence that oxygen is incorporated into the target, degrading the metallisation contact properties;

(b) Two targets, the substrates passing beneath each alternately; or (c) A composite target made from e.g. metal target with silicon wafers

attached to its face, or a silicon target with a metal foil covering part of its surface;

(d) Nitrides are prepared by reactive sputtering i.e. in an Argon/Nitrogen sputter gas mixture.

These latter examples allow a range of compound compositions to be deposited.

3.1 Refractory metal silicides

The thermal stability of tungsten silicide contacts on GaAs has been

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investigated by a number of workers as a function of the silicon content of the contact. These results are summarised in Table 1. Low Si/W ratios are favoured for stability, in contrast with silicon technology where WSi z is most commonly used. Ohnishi et al [12,13] have found that the stability depends on the Si/W ratio, and that an optimum value for good electrical and thermal stability is WSi o. 6: (Figure 2). This is the crystalline phase W sSis [14]. These contacts have a Schottky barrier height of 4>B = 0.72 eV which is stable after annealing at 750°C. These general results have been confirmed by other workers [15,16], using furnace anneals up to 9000 C; at lOOOoC interdiffusion has been observed using RBS techniques [15] (Figure 3). Lower Si/W ratios, x < 0.6, have also been shown to form stable contacts to GaAs, exhibiting electrical consistency after annealing [13]. These mixtures contain tX-W and W sSi s. At very low silicon content, in diffusion of tungsten has been observed at high temperature [14]. Silicon-rich silicides contain the WSi 2 phase and are generally unstable on GaAs, indiffusion of silicon is noted [16].

TiWSix/GaAs

The thermal stability of TiW contacts can be improved by the addition of silicon during the sputter deposition to produce the silicide. Compound targets show little improvement due to incorporation of contaminants in the films, the use of two targets, TiW and Si giving most improvement in performance. Figure I illustrates the improved stability of the silicide contact in comparison with the TiW system: the barrier height is constant up to 6500 C, with a slight rise thereafter. SIMS measurements indicate some movement of titanium towards the GaAs at temperatures greater than S500 C.

TaSiz/GaAs

This metallisation system has been studied by a number of authors [l0,IS-24] and has been shown to exhibit good thermal stability. Figure 4 shows the Rutherford backscattering spectrum of a layered Si/Ta/Si/GaAs structures before and after annealing at SOOoC and 9200 C for 20 min. in an arsenic overpressure ambient. Note that there is no change in the GaAs front edge in the SOOoC annealed spectrum which indicates that little metallisation -GaAs interdiffusion has taken place. The drop in the Ta peak height and change in the Si peaks arises from the intermixing of these components to form TaSi z on top of the GaAs (see inset). Complete TaSi z formation is observed after the 9200 C anneal for 20 min. The GaAs front edge shows some broadening which can arise from either a non uniform TaSi z layer or slight TaSi 2 -GaAs interdiffusion. Corresponding TEM studies [IS] show that the TaSi 2 /GaAs interface is non uniform. The peak around 2.4 MeV in the RBS spectrum is gallium and/or arsenic outdiffusion into the silicide. Note also the In peak is a result of In indiffusion into the silicide. (InAs was used to provide the close proximity source for the arsenic over pressure).

Similar studies by Tseng and Christou [19] have been concerned with sputtered tantalum silicide on GaAs annealed up to 8000 C Auger profiling studies indicate that the interface is stable up to this temperature (figure 5) showing no evidence of interdiffusion. The barrier height on these contacts were initially relatively poor (:;: 0.6 eV) but increased to 0.8 eV at about

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3500 e and thence remained constant [23,33] (figure 6). This is not unusual for sputter deposited films and is a result of the sputter induced defects produced at the GaAs interface.

More recent work on this metallisation system (TaSi 1 • 4 ) confirm these earlier studies [22,23]. Sputter deposited films have been capped with Si aN 4 and subjected to transient optical annealing for 10 seconds up to 10500 e. At 8500 e the interface is stable. At 9500 e Ga and/or As outdiffusion occurs (figure 7) which is further enhanced at 10500 e. The corresponding figures for the Ga (or As) concentration at the midpoint of the silicide is around 3% at 9500 e and 7% at 1050°C. In all these cases the film quality remained excellent with no evidence of the development of pin-holes or peeling.

One very interesting feature of these results is the possibility that the outdiffusion and intermixing at the interface is dependent on the dislocation density in the starting GaAs layer. A comparative study of the degradation of identical Ta silicide films sputter deposited at the same time on a standard semi-insulating GaAs and one with an In doped low dislocation density layer, exhibit contrasting results above 9500e. For the indium doped samples no interdiffusion was observed for annealing up to 10500 e. A possible explanation of this result is that the interdiffusion between thin metallic films and GaAs is a crystalline defect assisted process [25]. Further work is needed to corroborate these observations and to estimate its relevance to device production.

VSi/GaAs

Very limited work has been reported on this system and this has centred on transient annealing, Morgan et al [23] have reported results on VSi 1 9

deposited on semi-insulating GaAs, capped with silicon nitride and annealed at 850, 950 and 1050°C. At 9500e and 10500e a very small amount of outdiffusion is observed but it is too small to be measured quantitatively by RBS.

3.2 Refratory Metal Nitrides

WNx/GaAs

Tungsten nitride films are prepared by sputtering of a tungsten target in a nitrogen-containing ambient. The nitrogen content of the sputter gas mixture p[N 2 1/(p[N 21 + p[Ar]) is usually below about 20%, resulting in a WNx film where x lies in the range 0.04 to 0.14 [26]. The deposited film is polycr ystalli n e wi th a large grai n si ze an d less well-defined boundaries in comparison with tungsten films. On anneali ng, this film crystallises above 6000 e to yield a-Wand W 2N phases. The metallisation has proved mechanically and electrically stable on GaAs, at temperatures up to 8000 e in furnace anneals, and 9750 e in RT A [39-42:]. The Schottky barrier height after anneal is commonly reported to be 0.72-0.74 eV [26,28-30]. The interface with GaAs appears stable on investigation by SIMS, AES and RBS techniques. At 9000e in furnace anneal, and 10000e in RTA, considerable interdiffusion of all components is observed indicating significant contact degradation [27].

Page 188: Semiconductor Device Reliability

182

Titanium-tungsten nitride contacts to GaAs have also been reported, these also showing good stability to indiffusion and contact degradation at anneal temperatures up to 8100 C [31]. These contacts have been employed as gates in power FETs [32]. The thermal stability of a range of nitride contacts on GaAs is summarised in Table 2.

4. DEVICE F ABRICA TION

Up to this point the discussion has been confined to basic studies of inter diffusion at the conductor semiconductor interface with corroborating measurements on the electrical stability of Schottky barrier diodes. The technology, however, has progressed beyond this phase and results are now available on real MESFET and HEMT device structures. A summary of the available evidence is shown in Table 3. In general terms these early studies indicate significant promise for this technology. The work of Matsumoto et al [9,24] deals with a basic refractory metal tungsten and in spite of the peel off problem discussed earlicr this work shows that the mctallisation system can be made to work for the self aligned technology. An annealing sequence of 9000 C for 10 minutes was used on two gate length structures of 0.3 /Lm (minimum) and 0.18 /Lm (maximum) and these resulted in a best value mutual conductance of 225 mS/mm. The output characteristics did not, however, exhibit channel pinch-off.

The system TiW has been reported by Tseng and Christou [19,20] and Sadler and Eastman [34] for gate lengths of down to 0.6 /Lm. In these results the pinch-off was again absent in the device characteristics.

One of the earliest reported device results was the work of Yokoyama et al [9,10,12,13] using a TiW silicide metallisation. The calculated gm values of this work indicated that the self aligned MESFET had a value of four times larger than the equivalent conventional device and furthermore the parasitic series resistance was some five time smaller. Another observation was that the selective etchability of the TiW-Si was superior to that of the TiW system. Work on this silicide system has reached the point when a 1024-bit GaAs static memory has been successfully produced using the silicide gate.

The TaSi metallisation reported by Tseng and Christou has not been tested as fully. Although the Schottky test structures have been evaluated up to 850°C. The real MESFET structures have only been subjected up to 4500 C for 2 min. this being the Ohmic contact metallisation alloying temperature. The MESFET structures fabricated were ~2 /Lm and exhibited good channel pinch-off.

Included in this category are some preliminary results on HEMT and HIFET devices. The HEMT results [35] were aimed at a low noise device structure and have achieved a noise figure of 9.54 at 12 GHz.

Kamada et al [36] have reported preliminary results of a W /WSi gate self aligned HIFET using an AlInAs/GaInAs heterostructure. The devices exhibited good d.c. performance with a transconductance of 280 mS/mm. In both these examples the published results though preliminary exhibit excellent potential for the devices concerned.

Page 189: Semiconductor Device Reliability

183

Tungsten Nitride and (TIW)-Nitride MESFETs and ICs have also been fabricated. The gate material is deposited by reactive sputtering techniques, as outlined in the previous section. The gate structure is defined by reactive ion etching, often using SF 6 which does not etch the GaAs surface. Metal masks such as nickel can be used to define the gate, and these can be selectively wet-etched later. Furnace and RT annealing processes have been employed in device fabrication.

The electrical properties of the contacts are determined using C-V and I-V techniques, and the barrier height after annealing is found to be 0.72-0.74 eV [26,28]. The C-V measurement shows a higher barrier height than I-V, thought to be due to the presence of an interfacial region, which may arise from damage due to the sputter deposition [26].

Tungsten nitride gate enhancement and depletion mode MESFETs have been made, with transconductances of typically 236 mS/mm for E-mode FETs and 158 mS/mm for D-mode devices, of 1 micron gate length [28]. Short channel effects were noted for FETs with gates of kngth less than 1.5 microns. In these devices it was found that furnace annealing produced better results than RTA. The tungsten nitride gates are attractive for enhancement mode FETs in DCFL applications as the gate can be driven up to 10.8 V into forward bias without any appreciable leakage current [26].

Tungsten nitride gates to p-type GaAs have been investigated, for complementary logic applications where the power dissipation per gate can be very low, below 50 /lW [30]. The nitride showed a high barrier of 0.68 eV on p-GaAs, but with quite high ideality factor of 1.4. Enhancement mode FETs were fabricated, with a transconductance of 4.2 mS/mm, about 20-30 times smaller than comparable n-channel devices.

One of the most thorough studies of refractory nitride gate FET fabrication and characterisation has been the development of a titanium-tungsten nitride gate process technology for a power FET requirement at C-band [30,32]. Over 20,000 devices have been made. The resulting FET device has an overall gate periphery of 2.5 mm at 0.8 /J.m gate length. The dc characteristics show a saturated drain current of almost I A and pinch-off voltage of -5 V. The transconductance of the FET is 260 rnA/V, corresponding to 105 mS/mm. The rf performance is close to the state of the art for GaAs power FETs: 920 mW at 1 dB compression with 42% power-added efficiency at 5.5 GHz. The device is intended for use in a power amplifier at 5-6 GHz, where 3W output at 7dB gain and 28% efficiency have been measured.

S. CONCLUSIONS

Gallium Arsenide MESFET and HEMT devices have now been established as important components for high-frequency analogue and high speed digital circuit applications. At the demands on device performance has increased the need for advanced technologies has emerged.

Devices with high reliability are necessary together with low paraSItIc circuit elements which degrade the device performance. The self aligned gate

Page 190: Semiconductor Device Reliability

184

structures embody advantages which bring about these special characteristics. In this paper we have shown that the current state of the art with refractory silicide and refractory nitride gate have now matured beyond the first stages of development. Metallisation systems have been developed which have been shown by basic studies to have the necessary thermal stability. Furthermore the devices fabricated from such systems have been used in real devices structures and exhibited many of the potential advantages anticipated.

We are very grateful to our colleagues Dr. H. Thomas (UWCC), Drs. W. Anderson & A. Christou (NRL), Dr. C. Palmstrom (Bell Comm.) for their valuable comments on the topic of this paper.

REFERENCES

1. C.J.Palmstrom & D.V.Morgan, Chapter 6 in pp.185-245 "GaAs materials devices and circuits" Ed. M.J.Howes & D.V.Morgan, Wiley 1985.

2. J.Mun (Ed.) "GaAs integrated circuits", BSP, London 1988.

3. D.V.Morgan & J.Wood, Proc. International Workshop Metals and Silicides" Houthalen, Belgium, March 1989. Science. (In press).

4. A.K.Sinha & J.M.Poate, App.Phys.Lett.23, 600-608, 1973.

on "Refractory Applied Surface

5. A.K. Sinha & J.M.Poate, Jap.J.Appl.Phys.SuppI.2 p.841 (1974)

6. D.V.Morgan & S.D.Mukherjee, Internal University of Leeds Report for SERC (1977).

7. A.K.Sinha, T.E.Smith & H.J.Levinstein IEEE Trans.Elect.Devices ED-22 218 (1975).

8. A.K.Mukherjee, D.V.Morgan, M.J.Howes, J.G.Smith & P.Brook, JVST .!.2., 138 (1979).

9. N.J.Yokoyama, T.Ohnishi, K.Odani, H.Onodera & M.Abe, IEDM 8 (1981), paper 4.1.

10. N.Yokayama, T.Ohnishi, K.Odani, H.Onodera & M.Abe, IEEE Trans.E1ec.Dev. ED-29, 1541-1547 (1982).

11. E.Kohn, IEDM Tech.Digest p.469 (1979)

12. T.Ohnishi, N.Yokoyama, H.Onodera & A.Shibatomi, App.Phys.Lett. 43 (6) 600-602 (1983~

13. N.Yokoyama, T.Ohnishi, H.Onodera, T.Shinoki, A.Shibatomi & H.Ishikawa, IEEE J.-SSC, SC-18, 520 (1983).

14. A.G.Lahav, C.S.Wu & F.A.Baiocchi, JVST B6(6), 1785 (1988).

Page 191: Semiconductor Device Reliability

185

15. Z.Zhongde, N.W.Cheung, Z.J.Lemnios, M.D.Strathman & J.B.Stimmell, JVST, B4(6), 1398 (1986).

16. D.A.Allan, lEE Proc. ill (I), 18 (1986).

17. T.N.Jackson & J.F.De Gelormo, JVST B3(6), 1675 (1985).

18. K.L.Kavanagh, S.H.Chen, C.J. Palmstrom, C.B.Carter & S.D.Mukherjee, Mat.Sci.Res.Symp. 25 143-148 (1984).

19. W.F.Tseng & A.Christou, IEDM Tech.Digest, 174 (1982).

20. W.F.Tseng & A.Christou, Elec.Lett . .!.2. 330 (1983).

21. W.F.Tseng, B.Zhang, D.Scott, S.S.Lan, A.Christou, B.R.Wilkins, lEE Trans. Elec. Devices Lett. EDL-4 207 (1983).

22. D.V.Morgan, H.Thomas, W.T. Anderson, P.Thompson, AChristou & D.J.Diskett, Elec.Lett 23 No.21 1154-1155 (1987).

23. D.V.Morgan, H.Thomas, W.T.Anderson, P.Thompson, A.Christou & D.J.Diskett, Phys.Stat.Sol.(a) ill 935 - 940 (1988).

24. K.Matsumoto, N.Hashizume, N.Antoda, K.Tomizawa, T.Kumosu & MIida, Inst.Phys.Conf.Series 65, Chapter 5, 317-324 1982.

25. J.R.Waldrop, S.P.Kowalczyk & R.W.Grant, JVST 21(2), 607 (1982).

26. N.Uchihomi, MNagaoba, K. Shimodo, T.Mizoguchi & N.Toyoda, JVST, B4(6), 1392 (1986).

27. J.Y.Josefowicz & D.B.Rensch, JVST B5(6) 1707 (1987).

28. S.K.Cheung et al. JVST B6(6), 1779 (1988).

29. H.Yamagishi, Japan JAP 23, L895 (1984).

30. J.Woodhead, N.Uchitami, A.Kameyama, Y.Ikawa & N. Toyodo, IEEE Trans. ED-34, 170 (1987).

31. A.E.Geissberger, R.A.Sadler, M.L.Balzan & J.W.Crites, JVST B5, 1987.

32. A.E.Geissberger, I.J.Bahl, E.LGriffin & R.ASadler, IEEE Trans. ED-35, 615 (1988).

33. L.C.Zhang, C.L.Liang, S.K.Cheung & N.W.Cheung, JVST B5(6), 1716 (1987).

34. R.ASadler & L.F.Eastman, IEEE Elec. Dev. Lett. Vol. EDL-4 215-216 (1983).

35. I.Hanyu, S.Asai, M.Nunokawa, K.Joshin, Y.Hirachi, S.Ohmura, Y.Aoki & T.Aigo, Elec. Lett 24, No.21 pp.1327-28 (1988).

Page 192: Semiconductor Device Reliability

186

36. M.Kamada, H.Ishikawa, K. Kaneko & N.Watanabe, Elec. Lett. 24, No.5 271-272 (1988).

37. J.H.Magerlein et a1. JAP §l, 3080, (1987).

Page 193: Semiconductor Device Reliability

SIL

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Page 194: Semiconductor Device Reliability

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Page 195: Semiconductor Device Reliability

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Page 196: Semiconductor Device Reliability

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Page 197: Semiconductor Device Reliability

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Page 198: Semiconductor Device Reliability

192

2: l-I CJ W I ([ W ([ ([

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/ ' I "

x I ,

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1.2 ([

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>-I--l « w 0

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o I ~.<.-~ -,-I __ --'-__ --'-__ --'--__ -'--__

as-deposit 500 600 700 800 900

ANNEALING TEMPERATURE (DC)

Barrier height ( 4>Bn) and ideality factory (n) plotted as a function of annealing temperature for TiW, WSi and TiW on GaAs. (After Ref. 13).

Page 199: Semiconductor Device Reliability

Ie

Figure 2.

t

o

Figure 3.

1.°r 0.8

0.6

ol

'} 1.3

1.1

oL..;, o I

WSix I GaAs annealed at 800°C

.. ....• . •

...-----~ -+--

I (j---J 0.5 0.6 0.7 0.8 2.0

ATOMIC RATIO OF WSix

Barrier height (!/IBn) and ideality factor (n) plotted as a function of atomic ratio W/Si for barriers on GaAs. (After Ref. 12).

as deposited

lOOO°C. 20 min

Co-sputtered WSi 0.59

Thickness = 0.15 I'm

2.275 MeV He

1650 RBS

100 200 300

CHANNEL NUMBER ~

( I

w

500

RBS spectra of WSi~ I e/GaAs contacts showing an interfacial reaction after a 1000 t anneal for 20 min. (After Ref.27).

193

Page 200: Semiconductor Device Reliability

194

100

o ..J 80 w >-o W N 60 ..J « :;;: cr o z

20

++ 0

3 MeV He 60 tilt

Unonneoled

GoAs

interface

Unol'¥lealed

To

80ac 20min

920°C 20min !I !f I!

if Gal As f!

I In at Ii interface 'i

I t

To

O~~~L-~~--~---.---------.~~~~~~/~----~~~ i

300 :350

Figure 4.

400 450 500 550 CHANNEL

RBS spectra of a SijTajSijGaAs structure before and after annealing at soooe for 20 mins. (After Ref. IS).

Page 201: Semiconductor Device Reliability

1.0

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Page 202: Semiconductor Device Reliability

,.... 2 c:

:l

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~

Page 203: Semiconductor Device Reliability

Reliability Limitations of Ketal Electrodes on GaAs

BoLo Bartnagel Institut fUr Bochfrequenztechnik Technische Bochschule Dar.mstadt

Herckstro 25 6100 Dar.mstad.t

Federal Republic of Germany

ABSTRACT. The reliability of metal electrodes on GaAs is limited by diffusion processes, which can be enhanced by local high electric fields, and by electron wind effects, when large current densities occur. In both cases, the semiconductor-surface quality before metallization has a strong influence. New metallization schemes are presented to reduce such problems.

10 Introduction

The life-times of GaAs devices, such as FETs and led's, depend stron9ly on the stability of their metal electrodes, L.e. Schottky-, ohmic and heat sinking contacts. Three important effects have to be considered in detail, namely

1. the long-term sandwiches ,

interdiffusive effects of metal

ii. the electric-field stability of electrode edges concerning in particular metal migration between closely spaced neighbouring electrodes and

iii. material migration along narrow conductors carrying large current densities.

Regarding the first case, it is well known that certain metals such as Au or Ni must not interact with GaAs since an exchange process involving particularly Ga causes a slow deterioration of the contact quality. Therefore, a diffusion barrier based on WSi 2 was selected.

197

4. Chris/au and B. A. Unger (eds.), Semiconductor Device Reliability, 197-210. ~ 1990 Kluwer Academic Publishers.

Page 204: Semiconductor Device Reliability

198

An often life-time limiter of planar GaAs devices is given by lateral material migration across the GaAs surface between neighbouring electrodes, which finally leads to an interelectrode short circuiting bridge. The mechanism responsible for this catastrophic failure can be attributed to the existance of high electric surface fields and can be described by the phenomenon of field­assisted surface diffusion. The effect of surface treatment on this lateral material migration is significant as XPS (X-Ray Photoelectron Spectroscopy) studies of (100) - GaAs surfaces demonstrate.

The third effect to be discussed here concern electromigration of material in narrow metal conductors. This also exhibits behaviour which depends strongly on the type of GaAs surface onto which the conductor lines are deposited.

2. Stability Enhancement by a Diffusion Barrier

Highly stable ohmic contacts can be obtained for example by using

(i) e-beam evaporated 100 nm Ge (as dopant after annealing at above 500oC);

(ii) 100 nm WSi2 sputter deposited and

(iii)a layer of Au (Fig. 1).

The ohmic behaviour is demonstrated by Fig. 2. Using transmission line and sidewall resistor gtetho~s, ( giving both s pecific6 resis tances better than 10- Qcm for nGaAs with n = 101 cm- j , Si doped), and based on XPS studies involving Ar+ ion etching (Fig. 3 + 4), one can establish that up to values higher than 4600 C no modification of the contact resistance or the compositional profile could be observed, even after prolonged thermal stressing for more than 200 hours. The W profile of the XPS data remains stable with respect to the WSi 2-Ge interface up to temperatures of 510oC. Such work shows that it is possible to produce reliable contacts on GaAs operating even at elevated temperatures in contrast to commonly employed ohmic contacts of AuGeNi and others.

Page 205: Semiconductor Device Reliability

199

3. Edge-Stability of Metal Electrodes

Interelectrode material transport in unpassivated and in PECVD-Si3N4-passivated GaAs planar structures was studied (Kretschmer et al 1987, Kretschmer et all 1988). Metal migration between the electrodes due to the application of an electric field was found to depend strongly in both cases on the GaAs surface condition prior to structure deposition. Alkaline etchants are found to be superior to acidic ones to terminate the treatment of the GaAs surface before the various thin-film depositons.

XPS studies have shown that the onset of material migration is directly proportional to the amount of As 203 on the GaAs surface (Fig. 5). The best results were achieved with an ammonia treatment of the GaAs surface, whose compositional development is given by Fig. 6. Fig. 7 shows a scanning-electron micrograph of an interelectrode short circuiting bridge. Fig. 8 illustrates the areas of interest. This MeSFET type structure consists of two metal contacts on GaAs. The positively biased ohmic contact at the left side of the Figures is a AuGeNi-alloy, the Schottky contact at the right side consists of AI. A passivation layer does not prevent mirgration entirely. Fig. 9 shows an electrode gap consisting of two AuGeNi contacts passivated by Si3N4. Migration took place from the positively to the negatively biased electrode. It seems that the locality of migration is the interface between the GaAs surface and the Si3N4- layer. This point seems to be confirmed by other observations.

We obtained satisfactory Si3N4-GaAS interfaces if we applied an ammonia plasma-trE~atment before Si3N4 deposition to the GaAs surface. This treatment was performed in the same reactor and with the same conditions as for Si3N4 plasma deposition, but the silane input simply switched off.

It is thus possible to select an optimized technology to reduce material instabilities due to electric fields between closely spaced electrodes.

4. Electron-Wind Studies

There are reports that electromigration of metals occur primarily with Al electrodes, but also with other conductors such as Au. In order to evaluate the influence of the type of GaAs surface before metallization, Al electrodes can be used. Al is deposited by evaporation on a polished semi-insulating GaAs wafer of (100)

Page 206: Semiconductor Device Reliability

200

orientation, after organic-chemical cleaning (acetone, trichloroethylene and methanol) and, the usual chemical etching. Electromigration was determined by measuring the change in resistance of the conductor line using high­impedance monolithic potential probes. The test structures were manufactured by photolithographic lift-off using Shipley's Photoresist 1350. The electrodes were from 850-1000 A thick, and always evaporated with exactly the same rate of 4 A/sec for the first 500 A and subsequently with 8 A/sec for the next 500 A. If any etch step was applied, this was always for one minute.

The migrating ion flux density for the transported Al is Ji=N . va' where N is the number of transported ions and vB is their drift velocity. The ion drift can be approximated by an equivalent mobility ~i and the force F exerted by the electron wind so that va=~i . F, where F is given by the effective charge of the mlgration ion and the electric field E=J/cr (J is the electric-current density applied to the conductor and cr is the electrical conductivity of the Al film).

The mobility can be expressed by

~=D/fkT

Where D is the diffusion constant, kT is the Boltzmann constant times temperature in K and f is the correlation factor, depending on type of lattice; and where

Here EA is the these relations velocity is

relevant activation energy. together, one finds that

Taking all the drift

(vB is determined from the measured rate of increase of resistance of the current-stressed conducting line and that EA can be found by plotting VaT/J versus l/T from the slope of the straight lines accordlng to

where k is a constant containing all the remaining terms introduced above.

Page 207: Semiconductor Device Reliability

201

The experimental findings are given in Fig. 10, which gives the activation energy values, the constant k and the drift velocity at 1000 C, as presented by the Table . It is instructive to consider also va versus T (Fig. 11) since it directly indicates which GaAs-surface treatment is preferable. This appears to be etching with NaOH + H202~ al though EA is not of the highest value of the cases tested, it does have the lowest values of vB at temperatures up to around 1800 C.

5. Concluding remarks

It is therefore possible to design a GaAs technology for long device life times. Addi tonal improvements of ohmic and Schottky contacts can be obtained (Wiirfl, 1989) by using improved diffusion barrier sequencies involving a thin layer of Ti between the WSi2 and small additions of Au and Ni to the Ge in order to incorporate Ge better into the GaAs surface layer for reduced contact resistances (where all the Au and Ni needs to be consumed in this drive-in process to maintain the high contact stability of the diffusion-barrier scheme). Similarly, heat sinking and via-hole technology need to be considered (Oaga, et all (1986), Hartnage1 1989).

The problem of field-assisted surface migration of material seems to be associated with surface-roughness effects of GaAs with residual AS20 3 layers, as found by til ted double replica TEM ( Seth~ , et a1 1986 ) and by Scanning Tunnelling Microscopy (Richter, et a1 1988).

The electron-wind phenomena in high-current-carrying narrow conductors depends of course strongly on the crystallite size of the polycrysta11ine conducting film, since material transport occurs primarily along grain boundaries and not along crystalline material (Sethi, et a1 1985).

This crystallite size is determined by film-deposition parameters and the GaAs surface conditions. Therefore the final semiconductor-surface treatment beforemeta1 deposition leads to various activation energies and it is thus quite possible to obtain improved stabi1i ty against e1ectromigration by selecting an optimum GaAs surface etch.

6 • References

J. Wrfl "Herstellung und Untersuchung zuverlassiger Metallkontakte auf GaAs zur Entwicklung von Hochtemperaturstabi1en

Page 208: Semiconductor Device Reliability

202

Halbleiterbauelementen" , Doctoral Thesis, Techn. Univ. Darmstadt, Jan. 1989

H. L. Hartnaqel "Verbindungstechnik fur Hochstfrequenzhalbleiter" , Verbindungstechnik in der Elektronik, Heft 1, Marz 1989, p. 10-12, DVS-Verlag, Dusseldorf

O.P. Daga, E. Fricke, B.L. Hartnagel "Improved Via-Hole Etching for Source Grounding of Microwave MeSFETs, J. Electrochem. Soc. 133 1986, p. 2660

R. Richter, B.L. Hartnagel "Studies of Chemically treated GaAs (100) Surfaces by STM in air, October 1988, Int. J. EI., 1988, vol. 65, 779-787

B.R. Sethi, H.L. Hartnagel, G. Jourdan "Surface Topography of Etched GaAs Surfaces", Int. J. EI., vol. 60, no 5, 561-563, 1986

B. R. Sethi, H. L. Hartnaqel "Characterization of Electromigration Damage in Current­Stressed AI-Gates as Used for GaAs MeSFETs", J. Phys. D:Appl. Phys., 18 L9L13, 1985

E.-H. Kretschmer, B.L. Hartnagel "Interelectrode Metal Migration on GaAs", paper presented at IEEE Reliability Physics Symposium, San Diego, CA, USA, April 6-9, 1987, Conf. Proc. CH2388-7/1987 IEEE/IRPS

E.-B. Kretschmer "Die Laterale Materialwandlung zwischen Elektroden und ihr EinfluB auf die Zuverlassigkeit planarer GaAs­Bauelemente" , Doctoral Thesis, Techn. Uni v. Darmstadt, FRG, Fortschritt-Berichte, VDI-Verlag Dusseldorf, Reihe 9: Elektronik, Nr. 76, 1988

Au 140 nm)

WSi21100nm) Ge 1100 nm)

bulk GaAs

Fig. 1 Structure of the metallization used

Page 209: Semiconductor Device Reliability

lImA ,

Ge-WSi2 -Au 1 , , , , n -GaAs (6.1017/em3)

A = 32·10 - 4 em 2 , 0,5 ,

-3

,

, : -0,5 , ,

I , -1

2 3 U IV)

- - - annealed at 500 0 C for 2min

-- unannealed

Fig. 2 I/V characteristic of two circular pattern (area A)

.,. -

100----------------...,

Ga 2P3/2

Au 4f /~ ...-- -- ---

/' As 2P3/1 __ _ _ Ge 2P312 ' ,.-~-----

// '§ , =- 50 W4f .... c:I .... -.c .... c:I

.............. .' •••• I I ..... -..

_"":'"--, ". I : /" SI2s \..... "

. : / \ ... I, \ : ,." .~ \\. ;' V: K-'l. ':,. .-.~.-.-. ';;I. .. ",

00 -20 40 60 80 100 120 140 160 180 Sputter-time (min)

Fig. 3 XPS-sputter profile of a sample annealed at 460°C for 1 hour

203

Page 210: Semiconductor Device Reliability

204

1 =::: 0 > -Cl.I c::n c

=::: 0 > -c -0 ~ en Cl.I ~

~ ......

100 r-------------------,

fI) -C :::>

01s -" ,......-,/" As2P3/2

-~------W 4f >. 50 ...........

/ ...... , .. / ", ...

~ ... -..c ... ~

.. Si2s

20 40

, , , , ,

160 160

Fig. 4 XPS-sputter profile of a sample annealed at 610°C for 1 hour

60

45

30

15

Electrode distance/llm 5 20 40

150

100

50

320

240

160

80 alkaline etched GaAs •

A 51lm .201lm X 40llm

acidic etched GaAs ..

0.2 20 XPS ratio As 2p 3/2 (oxide) : As 2p3/2 (GaAs) -

Fig. 5 Theshold voltage for material migration versus XPS-ratio As (oxide) : As (GaAs)

Page 211: Semiconductor Device Reliability

As 2

P3/

2 Ga

2P

3/2

01s

As 3

d G

a3d

Ga !o

xide

) As

!GaA

s)

IIGa!

GaA

s)

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aAs)

A

s!ox

ide)

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(2)

u .., ."

-.. =- -. iii c ..,

13)

-c 14)

I II

I I

I I

I I

I I

I I

II

I 36

2 37

0 95

1 95

9 14

41

1449

1463

14

71

Etch

time:

(1

) 0

min

., (2

) 1/

2min

., K

inet

ic e

nerg

y E

kin le

V ---

(3)2

min

., (4

) 4m

in.

Fig

. 6

XPS

-spe

ctra

of

(lOO

)-GaA

s su

rfac

es t

reat

ed b

y NH

40H

(25

%)

H 20 2

(30

%)

H 20

~

with

the

rat

io 2

: 1

: 30

0 ~

Page 212: Semiconductor Device Reliability

206

Fig. 7 SEM micrograph of interelectrode short-circuiting bridge

Area of material depletion

small initiations of migration

Drain (AuGeNj)

Gate - Rec ess Edge

Gate (AI)

Droplets due to material accumalation

material­migration lines

Fig. 8 Illustration of interelectrode short-circuiting bridge according to Fig. 7

Page 213: Semiconductor Device Reliability

Fig. 9 SEM micrograph of interelectrode short-circuiting brigge of PECVD-Si 3N4 passivated device. Angle of tilt is 75 .

207

Page 214: Semiconductor Device Reliability

208

\ VB T

J

-11 10

5

-12 10

5

CM/s, K (Afo1. ) AI

-13 10

5 x 10-1LJ

c ~ERATURE

I

L

NACH + ~C2

2,0 2,2 2,LJ 2,6 2.8 3.0 3,2 3,LJ 3,6 3 -1

10 IT (I( ) --+

-11 10

5

-12 10

5

-13 10

-14 5 x 10

Fig. 10 Arrhenius plots for electron-wind damage parameters vRT/J from resistometric measurements of A1/~aAs ~l evaporated on differently treated GaAs surfaces, J=1·8 x 10 A/cm).

Page 215: Semiconductor Device Reliability

1

-7 10

-8 10

-9 10

5

5

=10 10

5

209

-8 10

-9 10

-10 10

-11 ill ~ __ -4~ ______ ~ ______ ~L-______ ~~-11 10

100 150 200 TEI'1PERAlURE (Oc) ~

Fig. 11 Drift velocity va of Al-ions at different temperatures (in A16metal~ization evaporated on differently treated GaAs surfaces, J = 1·8 x 10 A/cm).

Page 216: Semiconductor Device Reliability

2\0

Table 1: Electromigration damage parameters in Al/GaAs structures

(AI-metallizations evaporated on differently-treated GaAs

surfaces)

GaAs surface treatment TE!Ilperature EA k VB range 3 at 10:Fc for °c eV (an K)

J = 1.8x106 Alan As

(an/s)

Al/GaAs

1. GaAs -- unetche::l 60 - 140 0.62:0.05 -4 2.81x10 4.63 x 10-9

2. GaAs etched with 0.52:0.02 -7 1.79 x 10-10 NaCl:! + H202 100 - 220 4.0 x10

3. GaAs etched with 0.37:0.045 3.55x10-9 1.35 x 10-9 H2S03 + H202 + H2O 80 - 155

4. GaAs etched with 0.15:0.23 4.42x10-11 -9

KOH + Hp 50 - 150 2.08 x 10

5. GaAs etched with

NH3 N

solu +Hp2+Hp 45 - 130 0.113:0.015 2.66x10-11 -9 3.86 x 10

Al/Cr/GaAs

6. GaAs - unetched 20 - 100 0.14:0.03 1.26x10-1O -9 7.96 x 10

Electromigration damage rarameters in Al/GaAs structures (Al-metallization evaporated on differently-treated GaAs surfaces).

2

Page 217: Semiconductor Device Reliability

FAILURE MECHANISMS OF GaAs MESFETs AND LOW-NOISE HEMTs (#)

Fabrizio Magistrali (:), Carlo Tedesco (*), and Enrico Zanoni (*)

(:) Telettra S.p.A., Via Trento 30, 20059 Vimercate (MI), Italy.

(*) Dipartimento di Elettronica ed Universita' di Padova, Via Gradenigo 6/A, Italy

ABSTRACT

Informatica, 35131 Padova,

Reliability of low and medium power GaAs MESFETs has been evaluated by means of a comprehensive test plan, performed mainly on commercially purchased devices manufactured by different technologies. Main failure mechanisms identified are related to gate metallization and Schottky contacts (metal/GaAs interdiffusion, gate E~lectromigration), ohmic contact degradation (increase of contact resistance, drain/source electromigration), surface effects and high humidity effects. Reliability of low noise HEMTs of different suppliers and technologies has been evaluated by thermal storage at 250 ·C. Degradation appears to be dominated for shorter times «500 hours) by interdiffusion / interfacial effects which affect the Schottky contact and/or cause variations in the 2-DEG concentration, with consequent degradation of Idss and Vp. For longer times (>500 hours) increase in Rs and Rd takes place, which gives raise to an increase in RL and is possibly due to ohmic contacts degradation.

(#) Work partially supported by CNR, Progetto Finalizzato Materiali e Dispositivi per l'Elettronica a Stato Solido.

211

A. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 211-267. © 1990 Kluwer Academic Publishers.

Page 218: Semiconductor Device Reliability

212

1. INTRODUCTION

The GaAs MESFET is the key semiconductor device for microwave radio links, radar and satellite applications. For this reason, a considerable amount of accelerated life testing of both low noise and power MESFETs in conditions of no bias, dc bias and rf operation has been conducted in the past in several laboratories [1,2,3,4]: early devices were affected by Au-AI interaction [3], ohmic contact resistivity increase [5] and electromigration of the ohmic metallization [6]: these problems have been overcome by suitable technological improvements [2,3]. On the other hand, some failure mechanisms still represent a concern for the reliability of GaAs MESFETs.

In operating conditions, the dominant failure mode of power GaAs MESFETs is device burnout, i.e. a catastrophic process which leads to device melting: being usually completely destructive, burnout phenomena are of different interpretation: long-term burnout has been attributed to surface degradation phenomena [7], while pulse burnout has been characterized using Boltzman equation [3,8] and has been attributed to hot electron injection from the drain, and propagation of Gunn domains from the gate to the drain. Other failure mechanisms can induce parametric degradation of devices including GaAs surface degradation [9], backgating [10], gate electromigration [11] and degradation of Schottky [12,13] and ohmic contacts [5,6].

Due to their better noise figure and transconductance, High Electron Mobility Transistors (HEMT) are rapidly replacing GaAs MESFETs for low noise applications. The main feature of the HEMT is the spatial separation between the carriers (electrons confined in the two dimensional electron gas, 2DEG) and their parent impurities (confined in the AIGaAs layer ), thus achieving extremely high electron mobility. In a way, the HEMT can be viewed as a MOSFET where the insulator has been substituted by a wider gap semiconductor. Electrons are confined in a potential well at a fixed and very small distance from the gate, thus obtaining a high transconductance. Due to the novelty of these devices, very few data are available concerning their reliability: reported failure mechanisms are, beside burnout [14], ohmic contacts degradation [15-19], surface effects [20], changes in the 2DEG concentration [21-26] and impact-ionization related phenomena (kink effect) [27].

This paper reports results obtained during a comprehensive reliability evaluation plan of both power GaAs MESFETs and low noise MESFETs and HEMTs, performed mainly on commercially purchased devices manufactured by different technologies. Only failure mechanisms identified during dc accelerated testing will be discussed: burnout phenomena,

Page 219: Semiconductor Device Reliability

213

being typical of rf operation, will not be analyzed here. After a review of device electrical and thermal characterization techniques (section 2), failure mechanisms of power GaAs MESFETs are reviewed (section 3). These include reliability problems due to Schottky contacts and metallizations (3.1), ohmic contact degradation (3.2), humidity effects (3.3) and surface effects (3.4). A short description of contact failure analysis methods based on the "backetching" technique is given in paragraph (3.1.3). Finally, thermally activated failure modes of low-noise HEMTs are described in section 4, followed by Conclusions.

2. DEVICE CHARACTERIZATION TECHNIQUl~S

2.1 ELECTRICAL CHARACTERIZATION METHODS

In order to obtain meaningful results, accurate electrical characterization of devices must be performed both before and during accelerated tests. Basic device parameters (Idss, Vp, gm' Po, ... ) Gan be directly estimated from device electrical characteristics. As reported in the introduction, however, variations of these parameters can be due to many different failure mechanisms, so that a deeper characterization is required to identify which device areas have been affected by the degradation phenomena. In both MESFETs and HEMTs, ohmic contact degradation can be followed by measuring parasitic series resistances Rs and Rd, while the integrity of gate Schottky contact and metallization directly influence the Schottky barrier height ~ and ideality factor n, the open channel resistance Ro and gate parasitic series resistance Rg. variations in the 2DEG electron concentration of HEMTs will affect Ro, Vp, gm and Idss. The extraction of these parameters from device characteristics can be obtained by different methods [28-35]. For MESFETs devices the Fukui method [28] is the most widely used. The technique is based on the Shockley analysis of the JFET behaviour [33]. It enables Ro and the sum Rs + Rd to be evaluated assuming a.n ideal gate metal­semiconductor junction with constant doping and carrier mobility across the gate length and the epitaxial layer thickness. Source (drain) series resistances of FET's can be also evaluated by means of "end resistance" measurement [29-31]. In this case the FET is modeled as a distributed diode­resistance network, and the knowledge of the doping profile is not required, thus enabling ion implanted MESFETs to be easily measured; moreover, the method can be applied also to HEMTs. Unfortunately, pure "end-resistance" measurements do not enable the contribution of the channel resistance to be separated from the parasitic resistances Rs and Rd. In [35] t.he sum Rs+Rd for HEMT devices is obtained by plotting

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214

Rds=Vds/Ids in the linear zone as a function of 1/(Vg-Vp). Unfortunately, this approach is based on the hypothesis of complete depletion of carriers in the AIGaAs [36], which has been shown to be false by more accurate modelling [37]. The problem of evaluating Rs and Rd in HEMTs is further complicated by short channel effects [38], by the fact that in low-noise devices the open channel resistance is comparable to Rs and Rd, and by the two-layer distributed nature of the access regions between the ohmic contacts and the device active area. During our accelerated tests, beside basic device parameters Rs, Rd, Rg and Ro of MESFETs have been evaluated both according to the Fukui method [28] and to the "end-resistance" method [30,31], and the results obtained have been correlated: for HEMT devices, Rsend, Rdend and Rg have been measured according to [31].

2.2 THERMAL CHARACTERIZATION METHODS

Accurate evaluation of the channel temperature of devices submitted to test is needed to correctly accelerate the different failure mechanisms and to evaluate their activation energy. The channel temperature Tch of an electronic device is conventionally described as the sum of the case temperature Tcase and of the product of the power dissipation Pd by the thermal resistance Rth. To evaluate Rth of microwave MESFETs, the electrical method based on the forward I-V characteristics of the gate Schottky barrier diode [39,40] is widely used: it enables Tch (LiVgs) to be evaluated through a calibration curve, so that Rth is then obtained from the knowledge of Tch ( Li Vgs) , the case temperature Tcase and Pd: Rth = (Tch-Tcase)/Pd [39,40]. It should be noted that also Rth is itself a function of T. In operating conditions, or during accelerated life tests, however, the power dissipated in device active areas leads to a non-uniform increase of the device temperature. Tch(

LiVgs) is therefore an unknown weighted average of the temperature distribution on the device and can therefore be very inaccurate, in particular if a small area of high temperature exists within the structure [41].

The actual temperature distribution on the chip can be measured by liquid crystals techniques [42] or directly observed by means of high lateral resolution IR thermography, which allows the detection of thermal gradients due to local differences in the heat dissipation or structural inhomogeneities.

Figure 1 shows the temperature profiles taken perpendicularly to gate fingers in the hottest areas, measured by an IR thermography microscope (Barnes CompuTherm), in two 10-gate 1/2 W devices: #11 with via holes and lower substrate thickness (30 pm) and #7 with a conventional structure (substrate thickness 50 pm). The

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215

40

x 30

GATES

Fig. 1 Temperature profile measured perpendicularly to gate fingers in MESFET #11 (with via holes) superimposed with the corresponding profile of device #7 (without via holes): Pd = 2.8 W, Tcase = 35 'C. The profiles were performed crossing the hottest area of the device.

devices were chosen as examples because they show anomalies due to gate misalignments. The temperature evaluated by electrical measurements marked as a dotted line. Beside a noticeably better behaviour of the via-hole device, several features observed in Fig. 1:

thermal channel

is also thermal can be

i) Temperature distribution is markedly nonuniform, with a large temperature increase corresponding to each gate finger.

ii) Maximum temperatures of gate active areas tend to follow a bell-shaped profile with the maximum at the centre of the device. Misalignments, however, cause an abnormally high value of temperature of some gate fingers, which are 10 ·C -20 ·C hotter than others [43,44].

iii) Drain and source regions are up to 50 ·C colder than the active areas.

iv) In devices with a high number of gates, large active

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216

area and marked thermal nonuniformities, Tch( measurements tend to underestimate ( = 10 ·C in Fig. actual maximum temperature present on the chip, as observed by other authors [41].

Ll Vgs) 1) the already

These data suggest that extrapolation of accelerated test results based only on the measurement of Tch( Ll Vgs) by conventional electrical methods should be performed very carefully and that IR thermomicrography techniques, even if affected by other problems [41], can provide much more insight into thermal behaviour of devices, and, consequently, on their long-term stability.

3 FAILURE MODES AND MECHANISMS OF POWER GaAs MESFETs

3.1 RELIABILITY PROBLEMS DUE TO GATE METALLIZATION

The gate Schottky contact directly influences device electrical parameters in term of drain saturation current, reverse breakdown voltage, input capacitance, gate parasitic series resistance. To obtain a reproducible and thermally stable Schottky barrier, a correct choice and control not only of the gate metallization scheme and of the deposition method, but also of the GaAs surface cleaning procedures, of the impurity content of the metal layers, and of the chosen passivating material and its deposition process is required.

In most low-noise and power GaAs MESFETs for microwave applications, gate fabrication follows ohmic contact formation, and it is not required that the gate Schottky contact is able to withstand the ohmic-contact annealing procedure. The metal chosen for the gate contact should (i) provide a good Schottky contact with low leakage current and sufficiently high barrier height; (ii) have a good adhesion to GaAs; (iii) have a low sheet resistivity; (iv) have good processing and lithographic qualities; (v) be thermally stable with respect to interdiffusion phenomena; (vi) have a low tendency to electromigration and corrosion.

The combination of the requirements listed above reduces the possible choice to a few metals [45,46]: Al and Ti are by far the most used. The Al/GaAs contact is thermally stable up to 400 ·C, 1 hour [46]. Moreover, Al has sufficient electrical conductivity to be used as single component of the gate for microwave devices. On the contrary, Ti can not be used alone because of its high resistivity. and Ti oxidizes easily making wire bonding difficult. An Au overlayer is therefore commonly superposed to enhance conductivity and solve bonding problems.

Because the AU/Ti/GaAs system is not thermally stable even at 200 ·C [47], interdiffusion barriers are used

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217

between the Schottky contact and the top gold layer. The more commonly employed systems are Ti/Pt/Au, Ti/W/Au, Ti/Pt/Cr/Au, Ti/Pd/AU.

The increased complexity of Au-based systems is balanced by a better compatibility with ohmic contacts, which are generally based on alloyed Au-Ge or Au-Ge-Ni. A large number of MESFETs failures in early applications, in fact, was due to Au-AI interaction, which originates purple­plague formation and galvanic corrosion [3], with consequent interruption of the gate metallization. other advantages include the increased resistance to electromigration and to corrosion phenomena [45] , while minor problems are due to the thermal expansion difference between Ti-w and GaAs which results in the generation of defect:s just below the gate, with increase in leakage current and reduction in carrier mobility.

The specific failure mechanisms of both Au-based and AI-based gate metallization systems are described in the following.

3.1.1 Interdiffusion in ilie Au/interdiffusion barrier/Ti/GaAs systems.

The main failure mechanism of the Au-based gate metallizations is due to the interd:iffusion of Au into GaAs through the interdiffusion barrier metals. As an important example, we will report here data concerning commercial devices with Ti/W/Au gate metallization and reference test devices with Ti/AU gates, whose reliability was investigated by means of: i) unbiased high temperature (HTS) storage at Ts=245 ·C ~ii) high-temperature reverse bias (HTRB) test at Tch=125 ·C and Vgs at the maximum allowed reverse bias~ iii) high forward-gate current (HF~C) te~t at forward gate current densities up to j = 5 . 10 A/cm at Tch = 200 ·C~ iv) dc life tests at different channel temperatures up to Tch=185 ·C (HTOT,High Temperature Operating Test). Dominant failure mode consists of a decrease in Idss and Vp and an increase in open channel resistance, Ro. This failure mode is common to all the accelerated tests performed, and appears therefore to be mainly thermally activated. Fig. 2 shows Idss, Ro and Vp measured by the Fukui method [28] as a function of time for a Ti/W/Au device that failed during HFGC tests. Auger analysis of the gate metallization was performed [13] and clearly indicated that interaction between gate metallization and GaAs active layer has taken place in these devices. In fact, Au diffused through the W and Ti layers and penetrated deeply into the GaAs substrate.

The interdiffusion of gate Au metallization and GaAs can affect channel properties through two mechanisms [48]. One of these is the advancement of the metal/semiconductor interface into the channel, thereby decreasing the available

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218

4 HFGC Tch ;200°C OJ

~

j;5 0 105 A/cm2 a

> "0 0:: H uS

~ f- 5 u UJ Z 150 Z

c.!l w ~ <t 0:: CJ) f- '" ...J :J CJ)

0 U CJ)

> Z LJ.J

u- 2 100 '" u- ~ ...J 0 f- LJ.J I <t Z

I '" Ro z U :J <t Z !;:( 50 I a. CJ) U 0 • •

0 0 0 0 500 1000 1500 2000

TIME (h)

Fig. 2 Degradation of Idss, Vp and Ro in Ti/W/Au gate MESFET. Same results were obtained after unbiased thermal storage at 200 ·C and biased life tests such as HFGC.

channel thickness. The other is the dopant action of the diffused metal atoms with resultant alteration of the net donor density in the channel~ in particular Au is reported [49] to compensate donors in n-GaAs. Both mechanisms should manifest themselves in reduced Idss and Vp and in increased Ro.

To ascertain whether channel thickness reduction has taken place in failed devices, the "backetching" technique [50] was adopted. This technique, described in par. 3.1.3, allows to expose the metal-semiconductor interface by means of chemical etch from the semiconductor side. Fig. 3 shows the exposed surface of the gate metallization after complete GaAs etching in an unfailed, Fig. 3 a) and failed, b), Ti/W/Au device (after 3000 h of thermal storage at 245 ·C). In the failed device we observe a marked metal/semiconductor interdiffusion , with formation of voluminous Au grains, 300-500 nm wide, which may have completely penetrated the active channel thickness. These large grains are mainly located in the gate area, although with different distribution and size. Au grain formation takes place through solid-state diffusion of Au through the Wand Ti layers and subsequent regrowth onto the GaAs substrate [51). This causes a reduction of the active channel height, and explains the observed lowering of Idss and Vp, and the increase in Ro.

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Fig. 3 Rear side of Ti/W/Au metallization in : a) MESFET and b) annealed one after 2000 hours at Tch

219

untreated 200 ·C;

The effectiveness of the interdiffusion barrier depends on chosen materials, their thickness, their impurity (0, N) content. In particular, it has been shown that an oxygen content of = 4% in the W layer markedly improves the capability of the W/Ti layers to act as an interdiffusion barrier, probably through grain boundary decoration [52]. Due to the small dimensions of gate fingers, defects and inhomogeneities can playa major role in determining the contacts long-te.rm stability.

In particular, thermal gradients along gate fingers enhance interdiffusion effects in localized device areas [53]. Fig. 4 shows the IR temperature profile along two gate fingers in a 0.25 W, 4-gate MESFET with an unusually high Rth value (85 ·C/W with respect to an average value of 50 ·C/W). A marked nonuniformity of gate finger temperature is also evident in the~ Figure, possibly due to variations of the channel thickness under the gates, that can be attributed to a non-uniform recess etch of the channel and/or to defects in the die-attach. When these devices are submitted to accelerated test (4000 hours of dc life test at Tch = 200 ·C) enhanced interdiffusion effects take place in the central zone of the gate finger, where the temperature is higher than at the finger ends. The stronger Au-GaAs interaction is indicated by the presence of larger

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220

90 # 21

Teh ( il Vg s I

\ .', . /GATE 2 () 80 __ ~ _____ ,/l' __ '~'_::L

0 ,( i I

" I

! ". ",,://GATE 4 W

e::: 70 ' ( " , , /, ::::> :1 , 1"""1' ..... ,./\,, •.

'.' •• I. .. ~.

i (' 1\ I- ". , « /, I .~ I

" / I" I

e::: 60 '<, \ / II \1 \\ W / I ~ \ a. , I, ~ i (, :\ "

f

" , r \"J I. W 50 I ! ' , " I. l- I I : ' I, ,

\". .) ~

, ,

40 I-f :=C: ---; , GATE Y , MES4 & GATE' Y ~----'

WIDT H (Wi

* GATE LENGTH-WIDTH RATIO NOT IN SCALE

Fig. 4 Temperature profiles measured along two gate fingers of a 4-gates MESFET with a nonuniform temperature distribution between different gates.

Fig. 5 SEM micrograph of gate finger of a MESFET after 4000 hours of life test at Tch = 200 ·C; a) rear side; b) magnified zones.

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221

Au grains as revealed by the SEM micrograph of the backetched device, Fig. 5. By increasing the time, the reaction proceeds and large Au grains grow over the whole gate area.

structural inhomogeneities a1: the borders of the gate finger can also affect the properties of the interdiffusion barrier, thus causing enhanced interaction [53].

Table 1 summarizes results rE~ported in the literature for Ti-based schottky contacts on n-GaAs, with and without Au overlayer. Reported data confirm that observed degradation of Au-based gate MESFETs with Ti Schottky contacts cannot be due to Ti/GaAs interdiffusion effects only. Some authors report the formation of stable, interfacial TiAs compounds with a slight increase in Schottky barrier height from = 0.7 eV to 0.8 eV [54-57] after high temperature annealing (450°C, 30 min) In MESFET devices, it causes a slight decrease in Idss due to the widening of the gate depletion region at Vgs = 0 due to the increase in barrier height. 01:her authors [58] have observed Ga outdiffusion and Ti indiffusion in Ti/pt/AU metallized samples after 100 hours at 300°C. This however only induces an increase of leakaqe current in the gate diode characteristics.

Several authors have observed reduction of Idss, Vp and gm in Au-based gate MESFETs, Table 2; even if the failure mechanism involved has not always been well identified, interdiffusion effects with Au penetration have been repeatedly observed both in test structures [47,58-60, 61] and in devices [2, 6, 13, 60, 62-65]. As mentioned above, the reduction in Idss, Vp and gm has consequently been attributed to two mechanisms : (i) reduction of active channel thickness [13, 62, 64] or (ii) decrease in net donor concentration due to compensation effects [61, 66]. Neither of the two effects has been thoroughly investigated, even in test structures. Our technique, based on back-etching, allowed us to clearly demonstrate the reduction of channel height in treated devices.

3.1.2 Failure mechanisms of AI-gate MESFETs

Aluminum thin films were used for gate metallization in GaAs Schottky barrier MESFETs since the early years and are still widely adopted with excellent results. Al layers provide a barrier to the outdiffusion of dopant impurities and host atoms from the substrate and do not significantly indiffuse at the temperatures required for device processing and operation. Beside Au-AI interactions in early devices, two specific failure mechanisms of AI-gate MESFETs have been reported : Al/GaAs interdiffusion and gate electromigration.

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222

TABL! I InBRDIPFUSIOI 0' THASKD nTALLIZATIOIS 01 GUs 'ITH AID ,mOUT At OlBIL1TBIS

Bela I sehele Thenal treatleat Blectrlcal renllS Betallaretcal IDteraclioD lefereDce

Tl/Pt/Au 250 C, not reporled Tl-Ga-As Inter41ffuloD [U[ sa ouldlffulon ID TI Pt ln41 ffuloD lD Gals

TI 500 C, 2 h tb frol O. 62 TUs forlatlon [53[ to 0.65 e'

TI/Pt 350 C, 16 h stable stable [531

500 C, 2 h tb froiD. 60 'orlltioD of Tlls, to O. 66 eY PUs2, Pt3Ga

Tl 460 C, 30 liD aDreporte4 "rlatln of rus, [54 I TI2613, Ia: I. T el

AU"(Tl1 500 C, 24 h tb frol 0.65 Au llD1fOllly 41strlblte4 1601 to O.TO eY ID the '(Ttl llyer aDt Decrease lD 40Dor tatUnl off lDto the cODcntratioD. Gals.

Tl 400 C, I h tb frol O. TO IDlerlillDI renlt.1D (561 to 0.60 el I T1/t1:61/TI:U/GIU

Ilnctlre

Tl 360 C, 30 lID SUllIt IDeruse ID TI-UU IDterlelioD (STI tb IP to 0." 41 f fUUI-CODtrolled el lUll la : 1. T5 el

The forle' TUs reun II' tile rUIIlll, tb are stOle.

Tl/lu , 200 - 450 C lacPease II f1l1 PeaetralilD of 11 lIto (nl rU!Stlllly nt ' the Ictln all. llyer 410te I Ullce un It ZOO C.

ll-TI hterlclloa.

TIllu 100 - 500 C, I 11 Decrease of tb "-Tt-hl. llleP4lffuloD (III a .. !Deruse of D .tarllD, at 300 C

TllPtlll 100 - 500 C, 1 11 Decrease of n lOt re,.rtet (II) aDt IDcruse If D .tlltlD, at 350 C

TI/I/lI 100 - 500 C, I 11 Decruse .f tb .. nUlffu1t1 .. tt, Ill! ID' lIeltas. of D of 11 at US C. startlD, It 400 C

Page 229: Semiconductor Device Reliability

TAlLi 2 FAlLUn nCRUlS!S OF AU-BAn» GArB nSFBT's

GATi BBTAL

TI/V/AU

Cr / Au

TI/V/AU

TI/V/AU

TI/Pl/Au

TI/Y/lu

TI/Y/&I

TI/llIAI

T1/Pl/ll

TI/Y/AU

TI/Pd/AI

TI/Pd/AI

ACCBLlRA nD nST

30 - 160 C Tan life lesl

ITO-mc Teh lilh aod lilhoul de bias

m - 300 C slorace, 140 - 250 C life lesl

Slorace and II Ie lesl al Teh m - m C

life leslS slorace 290 - .00 C

I1fe lesls slOnce m - m C

»C )Ias 140 C, 250 C

rf l1fe lUl Teh : 200 C

Slonce, US C

Slorace 245 C de 11ft lesl Il Tch : ZOO C

FAlLUn HODBS

Tp Increase t) decrease CIT) uncuneed

Idss decrease Ba:!, 5-1. T tY t) Increase

Unspecified

Idss and Yp decruse, Inc ruse of Rd, Rs

Gale lealace h : 1. 3 ef

,I decrease h:l.5eT

Gale delerlOral1oo ia : 1. a n

Decrease lD 14ss an4 CI

I, leallce

Decrease 10 ldss 104 'po Iocrease lD 10.

slonce ZH-3l0 C: Decreue iD Idll dc lUe lesl nd 'po Tch : 115 C IDcrease lD Ids.

slOnCt at 300 C Decreue lD UII (-l01 10 100 IlD. I and fp.

PAiLUn nCRUmS

Uoldenl1fIU

C(ll profiles shol redlcllon of Icll,e chlnnel lhlckDess

At InlerdlfflS100

COlpeoslllon due lo OIl-diffUSion of dooor frol epl-layer: or lndlffuslon of llpnll1es

UD1dnl1 fied

JDldnl1f1ed

Voldnl1 fied

UD14nl1f1U

At-61 10UrU ffllin

At IDd1lfuion I"ulion of chuDe I htiChl deteclU ~, blcltlCIl1D,.

'I IoU ffuloo Redlcl10n of channel heiChl delect" ~, Cnl

'I 10411fuloo

223

RlF.

[TSI

(nl

( 61

( 661

( 21

( 21

(21

(21

121

1131

lUI

,HI

Page 230: Semiconductor Device Reliability

224

O~-------,--------.--------,--------.-------~

~'''' I \ -""'l .... A e -gates 1.. -.- __ _ I ....... _. _e_ l - ---Il_ l --- __ -~_..:_- .... ---e---~

_10 , -~----.---~~~. ?!< , , ~ ~_ ..... __ ... ____ -L __ .... ___ j. .. _"' ___ .. _A_

~ 20 .STORAGE (TCh =245°C); .HTOT(Tch =250°C)

... HFGC (TCh= 200°C; J=5·10 5 A/cm2)

o 500 1000 1500 2000

TIME (hours)

250

Fig. 6 Percentage of decrease in drain saturation current Idss observed in AI-gate during various accelerated tests.

a) AI/GaAs interdiffusion

Several authors [3, 10, 64, 67-69] have observed slight decreases in Idss of AI-gate devices after dc and rf life tests and storage treatments at high temperature.

Figure 6 reports results obtained on commercial 0.5 W AI-gate devices submitted to storage (245°C, HTS), dc life test (Tch = 250°C, Ids = 130 rnA, HTOT) agd hi~h forward gate current tests (up to 200°C, j = 5·10 A/cm , HFGC). The decrease in Idss was observed in all tests at temperatures higher than 150°C. The presence of a forward gate current crossing the AI/GaAs interface markedly enhances and accelerates the phenomenon. A sudden degradation of Idss does indeed occur in the HFGC test during the first hundred hours and saturates at about 85% of the initial value. A slower degradation was observed in the other conditions, despite the higher temperatures of the storage test and of the operating life test (Tch = 245°C and 250 °C respectively). The decrease in Idss is accompanied by an increase in barrier height, which can be reliably measured by the activation energy method [70]. This method does not require to know the diode area, which can change during the test due to gate electromigration.

Barrier height increases from 0.80 eV to 0.97 ~v after 24 hours of te~t at Tch=200 °c, j=5·105 A/cm, corresponding to 5.4·10 A/cm2 through each gate contact, Fig. 7 [12]. The observed increase in barrier height justifies the decrease in Idss observed in Fig. 6; in fact, the depletion region induced by the built-in junction

Page 231: Semiconductor Device Reliability

-12 10

-14 ~ 10

~ -15 ~ 10 N

-'==--VI -16 - 10

-17 10

CPB= 0.97 ± 0.01 eV

- - - - UNTREATED -18

10 --AFTER 24 HOURS

HFGC

T=5,105 A/cm 2

Tch= 200 'c

AI/GaAs-n

1019L-J-~_l-~~~l--L-J~~~~~,L--L-7~~J 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4

1000/ T (K -1)

225

Fig. 7 Activation energy plot for the measurement of barrier height of Ai gate MESFET before and after 24 hours of HFGC test.

potential widens and narrows the channel. The decrease in the pinch-off voltage Vp measured during the forward gate current test results to be 200 mV, in sUbstantial agreement with the increase in barrier height.

The increase in barrier height would suggest that a modification of the interface has taken place, possibly caused by Al/GaAs interdiffusion effects. Table 3 summarizes results reported in the technical literature about interdiffusion phenomena in Schottky diodes. In the early studies, Ai films on n-GaAs were submitted to high temperature (250'C - 500 'C) aging in vacuum or inert gas to evaluate the stability of metal/GaAS interface and of the electrical characteristics. An inc:rease of barrier height from about 0.7 up to 0.9 eV was found [46, 71] and atomic in-deep profiles of annealed structures showed that: i) oxygen was always present at th; metal-GaAs interface even for films deposited at Pa = 10- Torr [71] and it migrates from the interface into the Ai film towards the Ai surface; ii) As, and in particular Ga, migrated away from the GaAs surface into the Ai film generating stoichiometric deficiencies at the Al/GaAs interface. This interface change was taken as the main reason of the electrical characteristics variations [72].

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226

fULl 3 : IItllDJrrVSIOI II lI/IU. SelOfHf eOl!lm

flerlll lrutllDl : Ileclrlcll IUlne I"e PUlue lec ... UI lefereDee

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227

A new and more detailed explanation [73-76] has been proposed in the technical literature in recent years: aluminum films were deposited both with conventional procedures and in ultra-high vacuum conditions, and were studied by means of photoemission electron spectroscopy [76], Raman scattering [74], e(V) and r(V) electrical characteristics. The fundamental reaction scheme which emerges from these studies is one in which an AlAs-rich interfacial layer forms as long aE~ there is an aluminium sink (unreacted Al film) present. Depletion of this sink followed by continued reaction then presents a situation in which an interdiffused AlxGa1_xAs is detected. Because for all AI/AlxGa1_xAS systems the Schottky barrier height is greater than that of the AI/GaAs system, the formation of the ternary phase causes an increase of the r(V) barrier height of the treated AI/GaAs diodes, as long as the reacted region is thick enough so that it is not completely transparent to electron tunneling through it.

Similar results have been obtained also in schottky diodes fabricated by "in situ" deposition of Al on GaAs grown by molecular beam epitaxy [75]: annealing at 300 ·e led to a rapid increase of the barrier height from 0.75 eV to 1.05 eV owing to the formation of an AlxGa1_xAs interface layer detected by Auger atomic in-depth profiling.

These data suggest that also in our samples the increase in barrier height could be due to the formation of an AI~Ga1_xAs interface layer. The AI/GaAs interaction is markedly accelerated by a forward gate current, as is evident in Fig. 6. A possible explanation may be the presence of an interfacial oxide between metal and semiconductor in the untreated samples. This interfacial oxide layer possibly inhibits and/or delays interaction between Al and GaAs, when only thermally promoted, while during forward gate current tests the intense electron flux from the semiconductor to the metal may contribute to the breakdown and removal of this interfacial layer, thus promoting AlxGa1_xAs formation. Similar effects have been reported in [56] for Ti/GaAs cont.acts, whose increase in barrier height under thermal treatments is more rapid for UHV deposited samples than for conventional ones. Miret et al. [77] have studied the effect of electrical stresses on Schottky contacts on GaAs. Diodes were both forward (V=0.6 V) and reverse (V=-9.7 V) biased at room temperatu~e (20 ·e), with extremely low current densities (j=l A/cm ). At these current densitys levels, no effect for Al/GaAs diodes has been found (the increase in barrier height is smaller than 10 meV).

Although earlier works have reported decreases in rdss due to AI/GaAs interaction failure mechanisms does not seem to be a major problem for Al-gate MESFETs of more recent

of large [64], this reliability

fabrication,

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228

causing only moderate parametric degradation with decrease in drain saturation current Idss (see which stabilizes in the long term; appropriate during manufacturing could avoid this instability.

b) Electromigration of AI-gate metallization

a slight Fig. 6), annealing

In power MESFETs, large rf signals can cause net (dc) currents, which may be either of forward or reverse polarity, depending on the t~ning agd bia~ adjustments. Current density can reach 10 - 10 A/cm [78). AI-gate electromigration can therefore be a reliability problem for power MESFETs, and can become a threat when metal inhomogeneities and defects are present. Electromigration induces voids and openings in gate fingers, with loss of control of device drain current. Current density levels at which electromigration is observed in multilayer AU-based metallizations are higher; this failure mechanism, therefore, appears to be relevant only for Al devices.

r=~-----"""J------'J"'~ ···················-........,1----.....,

150;":.5 VIRGIN AFTER 3400 Ii :~ ,<

,~ ~~~ ~ ~ o "',,-.1 e /" ~ ,

,.. ~~~--'"

.~'~ . ~.'~::-~::: , .... "...

100~ l Vns (500mV!div) ; Vcs(SOOmvjstep) I

I ~ j#s #A.I ~I

! 50:-

If p'

2 TIME (k hours)

HFGC

T:= 5x 105 AI crn2

Tch =200 °c AI-

3 4

Fig. 8 Increase in the minimum drain current Idso at Vds = 3 V as a function of time during HFGC test for two samples. In the insert the drain characteristics of sample B after 3400 hours of HFGC test are compared with those of the untreated sample.

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To evaluate the resistance to electromigration of gate metallization, the gate Schottky junction was forw2rd biased, so that high current densit.ies ( = 102 -106 A/cm ) flow through the cross section of the gate metallization of each gate finger. The device wa.s kept at high ambient temperature ( 200 ·C) [12).

The two transistor charact~eristics inserted into Fig.8 refer to a virgin sample ang to a transistor submitted to a 3400 hours test at j = 5·10 A/cm2 at Tch = 200 ·C. In the failed device, control of drain current was lost, and it was no longer possible to reach the pinch-off condition.

I---i 40{-tm

a)

Fig. 9 a) EBIC image of a degradated sample after 2000 hours of HFGC test; b) magnified SEM micrographs showing the points A, B, and C where the gate fingers are interrupted.

The degradation can be followed during the test by measuring the minimum drain current IOSO' which can be achieved by increasing the reverse gate bias at a fixed drain voltage vos = 3V. Figure 8 reports Ioso as a function of the test time for two typical samples. The loss of control on the drain current is due to the opening of the device gate fingers caused by electromigration. Gate interruptions can be easily identified in SEM-EBIC (Electron Beam Induced Current) images of the Schottky gate junction, obtained by collecting the signal between gate and source/drain. Figure 9 a) reports the EBIC image of a failed

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test. from the a) •

A, Al

device after 2000 hours of forward gate current Electron beam induced current can not be collected those parts of the gate Schottky diode which are beyond metal interruption, and therefore appear dark in Fig. 9 The SEM micrographs of the gates corresponding to points Band C, Fig. 9 b), confirms the presence of voids in the fingers.

Beside Au-AI interaction, which was mainly observed in older devices [3], Al electromigration appears to be the major reliability problem of AI-gate power MESFETs, reported by almost all authors who have undertaken rf and forwar~

gate cur~ent t~sts at current densities between 103 A/cm and 5·10 A/cm and temperatures in the 175 ·C-300 ·C range [4, 68, 79-84]. In some cases electromigration is accompanied by Au-AI compound formation [3, 83]. Only Fukui et al. [67] observe no gate interruption after 30g hour~ of rf power test with a net dc gate current of 2.5·10 A/cm at 175 ·C-250 ·C. Because of the submicron dimensions of the gate fingers, film structure and homogeneity can have a SUbstantial effect on Al electromigration phenomena, as for si devices [85], and this can explain the data dispersion. The only alternative explanation was r~porte~ in [69] where gate openings were observed at j = 10 A/cm during life tests of 4W devices at Tch = up to 250 ·C; because of the low current density electromigration was refused as possible explanation, and voids were attributed to Al/GaAs interaction with complete metal consumption; however, no microanalytical data were reported to confirm this hypothesis.

Finally, multilayer structures such as Ti/AI/Ti, Ti/AI [84] and Al/Cr [86] have been tried in order to improve resistance of Al gates to electromigration; unfortunately, Ti is prone both to oxidation and to interaction with AI, while Cr was found to have a detrimental effect on stripe lifetime.

3.1.3 The back-etching failure analysis technique

Failure analysis of metal-semiconductor interdiffusion effects in GaAs MESFET devices presents some specific difficulties due to the nature of the device itself. In particular, difficulties may arise with conventional surface microanalytical techniques, like SIMS (Secondary Ion Mass Spectroscopy) and Auger spectroscopy, due to several problems: (i) the gate is extremely narrow «1 pm) and is embedded between the two high walls of the ohmic contacts. The lateral resolution of the employed technique can be too poor to allow the analysis; (ii) reaching the metal/semiconductor interface requires sputtering of the thick top metallization layers thus giving

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raise to loss of in-depth resolution and apparent interdiffusion effects; (iii) in Auger microanalysis, interferences between energy peaks of the different elements may markedly affect the sensitivity in the detection of low level of impurities or indiffused metals [13]; (iv) metal/semiconductor interaction may take place only in weak points, so that interdiffusion effects may be completely missed during spot analysis. For these reasons, microanalytical techniques should be complemented by an analysis method which enables the metal/semiconductor interface to be directly examined by SEM observations. The "backetching" technique based on the selective removal of the GaAs enables the metal/semiconductor interface to be observed from the "back" (i.e. from the GaAs substrate point of view), thus overcoming the difficulties listed above [50]. Selectivity is needed to preserve the bottom metal surface, which possibly retains the trace of the degradation mechanism. This could be a problem, mainly dealing with aluminium gates, because of the large amount of GaAs to be etched away, resulting in a rather strong reactivity of the chemical solution. Practical operations can be summarized as follows. The whole device (after removal of the package cap) is first of all molded in epoxy resin, as is usually done for metallographic specimen preparation. The choice of the resin is not critical, provided it penetrates all cavities of the package and of the chip surface (particular care must be taken for flip chip mounts) and hardens at room temperature and pressure without E~xcessive shrinking. Many suitable products are commercially available. In order to eliminate mechanical stresses that could destroy the thin metal and passivation layers after GaAs removal, the gold wires, when present, should be cut before molding. Then, the bottom of the chip is exposed by mechanically grinding the package, the die attach and the rear metallization of GaAs. This mechanical work could be reduced by dismounting the MESFET die from the package and embedding it alone into the epoxy resin, but in our experience the above method resulted safer provided that mechanical sh()cks be carefully avoided during the grinding time. Chemical removal of package material (with particular attention to die attach metallization) was also attempted, but it needs a very long time or excessively strong chemical reactions. Therefore, it was decided to proceed in grinding die attach and chip rear metallization by means of 1200 grit sand paper, up to completely expose GaAs. Chemical etching of GaAs is then performed, until the semiconductor has been totally removed. After proper washing and rinsing (deionized water and isopropilic alcohol), the specimen is mounted on a SEM specimen holder and coated with

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a conducting gold or carbon film according to observation requirements. The choice of the etchant solution MESFETs, and for this reason much devices with Au based gates. In solution, made of:

is critical for Al gate work was done first on this case a standard

13:20:5

at room temperature with continuous agitation etched the about 200 pm thick GaAs die in 35 min.

a b

c d

Fig. 10 A small cavity on the flat surface of the resin block indicates (a) the position of a back-etched chip; the bottom of that cavity shows (b) the MESFET structure; large magnification reveals Ga/Au islands at ohmic contacts (c) and a replica of GaAs surface ondulation in the gate area (d) •

A typical result is shown in fig.lO, zooming into the cavity

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left by the etched chip into the resin block (a) until showing the whole etched area (b) and focusing on very fine details as Au/Ga phases at ohmic contacts (c) or gate interface to GaAs (d). The backetched chip shown in Fig.10 is unpassivated, recessed gate and flip chip mount. It is relevant to recognize the replica of the GaAs free surface that the epoxy resin kept in the r.acessed region around the gate: the same interfacial ondulation of the latter is preserved outside the contact area, indicating a characteristical feature of the manifacturing process. The previous etchant can not be employed on aluminum, being non-selective. The following etchant was found to provide removal of 80 urn of GaAs in 40 min., with high selectivity against AI:

1:1:16

An example is reported in Fig. 11 ,where the backetching SEM image of an Al gate is reported.

Fig. 11 SEM backetching image of an AI-gate device showing selective removal of Al versus GaAs by NH40H:H20 2 solution

3.2 DEGRADATION OF OHMIC CONTACTS

The contact resistance of source and drain ohmic contacts directly influences parasitic resistances Rs and Rd and therefore affects device parameters like Idss, gm, Po, NF, etc ..

The AuGeNi alloyed system is the most widely used process for ohmic contacts to GaAs because it is capable of giving the low contact resistance (0.1 - 0.5 ohm-mm) needed for high frequency and high power applications.

Results of the studies on Au-Ge-Ni contacts on test patterns most recently performed are summarized in Table 4 [87-101]. Increase in contact resistance has been attributed

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TABLS DBGUDATIOI OF ALLOm Au-Ge-11 ORBIC comCTS

Cootact strueture Cootact reHstlllly Obsened 10teractlOas Refereoce or cootact reslStaoce

Au-Ge 10-~ ohl-cl2 AlI-Se creates 6a Henein. [aT] As lODe as there Is Se, Heaoein are replaced by Se aDd Ie eootlous to drop. After, a aoastolChloletrle coodltloo oecus, IUeh creates a reeloo of hl'h reslStluty

II (120011/ Au -Se (14001) IGaAl uoreported Coollet stability depends 00 [ &&] the foraatloo of a IUs phue eoatalaio, Ge

11 (3001) I AU-Ge (UOOI) IGUs I o-~ ohl-ca2 De,radatloo of the Tl/ltlA. ( 89] TI/Pt/Au, TIIAu, TI/V/AU structure (51 loereue 10 Ie ourlayers after 1000 h at 2500C)

SUbstltutloo of 11 by Pl. 10 nalysls reported.

11 ('001) I Au-Ge ( UOOll/GaAs 2 10-~ ohl-cl2 De,radatloD to IO-~ obl-cl2 ]90) after 200 brs at 225 C Unspecified fillure I"buin

Au( 11501) 111 (53al) IAu-Se 6 10-50bl-ca2 lacrease to 10-4 Obi-ell [91] (IOloII/GUs Ifter 100 brs at 390 C

Ottdlffuloo of Sa nd IDdlffulOa Of AI IDd II

'a (50011111 (20011/AI-6e 10-6 Obi-cal (ocrease to 6 10-6 01-c12 /92] (( 00011/6aAs Ifter 200 S It 450 C

hltnctlOD of tbe IIIenC stnctlre lid rUteU •• 11 112GeAs/GUs coatact arus

11 (20all/AI( 100DII/At-Ge 3 10-6 obl- cl2 (ocrease to 2 J - 3 J after [93] (35DI) /GaAs 100 blS It 330 C.

PeaetratloD of 11 IDtl 6a.ls IDd reduUoo of Ge toaor cooceotratloa

Au (( 00.11/11 (30011 /AI-It Ic O. I -0. lobi-II (.ereue I, to 0.' oo-u after [94] (100011/111501) /GaAs 100 bn at 410 C

Se,recall .. Of 10terflcIIl IUs(Ge] cralDl nlell nCtces

~ lIll. CODtact .lrus.hllul tilt IUs(8el ,raiDS lOt 61A1

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235

to four effects: (i) Excess gettering of Ga by AU, with consequent Ga outdiffusion, creates a non-stoichiometric defect-rich region of high resistivity under the contact. This effect can be reduced by adopting suitable interdiffusion barriers between the Au layer on top and Au­Ge-Ni [89). (ii) The overlayer structure, however, can be detrimental to the contact, possibly due to interdiffusion effects [89, 96, 97]. (iii) Indiffusion of Au and Ni can reduce the doping concentration in the semiconductor under the contact [91, 93, 96, 99). (iv) Reduction of the contact areas between the NiAs(Ge) [94, 95) or Ni2GeAs [92) phase grains and GaAs can take place under annealing.

Similar effects have been quoted to explain an observed increase in source and drain contact resistance of MESFETs submitted to thermal storage and/or life test, Table 5.

3.2.1 Increase of contact resistance due to interdiffusion effects

In order to achieve the ohmic characteristics, the AuGeNi multilayer is currently annealed over the AuGe eutectic temperature (356 ·C). During the thermal treatment, some GaAs is involved in different chemical reactions with the metallic elements. After cooling, a few different intermetallic phases are found such as AuGa, Ni2ASGe. Ohmic properties are generally attributed to the (localized) formation of a n+-GaAs surface layer, due to Ge indiffusion and occupation of Ga-vacancy sites, which enables the onset of a tunneling conduction mechanism [45).

Several reliability problems can be associated with this process :

poor morphology, poor reproducibility and poor uniformity across the wafer;

poor thermal stability during device processing; in some applications, chip packaging requires high temperature processing at about 400 ·C for few hours;

poor long-term stability of ohmic contacts, consequent parametric degradation of devices during operating life [87-101).

with their

Excellent contact stability and uniformity can be achieved by sputter cleaning of the surface prior to deposition. In fact, when a continuous oxide layer is present between the metal and the GaAs, the alloying reaction will initiate at the sites of defects in the oxide, which will likely affect the distribution of the compounds formed. Also, a noncontinuous contamination on the surface

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TlDlt 5 : IILUIILITl PROILDS 0' GUS mms DUB TO OBIIC comCTS DIGIUATIOI

Type of coatul : Acceleraled lesl hUlle lode '11 I Ire IIUnll1 lef.

AI/6t Tch : 250 C Itls and II BaIUDI of lhe II/AI-6e [9TJ dec.eul coaUcl 11th IDc.me ID

!D/AI-61 j:10'I/cI2 coaUcl .eslSUDce

II/Au-61 Ol1l1c cODtacl Hlcl,o'UratltD

AU/Cr /PIiAl-61

PI/lu-il Slorlll al i.UIU del.ldatlon !Dcum In Is, 14 11th II : ['J , m c, 1100 hrs Of I tis. 10 chlDle I. 8 If. IDdllfUltD of ohllc Life lests ID Yp. cODtacl IIIUUI IDto Ihe

acUn ChIDDel aDd/or c.nUoD of deflcls

I1/A1-61 Slo.111 al 300 C, +10 I coaUcl fes. 101 flpO.IU [98J 80 hrs

PI/lu-61 ,TS I coaUcl 'es. 101 .IPo.ted [91J

lClAI-6e Life lesl II TI : ,50001 CODUcl 6a 011d1llulOa. [3J 250 c, ,00 hrs fesUUllty, 6a IIClDCles ICI II Icceplors,

,501 Is hU1D1 to I COIPlIIIUOD of -151 Ids. lhl D' hYI' lllnih lhl

CODUcl.

IlIAl-61 Sto.11I IP to : IOL .lpo.114 'rala elecl'OII,ratioD IIJ 300 C. Life lesl .pUTca, 15H

AI/I1/AI-Ie Stora,l IP to Ids. lecrell., Is 11 ID411111101 ID IU. 199[ me II' p IICrtl1l 'llh II : 0.' - I ",

Clull, la lacrtlll II Is.

11/ A,/ Al-le Lilt IIlIS IP to Ids. 'eertllt D' 10 ,.uum. le,.IUtioa III tea , 250 e tl CUutl II the olll1c co,lIel. I.,.UIIUI.

AI-I. LU. tilts IP tl Itl repo.l" SI.,er .lecl.tI1,.IIU. 199J !ca,me tllDc .. ay II 011411111101 'rOl the IUIUIt. D. tl Ullml, a, AI. II , I. I t'

A./rl./lI/l1{ll-l. : LU. tts! II rcl ., It m e

Itt .Ipo.lt' OlII1c coIUcl .ltct.OIl,.m .. 11011 :

1./C,"l-1t/11 StUI, •• p 10 Decrellt II 141. 8t m41I1.,I •• CII : 0.5 e', I9IJ : me, I a llIrelll 11 COlllel 11 114111111 •• CII : '.11 t', LU. lest ., It .tIIltUCt .. u' I. OII41ffUI., rcl : III C CII , 0.12 e"

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due for instance to carbides or oxides could result in regions of high resistance simply c:aused by the intervening contamination in the contact. By cClmbining sputter cleaning and deposition of Ni as first layer in a Ni (5nm)/Au 73-Ge. 27 (10? nm)/Ni (35 nm)/Au (50 nm) structur7, Shih et ·al. [95] obta1ned an alloyed contact (440°C, 2 m1n) formed by a homogeneous two layer structure. The first layer contacting the GaAs consists of a high density of the NiAs(Ge) grains and the second layer is a uniform JLayer with large grains of the ~ -AuGa phase.

The NiAs(Ge) phase is essential for low contact resistance values, because it satisfies the condition that the Ge atoms diffuse into the Ga vacancy sites forming a heavily doped n+ layer at the metal/GaAs interface. Average contact resistance Rc is 0.11 ohm·-rom and increases up to a maximum value of 0.6 ohm-rom after 57 hours at 410°C. [92, 93,94]

0

- 1

"" .- -2 (/)

rJJ u

<l -3

2 W device -4

Tch = 260 DC

LIFE TEST

-5

0 o 5 1.0 1.5 2.0 2.5

TIME (10 3 hours)

Fig. 12 Source (Rs) and drain (Rd) parasitic 1n a 2 W commercial device during a life operating point and at Tch = 260°C.

15

"" 10 .-

(fJ

0::

<l

5 ~

u 0::

<l 0

-5

3.0

resistances test at the

Results of accelerated life tests on commercial microwave MESFET devices confirm that the stability of AuGeNi ohmic contacts does not appear a major reliability concern in operating conditions. In fact, despite the fact that many authors in the past have reported decreases in saturation current and increase in contact resistance after thermal treatments and/or operating life tests, see Table 5, we have observed these degradations very rarely. As a

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representative example, Figure 12 shows the behaviour of Rs and Rd series resistances during an accelerated life test at Tch = 260 ·C, Vds = 10 V, Ids = 800 rnA on 2 W devices with AuGeNi ohmic contacts. Increase in series resistance is limited to less than 5% after 1000 hours of test, ruling out both interdiffusion and electromigration effects in these devices.

r-.···.]. ALLOYED OHMIC CONTACTS

Fig. 13 a) Schematic diagram of electron wind finger; b) , c) SEM images of a drain contact that endured 5000 hours of life testing at Tch j=5.3 ·C 105 A/cm2 .

3.2.2 Drain/source electromigration

along drain on a device = 200 ·C and

Electromigration of ohmic contacts, with consequent increase of series resistances, has also been reported in the technical literature [6, 100, 101]. Due to material transport induced by the elctron wind, material depletion takes place at the end of drain contacts, Fig. 13, while accumulation can be observed on source metallizations. Fig. 13 a) shows a sketch of the electron flux in the drain finger. Fig. 13 b) and c) refer to two drain contacts of a medium-power MESFET with Au/Ti /Au-Ge-Ni ohmic contacts, after 5000 hours of life testing at Tch 200·C and

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j=5.3·105 A/cm2 through the cross section of each drain finger. Both gold removal at the end of the fingers and accumulation at the beginning are evident, in agreement with the flow of the electron wind, as indicated in Fig. 13 a). This effect seems to be much clearer than those reported in the literature thus far [100, 101].

It should be stressed that, in our experience despite the high number of components-hours submitted to life-test, ohmic contacts electromigration was observed only once,possibly due to a too thin Au layer on top of metallizations.

As already observed sourcel and drain contacts are much colder than active regions, sele Fig. 1; moreover, use of interdiffusion barriers and electrolytic gold grown on top of ohmic contacts greatly reduces current density in operating conditions, so that this failure mechanism normally does not introduce risks during the operating life of devices.

3.3 FAILURE MODES AND MECHANISMS DUE TO HUMIDITY EFFECTS

The effects of humid environment on silicon devices have been extensively studied in t:he last 15 years due to the introduction of non-hermetic plastic packages, main failure mechanisms have been invE!stigated and the proper counteractions have been applied. On the contrary, GaAs devices are traditionally employed in hermetic metal-ceramic packages, so few works have been done on humidity influence on GaAs [3, 102, 103]; anyway in the last few years, there is a growing interest in using discrete and IC GaAs chip devices directly mounted on hybrid modules mainly due to the high prices of suitable packaging solutions at high frequencies. To evaluate main failure mechanisms of GaAs components due to combined humidity, temperature and bias, devices from three different manufacturers were tested using the standard THB (Temperature-Humidity-Bias) and HAST (High Accelerated Stress Test) techniques.

Table 6 summarizes the main technological and electrical features of the tested devices. The hermetic packages were opened from the top, and devices were mounted into a test vehicle able to drive every single MESFET, a reverse bias of 4 Volts was applied and 85% R.H.-85 ·C and 85%R.H.-125 ·C life tests were performed up to a significant failure percentage accumulation. An extended number of dc parameters, including parasitic and channel resistances, was recorded periodically according to the methods described in paragraph 2.1 ..

Aluminium gate devices showed a noticeable decrease in drain saturation current, both in THB and HAST life test, together with the increase of source and drain parasitic

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resistance and the appearance of non-pinched off phenomenon.

Table 6

Gate length Gate width SID spacing Gate metal

Technological characteristsics of submitted to humidity tests.

A B C

(pm) 0.5 0.5 0.5 (pm) 300 300 150 (pm) 3 2 4

AI-Ni Ti-Pt-Au Ti-Pd-Au Ohmic Contact Au-Ge-Ni Au-Ge-Ni Au-Ge-Ni Passivation Si3 N4 Si3Ni Si3 N4

(double ayer) Idss (rnA) 15-80 30-110 30-50 Vp (V) 0.3-3.5 0.7-3 >1 gm (mS) >20 40 typo >20

devices

D

1 150

5 Ti-Pd-Au Au-Ge-Ni

Si3 N4

120-220 >10 >20

Failure analyses were performed by means of conventional SEM techniques mainly showing metallization degradation. As it's well known from literature on si devices, aluminium is prone to corrosion which causes metallization opening in negative biased structures; in GaAs FETs, gate interruption causes the marked non pinch-off phenomenon that was observed during our life test; a good way to identify Al corrosion is therefore the EBIC technique (Fig. 14).

Fig.14 Gate interruption due to Al corrosion is shown by means of SEM image (left) and EBIC technique (right).

Another kind of corrosion was detected involving ohmic contacts, i.e. anodic gold corrosion (Fig. 15); the same mechanism was responsible in the past for the degradation of plastic encapsulated si devices, and was found to be caused by the reaction between gold and humidity (no contaminants are needed even if they can accelerate the phenomenon)

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leading to formation of voluminous conductive gold hydroxide (Au(OH)3) [104].

Fig.iS (left) Evidence of anodic corrosion leading to formation of voluminous conductive gold hydroxide.

Fig.16 (right) Filamentary Ni growth from ohmic contacts along electric field direction.

Fig.17 between channel.

The X-ray EDS As profile taken along the white line gate and source indicates As dissolution in the

Finally, ohmic contacts degrade due to Ni extrusion: this mechanism, which has not been described previously, could be considered responsible for contact resistance increase, and it is much more impressive in gold gate devices: in this case it can create a filamentary growth along the electric field direction that can shorten the

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electrodes (Fig. 16); the one shown is an extreme case but anyway some kind of Ni "movement" from the ohmic contacts toward gates, above or below passivation layer, was detected on a large number of devices from different suppliers. The last detected failure mechanism was As dissolution: Fig. 17 shows the EDS profile of As k alfa (lower line) detected on the channel region along a line parallel to the gate finger, where humidity penetration through the passivation edge, close to the observed area, was suspected. The detectability of As dissolution by means of a bulk technique (as EDS should be considered on the micrometric scale) indicates a deep extension of the chemical degradation, possibly across the whole channel thickness; massive As dissolution was already reported [105], postulating that it leads to reduction of channel thickness so Idss decreases and parasitic resistances increase.

Table 7 : Summary of humidity test results

DEVICES A D

THB 310 4820 MTF

HAST 132 1500

0.26 eV 0.36 eV

Table 7 summarizes the results of completed tests on two type of devices; failure distributions were found to fit quite well a lognormal law with very low activation energies «0.4 eV) which demonstrates the major role of humidity penetration. Aluminium gate devices show lower MTTFs than gold gate ones, mainly due to cathodic corrosion. Anyway, metal corrosion (both cathodic and anodic) strictly related to GaAs technology but was already si devices. Arsenic dissolution was previously during operating life test in hermetic packages; can strongly accelerate this phenomenon.

is not found on reported humidity

Ni extrusion from ohmic contacts is , up to our konowledge,a new mechanism which seems to be caused by the combination of electric field and humidity.

3.4 SURFACE EFFECTS

3.4.1 Effects of surface states in power MESFETs

The presence of slow surface states in the regions between gate and ohmic contacts can strongly affect performances and electrical characteristics of GaAs MESFETs. Their existance is revealed by phenomena as "gate-lag" [106] and

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or by level

MESFETs

transconductance dispersion [lOS, 109, 110] characterization techniques as conductance deep transient spectroscopy (OLTS) performed on characterized by various gate widths and drain to source spacings [109]. Transconductance dispersion consists in a decrease of gm(f) with increasing frequency and can be observed expecially when the device is operated at low drain voltage in the ohmic region of the current-voltage characteristics where parasitic resistances of source and drain strongly influence MESFETs. Surface states are not completely understood yet but the gm(f) dispersion seems to occur when the surface-state occupancy is not able to follow the signal, i.e. when the characteristic frequency of the surface states is lower than the one of the applied signal. The magnitude of the gm(f) dispersion is proportional to the occupied state density [lOS]. Moreover, when a negative surface charge is present, the peak field at the drain edge of the gate is reduced for a given value of VOG [lOS]. Hence, VOG can be increased before impact ionizat10n at the drain edge of the gate (i.e. breakdown) is reached. In particular, the fractional increase in breakdown voltage approximately equals the increase in surface charge [10S].Ouring the evaluation program of device reliability, we observed thermally induced changes of gm(f) dispersion and a decrease of breakdown voltage in power MESFETs.

Tested devices were commercially available 2W MESFETs with the following characteristics: Ti/Pt/Au gate metallization, Si3N4 passivation, gate length 1 um, gate width 6 mm, gate-dra1n distance 1.5 um.

Oevices were submitted to the following accelerated tests to compare degradation induced by temperature or bias: i) unbiased thermal storage at 170 'c and 230 'C, ii) biased life test at the operating point VOS=10 V and lOS = O.S A at two different channel temperatures: Tph=170 'c and 230 'C.

The reverse gate-drain (source) characteristics and gm(f) dispersion curves were measured at various times during accelerated tests. In particular gm(f) was measured between 20 Hz and 5MHz, at VOS=0.2 V and VGS=-O.l V, with a pure sinusoidal signal with amplitude 0.2 V applied to the gate. The loS signal was measured across a 1 ohm resistance connected to drain by a rf voltmeter.

At increasing time of tests we observed a continuous decrease of breakdown voltage in gate-drain (source) characteristics. Fig. lS reports reverse I-V gate-drain curves for a typical device at different steps during life test at Tch=230 'C. VB is continuously reduced at increasing life-test time up to 552 hrs, though the largest variations occurred during first 200 hrs. Similar results were found also between gate and source.

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-.5 MESFET 2 WATT

LIFE TEST - .4

Tch 230°C

:;{- .3 E -en .....

- .2

- .1

0 0 -2 -4 -6 -8 -10

Vgd( V)

Fig. 18 Reverse gate-drain I-V characteristics of a 2W power MESFET: as received (0 hrs): at different times of life-test at Tch=230 DC: after the final Si3N4 depassivation.

1.05 MESFET 2WATT LIFE TEST Tch=230·C

1.00 552hrs

N :r 0

'" E

'" -.:::::- .90 552 hrs+depassivation -E

'"

Ohrs • 75 L_----1..--_~~~~~~:!::;!:=:!::::'~=:::.U

10 102 10 3 104 105 106 107

FREQUENCY (Hz)

Fig. 19 gm(f) dispersions: for the as received device: after 552 hrs of life-test at Tch =230 DC: and after the final Si3N4 depassivation.

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The VB decrease during aging 'tests appears correlated to an improvement of gm(f) dispersion. Typically the as received samples showed a g (f) decrease of about 25% between 20 Hz and 1 kHz, whic~ can be attributed to slow surface states in ungated regions, as reported in Fig. 19 for the same device of Fig. 18. After tests, samples showed a negligible gm(f) dispersion as that reported in Fig. 19 after 552 hrs of life test at Tch=230 ·C, suggesting a decreased density of slow surface sfates. Similar results to those of Figs. 18 and 19 for life-test have been observed after unbiased storage tests indicating that these effects are thermally activated.

99.9 MESFET 2WATT 99.B 99.5 LIFE TEST Ea= .9BeV 99.0 -98.0

?P. 95.0 ----en 90.0 w

. / a: :::l BO.O Tch 230°C -' c:( 0 "- 60.0 w 0

> 40.0 /".C ;::: c:( -' :::l 20.0 :::!: :::I 10.0 CJ

5.0 2.0 1.0

102 103 104

TIME (hours)

Fig. 20 Cumulative failures of 2W ~[ESFETs as a function of life test time at Tch=170·C and 230·C.

The activation energy was obtained from the cumulative failure curves shown in Fig. 20 and relative to two sets of 10 devices submitted to life-tests at Tch=170 ·C and 230 ·C respectively. The failure criterion was defined as the 500% increase of the gate-drain reverse current at VCs=-5 V. An activation energy of 0.98 eV has been deduced WhlCh appears reasonable for surface reactions, such as reduction or compositional modifications of the native surface GaAs oxides, [107].

The effects of GaAs surface sta.tes on VB and gIll(f) have been further tested by removing the Si3-N4 passivatlon after aging tests, with a selective reactive ion etching in a CF4-02 mixture, which has a low etching rate also for GaAs. Device characteristics were monitored after each ion etching

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step to check the time of complete Si3N4 removal. After complete depassivation both VB and gm(f) dispersion magnitude increased again toward the values of the as received devices, as reported in Figs. 18 and 19 respectively.

We ascribed this effect to the surface damage and to the consequent high density of slow surface states caused by ion etching on ungated GaAs regions just after removal of Si3N4 passivation [111, 112].

The reduction in the state density at the Si4N4/interface caused by thermal treatments improves the gm(f) characteristics but cause a corresponding decrease of VB which can give rise to the burn-out device in apparatus. On the other hand, the use of suitable passivation materials and processes can eliminate the problem of slow surface states in GaAs ungated regions, thus providing stable and flat gm(f) characteristics and high Vb values.

3.4.2. Surface metal migration

Another limit to the reliability of planar GaAs devices is given by lateral material migration across the GaAs surface between neighbouring electrodes, which finally leads to an interelectrode short circuiting bridge and can cause device burn-out [113-117].

The initial physical failure mechanism was found to be high-field induced lateral metal migration across the GaAs surface, usually from the positively to the negatively­biased electrodes, finally leading to this interelectrode short-circuiting bridge [114-116, 118, 119]. This migration is also temperature-dependent and therefore enhanced or enforced by thermal effects such as increased channel temperature during operation, the occurrence of avalanche breakdown at the drain contact [120] or thermal runaway at the substrate/active channel interface [121].

Fig. 21 a) shows a scanning electron micrograph of an interelectrode short circuiting bridge, while Fig. 21 b) reports a sketch of the areas of interest. This MESFET-like structure consists of two metal contacts on GaAs. The positively biased ohmic contact at the left side of the figures is Au-Ge-Ni alloy, the Schottky contact at the right side consists of AI. Both electrodes have a thickness of approximately 100 nm. The AI-gate is recessed; the device is unpassivated.

Migration takes place from the drain to the gate. This is clearly seen by the area of material depletion at the drain and the droplets at the gate due to material accumulation. The electrode were short circuited by material migration lines. Furthermore, small initiations of migration are visible at the edge of the drain contact beside the primary material migration lines.

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247

a)

Fig. 21 a) Sketch of interelectrode metal migration; b) SEM micrograph showing a short-circuiting bridge due to surface material migration in unpassivated devices.

Accelerated material migration could be observed when applying high voltages between neighbouring electrodes. The threshold voltage required for practically instantaneous complete short circuiting of the electrodes by material migration strongly depends on the amount of arsenic oxide on the surface. Samples where the GaAs surface were etched with H2S03 showed a by 50% reduced threshold voltage as compared to the non-etched surfaces. This etchant, in fact, increases the As(oxide) to As(GaAs) surface ratio, as detected by XPS measurements. On the contrary, alkaline etchants sufficiently remove the native oxides and were therefore found suitable as final surface treatments to achieve high reliability of planar GaAs devices, leading to an increase of about 35% in threshold voltage.

As already mentioned, another suitable surface treatment is plasma-enhanced hydrogenation and nitridization [111,112]. The use of nitrogen prevents any free, non-bonded Ga formation from the start by replacement of As with N. The surface converts then to a thin wide band-gap GaN layer, which is possibly also a favourable interface to SiN [112].

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Plasma enhanced hydrogenation and nitridization, followed by SiN surface passivation, has been claimed to practically eliminate long-term burn-out phenomena in MESFET devices (122).

3.5 THERMALLY ACTIVATED FAILURE MODES AND MECHANISMS OF HEMTs

In recent years, High Electron Mobility Transistor (HEMT) has emerged to be a very promising device for both high-speed digital circuits and high frequency low-noise amplifiers, becoming a possible replacement for conventional GaAs MESFETs. These devices take advantage of the enhanced mobility and velocity of electrons in the two dimensional electron gas formed at selectively doped GaAs-AlGaAs heterojunction and show a high transconductance with best results in the range 300/400 ms/mm [36,37).

Up to now, the reliability of this device has not been thoroughly studied and very few data are available concerning failure mechanisms.

Reported reliability problems include both ohmic contact degradation [15-18], changes in the 2DEG concentration [21-26), surface effects [20], soft drain breakdown phenomena (kink effect) [27] and burnout phenomena [21]. Other problems, like I-V collapse in the dark and persistent photoconductivity seem to be more closely related to control of fabrication processes than to devices long­term stability.

To evaluate failure modes and mechanisms of low-noise HEMTs, devices of five different suppliers were submitted to different high temperature storages and life tests, together with low-noise GaAs MESFETs for comparison. We will report here results concerning the first 2000 hours of the thermal storage test at 250 ·C with no bias applied. Parametric degradation has been followed by monitoring Idss, gm, Vp and the gate breakdown voltage. Parasitic resistances Rs, Rd and Rg were evaluated by means of "end-resistance" [30,31,35) measurements.

Technological characteristics of the five suppliers are summarized in Table 8. Devices mainly differ in gate metallization: some suppliers (A,D,) adopt pure AI, which can not be directly deposited on AIGaAs, because this gives raise to a leaky junction and therefore requires growing a thin n+-GaAs layer on top of the AIGaAs. On the contrary, refractory gates (C,E) can be directly deposited on the ternary phase.

Degradation appears to be dominated for shorter times «500 hours) by interdiffusion/interfacial effects which affect the Schottky contact and/or cause variations in the 2DEG concentration, with consequent degradation of Idss and Vp.

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Table 8 Technological characteristics of HEMT devices submitted to storage test at 250·C.

PASSIV. GATE length/width pm

A SiN/SiG Ai .35/200

B SiN Al/Ni .70/200

C SiN WSi/Ti/Pt/Au .25/200

D SiN Ai

.60/200

E UNPASS. Al/Ti .40/200

LOW SiN AlINi NOISE .5/300

For longer times (>500 hours) increase in R~ and Rd takes place, which gives raise to an increase in RL and is possibly due to ohmic contacts degradation.

20

10

I:

.2

g; -10 g

-20

fl.,A D.B o,c .... D _.E

HEMT STORAGE TEST Tch = 250°C

-30~~-L~~~~,~-LI~~~'~~I~'-L~~'~'~L o 0.5 1.0 1.5 2.0 2.5

TIME (hours .1000)

Fig. 22 Idss percentage variation during storage test at 250 ·C of HEMT devices of five different suppliers.

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250

c: o -.!!! <0 >

I>,A D,B e,C

HEMT STORAGE TEST Tch 250°C

0.5 1.0 1.5

TIME (hours .1000)

&,0 • ,E

2.0 2.5

Fig. 23 RL percentage variation during HEMT storage test at 250 °C. Results are averaged on all treated samples.

Figures 22 and 23 report as a reference percentage variation of Idss and RL respectively (averaged on all tested devices) as a function of time. RL is defined as Vds/Ids for Vds=100 mV and Vgs=O V and comprises obviously both the contribution of the channel resistance and of parasitic resistances Rs and Rd.

The more relevant effect at shorter times is the fast increase (+30%) in Idss of devices D, with pure Al gate metallization. This effect is accompanied by an increase of pinch-off voltage Vp (+18%) and a decrease of RL. This degradation can be attributed to AI/GaAs interdiffusion effects, which may have been inhibited in devices A by the possible presence of an interfacial oxide layer.

Both AI/Ti (E) and AI/Ni (B) devices present a slight decrease in Idss, Fig.22i when the Ids(Vgs) and gm(Vgs) characteristics before and after storage are compared, Fig. 24, a rigid shift of the curves is noticed. This effect can be correlated with a decrease in the saturation current of the gate diode, Fig. 25. Since the behaviour of the gate diode at low forward voltages «0.8 V) is dominated by the metal-semiconductor (AIGaAs) Schottky diode [36], the observed change in the I-V characteristics is attributed to an increase in the Schottky barrier height due to metal­semiconductor interdiffusion effects.

Both the increase in barrier height and the possible reduction in the AIGaAs thickness due to interaction can

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251

4 .---.--.--,-----. _ Tch 250°C 40

SUPPLIER B " ---- 3 Ohrs C\J

0 30 ---1500hrs

E E 2 «

---- 20 -.S CJ)

E -c ...... E

OJ 10

" Vds = 2V

0 ./ 0 ~_,L

-1 -0.6 - 0.3 0 0.3

Vgs (V)

Fig.24 Shift in Id(vgs) and gm(Vgs) characteristics due to thermal storage in one device from supplier B.

-5 10

-9 10

-11 10

o

/ I

Tch == 250°C

SUPPLIER B

,.­/

0.2

'" /. '" ,.-

/ /

/

/

/ /

0.4 0.6

Vgs (V)

/

,.­,.-

--

o hrs

1500hrs

0.8 1.0

Fig. 25 Changes in gate diode forward I-V characteristics due to thermal storage in one device from supplier B. Saturation current decreases from 1*10-11 A to 3*10-13 A . Ideality factor n remains practically unchanged (n=1.56 at 0 hours, = 1.59 at 1500 hours).

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252

cause a decrease in pinch-off voltage (Vp) and induce shift reported in Fig. 24. The same effect increases channel resistance and therefore the linear resistance Fig. 23, thus producing a reduction in Idss (-10% and -for supplier Band E respectively).

18

15

----. <t: E

10 OJ

5

Tch 250 DC SUPPLIER E

0.7 0.9

Vg (V) 1.1 1.3

the the RL,

20 %

Fig. 26 Degradation of linear I-V characteristics of the gate-diode of one device from supplier E due to increase of Rg. Rg increases from 9 ohm (0 hours) to 23 ohm (456 hours) .

Supplier E also presents another failure mode, consisting in a drastic increase (+300 % in 1000 hours) in the gate series resistance Rg, which can be measured by driving the gate-source Schottky junction by a forward current Igs, reporting the corresponding drain voltage and plotting the Vds/lgs curve, which saturates at the Rg value, as reported in (31]. The increase in Rg during storage test can be evidentiated by reporting the linear Igs-Vgs characteristics of the gate diode, Fig. 26. The inverse slope of this curve at sufficently high gate voltages (Vgs>= 1.0 V) provides the total series resistance, which is due to the sum of gate resistance (Rg), source resistance (Rs) and of a fraction of the channel resistance (31]. The increase in Rg is possiby due to Al/Ti interaction in the gate metal film. Interdiffusion and compound formation in the Al/Ti system with increase in sheet resistivity has, in fact already been reported (55].

After approximately 500 hours of test, a marked increase in RL takes place in some devices (D and A) without

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253

any apparent effect on Idss. This increase in RL can not therefore attributed to an increase in channel resistance, i.e. a change in the 2DEG concentration or mobility, and has been therefore attributed to ohmic contacts degradation. RL increases up to 30% in devices Di it should be noted that much larger increases in Rs and Rd should take place to have an observable effect on Idss.

Results on thermal storage of HEMTs have evidentiated both interdiffusionjinterfacial effects in gate active area (at shorter times) and ohmic contacts degradation (at longer times). By comparing Idss percentage variation (Fig. 22), however, only suppliers D and E show significant changes in electrical characteristics, while other devices show excellent stability up to 2000 hours of test at 250 ·C.

4 CONCLUSIONS

Degradation mechanisms of low and medium power microwave GaAs MESFETs have been identified during a comprehensive reliability evaluation plan on commercially purchased devices manufactured by standard technologies, including Al or Au/interdiffusion ba.rrier/Ti gate contacts, alloyed Au-Ge-Ni ohmic contacts, unpassivated or SiN passivated surface.

Results show that as long as contact stability is considered these technologies have reached sufficient maturity, so that suppliers and technologies with extremely good levels of reliability are available. An example of the long-term stability of devices during accelerated operating life tests is shown in Fig. 27, where Idss is shown as a function of time for a life test at the operating point and at Tease = 150 ·C on devices coming from five different suppll.ers. Owing to the difference in device thermal resistance, the channel temperatures of different devices was different, as shown in Figure 27. Best results were obtained by suppliers A, Band C (respectively with Ti/Pt/Cr/Au, Ti/Pt/Au and Al gate metallization), while suppliers D (Ti/Au) and E (Ti/W/AU) showed an unacceptable decrease of saturation current during the tests.

When the fabrication processes were not mature or when the environmental and operational conditions were extremely severe, devices showed specific failure mechanisms, correlated with the technology (i) Au interdiffusion and penetration into GaAsi (ii) Al gate electromigration (iii) ohmic contacts degradation and electromigrationi (iv) humidity effects: AI-gate corrosion phenomena, ohmic contact anodic gold corrosion and Ni extrusion, As outdiffusion; (v) transconductance degradation and changes of breakdown voltage due to surface states; (vi) surface metal migration and short-circuiting of closely spaced electrodes on GaAs. These mechanisms are well

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254

described in the literature, but they may still represent a

SUPPLIER A, T ch = 185·C, Au

0 ~ B , T ch = 208 ·C, Au

-10 'C,TCh =215·C,AI

~ -20

~ -30 "0 ~-D, Tch ' 171°C, Au

<J -40

-50 - ......... E. Tch = 202 °c, Au

-60 LI FE TEST

-70 T case = 150·C

o 2 3 4 5 6 7 8 9 10

TIME (10 3 hours)

Fig. 27 Percent variation of Idss during biased life test at the operating point; Tcase = 150 ·C and Tch around 200 ·C for commercially available GaAs MESFET differing in the gate metallization: A) Ti/Pt/Cr/Au ; B) Ti/Pt/Au; C) AI; D) Ti/AU; E) Ti/W/AU.

reliability problem in GaAs power MESFETs. They can, however, be unambiguously and objectively identified by resorting to available electrical analysis methods and microanalytical techniques.

Some reliability problems of GaAs MESFET still require research efforts. In particular, surface stability, surface treatments and passivations should be carefully investigated, because they can give rise to different reliability problems, like Idss decrease [123,124], gate and drain lag effects [124,106], backgating and sidegating [125,126], both in discrete devices and in digital and MMIC integrated circuits.

Finally, we have not reported data on more advanced ohmic and Schottky metallization schemes. These include : a) refractory metal nitrides and silicides, suitable for the gates of self-aligned, ion implanted MESFETs, which should whitstand the high temperature (800 ·C - 900 ·C) annealing of the induced damage; b) more uniform, reproducible and thermally stable ohmic contacts, based on PdGe solid state epitaxy [127], In-based ohmic contacts [128] rapid thermal

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255

annealing procedures. Assessment of these technologies, still under development, will be necessary both to improve GaAs integrated circuit devices and to reach higher working frequencies.

Results on thermal storage of HEMTs have evidentiated interdiffusion/interfacial effects which affect the Schottky contact and/or cause variations in the 2DEG concentration at short times «500 hours). For longer times ohmic contacts degradation can take place. Parametric degradation is in any case limited and only a few suppliers are affected by significative changes of dc electrical parameters.

Again, further study is needed to evaluate the effect of dc and rf bias during accelerated tests to study the stability of different heterojunction structures and to ascertain surface stability and parasitic effects [129].

ACKNOWLEDGMENT

This work would not have beeen possible without the effort and help of Telettra Quality and Reliability Department, and in particular of Piero Brambilla, Enrico Corti, Dario Ogliari, Marco Sangalli and Massinlo Vanzi. We would like to thank Claudio Canali (Univ. Padova), Giampiero Donzelli (Telettra, Components), Fausto Fantini (S.S.U.P. of Pisa) for comments and suggestions, Giuseppe Castellaneta (Tecnopolis CSATA, Bari) for HEMT characterization. A special thank to Prof. H.L. Hartnagel (Institut fur Hochfrequenztechnik, Darmstadt) for allowing us to report his results on surface metal migration and to Dr. A. Callegari (IBM, J. Watson ) for providing us with his results on ohmic contacts characterization.

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metallized commercially available power GaAs FET's", IEEE Int. ReI. Phys. Symp., 1979, pp. 156-160.

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(86) B. R. Sethy and H. L. Hartnagel, "Characterization of electromigration damage in current·-stressed Al gates as used for GaAs MESFETs", J. Phys. 0 : Appi. Phys., 18, L9-L13, 1985.

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(89) C. P. Lee, B. M. Welch, W. P. Fleming, "Reliability of AuGe/pt and AuGe/Ni ohmic contacts on GaAs", Electronics Letters, 17 (12), pp. 407-408, 1981.

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(4), pp. 259-266, 1983.

(92) T. S. Kuan, P. E. Batson, T. N. Jackson, H. Rupprecht and E. L. Wilkie, "Electron microscope studies of an alloyed Au/Ni/Au-Ge ohmic contact to GaAs", J. Appl. Phys. 54 (12) , pp. 6952-6957, 1983.

(93) A. Iliadis, K. E. singer, "Metallurgical behaviour of Ni/AU-Ge ohmic contacts to GaAs", Solid State Communications, 49 (1), pp. 99-101, 1984.

(94) A. Callegari, E.T.-S. Pan, M. Murakami, "Uniform and thermally stable AuGeNi ohmic contacts to GaAs", Appl. Phys. Lett., 46 (12), pp. 1141-1143, 1985.

(95) Y.-C. Shih, M. Murakami, E. L. Wilkie, A. C. Callegari, "Effects of interfacial microstructure on uniformity and thermal stability of AuNiGe ohmic contact to n-type GaAs", J. Appl. Phys., 62 (2), pp. 582-590, 1987.

(96) J.F. Bresse, "Reliability of the Ge/Ni/GaAs in low noise dual gate Reliab. 25(3), 1985, pp. 411-424.

structure GaAs FET" ,

Au/Cr/Au­Microel.

(97) D. A. Abbott, J. A. Turner, "Some aspects of GaAs MESFET reliability", IEEE Trans. on Microwave Theory and Tech. , MTT-24 (6), pp. 317-321, 1976.

(98) R. E. Lundgren and G. O. Ladd, "Reliability study of m1crowave GaAs Field Effect Transistors", 16th IEEE Int. ReI. Phys. Symp., pp. 255-260, 1978.

(99) K. Mizuishi, H. Kurono, H. Sato, H. Kodera, "Degradation mechanism of GaAs MESFETs", IEEE Trans. on El. Dev., ED-26 (7), pp. 1008-1014, 1979.

(100) A. Christou, E. Cohen and A. C. Macpherson, "Failure modes in GaAs power FET's : ohmic contact electromigration and formation of refractory oxides", IEEE 19th Int. ReI. Phys. Symp. pp. 182-187, 1981.

(101) F. Wilhelmsen, 1. Zee, "Effect of electromigration on GaAs FET reliability", Proc. ISTFA 1984, pp. 163-169, 1984.

(102) W.T. Anderson,A Christou and K.J. SIeger, "Ionic Contamination-Humidity Effects on GaAs FETs",17th Annual Proc. ReI. Phisics Symp., pp.127-132,1979

(103) M.Spector and G.A. Dodson,"Reliability Evaluation of GaAs IC pre-amplifier HIC", GaAs IC Symposium,pp.19-21,1987

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(104) E. Brambilla,P. Brambilla,C. Canali,F.Fantini and M.Vanzi,IIAnodic gold corrosion in plastic encapsulated devices II , Microelectronics and Reliability,vol. 23,pp.577-585,1987

(105) S. Igi, T. Suzuki, K. Mitsui, K. Miyamoto, M. Shimodaira and S. Kuboyama,IIThe effects of the passivation film on the reliability of high power GaAs MESFETslI Int. Symp. for Testing and Failure Analysis,pp.302-310,1983

(106) J. M. Dumas, F. Garat, D. Lecrosnier, IIDevelopment of gate-lag effect on GaAs power MESFETs during agingll, El. Lettrs., 23, pp. 139-141, 1987.

(107) M. Rocchi, IIStatus of the surface and bulk parasitic effects limiting the performances of GaAs IC'sll, Proc. ESSDERC 85, J.P. Noblanc and J. Zimmermann, eds., North­Holland, Amsterdam 1985, pp. 119-138.

(108) P.H. Ladbrooke and S.R. Blight, II Low-Field Low­Mobility Dispersion of Transconductance in GaAs MESFETs with Implication for other Rate-Dependent Anomalies ll , IEEE Trans. Electron Devices, vol. ED 35, n. 3, pp. 257-267, 1988.

(109) J. Graffeuil, Z. Hadjoub, J.P. Fortea, and M. Ponysegur, IIAnalysis of capacitance and transduxtance frequency dispersion in MESFETs for surface characterization II , Solid-St. Electronics, vol. 29, pp. 1087-1097, 1986.

(110) 5. M. Ozeki,K. Kodama, and A. Shibatomi,IISurface analysis of

GaAs MESFETs by gm frequency-dispersion measurement of transconductance II , Fujitsu Sci. Tech. J., vol. 18, pp. 475-486,1982

(111) C. D. Thurmond, G. P. schwarz, G. W. kammlott, B. Schwartz, IIGaAs oxidation and the Ga-As-O equlibrium phase diagram", J. Electrochem. Soc., 127, pp. 1366-1371, 1980.

(112) F. Capasso, G. F. Williams, "A proposed hydrogenation/nitridization passivation mechanism for GaAs and other III-V semiconductor devices, including InGaAs long wavelength photodetectors ll , J. Electrochem. Soc., 129, pp. 821-824, 1982.

(113) J. IIMicrowave MESFETslI, 1026-1031,

J. Whalen, nanosecond

IEEE Trans. 1979.

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on Microw. Theory and Tech., 27, pp.

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(114) J. Dell, T. S. Kalkur, Z. Meglicki, A. G. Nassibian, H. L. Hartnagel, "Au-Ge-Ni migration affected by operating conditions of GaAs FETs", Solid State Electronics, 27, pp. 447-452, 1984.

(115) K. H. Kretschmer, H. L. Hartnagel, "XPS-analysis of GaAs surface quality affecting interelectrode material migration", 23rd Ann. Proc. IEEE Int. ReI. Phys. Symp., pp. 48-58, 1985.

(116) K. H. Kretschmer, H. L. Hartnagel, "Interelectrode metal migration on GaAs", 25th Ann. Proc. IEEE Int. ReI. Phys. Symp., pp. 102-106, 1987.

(117) s. H. Wemple, W. C. Niehaus, H. Fukui, J. C. Kevin, H. M. Cox, J. C. M. Hwang, J. V. DiLorenzo, W. O. Schlosser, "Long term and instantaneous burnout in GaAs power FET's Mechanisms and Solutions", IEEE Trans. on EI. Dev., ED-28, pp. 834-840, 1981.

(118) S. Loualiche, V. Parguel, H. L'Haridon, L. Henry, C. Vaudry, "InGaAs photoconductor failure observation", El. Lettrs., 21, pp. 1101-1102, 1985.

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(128) M. "Thermally and NilnW 1974-1982,

Murakami, Y.-C. Shin, W.H. Price, E.L. Wilkie, stable ohmic contacts to n-type GaAs. III. GelnW contact metals", J. Appl. Phys., vol. 64(4), pp. 1988 and references therein.

(129) A. Belhadj, P. Audren, J.M. Dumas, S. Motter, J. Pangam, C. Vuchener, "Experimental study of functional parasitic effects of MODFETs in integrated circuits", 4th International Conference Quality and Electronic Components, Bordeaux 1989, pp.128-132

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METAL CONTAcr DEGRADATION ON III-V COMPOUND SEMICONDUcrORS

G. Kiriakidis, W.T. Anderson+, Z. Hatzopoulos, C. Michelakis D.V. Morgan*

Institute of Electr. Structure and Laser, RCC/FORTH, Heraklion, Crete, Greece.

+ Naval Research Laboratory, Code 6835, Washington, DC 20375-5000, U.S.A

* UWCC, School of Elect. Electr. and Systems Eng. P.O. Box 904. Cardiff, CF1 3YH, Wales, G. Britain.

1.0 INTRODUcrION

Discrete low noise MESFETs, power FETs as well as high speed digital GaAs ICs and monolithic microwave integrated circuits (MMICs) require a stable metal contact technology, low parasitic resistance and a high degree of reliability and reproducibility. Self-aligned gate FETs in digital GaAs integrated circuits require gates which must withstand a high temperature anneal treatment. For long term high temperature applications, stable Ohmic contacts are also required since present AuGe contacts are stable only up to about 3500 C. A promising approach for achieving high reliability is through the use of a refractory Ohmic and Schottky contact technology based on amorphous (a-) metallization.

On III-V semiconductors, and in particular on GaAs FETs, the dominant failure mechanisms can be classified into two main categories: a) those associated with the bulk material and its surface (Le. defect formation, net donor denSity, traps etc.); and b) those associated with the metallization (i.e. interdiffusion and electromigration). Of the two, metallization related failures are known to be the more serious and more frequent cause of FET degradation. [1, 2]. An ideal metallization for the gate, source and/or drain contacts of a GaAs FET should be characterized by as many of the following properties as possible: 1) good adhesion to the GaAs surface, 2) high electrical conductivity, 3) low or no tendency to electromigration, 4) inertness to its immediate environment, 5) good bonding with leads, 6) ability to apply lithographic processes and sustain high temperatures, 7) accurately controllable penetration into the GaAs or none at all, during processing, 8) low contact resistance in the case of Ohmic source and drain contacts, and 9) reasonably high barrier height for the gate metal. It is obvious that no single metal or alloy can meet all these requirements. In most cases trade-offs have to be made between conflicting properties.

269

A. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 269-289. © 1990 Kluwer Academic Publishers.

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2.0 DEVICE DEGRADATION

2.1 Discrete Devices

Failure mechanisms due to metallization in both low-noise and high-power GaAs FETs may be divided into those associated with the Ohmic source and drain and those associated with the Schottky gate. In most source and drain metallization schemes, low contact resistance is achieved by alloying a thin AuGe film into a n+ GaAs epitaxial or ion implanted layer. A thick layer of Au is subsequently deposited to provide bondability, corrosion resistance and above all high conductivity. The main drawback of such a system is its instability with temperature and its time degradation. It has been found [3, 4, 5] that Ga readily diffuses through the AuGe into the Au layer which acts as a sink while Au (and 02) diffuse inward. As a result, the contact resistance incr~ases and can eventually degrade the performance of the transistor. Candidates, to prevent the undesirable interdiffusion of Ga and Au by the formation of a suitable barrier may be Cr, Ni, Pt, Ta, and Ti. If inadequate or no diffusion barrier is provided, degradation of the contacts proceeds with an activation energy of 0.8 to 1.8 eV [6, 7]. This relatively high energy assures reasonable contact life if the operating temperature is low enough «100°C) but also means rather rapid deterioration at temperatures in excess of I50a C.

The gate of the GaAs FET is usually the most common origin of reliability problems. One of the earliest choices for gate metal was AI, mainly due to its ease of fabrication. Investigations of the Al/GaAs system [8, 9, 10] employing secondary ion mass spectrometry (SIMS) and Auger electron spectroscopy (AES) indicate that interdiffusion occurs between aluminum and GaAs at temperatures as low as 125 ° C with the presence of AI~03 at the metal-semiconductor interface. In addition to the AI-GaAs interdiffuslon, AuAl phase formation has also been reported as a reliability problem. Pulse burnout, electromigration and electrolytic corrosion have also been reported as major failure modes of AI. Some designers switched over to gold refractory gates to avoid the frailties of AI. The most successful gold-based systems have been TiW/Au, TiPt/Au and Ta/Au, of which TiW/Au was the most stable for high temperature operation. However the thermal expansion difference between TiW and GaAs resulted in the generation of defects just below the gate and thus resulted in reduced carrier mobility. In addition, the high temperature limit for the TiW-GaAs system has been found to be 450°C.

Other metallization systems such as Ti-Pt-Au although used with great success in the silicon beam lead technology, revealed a number of reliability problems when used for GaAs Schottky barriers, among which were: 1) a temperature-time dependent interdiffusion between GaAs and Ti; and 2) formation of a TiOz _layer above 1500 C and a significant non-stoichiometric interface region which influences device performance. A Ta refractory metallization system used by Calviello [11] for high reliability varactor diodes and FETs was very successful. Results with tantalum gate FETs [12] had shown that the saturated drain current Iuss at zero gate bias, the transconductance gm and the pinch-off voltage Vp all decrease as functions of anneal temperature and this was attributed to Ta-GaAs interdiffusion at

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temperatures between 125 and 250°C.

Amorphous thin films for Schottky gates offer the possibility of eUminating most of the failure modes present in state of the art GaAs FETs. Amorphous thin film diffusion couples have been shown to have diffusivities of 10-22 cm2/sec, and, hence many orders of magnitude smailer than in polycrystailine metal films [13, 141. The main reason for this observation has been the eUmination of the grain boundary component to diffusion. In addition, amorphous films are corrosion resistant [15], since they do not contain the typical nucleation sites at which chemical attack takes place.

2.2 IC Problems

Use of a refractory metal gate in self-aligned MESFET technology is a promising approach to digital GaAs IC fabrication due to the high uniformity in I-V characteristics and process simplicity. However, little attention has been paid to this approach for low noise device applications, mainly for the following reasons: high gate resistivity, poor sticking capability of refractory metals, low gate breakdown voltage, and high leakage current through sub-micron short channels.

A refractory-metal gate self-align process for GaAs analog MMICs has been introduced by Ohta et al [16] utilizing a W/Tal_xWxSi2 double layer gate and side-wail assisted n+ ion implantation, to overcome the above problems. It was found that this compound silicide Tal_ W Si2 provides an almost identical thermal expansion coefficient to the ~ substrate and excellent Schottky characteristics at an appropriate mixing fraction of x = 0.77. In addition excellent sticking, no cracking or peeling was observed for relatively thick, 0.5 IUD, films even after annealing at temperatures as high as 900° C. Auger analysis of the Schottky junction before and after annealing up to 800° C for 40 minutes showed no interdiffusion between the GaAs substrate and the Tal_x W xSi2 film. Also the resistivity decreased with increasing annealing temperature and at 800°C was 56 !to cm. Fabrication of 1.2 IUD gate FETs showed a high gm value of 172 mS/mm and a low NF of 0.92 dB at IGHz, a promising performance for analog MMIC implementation.

Naoki Yokoyama and co-workers [17], on the other hand, have reported the fabrication of a GaAs lK static RAM using W-Si gate self-alignment technology. The W -Si film was deposited by rf co-sputtering. Barrier heights and ideality factors of TiW, TiW -silicide, and W -silicide Schottky contacts as functions of annealing temperature up to 900° C have shown the superior behavior of silicide films over TiW with no significant degradation up to 850° C. Average transconductance for 21UD gate FETs was 127 mS/mm.

2.3 Contacts for High Temperature Electronics

Of the many problems that arise when electronic devices are operated at high temperature, degradation of the Schottky barriers, pIn junctions, heterojunctions and Ohmic contact are among the most important. These

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problems are discussed by Palmer et al [18] who concluded that Si devices are limited to 350°C and GaAs devices to 500°C. This Sandia Report found that the GaAs devices tested operated up to 300°C but that new Schottky barriers and ohmic contacts are required without the use of Au and on material with higher carrier concentration. Problems in developing GaAs diodes were investigated by Behle and Zuleeg [19] by studying the high tempemture degradation of implanted pIn junctions using Mg, Be, and Zo. During this study it was found that the Ohmic contacts degraded above 400° C, including AlGe contacts. JI!gh temperature applications are required for control of nuclear reactors [20] (250 C), geo-thermal well exploration (350° C), jet engine control [20-22] (300-450° C), and space exploration [23].

As the dimensions of high speed devices shrink below 0.5 J.UIl it can be assumed that alloyed contacts such as AuGe will not be sufficient for dimensional control because of vertical spiking and lateral spreading during the melt phase. While non-alloyed contacts are desired for VLSI, they are also important for high temperature and high reliability applications. High temperature contacts are required for self-aligned gate (SAG) processing [17] and for improved reliability in power FETs operated with high forward gate current and high drain current. These opemting conditions result in much higher channel temperatures than occur in small signal devices. Besides FETs, GaAs bipolar transistors can also be operated up to 400° C [24] and thus not only must n- and p- type Ohmic contacts be stable in these devices during long periods of high temperature operation, but the pIn and heterojunctions as well.

A number of studies have shown the advantage of amorphous metallizations [25-27] for diffusion barriers in higlI temperature and high reliability applications. It has been demonstrated [28] that GaAs FETs can be fabricated with good high temperature stability by sputter depositing the amorphous metal gate directly on GaAs. However the metallizations need not be amorphous for high temperature applications. Polycrystalline silicide metallizations were found to be sufficiently stable up to 950° C for rapid thermal annealing in SAG processing [29].

2.4 High Temperature Ohmic Contacts

Ohmic contacts have been developed for high temperature applications using epitaxial Ge films, refmctory metallizations, and pulsed laser annealing [30]. Laser annealing was used to form these contacts L31] because when a refractory metal overlayer deposited on an epitaxial Ge film grown on the n-type GaAs was sintered it was found [32, 33J that oven anneal temperature in the range 500-750° C were required. Subjecting the entire substmte to these high temperatures can have deleterious effects on the active and semi-insulating GaAs layers and to other metallizations previously deposited on the chip, e.g. for the purpose of fabricating integrated circuits. This problem can be obviated by selective contact annealing with a laser beam. Pulsed laser annealing may also be important in obtaining enhanced activation of implanted dopants and in obtaining certain doping profiles when rapid heating and cooling are important.

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The refractory films on epitaxial Ge layers studied were TiW (88 wt. % W, 12 wt.% Ti)/Ge, Ta/Ge, Mo/Ge, and Ni/Ge. These refractory non-alloyed Ohmic contacts have two areas of applications: 1) devices which are designed to operate for extended periods of time in a high-temperature ambient (above 150° C) [20] and 2) improve the reliability of devices which experience high channel or contact temperatures, such as power field-effect transistors (FET) and transferred-electron devices (TED) [34J. In both cases, local melting at imperfections in the contacts can result in device failure. Formation of an n+ layer at the GaAs-contact interface by Ge doping can also result in significant performance gains in power FETs and TEDs through reduction in contact resistance and increased voltage levels. A number of different types of contacts were investigated as described in [30]: TiW/Ge, Ta/Ge, Mo/Ge and Ni/Ge, both with and without a high dose of Si or Se ion implanted (12) at the Ge/GaAs interface. Ohmic contacts were fabricated on n-type epitaxial GaAs layers with carrier a concentration of 2 x 1017 cm-3 grown on N+ (100) oriented GaAs substrates doped to 2 x 1Q18cm·3 or on GaAs epitaxial layers (n=1X 1017cm-3, 2000-A thick) grown on semi-insulating (SI) GaAs substrates. Typical contacts are shown in Fig.l. In the case of TiW/Ge!I2Si contacts to the GaAs epitaxial layer on SI substrates, transmission line model (TLM) contacts were formed by etching the mesa, TiW, and Ge in three separate etching steps.

o I 650 A TiW 1 1010 A I 200 A Epi Ge j [r-- - _I~N~L~Y~R_ - -ls2 m

t N = 2 X 10'6 cm-3 GaAs Epi 1. I"

N+ = 2 x 10'8 cm- 3 GaAs

\ AuGe/Ni

\ IMPLANTED Si

) 175 keY, 5 x 1014 cm- 2

\200 keY, 3 x 10'4 cm-2

t= 2 x 10'7 cm- 3 GaAs o!151"m ------1-1-

N+ GaAs

AuGe/Ni

Figure l. Schematic cross sections of typical refractory metal/Ge Ohmic contacts to GaAs.

Thermal annealing of the TiW/Ge!I2Si contracts (1500 A TiW/400 A Ge!I2Si at 60 keY, 2 x 1014cm-2) was carried out in vacuum and in forming gas at 700° C. Near optimum annealing conditions of 25 min, the sIJecific contact resistance was 1 x 10-6 Q·cm2 as measured by the TLM method [35]. AES sputter proftles, as deposited and after sintering in vacuum, are shown in Fig.2. After sintering, Ge migration into GaAs was observed indicating an n+ doping layer at the GaAs surface. This condition is necessary for a low specific-contract resistance [36]. The Si implant may also have been partially activated resulting in a further increase in the concentration of the n+ doping layer. After 25 min. at 700° C, Ga outdiffusion was also observed, allowing vacant sites for Ge or Si doping atoms.

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274

TiW-Ge-GaAs PROFILE AS DEPOSITED

SPUTTER TIME, MIN

A W o Ti o G.

Go'"

1110 W

A,6,.6. All

75

50

25

TiW-Ga-GaAs 7OOOC/15 MIN. 10---9 Torr

G. I:.. lJ. Allo

A

00 Ti 0000000000

00 25

A-W 0- 1i 0- Ga

75 1110

Figure 2. AES sputter profile of TiW/Ge/GaAs contacts, (a) as deposited and (b) after Ohmic contact formation at 700°C for 15 min. at 10-9 torr.

Laser annealing was performed with a ruby laser which emitted a one joule, 22-ns pulse obtained by Q-switching the cavity with a Pockers cell. Experiments were performed both in single TEMoo-mode and in multimode operation. The single mode was used for small diameter Ohmic contact experiments while the multimode was employed for large area AES analyses. For the TEMOILmode case, a O.8-mm circular aperture was placed in the optical cavity. The output beam was then focused to form a 260-JUIl diameter spot at the sample. A 30- to 50-JUIl diameter spot, which contained only the center of the Gaussian beam, was obtained by use of a metal mask. Ohmic contacts were obtained at energy densities between 90 to 5000 mJ/em2, depending on the type of contact. For the multimode case, the full one joule output was homogenized by a method similar to that described by Cullis et al. [37J by sending it through a 1.2em diameter fused-quartz optical waveguide which was bent and tapered to obtain a spot diameter at the sample of 0.7 em. Although this "light guide diffuser" was effective in homogenization of the multi-mode structure of the beam and reducing speckle patterns, "hot spots" were still observed at the output (particularly apparent of GaAs surfaces). Hot spots which were still present after passing the multimode beam through the light gl!ide diffuser are shown in· the left and center pictures in Fig.3. It was found [38] that these micro-inhomogeneities could be eliminated by reducing the laser cavity aperture below a critical size, as shown in the picture on the far right in Fig.3.

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{al

8.5 mm CAVITY APERTURE O.46J/em2

(bl

5.0 mm CAVITY APERTURE 0.44Jlcm2

50 lim

275

tel

2.0 mm CAVIIY APERTURE O.50J/em2

Figure 3. GaAs suIface irradiated by multimode focused ruby laser beam as a function of cavity apertures, with laser energy density adjusted to observe the onset of hot spot activity.

'v '0» v i~ . , ,

,,~~:~v ~ ,

~-' BEFORE LASER ANNEAL VERT: 500JlAIdiv HOR: 1 V/div

O.14Jlom' VfRT: 20 mAidiv HOR: l00nNldiv

~;& """" ;»*,,~ ..... ~ .;~

~~~-~~.

6.04 Jlom2. 1 pulse VERT: 500 ftA/dlv HOR: l00mVldlv

f-----1 ",m PHOTOMICROGRAPH. O.14Jl<:m2

Figure 4. Curve tracer IIV curves of Ni/Ge/GaAs contacts before laser annealing and after laser annealing at 40mJ/cm2 (soft Schottky barrier) and 140mJ/cm2 (sufficient energy density to form Ohmic contact). Photomicrograph of Ohmic contact after 140 mJ/cm2.

Current/voltage (I/V) characteristics of a typical Ni/Ge contact before and after laser annealing are shown in Fig.4 as displayed on a curve tracer. Before laser annealing the contacts were reasonably well behaved Schottky barriers; the upper curve shows a reverse breakdown voltage of about - 5 V on 2 x 1017cm-3 doped GaAs. After a pulse of 40mJ/cm:l the rectification softens, indicating some very limited melting, perhaps associated with preferentially absorbing imperfections on the top suIface. At 140mJ/cm2 the

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contact was Ohmic and the photomicrograph of this contact, shown in Fig. 5, indicated very shallow, unifonn melting had ocurred. Similar results were found with TiW fGe, MofGe, and Ta/Ge contacts.

LASER ANNEALED OHMIC CONTACT TO GaAs

Ni/Ge mp TadGe mp

MolGe mp

10-' ,----------'------'--'------------,

<)

l000ANill000AGe

~ o 1000ATaI1000AGe

o

10.6 :-:---'--_L-"-'-:'-:---'-_--'-----'-LJ-'-:-_L----'-----'---Ll 0.01 0.1 1.0 10.0

ENERGY DENSITY IJlcm2,

Figure 5. Experimental values of specific contact resistance as a function pulsed ruby laser energy density; mp indicates approximate melting points as determined from surface photomicrographs.

Experimental curves of the specific contact resistance versus laser energy density are shown in Fig. 5. Measurements were made with a method similar to that of Cox and Strack [39]. These results were obtained using the TEMoo-mode with a 30- to 50-lUll diameter metal mask over 250-1Ull diameter isolated contacts. Approximate melting points for each each of the contact types are shown at the top, as determined from photomicrographs of the irradiated surfaces. However, the melting points could not be determined preCisely from the photomicrogrphs and very shallow melting probably occurred below these points. It was found that the contact resistivity was at a minimum near the melting point for Ni/Ge and Ta/Ge contacts. Similar TiWfGe Ohmic contacts fonned on n = 2 X 1016cm-3 GaAs epitaxial layers resulted in a specific contact resistance of 1 X 10-5 Q·cm2. The higher value of specific contact resistance evidently resulted from the lower doping concentration in the GaAs. Similarly, contact resistivity values for Ta/Ge, MofGe, and Ni/Ge were approximately an order of magnitude higher on 2 X 1016 cm-3 as compared to 2 X 1017cm-3 GaAs.

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AUGER SPUTTER PROFILES OF 2000'& Ni/2000A Ge/l2Si CONTACTS TO n-GaAs

20 40 60

SPUTTER TIME Imlnl

277

Figure 6. AES sputter profiles of a 2000 A Ni/2000 A Ge/GaAs contact before laser annealing and after laser annealing at 100mJ/cm2, just at threshold for Ohmic contact formation.

The interfaces before and after laser annealing were investigated using AES sputter profiling techniques. Fig. 6 shows AES sputter profiles of a Ni/Ge contact before laser annealing and after laser annealing at an energy density just high enough to form Ohmic contact. A multimode 7-mm diameter beam was used to irradiate a GaAs sample approximately 10 mm X 10 mm containing 2000 A Ni and 2000 A Ge prepared as discussed above. At 1 00mJ/cm2 , slight melting patterns could just be observed, indicating melting of the Ni and Ge just to, and including, the GaAs surface. This energy density corresponded to the threshold for Ohmic contact formation. Even at this low-energy density there was Ge migration into the GaAs, enough to greatly increase the n-type doping concentration at the GaAs surface. Similar profiles were observed with Ta/Ge laser annealed contacts. These profiles are also typical of Ni/Ge thermal annealed Ohmic contacts studied previously [32].

The TiW /Ge,fI2 Si Ohmic contacts formed on GaAs epitaxial layers on SI substrates and thermally annealed were studied by high-temperature aging in an ambient of forming gas. Fig.7 shows the change in the specific contact resistance after exposure to temperatures between 350 to 600° C for over 175 h. The behavior of a typical AuGe/Ni contact, included in the 350° C experiments, is shown for comparison. These results demonstrate the high-temperature reliability advantages of refractory metal/epitaxial Ge Ohmic contacts. With these contacts it was found that the contact resistance did not increase appreciably up to 190 h at 350° C, while that of AuGe significantly increased between 25-35 h at 350°C. High temperature aging experiments with the laser annealed Ohmic contacts (TiW/Ge,fI2Si, Ni/Ge/IlSi, Ni/Ge, Ta/Ge, and Mo/Ge) were also carried out by aging in vacuum at 10-4 torr. No measurable change in specific contact resistance was found after 350°C for 6h.

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278

1x10-4 ION· IMPLANTED TIW/Ge CONTACT ...

E AuGeNI CONTACT u I

01 5X10-5 NO BIAS

y ~ 55O"C W (J

1 X10-5 Z

~ IJ) 5000C en w 5x10-ii 450"C a: I-(J

3500C ~ Z 1 x10-ii 0 (J

O~--~----~--~-----L----~--~----~--~ ~ 100 1~ 1~ 1~ 200

ANNEAL DURATION, HOURS

Figure 7. Specific contact resistance of thermally annealed TiW/Ge and AuGe/Ni Ohmic contacts as a function of anneal time at various aging temperatures in forming gas.

The thermally annealed TiW/Ge Ohmic contacts were also subjected to high-~emperature aging under dc bias. Fi~,8 shows the results at 3000 C and 3500 C after exposure for 160 h. At 300 C the contact resistivity increased initially but stabilized at about 4 x 10-6 Q·cm. At 3500 C the increase in contact resistivity was much larger. This was partially explained by the large out diffusion of Ga, shown in the AES sputter profiles in Fig.9.

6 VOLT, 15 mA BIAS Au/TlW-G.tGaAs ION IMPLANTED CONTACT

~ lxl0.-s I r-------------------------~~~~~

'" ~ ~ 5x10 .....

iii ~ 1)(10-1

t;

~ 8

____ ----------------~D~

~ ~ ~ 00 100 1~ 1~ 1m ANNEAL TIME. HOURS

Figure 8. Specific contact resistance of thermally annealed TiW /Ge contacts as a function of anneal time under bias conditions at 3000 C and 3500 C in forming gas. Test structure used to measure contact resistivity (center mesa) and to study metal migration (long arms).

Page 284: Semiconductor Device Reliability

100,-------------------------------, 350OC, 40 HRS 6 VOLT, 15 mA BIAS

80

60

__ no-t"T"""> GALLIUM

40

°OL-~~~~~60L---L-~~~L-----~

SPUTTER TIME, MIN

279

Figure 9. AES sputter erofile (Ge and Ga) of thermally annealed TiW/Ge Ohmic contact after 350 C/40 h anneal in forming gas under bias conditions, showing large Ga outdiffusion.

3.0 REFRACTORY SILICIDE METALLIZATIONS

3.1 Sputter Deposition

An RF-magnetron sputtering technique was utilized for the deposition of amorphous refractory metal silicide films. The system consists of two targets with power splitting capability and substrate table rotation with variable speed. By adjusting the power delivered to the individual targets, Ta or TiW and Si, fine control of the composition of the amorphous metallization with atomic layer dimensions, as shown in Fig. [lOa, lOb], can be achieved. The sputtering pressure of Ar gas was 20 mtorr and the deposition rates were as low as 400-500 Alhour. This method has the following advantages over sputter deposition from a single target: a) overall average composition can be better controlled by varying the power, and thus film thickness on each pass, to the separate targets; b) amorphous films, which are desirable as diffusion barriers, are always obtained because a-Si in deposited on each pass of the Si target, a glancing angle x-ray diffraction spectra is shown in Fig. 11; c) because the substrate spends only a small time near the :~putter target as it rotates, the surface temperature remains lower than if a single sputtering target were used and photoresist can be employed to lift 1.0 !JIll long gates L28], as shown in Fig. 12.

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280

240

LAYERS ~%~~~~m7'7'7%~~~mm~

'CALCULATED

UNDOPED 51 GaAs

(a)

UNDOPED 51 GaAs

(b)

Figure 10 a) Schematic of the GaAs/Ta-Si Amorphous Metallization. b) Schematic of the GaAs/TiW-Si Amorphous Metallisation.

3.2 Laser Annealing of Metallizations

Annealing of the layered films was carried out with a 308 nm excimer laser to reduce the resistance in these amorphous films and to form Ohmic contact. The uniformity of the laser beam was established by mounting a Imm

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281

diameter aperture in front of a power meter and measuring the intensity of the primary beam from the laser at 2 mm intervals across the 2.4 em x 3.4 em beam in two orthogonal directions. Only the outside 0.6 cm of beam had reduced intensity and only the center 1 cm x 1 em of the beam was used in the experiments by use of an aperture. Slight focussing of the beam was accomplished with a quartz lens to final position the beam on the refractory silicide films and to adjust the size of the beam. A He-Ne laser was utilized for alignment of the excimer beam on the desired spot. Power densities up to 500 mJ/em2 per pulse were obtained, but it has been found that values over 400 mJ/cm2 are usually destructive. Best results were obtained when samples were maintained at 4S()oC during laser annealing. Laser annealing has the advantage over Rapid Thermal Annealing (RTA) or oven annealing in that it is not necessary to heat the entire wafer. Annealing is accomplished by adjusting the energy density to penetrate only part way into the films, ideally resulting in a phase change to polycrystalline material of lower resistivity at the top of the film leaving the bottom part of the film as a well behaved amorphous diffusion barrier.

The refractory a-metal silicides from Schottky barriers on n-type GaAs. It was found that laser annealing of these films results in significant increase (30% or more) in the conductivity for thicknesses s. 2000 A. If the metallization is approximately 400 A, Ohmic contact is formed because the heat pulse reaching the a-metal/substrate interface is sufficient to raise the temperature enough to cause interdiffusion.

Film resistivity was measured by the voltage drop between gate pads, see Fig. 12, for a given current passed through the width of the gate. The resistivity values in Figure [13] are based on the the cross-section of the gate finger. As the film was laser annealed, it is likely that only the top of the film changed in composition or crystal structure. Only the average resistivity can be calculated at present since the depth of laser beam and heat pulse penetration have not yet been measured. Resistivity values above 500 !-to -em are too high for device applications, but it can be reduced by reducing the Si content and by laser annealing. As can be seen in Figure [12], the laser anneal threshold energy density for reduced resistivity is, for the a-Tio.3W.l;lSi.85, -160 mJ/em2. As expected, raising the substrate temperature dunng laser annealing reduced the energy density required for a given resistivity. Because the energy density was limited to about 300 mJ/em2 due to film cracking, and in order to reduce the thermal shock to the surface and interfaces, the substrate temperature was raised to 4SQOC for other experiments. However, even at 300 mJ/em2 the unpassivated GaAs surface remained stoichiometric as measured by EDXA. All laser annealing was carried out in a vacuum of less than 5 x 10-5 Torr.

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282

t ~ Ul Z w ... ~ w >

1 w IX

CRYSTAL MISORIENTEO BY 2° TO REMOVE LARGE DIFFRACTION PEAK FROM SUBSTRATE CGaAsI.

CuKa X·RAY SOURCE.

110 100 90 80

RESIOUE OF GaA_ SUBSTRATE DIFFRACTION PEAK AFTER TILTING CRYSTAL BY 2°

~

70 60

28 (degl

50

AMORPHOUS FILM PEAKS

/ ~ 40 30 20 10

Figure 11. X-Ray Diffraction Spectra of 3500 A Ti.03W.13Si.84 Layered Film Sputter Deposited on GaAs.

1--1 2OOp.m

Figure 12. Micrographs of u-TiWSi Gates

Page 288: Semiconductor Device Reliability

600 I

200 e f-ttl

500 3000 e 1

E 400 <.l

Cl 3-

~ 300 :> i= III

RESISTIVITY OF EXCIMER LASER en w 200 ANNEALED a·Ti.03W.12Si.85 1/tm GATES a:

ON GaA5 AT SUBSTRATE TEMPERATURES OF 20°C AND 300°C

100 20n5 SINGLE PULSES, 30Bnm

0 0 100 300

LASER ENERGY DENSITY (mJlcm2)

Figure 13. Average resistivity vs Laser Energy Density of Laser Annealed a-Ti.Q3W. 1ZSi.85 1f-Ull Gates.

283

RBS analysis of the laser annealed interfaces has been carried out to detennine the amount of interdiffusion as a function of laser anneal energy density and substrate temperature. Figure [14] shows the RBS spectra of a 180 om thick layered TiW /Si/TiW /Si.../GaAs film on a commercially available undoped semi-insulating (SI) GaAs wafer "as deposited" and after two different laser anneals on different areas.

c -' w >= c ~ ::::; « ;:; II: o Z

100 0.8

80

ENERGY (MeV)

1.0 1.2 1.4 1.6 1.8

} (0) unannealed

a 1W&4-1 (1) 176 mJlcm2• 3OPPS. 20·C. 10 min (2) 149 mJlcm2• 3Opps. 450·C. 10 min

CHANNEL

Figure 14. RBS Spectra of Pulsed Laser Annealed 1800 A thick a-Ti.OSW.llSi.84 Layered Film Sputter Deposited on a Commercially Available Undoped GaAs Substrate.

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284

The spectra revealed Ga and/or As outdiffusion into the Ti;x W vSiz film and interdiffusion of Si, W and Ti into GaAs. Examination of tne 1aser annealed surfaces with an optical microscope to 1000 x and by SEM to 20,000 x has shown smooth and continuous surfaces except at the beginning of laser ablation at sufficiently high energy density above which fIlms are no longer useful. No defects such as ablated craters with raised rims that could result in similar RBS spectra were observed. Figure [15] shows the RBS spectra of a similar laser annealed fIlm, deposited at the same time as the film of Figure [14], only on an In-doped substrate with reduced dislocation density. Note that compared to the s~ectra of Figure [ 12], very little interdiffusion occured after a 180 mJ/cm2 room temperature anneal while large interdiffusion occured at 176 mJ/cm2 on a typical undoped substrate. Also note that the interdiffusion is about the same in the two cases after 45()oC substrate laser anneals but the energy density was 27 mJ/cm2 higher in the case of the In-doped substrate. This result is in agreement with that reported previously [41J for RTA of TaSix films and is explained by diffusion dominated by crystalline defects which are much reduced in In-doped substrates.

ENERGY (MeV) 0.8 1.0 1.2 1.4 1.6 1.8

a TWS-I-1 }

(0) un annealed

150 (1) 180 mJ/cm', 30pps, 20°C, 10 min (2) 176 mJ/cm', 30pps, 350°C, 10 min

0 (3) 176 mJ/cm', 30~ps, 450°C, 10 min ...J W

>= o 100 w N ::J ~ ::;; II: 0 50 z

0 200 250 300 350 400 450

CHANNEL

Figure 15. RBS Spectra of Pulsed Laser Annealed a-TiosW l1Si84 180nm Layered Film Sputter Deposited on an In-Doped GaAs Substrate. .

The indiffusion of Si, an n-type dopant, into GaAs revealed in Figures [14] and [15] suggests Ohmic contact might be fonned under sufficiently high laser anneal conditions and this was indeed the case. Ohmic contacts were fonned by laser annealing of layered a-Ta 13Si.87 (175 om), a-Ti.07W.12Si.81 (150 om) and a-Ti23W 5,lSi.Z4 (40 nm) on both unactivated and activated ion implanted n-type GaAs. TYPICal laser anneal conditions to form Ohmic contact are given in Table 1. The lowest specific contact resistance of the laser annealed a-Ti,24W.53Si.23 Ohmic contact was 4 x lQ-4Qcm2.

In addition, it was found that shallow implanted layers could be activated under the proper laser anneal conditions. For example, for the a-Ta.13Si.87

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285

film on 120 keY, 3.5x1012cm.-2 Si implanted GaAs, the threshold for activation was 190 mJ/cm.2 for a 10 min. 30 pps anneal at a substrate temperature of 450°C. As the energy density was increased the Schottky barrier characteristics became softer and Ohmic contact was formed at 260 mJ/cm.2.

Metallization Laser Anneal Conditions GaAs Implanted Layer

a-Tao. 13 Sio.87 203 mJ/cm2 , 30 pps, 10 min, 450·C N = 7 x 1016cm-3

a-Tao. 13 Sio.87 357 mJ/cm2 , 1 pulse, 450·C N = 7 x 10 16cm-3

a-Tao. 13 Sio.87 140 mJ/cm2 , 1 pulse, 300·C N = 1 X 10 18cm-3

a-Tao. 13 Sio.87 302 mJ/cm2, I pulse, 20·C N = 1 x 10 18cm-3

a Tio.07 W 0.12 Sio.81 260 mJ/cm2 , 30 pps, 10 min, 450·C N = 7 x 10 16cm-3

a-Tio.24 W 0.53 Sio.23 148 mJ/cm2 , I pulse, 450·C N = 3 x 10 18cm-3

Table 1. Laser Anneal Conditions for Refractory Amorphous Metal Silicide Ohmic Contacts on N-type GaAs.

3.3 All Refractory Metal FET

All-refractory silicide GaAs FETs were fabricated with 2000 A thick laser annealed a-metal silicide gates and 400 A thick Ohmic contacts on MBE grown material. It was found that 140 mJ/cm.2, 5 pulses at a substrate temperature of 45()oC was sufficient to obtain the lowest contact resistance. After Au pads were deposited, the highest transconductance for a 4 f..Ul1 long gate FET was 40 mS/mm and 72 mS/mm for a 2 f..Ul1 gate device. IN characteristics are shown for the 2 f..Ul1 gate FET in Figure [16]. The lower than expected transconductance values for the geometry and carrier concentration is attributed to high source resistance which is about 5 Q.

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286

Source 10 I'm 1--1

Gate

Drain

L = 2.0 ",m, 72 mS/mm, 9

1 x1017cm- 3 MBE

I o Vos

Source/Drain Current, los' vs

Source/Drain Voltage, Vos' with

- 0.2 V Steps on the Gate ( 5 mA/div

vertical. 1 V/div horizontal)

Figure 16. All-Refractory Silicide GaAs FET after Excimer Laser Anneal at 140 mJ/cm2, 5 Pulses at a Substrate Temperature of 4500C.

4.0 CONCLUSIONS

Future metallization systems will be required to withstand short duration temperatures of 900a C (- lOs) and long duration (- 100 h) temperatures of up to 4500

• The present Schottky barrier and Ohmic contact metallizations, e.g. AI or TiPtAu gates and AuGe/Ni source/drain alloyed contacts, are sufficient only for the present technology, i.e. for dimensions above 0.5 !IDl and channel temperatures below 125 a C. New metallizations will be required for VLSI and USLI chips of the future and for millimeter wave devices with source/drain separation less than 0.5!IDl. The laser annealed Ohmic contacts discussed in this paper were developed for this purpose and also have high temperature and high reliability applications. An all refractory metallized GaAs FET was fabricated to demonstrate the feasibility of the methods discussed. In the case of the highest speed devices, no compromises should be made in the use of new metallizations, but new types of metallizations will be required to reach the desired performance. However, in the case of high temperature and high reliability applications, trade-offs may have to be made with performance.

Acknowledgment The Authors wish to thank Dr. A Christou for active support during this

work. Partial support by the Office of Naval Research, NATO and ESPRIT 1270 is gratefully acknowledged.

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287

References

1) Irvin, I.C. and Loya, A (1978), Bell Syst. Tech. 1., 57(8) pp. 2823-2846.

2) White, P.M., Hewitt, B.L. and Turner, I.S. (1978), "Reliability investigation of GaAs power FETs with AI gate", Eur. Microwave Conf. Paris.

3) Christou, A. and SIeger, K. (1977), 6th Biennial Conf. on Active Microwave Semiconductor Devices and Circuits, Cornell.

4) Sinha, AK. and Poate, 1.M. (1973), Appl. Phys. Lett. 23, 666.

S) Chino, K. and Wada, Y. (1977), lpn. 1. Appl. Phys. 16, 1823.

6) !rie, T., Nagasaki, 1., Kohzu, A and Sekido, K. (1976), IEEE Trans. on Microwave Theory and Tech. MTT-24: 321.

7) Mizuishi, K., Kurono, H., Sato, H. and Kodera, H. (1979), IEEE Trans. Electron. Devices, ED-26: 1008.

8) Kim, H.B., Sweeney, G.G. and Heng, T. (1974), Res. Lab. Rep. 74-1F6-IMP ATT-Pl, (Westinghouse Corporation).

9) Christou, A, Scanning Electron Microscopy 1979, Vol. I, SEM Inc., AMF O'Hare, 1979.

10) Christou, A. (1976), 1. Appl. Phys. 47, 5464.

11) Calviello, 1.A and Wallace, 1.L. (1977), IEEE trans. Ed-24, 698.

12) SIeger, K. and Christou, A (1978), Solid-state Electron. 21, 677-684.

13) Chen, H.S., Kimerting, L.C., Poate, T.M. and Brown, W.L. (1978), Appl. Phys. Lett. 32, 461.

14) Rosenblum, M.P., Spaepen, F. and Turnbull, D. (1980), Appl. Phys. Lett. 37, 184.

15) Naka, M., Hashimoto, K., Masumoto, T. (1978), 1. Non Cryst. Sol. 28, 403.

16) Ohta, 1., Hamana, T., Nishiuma, N., Hagio, M., Kazumura, M., Kano, G. and Teramoto, 1. (1985), Inst. Phys. Conf. Ser. No 79: Chapter 9, 511.

17) Yokohama, N., Ohnishi, T., Orodera, H., Shinoki, T., Shibatomi, A, and Ishikawa, H. (1983), "A GaAs IK Static RAM using Tungsten-Silicide Gate Self-Alignment Technology", IEEE 1. Solid-State Circuits SC-18, p.520.

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18) Palmer, D.W., Draper, B.L., McBrayer, J.D., and White K.R. (Feb. 1978), "Active Device for High Temperature Microcircuitry", Sandia Laboratoiries Report SAND 77-1145.

19). Behle, A.F., and Zuleeg, R. (Oct. 1979), "High Temperature GaAs Device Development", McDonnell Douglas Final Report to Sandia, Contract No. 13-0319.

20) Coquat, J.A., Palmer, D.W., Eknoyan, 0., and Van der Hoeven, W.B. (1980), "GaAs Ohmic Contacts for High Temperature Devices", 1980 Proc. Elec. Components Conf. p.55.

21) General Electric, Phase 1 Final Report (March, 1980), Contract No. NOOI73-79-C-OOI0.

22) Nieberding, W.C. and Powell, J.A. (2 May 1982), "High Temperature Electronic Requirements in Aeropropulsion Systems", IEEE Trans. on Industrial Electronics, IE-19, No.2, pp. 103-106.

23) Jurgens, R.F. (2 May 1982), "High Temperature Electronics Applications in Space Exploration". IEEE Trans. on Industrial Electronics, IE-29, No. 2, pp. 107-111.

24) Doerbeck, F.H., Duncan, W.M., McLevige, W.V. and Yuan, H.T. (1982), "Fabrication and High-Temperature Characteristics of lon-Implanted GaAs Bipolar Transistors and Ring-Oscillators", IEEE Trans. on Industrical Electronics, IE-29, pp. 136-139.

25) Wiley, J.D., Perepezko, J.H., Nordman, J.E., and Kang-Jin, G. (1982), "Amorphous Metallizations for High-Temperature Semiconductor Device Applications", IEEE Trans. on Industrial Electronics IE-29, pp. 154-157.

26) Todd, A.G., "Amorphous Electronics-I, pp. 507-513.

Harris, P.G. Scobey, I.H., and Kelly, M.1. (1984), Metal-Semiconductors Contacts for High Temperature,

Materials and Characterization", Solid State Electronics 27,

27) Wickenden, D.K., Sisson, M.1., Todd, A.G., and Kelly, M.1. (1984), "Amorphous Metal-Semiconductor Contacts for High Temperature Electronics-II. Thermal Stability of Schottky Barrier Characteristics", Solid State Electronics 27, pp. 515-518.

28) Papanicolaou, N.A., Anderson, Jr. W.T. and Christou, A., (1983), "Small Signal MESFET with Sputtered Amorphous Metal Gate Defined by Lift-off", Gallium Arsenide and Related Compounds 1982, Institute of PhysiCS Conf. Series No. 65, (Institute of Physics, Bristol), pp. 407-414.

29) Morgan, D.V., Thomas, H., Anderson, W.T., Thompson, P., Christou A., and Diskett, D.l. (1988), "High Temperature Metallization for GaAs Devices Processing", Phys. Stat. Sol. 110, pp. 531-536.

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30) Anderson, W.T. Jr., Christou, A, Giuliani, J.F. and Dietrich, H.B. (1982), "Laser Annealed and Thermal Annealed Refractory Ohmic Contacts to GaAs", IEEE Trans. on Industrial Electronics, IE-29, pp. 149-153.

31) Anderson, W.T. Jr., Christou, A, Dietrich, H.B., and Giuliani, J.F. (1980), "Refractory Metallized Ion hnplanted Epitaxial Ge-GaAs Ohmic Contacts", 158th Meeting of the Electrochemical Society, Oct. 5-10, 1980, Hollywood, FL.

32) Anderson, W.T. Jr., Christou, A, and Davey, J.E., (1978), "Development of Ohmic Contacts for GaAs Devices using Epitaxial Ge Films", IEEE J. of Solid State Circuits, SC-13, p. 430.

33) Christou, A, Davey, 1.E., Dietrich, H.B., and Anderson, W.T. Jr. (1979), "Refractory Passivated Ion hnplanted Ohmic Contacts to n-GaAs Layers", 37th Annual Device Research Conf., Univ. of Colorado at Boulder, Co., June 25-27, 1979.

34) Anderson, W.T. Jr. and Christou, A (1980), "GaAs Transferred Electron Device Failure Mechanisms", Workshop on Compound Semiconductors for Microwave Materials and Devices, San Francisco, CA, Feb. 1980.

35) Berger, H.H. (1972), "Contact Resistance and Contact Resistivity", 1. Electrochemical Society 119, p. 507.

36) Chang, C.Y., Fang, Y.K. and Sze, S.M. (1971), "Specific Contact Resistance of Metal-Semiconductor Barriers", Solid-State Electronics 14, pp. 541-550.

37) Cullis, AG., Webber, H.C. and Bailey, P. (1979), 1. Phys. E. Sci. Instrum. 12, pp. 688-689.

38) Giuliani, 1.F. and Anderson, W.T. Jr. (1981), "Elimination of Micro-inhomogeities in a Ruby Laser Beam for hnproved Semiconductor Device Processing", Applied Optics 20, pp. 2497-2600.

39) Cox, R.H. and Strack, H. (1967), "Ohmi(: Contacts for GaAs Devices", Solid-State Electronics 10, pp. 1213-1218.

40) Anderson, W.T., Christou, A, Thompson, P.E., Gossett, C.R., Eridon, 1.M., Hatzopoulos, Z., Ethimiopoulos, T., Kudumas, M., Michelakis, c., and Morgan, D.V., (1989), "Laser Annealed Refractory Metal Silicide Films on GaAs", Electronics Letters (submitted).

41) Morgan, D.V. Thomas, H. Anderson, W.T. Thomson, P. Christou A and Diskett. DJ. (1987), Electron. Lett. (23) pp. 1154-1155.

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NUCLEAR METHODS IN THE CHARACTERIZATION OF SEMICONDUCTOR RELIABILITY

J. C. SOARES Centro de Ftsica Nuclear da Universidade de Lisboa Av. Prof. GamaPinto 2 1699 Lisboa Codex, Portugal

ABSTRACT. Ion implantation is a well established technique for semiconductors doping. The annealing of the samples has, however, to be done as the following step and in many cases the results are not well understood. A survey of applications of nuclear techniques for the characterization of the structural and electronic environment of impurity atoms in semiconductors in an atomic scale will be given. The potentialities, sensitvity and limitations of the nuclear techniques will be discussed. In particular, specific examples will be presented to illustrate the perturbed angular correlation (PAC) technique using gama­gama or electron-gama transitions and the Mossbauer spectroscopy in studies of defects in semiconductors.

1. Introduction

Nuclear techniques, like Mossbauer Spectroscopy (ME) and :eerturbed Y Y Angular C.orrelation (PAC) Spectroscopy do not belong to the type of experimental methods which can be applied for systematic studies of a wide variety of different materials. However, since they are nuclear techniques sensitive to the local environment of a radioactive probe atom, when applied to study special problems, they can be very helpfull. Mossbauer effect has a large spectrum of applications, particularly in the field of chemistry, solid state physics and metallurgy [1]. The PAC spectroscopy remained until very recently as a technique only used by very experienced nuclear physicists for the investigation of internal fields in hexagonal closed packed systems. In recent years, however, this technique had a great success when applied to metallic cubic systems for the study of the behaviour of the defects and mpurities in these materials during heat treatments [2]. These studies in metals pushed people to .he application of these teChniques also in the field of semiconductors where defects and impurities playa very important role in their reliability. It is the aim of this talk to introduce the methods and to show what are the problems in the field of semiconductors where the nuclear methods can be applied with interest. Mainly, we will show how the basic understanding of the semiconductor doping process by ion implantation or diffusion can be enriched with the information from these methods. We have, however, to call your attention for the fact that, being these techniques real microscopic, sensing the near surrounding of the probe nucleus, they are very appropriate for defects characterization of semiconductors. A big limitation derives, however, from the fact that we have only a few appropriate probes. The need to introduce the radioactive probe in the site of the crystal we like to investigate opens sometimes a real problem.

291

A. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 291-300. © 1990 Kluwer Academic Publishers.

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Being sucessful in resolving this problem, we will show that the results can be very interesting and the infonnation obtained is sometimes unique.

2. The PAC Technique

The PAC technique is based on the fact that the intensity of radioactive electromagnetic radiation, emitted by a set of aligned nuclei, measured in two directions fanning an angle of 900, is anisotropic. The anysotropy coefficient is time dependent and shows the spin precession of the nuclei.

The most used probe for the investigation of defects and impurities in semiconductors, using the PAC method, is the 5/2+ level in 111Cd which can be populated from the decays of 111In or ll1mCd. In Fig. 1, is presented the decay scheme of these isotopes.

417 hV

396 keY

245 k.V

"'---1""'-- 0.12 ns

.l---r~"""'- 48.6 mIn IIImCd

.L-~-"-- ~ ns

~_""'--2.8d

IIIln

99.99·.[(

Q(5/ 2·) '" 0.83(13) b

/.I.(~/2·) '" -O.766(3) ~I

JilIn 111·Cd

An ..- -0.18 "J: II< a.ll!

A •• '" 0.002 A. 4 '" -0.004

A,. e -0.204 ",. ~ 0.206

".2 ~ 0.001 A. J ~ -0.004

Figure 1. Schematic decay schemes of the PAC isotopes 111mCd and 111 In.

As is shown the level 5/2+ is the intermediate level of a very strong y y cascade in both the decays of 111 In and 111mCd. The anisotropy of the cascade and the lifetime of 2.8 d of 111 In makes this isotope easy to use. In order to use 111mCd we have to carry out the experiment in big facilities, like CERN, where the radioactive probe is produced by spallation in the ion source of an isotope separator on line with the cyclotron. The 111mCd activity is mass separated and implanted with the energy of 60 keY in the appropriate probes. Using 111In we are more flexible and the implantation energy can be chosen between few and some hundreds ofkeV.

In a hyperfine interaction experiment the nucleus senses the charge distribution of its surrounding and, therefore, the interaction of the electric field gradient (EFG), originated by the charge distribution, with the quadrupole moment of the probe nucleus, (eQ),which in this case is 0.83 (13)b, can be measured.

The EFG is the- second derivative of the electrostatic potential at the site of the nucleus and is described by a sec md rank tensor. It can always be transformed to a principal axis system where only the diagonai elements V xx, Vyy and V zz are nonzero. Since the density of the charge contributing to the EFG vanishes at the nuclear site, the Laplace equation, V xx + V yy + V zz = 0, shows that the EFG can be described by two quantities, i.e., its largest component, which is taken

by convention to be V zz, and the asymmetry parameter 11 == V x'V- VYY . This asymmetry zz

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parameter is a measure of the deviation of the EFG from axial symmetry and varies between 0 (axial symmetry along z) and 1. The strength of the EFG tensor as measured at the site of the probe

atom is expressed by the nuclear quadrupole coupling constant V Q == ~. This coupling

constant, measured with a precision of about I MHz, and the asymmetry parameter n guarantee the unique labelling of the probe atom environment which gives rise to the measured EFG.

In Fig. 2 we present results of a PAC experiment where the probe nucleus occupies the substitutional site of a GaAs crystal after annealing at 6000 C. The as implanted and the 4000C annealed spectra are also shown.These results have been measured using 111In implanted in GaAs.

Rltli

~:I~ -0.11

so

,4 . H

100 150 t Insl

Figure 2. PAC spectra of 111 In implanted GaAs measured after implantation and after annealing treatments at different temperatures.

These results are obtained with the experimental set up shown in Fig. 3.

,-... ,---, Radioactive " ... - " la_pie ----:----.. \

\ , \,

Figure 3. Schematic drawing of a two detector apparatus necessary to measure a y - y angular correlation. The dashed line shows the emission probability of a dipole radiation with M=±l relative to the quantization axis z.

Detector 1, through the detection of y 1, is able to give the starting pulse in order to follow the spin precession of the probe nucleus. The quadrupole interaction induces periodic changes of the m

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substate population, unless V zz is collinear with the quantization axis defined by the emission of y }. These changes are equivalent to a precession of the associated radiation pattern about the z-axis and lead to a time dependent evolution of the coincidence count rate N(t) between detectors 1 and 2

nmax N(t) ::: e- At L Sn(11,oq) cos{cn(11)VQt}

n=O with nmax being detennined by the spins of the nuclear levels and multipolarities of the radiative transitions involved in the y - y cascade. The leading factor describes the exponentially decreasing probability to register y 2 after the intennediate state with decay constant A has been populated by y }. Since A is usually accurately known this exponential factor can be eliminated and only the time dependent variation of the anysotropy due to the nuclear precession is analyzed. The frequency factors Cn depend only on the asymmetry of the EFG and can be calculated for all values of 11. Therefore, the factors Cn derived from a Fourier analysis of the observed interaction pattern N(t) allow an accurate detennination of the asymmetry parameter 11 of the EFG.

The coefficients sn( 11 ,0'1) also depend on the orientation of the principal axis system of the EFG (described by the Euler angles 0: 1) relative to the z axis defined by the emission of y 1. PAC measurements in oriented single crystals can therefore be used to detennine the orientation of the EFGs principal axis system relative to the crystallographic directions of the lattice.

In Fig. 4, just for illustration of the method, we present typical PAC results of a EFG for a probe in an interstitial site of a well characterized system [3].

~" .... : . \ ': " ~

~IIIOJ 'I'

O.ClO , I

• ·0.10

o 10 10 .0 .. 0 JO &(1

.... ~.. . ,',',

.~ I

·0.10

a UI '0 III .a "0 "0)

0010"'" I . . ! 2. J~~.. J ,/,,,IU!!lf: 11~~'~Il~~1

0.00

- •. '0 j ~.---c.'O~~'~O--~'o----,-,---u~--~,.~)

t 'TlI.e )

Figure 4. Time dependent anisotropy A(t) of the 133-482-keV cascade for 181Ta in beryllium Single crystal: (a) as implanted, (b) after annealing at 843 K, (c) after annealing at 843 K but with the c axis in the direction of one y detector .

As soon as the probe traps an oxygen, the frequency increases by a factor of 6 and if we align the EFG with the direction of y 1 the frequency disappears. A constant anisotropy is measured like in the case shown in Fig. 1 after annealing at 600oC.

If, however, in a near neighbour position of the probe we have an atom missing or a trapped impurity V zz is large and the spin precession takes the fonn presented in Fig. 4, where a Fourier analysis gives the sharp frequency which measures the strength of the interaction. The other

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frequencies in the Fourier analysis are the hannonics and for our probe with a spin 5(2 they are 2 ~o

and 3~o, being ~o the fundamental frequency ( ~ == ~:- ) with To the period of the spin

precession. The amplitude of the perturbation function gives infonnation on the number of nuclei in the respective configuration. If one part of the probe atoms are in one configuration and the other in a different one we observe two field gradients and, therefore, two frequencies and the respective hannonics. In this case, the spectrum can be very complex as we will show in a few examples later on.

We started to present the results for ideal systems where the probe is in a regular lattice site. This is not normally the case in semiconductors. The radiation damage created during ion implantation produces amorphization, defects or individual defect cascades. In this case what we observe is a frequency distribution that can be centered in vQ=O or in VQ=ttO. We will show at the end of this talk that the information we can get from these measurements can also be very interesting. In the following let us see a few examples of the results recently obtained for semiconductors.

3. The PAC measurement of the system In!i..iJ.A.5.

The first PAC experiment with indium implanted GaAs has been carried out to demonstrate the sensibility of the PAC technique when applied in the semiconductors field. In fact at the end of a conference where the results of PAC measurements of a tantalum probe implanted in metallic beryllium foils and single crystals have been presented (see Fig. 4) and where we tryed to show the potentiality of the experiment to identify an internal oxidation process, we were asked about the possibility to do the same experiment in implanted GaAs crystals. The answer was: we do not know, probably, tantalum is not the ideal probe for studies in semiconductors. In further discussions we realized that the system In~ could be of great interest and that the synthesis of In~ by ion implantation could be of great importance.

Our first aim was to study the possibility of introducing indium by ion implantation in regular Ga sites of GaAs. These results are presented in Fig. 2. After the implantation we observe a frequency distribution which is not related with the amorphization of the implanted region. In fact, the concentration of indium implanted at 80 keY was very low (_1012 Ion+/cm2) so that using the channeling technique we have no sensitivity to see any change in the channeling axial patterns of the crystal.

After furnace annealings of about 30 min. in vacuum drastic changes are observed. At about 6000 C we have a nearly constant anisotropy, characteristic of a system where indium must occupy a site with cubic symmetry. Since we did not loose activity we have not out-diffusion and, since we have no sharp frequencies, we have not indium segregated at the surface of the GaAs crystal. The first conclusion of this test experiment is that the PAC experiments can be conclusive in the semiconductors field. In fact, we are able to follow with a PAC experiment the radiation damage annealing process, we always need to do after the implantation of the samples. It turned out through the discussion of these results that it should be very interesting to repeat these experiments in samples of GaAs pre implanted with very high doses of In+ and Se+. In order to process these samples rapid thennal annealing followed by furnace annealing is necessary. Our method could improve the basic understanding of the physiCS involved.

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4. PAC measurements in In.G.ilM systems pre·implanted with very high In+ and Se+ fluences

Two identical samples of GaAs have been implanted with In+ and Se+ with both fluences of the order of 2 x 1015 ions/cm2. In one of the samples rapid thermal annealing has been done after encapsulation of the sample in the way that channeling shows a good recovering of the sample

::

o 100

GaAs -0.1 In+Se doped

.'

200 300

111In implanted

TA=295 K

oU---________________ ~ ______ ~~~· __ ~

-0.1

Figure 5. PAC spectra of 1111n implanted GaAs doped with In and Se measured after furnace annealing at different temperatures.

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surface. After this treatment, both samples have been implanted with a very low fluence of radioactive I11ln and an annealing programme has been done in many steps. In Fig. 5 and 6 are presented the results.

It is observed that the PAC method is sensitive to the rapid thermal annealing pre-treatment given to one sample. In fact we are able to explain the data for this sample by adjusting a frequency distribution centered in V Q = 0 with a large width. For the other sample, with no rapid thermal annealing pre-treatment a frequency distribution centered in a value of V Q *" 0 is obtained.

The most important conclusion, however, is related with the formation of indium precipitates in the sample only furnace annealed. In fact, once these precipates are formed, increasing the temperature the surface does not recover. On the contrary, the annealing behaviour of the rapid thermal annealed sample is very similar to the test experiment shown before.

--;-

o 100

GaAs In+Se doped RTA

200 300

111Jn implanted TA=295 K

0~--------4---------~--------~---1

°0~--------~1±00~------~2~0~O--------~3±00~--~

tin. J

Figure 6. PAC spectra of 1111n implanted GaAs doped with Se+ and 1+ and rapid thermal annealed.

5. PAC Measurements in Silicon

PAC experiments in silicon have been done many years ago for the first time [4], but, only very recently, the results started to be understood. In fact, it has never been possible to anneal completely an implanted sample as it has been shown in Fig. 2. Only very recently [5] similar results have been obtained for n-type silicon crystals using very high annealing temperatures. The same has not yet been obtained with p-type or intrinsic crystals. The results presented in Fig. 7 and Fig. 8 [6] show the In-donor and In-H atom pairing. PAC experiments are, therefore, appropriate

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IX

-0.15 r------:::,-------, Si: P(1.5·10 181 T.=900K

-010

o Si. Bi (7.1020) 1100K

-C10~J\ , .. ~~!§ .1'1'

-0.05\ " 0L.-.-SO--1OO·--'SO--200--2S-0--'3oo

t (nsec)

IX

0.0 ~--------------~

-0.1

../vl~JvwVVVl'~~ 00

oL.-.~S70-~100~'--'S~O-~200 , Insecl

Figure 7. PAC spectra of lllIn implanted in differently doped Si, measured after annealing at the indicated temperatures [6].

Figure 8. PAC spectra showing the formation of the identical 111In_H pairs following (top to bottom): plasma etching (13.56 MHz, 320 V, and 0.6 mbar), boiling in water, and implantation of 1. 1014 H+ cm-2 [6] .

for studies of activation energies of pair formation. The method is also appropriate for studies of defects in semiconductors and, particularly, to look for the site of the vacancy or impurity as is shown in the Fourier analysis shown in Fig. 9 for the hydrogen system in silicon.

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In-H1 Si r r r

6

~J,:rl~ (100)

r

J~ 2

<111 )

6

l.

2

.,..-v. ~l\ .A • • ... ..1.

LOO 800 1200 1600 2000 III IMrod/sJ

6. Mossbauer Measurements in Silicon and GaAs

299

Figure 9. Fourier transforms, belonging to different orientations of the y detectors with respect to the Si lattice, which show the <111> orientations of the complexes In-HI and In-H2 [6].

The advantages and limitations of the PAC experiments are extensive to the use of the Mossbauer technique. The application of the Mossbauer Spectroscopy to studies of the local surroundings of dopants relies on the availability of suitable Mossbauer isotopes. Amongst these, two are of practical importance, namely isoelectronic 119Sn and 121Sb donors. Absorption experiments have been performed with both isotopes in silicon. For In also conversion-electron experiments have been reported [7]. The application of various radioactive precursors, which decay to the Mossbauer states of these atoms enlarged the possibility to study the behaviour also of these precursors. These has been done using ISOLDE at CERN. It should be taken into account that using MS in addition to the electric quadrupole splitting, information is also obtained on the isomer shift and on the Lamb-Mossbauer factor. These two quantities are related with the impurity valence-electron configuration and vibrational impurity amplitude.

7. Summary and Perspectives

It has been shown that nuclear methods like PAC experiments and Mossbauer spectroscopy can be used to get basic information about the physics of semiconductor processing. Being both techniques very specialized they can be applied only if the appropriate probes are introduced by ion

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implantation or diffusion in regular sites of the systems. In this case these techniques are very sensitive to any microscopic change in the immediate surrounding of the probe atom and, therefore, infonnation can be obtained on the stability of the system and on the activation energy of a known process.

At the moment there are perspectives to extend the number of appropriate probes for semiconductor studies, using radioactive beams at the ISOLDE facility at CERN. There is a unique opportunity for the simultaneous application of Mossbauer, PAC, PAC with e--y and electron channeling techniques to study defects and impurities in semiconductors.

Acknowledgement

Many fruitful discussions with Dr. M.F. da Silva are greatly appreciated. The investigations were supported by JNICf (CERN project) and NATO.

8. References

[1] Carbucicchio, M. and Principi, G., Proc. of the International Symposium on the Industrial Applications of the Mossbauer Effect, Panna (1988), Hyp. Int. 45 and 46 (1989).

[2] Devare, H.G., Tandon, P.N., Devare, S.H., Proc. of the International Conference on Hyperfine Interactions, Bangalore (1986) Hyp. Int. 35 and 36 (1987).

[3] Soares, J.C., Melo, A.A., da Silva, M.F., Freitag, K., Herrmann, C., Herzog, P., Rudolph, H.J., Schloesser, K., Vianden, R., Wrede, U. and Boenna, D.O. (1984) 'Oxygen gettering by hafnium implanted in beryllium: A<OOOI> Hf-O dumbbell?', App. Phys. Lett. 45, 143-145.

[4] Kaufmann, E.N., Kalish, R., Naumann, R.A. and Lis, S. (1977) 'Annealing behavior of In implanted in Si studied by perturbed angular correlation', J. of App. Phys. 48, 3332-3336.

[5] Deicher, M., Grubel, G., Recknagel, E. and Wichert, Th. (1986) 'Detection of Electronic Perturbations in Silicon After EC Decay of 111In Observed by PAC', Nucl. Instr. and Meth. B13, 499-502.

[6] Wichert, T. (1989) 'Feasibilities of Nuclear Techniques for the Study of Molecular Defects in Metals and Semiconductors', Hyp. Int. 45, 143-160.

[7] Weyer, G. (1988) 'Applications of Mossbauer Spectroscopy to Characterize Highly Doped Semiconductors', in E. Recknagel and J.C. Soares (eds.), Nuclear Physics Applications on Materials Science, Kluwer Academic Publishers, Dordrecht, pp. 167-172.

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A Review of the Reliability of III-V Opto-electronic Components

S P Sim, British Telecom Research Laboratories Martlesham Heath Ipswich England IP5 7RE

Abstract

This paper summarises work at the British Telecom Research Laboratories to evaluate the reliability of laser diodes and transmitter modules, LEDs and photodiodes for use in optical fibre transmission systems. Results are presented which show that these components are capable of the high reliability needed for telecommunications use, but that they are still vulnerable to a number of failure mechanisms. Reliability assessment, failure analysis and the development of effective screening methods therefore play an important part in the development and application of opto-electronic components.

1. Introduction

As a major user of optical communication systems, British Telecom has a profound commitment to the reliability of opto-electronic components. Despite significant advances in optical component technology, not all commercially available laser and detector modules exhibit the performance or reliability required in telecommunications systems.

This paper describes some of the work that has been done at the British Telecom Research Laboratories (BTRL), both to further the advance of device reliability and to assess the reliability of commercially-available components.

2. Lasers and Laser Transmitter Modules

2.1 INTRODUCTION TO LASER RELIABILITY

Early GaAlAs lasers (850nm) were vulnerable to several degradation mechanisms, but considerable improvements were made following reliability studies during the 1970s and early 1980s [1,2,3]. Failure mechanisms associated with material defects, with stress, with facet degradation, and with bonding were identified and improvements in laser chip processing introduced as a result. GaAIAs lasers capable of lifetimes greater than 5 years at room temperature were developed and brought into use in optical fibre systems.

The InGaAsP lasers now being used in 1300nm and 1550nm optical fibre systems are capable of even longer lifetimes and, with thorough screening and testing, can have sufficiently high reliability for submarine systems [4,5,6]. The significant improvements

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A. Christou andB. A. Unger (eds.), Semiconductor Device Reliability, 301-319. © 1990 Kluwer Academic Publishers.

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that have been made in laser chip technology have led to the situation where the reliability of today's commercially available laser transmitter modules may well be dominated, not by the laser chips, but by failures associated with packaging; for example: loss of fibre light output due to instability in the fibre to laser alignment.

2.2 BURIED HETEROSTRUCTURE LASERS.

Large-scale lifetests have been performed at BTRL on more than 1000 buried heterostructure (BH) lasers grown by MOVPE, and over 2.5 million device hours have been accumulated. Lifetests were performed for durations of up to 12,000 hours, either at temperatures from 30·C to 90·C under lasing conditions, or at 125·C under electro­luminescent (EL) conditions. A range of failure analysis techniques. including transmission-electron-microscopy (TEM), were performed to identify degradation mechanisms in early wafers, as described below.

2.2.1 Degradation Mechanisms. Lasers from some early wafers exhibited relatively rapid degradation. TEM analysis of degraded lasers [7] revealed complex structural defects in the form of interstitial-type dislocation dipoles and loops originating from the active layer side walls and growing across the active layer in projected <100> and <110> directions. as shown in Figure 1. Such defects were not found in untested lasers.

Careful control of lattice mismatch between the InGaAsP active layer and the InP cladding layers using X-ray double-crystal diffraction techniques [8] has led to greatly reduced degradation, and such defect formations have been eliminated by maintaining lattice mismatch to between 0 and -300ppm. It can be concluded that lattice mismatch significantly influences degradation, even when the mismatch does not result in the formation of mismatch dislocations as for the untested lasers in reference [9].

BH lasers, grown by either MOVPE [7] or LPE [10]. usually show two distinct stages of degradation. There is a relatively rapid first stage which saturates. followed by a much lower rate of long term degradation. The first stage of degradation in MOVPE BH lasers is characterised by an increase in threshold current. but no change in the external efficiency at the same current. This observation indicates an increase in non-radiative recombination, as proposed for LPE BH lasers [11].

The increase in non-radiative recombination in degraded MOVPE BH lasers is caused by the growth of loop defects (typically up to 50nm in diameter) along the side walls of the InGaAsP active region. close to the regrown interface with the InP blocking layers as shown in Figure 2.

Both stages of degradation in MOVPE lasers can be minimised by careful attention to processing and to the first stage of overgrowth. Similar defects have been found in LPE BH lasers [12]. and a reduction in degradation has been reported [13] by using meltback of the active-layer side-walls prior to overgrowth.

2.2.2 Burn-in. To select lasers which will have long lifetimes, a burn-in is necessary. Experiments to study burn-in conditions for BH lasers have been performed using lasers taken from more than 50 wafers.

Three different burn-in conditions were studied, namely (i) 80·C and 4mW /facet, (ii) 90°C and 4mW /facet and (iii) 125°C and 100mA. It was found that 500 hours, 150 hours and 24 hours respectively were required to take the lasers beyond the first-stage of

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degradation. TEM analysis of lasers burned-in undE~r either lasing or EL burn-in conditions showed that degradation takes the same form. This result shows that degradation is driven by current and temperature, and that high optical power density during lasing is not essential for the degradation process. It is noteworthy that an EL treatment of 24 hours at 12S·C does not introduce additional degradation mechanisms.

The increase in threshold current (measured at 2S·C) after burn-in for 24 hours at 12S·C and 100mA is typically 1-2mA, and our lifetest results confirm that this burn-in provides a short, but effective screen. Other workers [10,14] have also found that a short EL burn-in at temperatures in the range 100-JISO·C is an effective screen for BH lasers.

2.2.3 Lifetest Results for BH lasers. After burn-in, the MOVPE BH lasers exhibit extremely low rates of increase in operating current" even at high operating temperatures. Lifetest results at 80·C for sixty 1300nm lasers taken from 6 wafers are shown in Figure 3, in which the operating currents to maintain a constant light output of 4mW are plotted as a function of time. Similar results are obtained for ISSOnm lasers.

Following burn-in, the increase in operating current with time on test is given by equation (l)

(1-10 )/10 = A tn exp(-EA/kT) ..................... (1)

where 1 is the laser operating current, 10 is the initial current, A is a constant, t is time in hours, n is the time exponent, E ~ is the activation energy, k IS Boltzmann's constant and T is the absolute temperature.

The lifetime of a laser on lifetest is obtained by extrapolating the percentage current increase as a function of time, to some defined failure criterion (for example a 50% increase) as shown in Figure 4. When failure is defined in this way, then it can be shown that the apparent activation energy, Eap' for the temperature dependence of the laser lifetime is equal to E A/n. The apparent activation energy for the lifetime of BH lasers (after burn-in) has been found to be 0.6eV for lifetests at temperatures in the range 30·C to 12S·C on lasers taken from two wafers. The current exponent, n, was found to have a value of about 0.5. Therefore, the true activation energy, E A' for laser degradation is 0.3eV.

The predicted median lifetime at 80·C is >106 hours when failure is defined as a 100% increase in operating current, and is >105 hours for a 50% increase.

2.3 OTHER LASER STRUCTURES

Ridge waveguide lasers have relatively high threshold currents and therefore cannot operate at such high temperatures as BH lasers. However, the active layer is not cut during processing, with the result that side-walls are not exposed during overgrowth. The ridge lasers do not therefore exhibit the two-stage degradation exhibited by BH lasers, but tend only to show slow gradual degradation. Typical life test results for ISSOnm

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ridge lasers grown by MOVPE, which had received no prior burn-in, are given in Figure 5, in which threshold currents (measured at SO·C) are shown as a function of time on lifetest at 100·C with 100mA drive current.

Very low degradation rates have been reported for other types of laser structure, including BH [10,15), V-groove BH [15,16,), DC-PBH (16), Buried Crescent (17) and ridge waveguide (18). For applications where reliability is at a premium, rigorous screening procedures, good quality control and sound packaging technology will all be required.

3. Distributed Feedback Laser Transmitter Modules

3.1 INITIAL PERFORMANCE CHARACTERISTICS

We have evaluated the performance and reliability of early production samples of a range of commercial distributed feedback (DFB) laser transmitter modules. Initial characterisation measurements, prior to life-testing, have shown the necessity for thorough initial screening of DFB lasers to prevent devices with anomalous spectral behaviour causing problems during system use. For example, six out of nine lasers from one manufacturer showed the onset of an additional spectral peak, associated with a non­linearity in the light-current characteristics, at fibre output powers of between 1.25 and l.SmW at 2S·C -- not far above the specified maximum output power at that temperature. Spectra for a typical laser are shown in Figure 6. At S·C, the change to the double peak mode occurs at output powers of between 0.5 and 1.0mW.

One laser (of ten) from another manufacturer had satisfactory performance at 2S·C, but showed excessive Fabry-Perot modes at O·C, as shown in Figure 7.

One laser from a third manufacturer which had a side-mode-suppression-ratio (SMSR) of 29dB when measured under CW drive at 2S·C, had a very poor spectrum under modulation conditions. At S90MBit/sec its SMSR was reduced to 16dB, as shown in Figure 8.

These measurements demonstrate how essential it is for DFB spectral and light current characteristics to be measured over the full range of the lasers' specified operating conditions, including extremes of temperature and operating power. Screening measurements should also include spectral performance under modulated conditions.

3.2 RELIABILITY OF DFB LASERS.

Following an initial characterisation, commercial DFB lasers have been life tested at temperatures in the range 40·C to 100·C for periods up to 12,000 hours. Despite the spectral anomalies observed during initial characterisation measurements, the lifetest results have been encouraging in terms of spectral stability. None of the six lasers which showed double spectral peaks at high output powers, have shown any reduction in the drive current at which the mode change occurs, although one of these lasers had three main spectral peaks at high output powers after 2,000 hours at 70·C.

Several early lasers showed significant increases in drive current after 2,600 hours at 40·C. Threshold current increases were between 25% and 90% but there were no

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significant changes in SMSR or in the line-width of the main spectral peak. The peak wavelengths (measured at 25·C) increased by between 0.2 and 0.8nm, indicating that the increase in junction temperature in these junction-side-up mounted lasers dominated over the reduction in refractive index caused by the increased carrier density [15,19].

Other DFB laser modules have now been on Iifetest for 12,500 hours at 50·e with ImW fibre output (Figure 9) and for 5,500 hours at lOO·e" 140mA with only small changes in drive currents and threshold currents. These results indicate that DFB lasers have the potential for high reliability. Several workers have reported results showing that DFB lasers can have low degradation rates and that the degradation mechanisms are essentially the same as those which would occur in Fabry-Perot lasers.

However, it has also been shown [20] that DFB lasers with inhomogenous lasing due to spatial hole burning are likely to degrade rapidly under severe operating conditions, and such lasers which exhibit superlinear light-current curves should be screened out. To demonstrate low failure rates for high reliability applications, large-scale life-testing of DFB lasers is required to demonstrate that localised degradation within the active region will not give rise to degradation of spectral performance under normal operating conditions.

4. InGaAsP /lnP Light Emitting Diodes

Light emitting diodes (LEDs) offer an attractive alternative to lasers in some short-to­medium distance systems where their low light output is not a disadvantage. Lifetests, at temperatures of between 100·e and 175·e, on ridge waveguide edge-emitting diodes (ELEDs) grown by MOVPE have confirmed reports [15,21] that LEDs are capable of very good reliability. Typical life test results are shown in Figure 10 in which only a very gradual reduction in light output has occurred after 11,000 hours at lOO·e with a constant drive current of 100mA.

Predicted lifetimes, where failure is defined as a IdB reduction in light output at 30·e, are shown in Figure II for a total of 56 ELEDs from several different wafers. The devices had received no prior burn-in. The plot includes results at four different temperatures for devices from one particular wafer and indicates an activation energy for the lifetime temperature dependence of appr~ximately 0.75eV. The predicted median lifetime at 25·e for wearout is therefore -10 hours. Larger sample sizes need to be evaluated to confirm low random failure rates.

5. Laser Packaging

There have been a large number of publications concerning the reliability of laser diodes, but there is considerably less information available on the reliability of laser transmitter modules. Such modules contain several other important components; for example, a monitor photodiode, a fibre pigtail, and often a thermo-electric cooler and thermistor for temperature control.

During evaluations of a wide range of commercially available laser modules, we have found that their reliability is, in several cases, governed by package-related failures.

For example, a critical alignment between the fibre tip and the laser facet is required in

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order to maintain a constant light output from the fibre pigtail. For monomode lasers, alignment is required to within a few tenths of a micrometre, unless lenses are used to reduce the alignment tolerance. During lifetests at BTRL at (constant) ambient temperatures between 30°C and 80°C, a very wide variation has been found in the rate of change in fibre light output. (The lifetests were performed with the laser drive currents adjusted to maintain constant monitor photodiode output.) Failure was defined as a 3dB fall in light output, and for those packages in which the reduction in output was less than 3dB during the lifetest, the time to failure was predicted by linear extrapolation. In some cases failure has been extremely rapid, even at temperatures within the specified operating range, as shown in Table I. It is interesting to note that some packages which include lenses have shown totally unacceptable short lifetimes.

Failure analysis of those transmitters which failed confirmed that the laser chips were still emitting a similar light output from both facets, and that the initial fibre output could be restored by re-alignment of the fibre.

Table I Median lifetime of laser transmitter modules due to loss of fibre-light-output (failure is defined as a 3dB fall in fibre output at constant monitor photodiode output).

Median Life (hours) Fibre coupling/ sample size at Temperature °C fixing method each temperature 80* 65 60 45 30

via spherical lens IQ 2xIQ5 6xIQ5 3xl06

via rod lens 10 2xl03 2xl04 I.5xl05

solder and epoxy Ixl03 5xIQ3 fix of lensed fibre IQ

via rod lens 4 <lxIQ3

welded fix of lensed fibre 4 >lx105

via spherical lens 5 >3xIQ5

* temperature above specified maximum operating temperature.

6. Mesa and Planar InGaAs PIN Photodiodes

There are two main types of InGaAs/InP PIN photodiode available, having either a mesa or a planar structure as shown in Figure 12. Both types of photodiode are capable of high reliability, but the mesa structure, which has an exposed p-n junction, is more vulnerable to failure through increased surface leakage (dark) currents at this junction.

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Our lifetests on commercially available devices have shown that a 'good' mesa PIN can have a wearout lifetime of several thousand hours at 150'C [22]. The relatively high activation energy (-leV) for leakage current failures means that predicted lifetimes at normal operating temperatures can be adequate. However, our results for mesa PINs have shown a considerable spread in reliability from batch to batch, indicating an inherent reliability problem with the mesa structure. This problem is demonstrated by the poor results in Figure 13, in which significant increases in dark current have occurred after only 100 hours at 70·C.

An improvement in the stability of mesa PINs can be obtained by using an organic passivation on the exposed mesa edge, as shown by the results in Figure 14. The wearout failure rate at the end of a 25 year operating life at 40·C was estimated to be approximately 5 FITs for these PINs, using the leV activation energy found from Iifetests at 125 and 150·C. However, the demonstration of low random failure rates, required for high reliability applications, is made difficult by the onset of wearout failures after approximately 3,000 hours and 500 hours respectively at these temperatures [23).

Planar PINs are capable of extremely high reliability because of the effective protection offered by the silicon nitride passivation, as shown in Figure IS by the stable behaviour of planar PINs on lifetest at 200·C for 10,000 hours without failure. Large scale studies [24] of planar PINs grown by MOVPE have confirmed the low failure rates that can be obtained with these structures. The median-time-to-failure at 20·C was predicted to exceed 101 hours, with a negligible failure rate due to wearout over a 25 year service life. The random failure rate was demonstrated to be <0.3 FITs at 20·C to 90% confidence.

7. III-V Avalanche Photodiodes

III-V avalanche photodiodes (APDs) are similar in structure to planar III-V PINs, but operate at much higher voltages to obtain multiplication of the photo-generated carriers. To prevent premature breakdown at the edge of the main p-type diffusion, APDs include a guard ring diffusion or ion implantation. The APD surface can be passivated, as with the planar PIN, but the higher electric fields in APDs might be expected to result in a greater tendency to failure by field related mechanisms, such as charge movement.

During reliability studies of III-V APDS from several manufacturers, we have observed the following two failure mechanisms which lead to increased dark currents:-

I. contact metallisation penetration into the junction region, 2. localised breakdown at the junction edge.

The metallisation failures occurred, in early samples from one manufacturer, after approximately 500 hours on life-test at 200·C with 100 uA constant current bias. Failure analysis by energy dispersive X-ray analysis showed alloying of the TiPtAu metallisation, and penetration of the gold into the semiconductor. Recent samples of devices from several manufacturers have not shown this type of failure after periods in excess of 2,000 hours at 200·C.

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The dominant failure mechanism for III-V APDs is associated with premature breakdown at the junction edge. Figure 16 shows the increase in dark currents due to this mechanism in a sample of eight APDs on life-test at 200°C and 100uA. In a further sample of nine of these components, the onset of the dark current increase was found to occur after approximately 3000 hours at 175°C, but no failures (dark current greater than lOOnA at 25°C) had occurred at this time. The increased dark currents in those devices degraded at 200°C were shown to be caused by localised breakdown at the junction edge, as seen previously in both silicon APDs [25] and III-V APDs [26].

The uniformity of response was measured by scanning a light spot, of either 1300 or 800nm wavelength, across the surface of the device under test with the bias maintained at 90% of its breakdown voltage. Figures 17 and 18 show plots obtained for a degraded APD. The localised gain peaks, which can be seen at the junction edge only under 800nm illumination, are typical of peaks seen on the other degraded devices examined by this method. Before the life-test, all the APDs showed ideal responses at both wavelengths, with no edge breakdown. The 800nm light is mainly absorbed within the top 0.5um of InP, whereas at 1300nm, the light penetrates to the main junction. The observation that localised breakdown takes place only at the shorter wavelength therefore indicates that failure is a surface effect. It is likely that localised high electric fields leading to premature edge breakdown are a result of the accumulation of positive charge in the passivation layer. This charge could come either from mobile ions within the passivation itself, or as a result of hole injection from the guard ring junction, as proposed elsewhere [26]. Further evidence that the localised breakdown is caused by charge accumulation is provided by the fact that the degraded APDs could be restored to their pre-test condition by baking (at zero bias) for 300 hours at 200°C. As expected, devices with metallisation penetration showed no recovery following baking.

The wearout lifetime of the APDs in Figure 16 is about one order of magnitude shorter at 200°C than that of typical planar III-V PINs (Figure 15). Nevertheless, because the activation energy for the dark current increase in APDs is about leV, the lifetest results indicate that long lifetimes can be achieved at normal operating temperatures, as shown by other recent results [26,27]. However, a small number of relatively early failures occurred in our life-tests suggesting that stringent burn-in conditions will be required for high reliability applications.

s. Conclusions

Developments in III-V material growth and device processing, together with large scale reliability evaluations and failure analysis, have led to significant improvements in the reliability of l300nm and l550nm lasers in recent years. Results have been presented here which show t~at BH lasers grown by MOVPE achieve a predicted median lifetime of greater than 10 hours at SO°C.

Lifetest results for DFB lasers indicate that, despite their more complex structure and the addition of a grating, they have the potential for similar reliabilities to Fabry-Perot lasers in terms of gradual degradation leading to increased threshold currents. However, the long-term spectral stability of DFB lasers is crucial to system performance and despite promising results, further work is required to demonstrate adequate stability for high reliability applications. Spectral anomalies observed during characterisation prior to life-test show the importance of measuring spectral performance at the extremes of the lasers' intended operating conditions.

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Laser packaging is a source of reliability hazards. In particular, lack of long-term stability in fibre/laser alignment has been shown to lead to rapid loss of fibre light output, and hence the failure, of a range of laser transmitter modules.

309

A study of ridge waveguide InGaAsP/InP edge emitting LEDs has shown that relatively high life-test temperatures (>IOO·C) are required to produce measurable710ss of light output in a life-test of reasonable duration. A median lifetime of IxlO hours is predicted at 25·C for a IdB fall in light output.

Planar InGaAs PIN photodiodes have been shown to be significantly more reliable than mesa structures, which are vulnerable to increased surface leakage currents. Planar devices have median lifetimes of > I 04 hours at 200·C and predicted wearout failure rates at normal operating temperatures are negligible.

111-V APDs have a more complex construction than PIN photodiodes and operate at higher bias voltages. The dominant wearout failure mechanism has been found to be the development of localised edge breakdown caused by the accumulation of charge near the surface. APD lifetimes (median life -1000 hours at 200°C) are shorter than those obtained for planar 111-V PIN photodiodes, but the high activation energy for wearout failures (-leV) results in long predicted lifetimes for APDs under normal operation.

9. Acknowledgements

Grateful acknowledgement is made to many colleagues at BTRL for their contributions to the work reported in this paper. Acknowledgement is made to the Director of Research and Technology, British Telecommunications for permission to publish this paper.

10. References

1. Ritchie S and Newman D H, "Gradual degradation of GaAs double-heterostructure lasers", IEEE J Quantum Electron, OE9, No 2, pp 300-305, 1973.

2. Ritchie S, Godfrey R F, Wakefield B and Newman D H, "The temperature dependence of degradation mechanisms in long-lived (GaAI)As DH lasers", J Appl Phys, 49, No 6, pp 3127-3132, 1978.

3. Goodwin A R, Kirkby P A, Davies I G A and Baulcombe R S, "The effect of processing stresses on residual degradation in long-lived GaAIAs lasers", App Phys Letts, 34, pp 647-649, 1979.

4. Jannsen A P, "Reliability studies on packaged single mode 1300nm laser for long haul optical communication", Proc Semiconductor International Birmingham, 1983.

5. Hakki B W, Fraley P E and Eltringham T F, "1.3um laser reliability determination for submarine cable systems", AT&T Technical Journal, 64, No 3, pp 771-808, 1985.

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6. Nakanyo Y, "Reliability of semiconductor lasers and detectors for undersea transmission systems", IEEE J on Selected Areas in Communications, SAC-2, No 6, pp 985-991, 1984.

7. Sim S P, Skeats A P, Taylor M R, Hockly M, Cooper D M, Nelson A W, Devlin W J and Regnault J C, "High reliability InGaAsP/InP buried heterostructure lasers grown entirely by atmospheric MOVPE", Proc. ECOC'88, pp 396-399, 1988.

8. Halliwell MAG, Lyons M H and Hill M J, "The interpretation of X-ray rocking curves from III-V semiconductor device structures", J Crystal Growth, 68, pp 523-531, 1984.

9. Rosiewicz A, Park C, Butler B, Jones C and Palin M, "Improvement of high reliability inverted rib-waveguide lasers by the observation of degradation mechanisms", Proc lEE, 132, Pt J, No 6, pp 319-324, 1985.

10. Hirao M, Mizuishi K and Nakamura M, "High reliability lasers for optical communications", IEEE J on Selected Areas in Communications, SAC-4, No 9, pp 1494-1500, 1986.

II. Fukuda M and Iwane G, "Degradation of active region in InGaAsP/lnP buried heterostructure lasers", J Appl Phys, 58, No 8, pp 2932-2936, 1985.

12. Chu S, Nakahara S, Twigg M, Koszi L, Flynn E, Chin A, Segner B and Johnston W, "Defect mechanisms in degradation of 1.3um wavelength channeled-substrate buried heterostructure lasers", J Appl Phys, 63, No 3, pp 611-623, 1988.

13. Fukuda M, Noguchi Y, Motosugi G, Nakano Y, Tsuzuki N and Fujita 0," Suppression of interface degradation in InGaAsP /InP buried heterostructure lasers", J Lightwave Technol, LT-5, No 12, pp 1778-1781, 1987.

14. Nash F, Sundburg W, Hartman R, Pawlik J, Ackerman D, Dutta N and Dixon R, "Implementation of the proposed reliability assurance strategy for an InGaAsP /InP planar mesa, buried heterostructure laser operating at 1.3um for use in submarine cable systems", AT&T Tech J, 64, pp 809-860, 1985.

15. Fukuda M, "Laser and LED reliability update", J Lightwave Technol, ~, No 10, pp 1488-1495, 1988.

16. Tatekura K, Niiro Y, "Reliability of new semiconductor devices for long-distance optical submarine-cable systems", IEEE Trans Rei, 37, No I, pp 3-13, 1988

17. Hirano R, Oomura E, Higuchi H, Sakakibara Y, Namizaki H, Susaki Wand Fujikawa K, "Position of the degradation and the improved structure for the buried crescent InGaAsP/InP (1.3um) lasers", Appl Phys Lett, 43, No 2, pp 187-189, 1983.

18. Rashid A A M, Murison R F, Haynes J D, Janssen A P, Stockton T E, and Henshall G D, "High reliability low threshold InGaAsP ridge waveguide lasers emitting at 1.3um", J of Optical Sensors, 2, No 4, pp 281-288, 1987.

19. Akiba S, Matsushima Y, Usami M and Utaka K, "Spectral behaviour of aged 1.55um lambda/4-shifted DFB lasers", Electron Lett, 23, No 7, pp 316-318, 1987.

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20. Fukuda M, Suzuki G, Motosugi G, Ikegami T and Yoshida J, "Degradation behaviour of buried heterostructure InGaAsP/InP distributed feedback lasers grown by liquid-phase epitaxy", J Appl Phys, M, No 2, pp 496-499, 1988.

21. Ettenberg M, Olsen G Hand Hawrylo F Z, "On the reliability of 1.3um InGaAsP/InP edge-emitting LEDs for optical-fiber communication", J Lightwave Technol, L T -2, No 6, pp 1016-1022, 1984.

22. Sim S P, Skeats A P, Skrimshire C P and Collins J V," Reliability testing of opto­electronic components", Br Telecom Technol J, ~, No 2, 1986.

23. Stokoe J C D, Putland P A and Sutherland R R, " A review of reliability evaluation techniques applied to InGaAs PIN photodiodes, Germanium APDs and InGaAS APDs", submitted to Quality and Reliability Engineering International.

24. Sutherland R R, Skrimshire C P and Robertson M J, "A reliability methodology applied to very high reliability InGaAs/InP PIN photodiodes", Br Telecom Technol J, 2, No I, pp 69-77, 1989.

25. Sim S P, "The reliability of silicon avalanche photodiodes for use in optical fibre transmission systems", IEEE Trans Electron Devices, ED-29, No 10, pp 1611-1616, 1982.

26. Sudo H and Suzuki M, "Surface degradation mechanism of InP /InGaAs APDs", J Lightwave Technol, §., No 10, pp 1496-1501, 1988.

27. Kaneda T, "The reliability of III-V avalanche photodiodes", Proc. Semiconductor Reliability; Advanced Workshop II, Nato International Exchange Program, 1989.

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Figure 1 TEM plan-view image of defect networks emanating from active layer side­walls of BH laser with lattice mismatch. «001) surface, [l10] direction side-walls)

Figure 2 TEM plan-view image of loop defects adjacent to active layer side-walls of IJH laser. «001) surface, [110] direction side-walls)

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Figure 3 1300nm MOVPE BH lasers life-tested at 80·C, 4mW per facet.

150

() 125 ° 0 co <ii 100 -< E

"E 75

~ 5 50 CJ

OJ > 25 :.§

0 0 1000 2000 3000 4000 5000 6000 7000

hours

Figure 4 Percentage increase in operating current for typical BH laser on life-test at 80·C, 4mW per facet (after burn-in).

1000

-g. OJ 100 (/) m

50 ~ CJ

.<::::

"E ~ 10 5 CJ

--- --- --- ----- -- -- --- - - _ .. -- -------- --~-:::

//,/,/'

1~ ______ ~ ____ ~~ ________ L-______ -L ______ ~

10 100 1000 10000 100000 1000000 hours

313

Figure 5 Changes in threshold currents (measured at 50·C) of 1550nm ridge waveguide lasers on lifetest at IOO·C.

-< E E

80

~ 60 5 CJ - ------ ------- -

~~=:-------

~ I I .c

~ ;5 40 ()

° o LO

20~_~ ____ ~ ____ -L ____ ~ ____ L-__ ~'

o 1000 2000 3000 time at 100°C, hours

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314

Figure 6 DFB laser transmitter module showing double spectral peak at high fibre output powers or at low temperatures.

spectrum at 1mW, 25°C 10

c:l 'C

.c;­'0; c 2 .!: -30 '3 c. '3 o lI! .0 -= -70~~------------L-------------~

1.504 1.514 1.524

spectrum at 1.25 mW, 25°C

10

c:l 'C

.c;­'0; c 2 c = -30 :J c. '3 o

'" .c -=

wavelength, I'm

-70~ ______________ ~ ____________ ~ 1.504 1.514

wavelength, I'm 1.524

Figure 7 DFB laser transmitter module showing excessive Fabry-Perot modes at Oee.

c:l 'C

-~ <J) c

.~

10

-70~ ________________ ~ __________________ ~

1500 1550 wavelength, nm

1600

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315

Figure 8 The effect of modulation on the spectrum of a DFB laser with a side-mode­suppression ratio of 29dB under CW operation.

CIl -0 >.

10

cw operation

f SMSR = 29dB

l .]5 -30 c .l!l .s

CIl -0

-70L-----------~----------~ 1 .544 1.554 1 .564

wavelength, I'm

modulated at 590 Mbitls

10

t

~ -30

SMSR = 16 dB t

c .l!l .s

-70~ ________ ~~=-________ ~ 1.5429 1 .5529 1 .5629

wavelength, I'm

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Figure 9 Changes in drive currents of DFB laser modules on lifetest at 50°C with ImW fibre output.

1.5

1.4

o 1.3

~ 1.2 C ~ 1 :; 1.

<J ~~;;:::::======== ill 1.0 > :§ 0.9

0.8

0.7 0 2500 5000 7500

time, hours 10000 12500 15000

Figure 10 Changes in light-output of edge-emitting LEDs (measured at 30°C, 100mA) on life-test at 100°C, lOOmA.

1.1

0.5 L..-___ ~ ___ .L__ ___ ..1_ ___ _'_ ___ ..J

o 2500 5000 7500 10000 12500 hours

Figure II Lifetimes of edge-emitting LEDs as a function of temperature. Failure is defined as a IdB drop in light-output at 30°C.

- all from same wafer

15 devices

~~ . . I

102 _--tempOC

175150 125 100 70 25

0.002 0.0025 0.003

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Figure 12(a) Cross-section through a mesa structure III- V PIN photodiode

p-electrode

n-electrode

solder d iebond -----:~tl;:;::;::;:;:;::;::;:;::;::;:;:;::;::;:;:;;:;:;:;:;~__r_

Figure 12 (b) Cross-section through a planar structure III-V PIN photodiode

silicon nitride passivation p-electrode

n Inp-=::~~~~~~~~~~~~l-__ n InGaAs - p + diffusion

n InP

n-electrode InP substrate

317

Figure 13 Dark currents (measured at 25°C) of mesa III-V PIN photodiodes on life-test at 70°C, 5V_

spec limit

« c

0.1 L-__ ----,'::-__ ----,-!-::-__ ----,.-::-':-: ___ ~ 1 1 0 1 00 1000 10000

time on stress, hours

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Figure 14 Dark currents (measured at 2S·C) of mesa III-V PIN photodiodes with organic passivation, on life-test at ISO·C, SV

« 1000 c C ~ :; u

100 -'" (;; "0

spec. limit - -- -- - - ----- - -- - - ------

1L-___ L-__ ~~ __ ~ ___ ~

1 10 100 1000 10000 time on stress, hours

Figure IS Dark currents (measured at 25·C) of planar III-V PIN photodiodes on life­test at 200·C, 5V.

104

spec limit

stress time, hours

Figure 16 Dark current (measured at 25·C, 90% Vbr) of III-V APDs on Iifetest at 200·C, 100uA.

600

« c 400 C ~ :::J U

-'" 200 (;; "0

spec limit

0 1

time on stress, hours

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Figure 17 Photo-response, under BOOnm illumination, of an APD which showed increased dark current during a life-test at 200·C.

microns

Figure 18 Photo-response, under 800nm illumination, of an APD which showed increased dark current during a life-test at 200·C.

« - 5.0

c ~ -5.5 ~ u

~ -6.0

microns

319

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CONSIDERATIONS ON THE DEGRADATION OF DFR LASERS

T. IKEGAMI, M. FUKUDA, AND M. SUZUKI NTT Opto-electronics Laboratories 3-1, Morinosato Wakamiva, Atsugi-shi, Kanagawa. 243-01 Japan

ABSTRACT. Reliability of recently developed 1. 3 pm and 1. 55 pm high power DFB lasers is investigated from the viewpoint of wear-out failure and random failure modes. The change in spectral characteristics during operation and the electric surge endurance level is also presented.

The failure modes are similar to those of FP lasers. The degradation speed mainly depends on the injected current density and is affected by BH interface degrad~tion. The median lifetime at 50°C is estimated to be greater than 10 hours for laser output powers of around 15 mW for 1.3 pm lasers and around 10 mW for 1.55 pm lasers. The random failure rate is also estimated to be less than 200 FITs. In addition. there is no dj~fference between the endurance level against electric surge of DFB and FP lasers and of lasing wavelengths of 1.3 pm and 1.55 pm. These results show that DFB lasers could operate at laser output powers of 10 mW even in practical optical transmission systems.

1. INTRODUCTION

The DFB laser has become one of the main optical sources used in optical fiber transmission systems and indispensable in recent high bit-rate or coherent systems. In the applicEtion of such lasers to transmission systems. reliability is a key factor and a great deal of research has been devoted to improving reliability.

Reliability study of DFB laser has started on thE: bases of Fabry-Perot (FP) laser reliability. though the ambiguitv for the reliability lay in the existance of corrugation grating in the vicinity of the active region. In several aging tests. there has been no evidence of a correlation between the existence of the grating and the physical device degradation and the reliability of DFB lasers is not different from that of FP laser [1] - [51.

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A. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 321-328. © 1990 Kluwer Academic Publishers.

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In addition to the physical device degradation, the reliability of the lasers is strongly dependent on the device characteristics such as current versus optical output power and its temperature dependence. For device characteristics, great progress has been made since DFB lasers were first developed. By these improvements of device characteristics and fabrication techniques related to the device structure, reliabiljty of DFB lasers has become gradually high. Good aging results have been reported at the relatively low optical output power of around 5 mW [2]­(4). Now long lifetimes even at output powers greater than 10 mW are possible for the recently developed lasers.

This paper presents recent reliability test results, especially of recently developed 1.3 pm and 1.55 pm DFB lasers under high power operation.

2. DFB LASERS

The 1.3 pm and 1.55 pm DFB lasers studied were of the conventional buried heterostructure (BH) type with a first-order grating on the InP substrate. The lasers were fabricated from liquid-phase epitaxial wafers using the cleavage process. The coupling parameter kL ranged from 0.7-1.0 where the cavity length L was about 300 pm and the stripe width and thickness were 1.5 pm and 0.1-0.15 p~, respectively. The front facets of these lasers were coated with an antireflecting film (1-3 %). After mounting on a heat sink, these lasers were packaged with dry nitrogen gas. The thermal resistance is about 40 oe/H.

The typical threshold current of these lasers is 15-25 rnA. The maximum laser output power is greater than 30 mW fro~ the front facet at room temperature. This high power operation results from optimizing the kL value, facet reflectivity. The side mode suppression ratio (SMSR) is over 35 dB even at optical output power of around 30 mW.

3. FAILURE MODES AND RELIABILITY

In general, semiconductor lasers fail in wear-out failure modes and random failure modes. In this section, our experimental studies of these two kinds of failure are described.

3.1 Hear-out Failure

Before the aging test, all lasers were subjected to screening tests under a constant current of 150 rnA at 70 0 e for 100 hours and a constant power of 10 mW at 50 0 e for 100 hours. No devices were rejected under the second step screening.

Results of long term aging tests for 1.55 pm DFB lasers operating at a constant output power of 10 mW from the front facet at 50 0 e are

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shown in Fig. 1. All lasers operated stably. The median lifetime obtained at each aging condition is shown in Fig. 2. The sample number tested was between 10 and 30 at each aging condition. The aging was 4800 hours for the 1.3 )1m lasers and 6500 hours for the 1.55 Jlm lasers. In the early stage of aging, the driving current increases linearly with time and then gradually tends to saturate after several thausands hours. The lifetime is defined as the time at which the driving current reaches 1.5 times its initial value and was estimated from a linear extrapolation.

~ 200

!z 150 UJ 0: 0: => U

(!) Z

> 50 a:: Cl

50'C, 10 mW APC 1.55 pm 30 Samples

O~-----L--__ ~~ ____ -L _____ ~~ o 1600 3200 4800 6400

AGING TIME (hr)

Figure 1. Results of long term aging tests for 1.55 Jlm DFB lasers operating at a constant output power of 10 mH at 50°C.

107r------------------------. (number of samples)

1.3]Jm,16mW iA / ~~/

"" (30).

1.55 Jim, 10 mW

(30) (3 a/ 1.3 Jim, 20 mW ......0 / /' (11) ~ P .f2'0)1.55]Jm,16mW

(6) _.JJ../ (201

t t t 50 40 30·C

3.0 3.2 3.4 3.6

1000/T (K-1 )

Figure 2. Median lifetimes of 1.3 Jlm and 1.55 pm DFB lasers and degradation rate of driving current I d , (Id(t)-Id(O))/Id(O)' t, under high power operation.

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Using the failure criterion mentioned previously and assuming a log-normal failure distribution for the devices tested, the median lifetime was caluculated and is shown in Fig. 2. Th~se lasers have long lifetimes and the median lifetime is greater than 10 hours under a constant output power even over 10 mW from the front facet.

The wear-out failure of BR type InGaAsP/InP DFB lasers mainly comes from degradation of the BR interface between the first growth-step layers (DR layers) and the second growth-step layers (burying layers) r 6 J, [7] , since the facet degradation (oxidation) is quite small and hardly affects the reliability of lasers even for output powers of around 15 mW. The degradation speed depends on the quality of the ER interface and the interface degradation is mainly enhanced by injected current. The activation energy of the interface degradation has been estimated to be around 0.5 eV [8]. This value agrees with that shown in Fig. 2. This suggests that these recently developed DFB lasers are also degraded by Ell interface degradation. Since the degradation speed of the lasers is governed by Bll interface degradation, 1.55 pm lasers are inferior to 1.3 pm lasers because the driving current for 1.55 pm laser is larger than that for 1.3 pm lasers under high temperature or high power operation.

3.2 Random FaHure

Random failure is mainly caused by the degradation such as bonding part and heat sink and the device operation stops suddenly or rapidly. Consequently, the random failure for DFE lasers is not different from that for FP lasers. To clarify the failure rate, 1000 FP lasers lasing at 1.3 pm have been tested under4a constant output power of 5 mYl at 10°C, 50°C, and 70°C for over 10 hours. The results aTe shown in Table 1.

TABLE 1. Random failure rate of Bll type FP lasers

Temperature Quantity Failures Device·hours

10 ·c 100 0 1.1 X 106

50 ·C BOO 0 1.0 X lOT

70 ·C 100 I 1.1 X 106

Totals 1000 I 1.2xlOT

Failure rate < 200 FITs

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7 There was one faiJure in l.2.xlO device hours (devi.ce number x aging time). By using an exponentia1_ (lj stributj on, the random failure rate is estimated to be less than 200 FITs with a margin.

The random failure rate is limited by tested device number and aging time, and much more field data are required to obtain reliabile esttnation.

3.3 Side Mode Suppression Ratio (SMSR) and Spectral Ljnewidth

From the viewpoint of svstem ~pplications, changes in the spectral characteristics such as S!1SR and spectral linewidth are important. The SHSR is defined as the intensHy ratio of the highest side mode to the J'lain mode and was greater than 35 dB before· nging. During aging, the SNSR do not change with keeping more than 35 dB. The center wavelength is elsa constimt throughout the aging.

Degradation of the spectral ljnewidth is a key factor in coherent optical transmission systems. Here, the change in spectral linewjdth during device degradation under accelerated aging test is discussed. 10 lasers were aged at a constant current of 200 rnA at 60°C. Typical change in spectral liTlewidth as a function of inverse power is shown in Fig. 3, 1;-,here paraneters are correspon(Hng to the increase in the threRhold current during aging.

60r-----------------------------,

N

~ 40

00 0.1 0.2 0.3 0.4

INVERSE POWER (mW-'j

Figure 3. Change in spectral U.newidth versus inverse power relation of one DFB laser.

Alth0ugh the lasing threshold current increases, the spectral linewidth in the low excited (power) region does not change. However, in the rebroadening region (and floor region), the linewidth increases or decreases as the threshold current increases. All lasers showed the same trend of change in spectral line~idth during degradation. The

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rebroadening and floor observed in spectral linewidth is mainly caused by inhomogeneity of optical field or injected carrier distribution, and the spatial hole burning effect (9]. On the contrary, the device degradation usually occurs inhomogeneously along the laser cavity. Thus, the degradation affects the distrbution of carrier density and optical field. This results in the increase or decrease in spectral linewidth at rebroadening region.

Any way, the device operation in the rebroadening region should be avoided to obtain the linewidth stability. Further investigation on linewidth stability, however, is needed for development coherent systems.

3.4 Surge endurance

Laser fails with wear-out or random failure modes during operation as described previously. In addition, in a practical system there is a possibility that the devices are degraded by an electrical surge.

Results of destructive surge tests are shown in Fig. 4 (a) and (b).

10 8 20 C( ~ > t- •• i5 • UJ 15 c:: 0 - % - ~

~ c:: • • ~ ::::l U 1.0 ~ 10 •• 0

• 1.55 JIm, DFB

~ c:: ~ o 1.3 JIm, FP 5 el.55pm,DFB c:: 01.3 )1m, FP 0 ~ LL. 0.1 CD 0

0.1 1.0 10 100 1000 1000

PULSE WIDTH (ps) PULSE WIDTH Ips)

(a) (b)

Fi.gure 4. Endurance levels of BH type 1. 55 pm DFB lasers and 1. 3 pm FP lasers against (a) forward su rge current and (b) reverse surge voltage (note: destructive test).

The results of 1.3 pm BH type FP lasers are also shown in the figure as a reference. In the forward surge current test, the current pulse amplitude was increased in 0.2 A/step and 50 pulses/step were applied to the laser while monitoring the lasing characteristics. For the reverse surge voltage test, the voltage pulse amplitude was increased in IV/step and 50 pulses/step were applied in a similar manner to the forward surge current case.

The endurance level against forward surge current gradually decreases as the pulse width increases and becomes constant at around 2

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A for pulse widths wider than 10 ps. The p-n junction is damaged, as reported in [10]. The trend for forward and reverse electrical surge is not different between 1.55 pm DFB lasers and 1.3 pm FP lasers. Therefore, it can be said that the influence of the grating on the surge endurance is negligible and the critical amplitude and the width of an electrical surge are the same for BH type DFB and FP lasers and for 1.3 pm and 1.55 pm lasers.

4. SUMMARY

The reliabi.lity of DFB lasers has become higher because of improvements in crystal growth and device fabrication technology. These improvements also allow the DFB laser to operate at higher output power. The reliability under the high power operation has been investigated systematically for the newly developed DFB lasers.

The median lifetime under ~n ambient temperature between 30°C and 50°C is estimated to be over 10 hours at around 15 mW for 1.3 pm and at around 10 mW for 1.55 pm. The random failure rate is also estimated to be less than 200 FITs. These lasers show extremely good reliability performance.

As to lamp characteristics, the failure modes are similar to those of FP lasers. The degradation speed mainly depends on the injected current density and is affected by BH interface degradation. In addition, there is no difference between the endurance level against electric surge of DFB and FP lasers and of lasing wavelengths of 1.3 pm and 1.55 pm.

Preliminary aging test shows that the spectrum behaviors are stable in the DFB lasers having stable "lamp" properties. However, discussion of margin for the stability is still under consideration.

Acknowledgment The authors would like to thank T. Nakanishi for his helpful

discussion.

References

1. Nakano, Y., Motosugi, G., Yoshikuni, Y., and Ikegami, T. (1983) 'Aging characteristics of InGaAsP/InP DFB lasers', Electron Lett. 19, 437-438.

2. Fukuda, M. Suzuki, M., Motosugi, G., Ikegami, T •• and Yoshida, J. (1988) 'Degradation behaviors of buried heterostructure InGaAsP/InP distributed feedback lasers grown by liquid-phase epitaxy'. J. Appl.

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328

Phys. 64, 496-499.

3. Wakabayashi, H., Akiba, S., Matsushita, Y., and Yamamoto, S. (1988) 'Reliability of ~/4-shifted DFB lasers fabricated on a mass-production basis', Electron. Lett. 24, 1175-1176.

4. Goodwin, A. R., Davis, I. G. A., Anslow, P. J., and Rashid, A. (1988) 'Reliability of DFB ridge waveguide lasers emitting at 1.55 pm in normal and overstress conditions', Conf. on Lasers and Electro-Optics (Anaheim, California), THM 50.

5. Shima, K., Yonetani, H., Kohno, K., Morimoto, M., Ushijima, I., Takada, T., and Shibata, T. (1988) 'High power 1.5-pm DFB laser diode for long haul optical transmission systems', 14th Europian Conf. Optical Corom. (Brighton, U.K.), 345-348.

6. Mizuishi, K., Sawai, M., Todoroki, S., Tsuji, S., Hirao, M., and Nakamura, M. (1983) 'Reliability of InGaAsP/lnP buried heterostructure 1.3 pm lasers' IEEE J. Quantum Electron., QE-19, 1294-1301.

7. Fukuda, M. and Iwane, G. (1985) 'Degradation of active region in InGaAsP/lnP buried heterostructure lasers', J. Appl. Phys. 58, 2932-2936.

8. Fukuda, M., Noguchi, Y., Motosugi, G., Nakano, Y., Tsuzuki, N., and Fujita, O. (1987) 'Suppression of interface degradation in InGaAsP/lnP buried heterostructure lasers', IEEE J. Lightwave Tech. LT-5, 1778-1781.

9. Yasaka, H., Fukuda, M., and Ikegami, T. (1988) 'Current tailoring for lowering linewidth floor', Electron Lett. 24, 760-762.

10. Ishikawa, H., Sugano, tf., and Imai, H. (1987) 'Reliability of DFB laser against surge current', 13th European Conf. Optical Comm. (Helsinki, Finland), 81-84.

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InP-BASED 4 X 4 OPTICAL SWITCH PACKAGE QUALIFICATION AND RELIABILITY

K. MIZUISHI, T. KATO, H. INOUE, and H. ISHIDA Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo 185, Japan

ABSTRACT. Wi th an or iginal f iber-coupl ing method, an InP-based 4 X 4 polarization-independent optical-switch array (OSA) module is fabri­cated. In packaging, precise alignment and secure attachment of the input/output fiber arrays to the OSA is essential. Presented here is a novel attachment method where the fiber array is inserted into a Si attachment containing a set of photolithographically defined pyramidal through-holes. Fluctuations in periodicity of the through-holes are within ±0.2 \lIII, which correspond to the accuracy of the photomask used. This results in the deviation of a coupling loss less than 0.2 dB for all four single-mode fibers aligned with an OSA chip. To ensure mecha­nical stability of the tapered fibers aligned with the through-holes, mechanical strength test and temperature agings are performed, with promising results. Fundamental characteristics for a complete module are also presented.

1. INTRODUCTION

Integrated optic packaging technology is essential for the successful deployment of optical devices in real systems. Presently, there is much interest in optical switch array (OSA) packages that require efficient coupl ing and time-saving methods for prElcise al ignment and secure at­tachment of several fibers to the ends of an OSA chip. To date, much effort has been concentrated on the efficient coupling of light from a single-mode fiber into a single-mode waveguide [1], [2]. However, an elusive problem is fiber-waveguide joint reliability, which strongly effect the insertion loss of the module.

As key components for future broadband communication systems, sev­eral nonblocking OSAs made of LiNb0 3 have been considered [3J-[5J. These devices have advantages of low crosstalk. low driving voltage. and low insertion loss. However, their drawbacks include size longer than 60 mm, strong polarization dependence, and wavelength sensi tivi ty. On the contrary, the InP-based OSA discussed in this paper exhibits polarization-independent switching characteristics, and a 4 X 4 OSA is only 8-mm long, making it sui table for large scale integration [6]. In general, insertion loss is caused by mode size mismatch, fiber­waveguide misal ignment. propagation loss, and Fresnel reflection. Due to the small size (5-um width by 1.5-um height) of the lnP-based OSA, precise fiber-alignment is essential.

329

A. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 329-342. © 1990 Kluwer Academic Publishers.

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This paper first discusses our original fiber-attachment method. This relatively time-saving method qual ifies as a packaging process sui table for precise al ignment of mul ti pIe fibers. Rei iabi I i ty tests performed are primarily concerned with mechanical and thermal stability of fiber-waveguide joints. Preliminary results obtained are encouraging for practical use of the fabricated module.

2. OPTICAL SWITCH MODULE FABRICATION

2.1 Optical Swi tch Array

A schematic view of the InP-based nonblocking 4 X 4 OSA is shown in Fig. 1. This was realized by monolithic integration of 16 single slip structure (S3) optical switch units [6J. The OSA was designed for 1.3-Urn wavelength. Each uni t is composed of one X-cross element and two Y-branches incorporating carrier-injection regions. Two Y-branch TIR optical switches were used in this S3 configuration to obtain a single mode, small, low-crosstalk switch unit. All waveguides were single­mode InGaAsP/InP ridge waveguides with 10· X-crossing angle and 5· Y­branching angle.

A schematic cross section and SEM photograph of the Y-branch re­gion in the S'I optical switch unit are shown in Fig. 2. The ridge wave­guide was 5-um wide and 1. 5-um thick, wi th an estimated mode spot size of (2.5 ±0.5) X (1.0 ±0.2) um. Details of the fabrication process have been published elsewhere [6J.

S3 (~ingle-~Iip 1lruclure) optical switch

Figure 1. Schematic view of the single-slip structure (S3) optical switch as a unit cell of an InP-based nonblocking 4 X 4 optical switch array.

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5~m

I' I I -Zn Clillusion

~=::;~~\~~~~i= InGaASP cap InP claG

InGQAsP wa"1'9uid ..

1 InP subslratr

F=========r- n .. sid .. lie-elrod.

.. . o

331

Figure 2. Schematic cross section and SEM photograph of a Y-branch re­gion of the SJ optical switch unit shown in figure 1.

160J.lm f. • • • • • • • • • • . . : . . . .. ... .... ... .. .

1+14---6.4mm--..... ·1

T 1.5mm -L

Figure 3. Photograph of the fabricated InP-based nonblocking 4 X 4 optical switch array.

A photograph of a fabricated nonblocking 4 X 4 OSA is shown In Fig. 3. To couple the single-mode fiber array, the waveguides are spaced 160 ±0.5 wn apart. The total device length is 8.1 mm, and the switching region length is around 6.4 mm. Since these lengths depend on waveguide spacing periodicity, they can be further reduced by shorten­ing the waveguide spacing in the switching region.

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332

2.2 Fiber-Array Attachment

A schematic view of the proposed fiber array !!ligned by Eyramidal through-holes (APT fiber array) is depicted in Fig. 4. Four tapered l'ibers were first located in the Si V-grooves, and then the entire fiber array was aligned to the OSA using a Si fiber attachment with truncated pyramidal through-holes. The fiber array tips of the hemi­spherical lenses were inserted into the through-holes. The single-mode fibers had a taper angle of 30 ±1° and a hemispherical lens radius of 15 ±2.5 urn. It should be noted that. in the final step for the pack­aged version performed at room temperature, the "overlapping" silicon chips [7], which also contained V-grooves (not shown in Fig. 4), were used to clamp the fiber-arrays using an epoxy adhesive heatproof to 100 "C.

OSA waveguide

Tapered fiber

V-grooved substrate

Figure 4. Schematic view of a fiber array aligned by pyramidal through­holes (APT fiber array) to OSA waveguides.

As shown in Fig. 5(a), the pyramidal through-holes were formed by anisotropic etching of a Si substrate using circular holes formed on a thermally oxidized Si (100) surface as a mask. Using a KOH etchant, the pyramidal shaped through-holes surrounded by (111) planes were formed, since the etching rate of the (111) plane is much slower than that of the other plane. The fabricated taper angles were 70.5·, and the through-holes were specified at 50 ±0.5 urn 2 at the truncated pyramid, as shown in Fig. 5(b). Since periodic positioning of fibers was deter­mined by a photolithographic process, less than ±0.5-urn preCISIon alignment was readily attained. Fluctuations in periodicity of the through-holes were wi thin ± 0.2 urn, which corresponded to the accuracy of the photomask used.

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(0)

Thermo! oxidization (1100OC)

Etching {50 'Cl KOH solution (t.Qwt%)

Thermo! oxidization (ll 00 "C)

Etching (60°C) KOH solution (1.0 wt%)

Si02 removal fR. T.)

HF.NH"F

333

(b)

Figure 5. (a) Fabrication process of pyramidal through-holes on a Si substrate. (b) Photographs of formed pyramidal through-holes.

This technique allowed the alignment of all fibers by adjusting only two fibers of the attachment. even if the fiber array had a two­dimensional structure; the other fibers were automatically aligned provided the array was properly fabricated. Furthermore, once the fiber attachment was installed in a package with the OSA, all fibers were aligned without additional adjustment, by inserting the tapered fiber tips into the pyramidal through-holes. Thus, manufacturing time can be minimized.

Shown in Fig. 6 is the dis tri but i on of coupl ing loss measured by inserting randomly chosen fibers one-by-one into the same through-hole. This indicates that less than ±O.5-um precision alignment is possible. In real use, fibers may be selected to be matched with the through­holes. Of course, this technique can also be successfully applied to the fabrication of laser-diode modules wi th fiber pigtails.

As illustrated in Fig. 6, the through-hole area of a fiber-Si at­tachment joint seems to be quite fragile. This is because only four points in the through-hole area are in contact wi th a fiber tip. To reinforce the mechanical strength, a new method was devised in which the Si surface was plated with Ni. The maximum mechanical strength of a Si through- hole was measured by pushing a fiber tip into the through­hole, until the Si contact area was destroyed.

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334

Displacement (}1m)

O.L 0.2 0 0.2 O.L 10~~~---r--~--~

~ n=20

R-l0}Jm

5

Coupling loss (d B)

Figure 6. Distribution of coupling loss measured by inserting randomly chosen fibers one-by-one into the same through-hole.

01 200 -..c g'

Calculated

'" Q.o .... V1

0 U 'c 0 ..c u Q.o ~

2 4 6 Ni-coating thickness(jJm)

Figure 7(a). Comparison of mechanical strength values between Si attach­ments wi th and without N i -coating. Sol id 1 ine is a calculated resul ts

based on Ni-layer deformation model.

Figure 7(a) compares the mechanical strength values of individual Si attachments, with and without Ni coating. The results show that Ni­coa ted (4-um th ick) sampl es are two orders of magni tude stronger than those without coating. It was found that this improvement was a result of the enlarged contact area caused by the deformation of the Ni layer. That is, the solid line in Fig. 7(a) is a calculated result assuming a Ni-Iayer deformation model. which well explains the experimental resul ts.

Shown in Fig. 7(b) are photographs of uncoated and Ni-coated Si­attachments subjected to the mechanical strength test. The uncoated sample was easily destroyed by 1 gf. while the Ni-coated sample suf­fered only a slight deformation of Ni-coating layer by 100 gf. Mechani­cal stress induced by a thermal expansion in the range of 25 to 100~ was estimated at 15 gf. Therefore, Ni-coated Si attachments are ex­pected to have a much higher mechanical stability.

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(a) uncoated (mechanical Strength41gfl

(bl Ni -Gooled (mechanicol slrenglh-l00gtl

Figure 7(b). Observations of uncoated and Ni-coated Si-attachments subjected to the mechanical strength test.

2.3 Fiber-Array Aligning and Attaching Method

335

A process of aligning and attaching the fiber-arrays to the OSA is shown in Fig. 8. As mentioned in Section 2.2, only two fibers need to be actively aligned to the corresponding waveguides.

First, a through-holed Si substrate and a V-grooved Si substrate were soldered (wi th In-Sn eutectic alloy) to a Kovar mount, called a "fiber mount". An OSA chip was also soldered to another Kovar mount, called an "OSA mount". These fiber mounts and OSA mount were roughly positioned and soldered to a Kovar plate. prior to the precision align­ment process.

While the solder layer on the Kovar plate was still molten, the fiber mounts and OSA mount were independently adjusted by microposi­tioners. In principle. the micropositioner for a fiber mount must be capable of six degrees of freedom. These adjustments were attained by repeated adjustments until maximum optical throughput power was found. Near field patterns of the output light from the facet of an OSA coup­led with the fiber array are shown in Fig. 9. Also shown are changes in normalized coupling efficiency (fiber-to-waveguide) with lateral ex. Y) and translational eZ) displacements relative to corresponding wave­guides. With these results. the deviation of a coupling loss was found to be less than 0.2 dB for all four single-mode fibers aligned with an OSA chip.

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336

(0) Alignment by micropositioners

(b) Mount assembly installed in package

Lid

<

(c) Reinsertion of fibers into package

Figure 8. Process of aligning and attaching fiber-arrays to OSA. y

zLx

¥' ~ 05 u ~

.~

~ ~ 0

-I.

® Fiber

'---'----'--'-------'--, -3 -2 -1 o

Lateral disploceml?nl x Ipml

10

Lateral displacement y I pml

10

a _'---_I_ ... --L--'_.L-~_'_----'--'

o 10 20 30 1.0 so Trc1nslolionol displacement l (J.lml

Figure 9. Photograph of I ight spots observed through four individual fibers, and changes in normalized coupling efficiency with X, Y and Z displacements.

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337

After obtaining peak power through the fiber-waveguide-fiber in process (a), the temperature was lowered below the eutectic temperature of the solder. When the solder solidified. the fibers were detached from the fiber moun ts, and, in process (b), the mount assembly was in­stalled in a package (15-mm wide, 10-mm high, 50-mm long). Then, the fibers were reinserted into the through-holes of the fiber mount via the holes on each side wall of the package (process (c)). Finally, the fiber-arrays were covered with the overlapping Si substrates. Figure 10 is a photograph of the complete module without a lid. One may notice that, in the above process, it is unnecessary to adjust mul tiple fibers in a package. This implys that the process is more productive and time­saving than the conventional ones, and makes it feasible to use a small package.

lOmm

Figure 10. Photograph of complete optical switch module without a lid.

3. OPTICAL SWITCH MODULE CHARACTERISTICS

To measure the fundamental switching and coupling characteristics of the fabricated module, 1.27-1.33-urn wavelength laser diodes were cou­pled into each fiber. The switching characteristics are shown in Fig. 11. Results indicate that the longer the wavelength of a switched sig­nal, the higher the swi tching current needed to maintain the same ext­inction ratio. At a 200-mA injection current, the extinction ratio reached 23.9 dB, and the minimum total insertion loss was 23.7 dB, in­cluding Fresnel reflection loss.

As shown in Table 1, a coupling loss through fiber-waveguide­fiber was calculated to be 2.8 dB, assuming a hemispherical lens radius of 15 urn, a waveguide fiber spacing of 25.5 um, and zero deviations in lateral and longitudinal waveguide fiber positioning. The calculation formula was based on reference [8J. With expected and measured values of total insertion loss, an excess loss was found to be less than 1.9 dB. This is a satisfactory figure compared to the results of one input and one output fiber precisely aligned with the conventional method.

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338

---:- 1.0 ::J o '::' 0.8

a.o 3 8. 0.6

1: gO.4 ..... ::J 0-'5 0.2 o

o 40 80 Injection

Electrode: En

120 current

160 (rnA)

200

Figure 11. Switching characteristics of a 4 X 4 optical switch module.

Table 1. Classification of insertion loss.

Propagation loss > 10 dB Scattering loss > 6 Fresnel reflection > 1.5 X 2 Coupling loss > 1.4 X 2

Total loss ~expected) > 21. 8 Total loss measured) > 23. 7

Excess loss < 1. 9

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339

4. RELIABILITY TESTS

4.1 Temperature Stress Tests

As mentioned previously. the OSA mount and fiber mount were soldered (In-Sn eu tect ic) to the Kovar plate. Epoxy adhes i ve was used only for the overlapping Si-substrate attachment used to clamp the fiber-array to the V-grooved Si substrate. Consequently. attention must first be paid to aging-induced changes in solder layer thickness. which would effect fiber-waveguide-fiber alignment.

The test sample configuration is shown in Fig. 12. along with its photograph. Two pieces of V-grooved Si substrate mount were separately soldered onto the Kovar plate so that the single-mode fibers (not shown ) on each mount were butt coupled together. Aging-induced deviations in coupling loss were periodically measured by monitoring fiber-fiber optical throughput. Results obtained for five samples during tempera­ture cycl ing through the range of - 45 to +- 80"C are shown in Fig. 13 (a). indicating a slight change in coupling efficiency with increased cycling. However. using a measurement accuracy of ±O.5 dB. critical deterioration is not apparent. The right-hand vertical axis shows cor­responding deviation in fiber-fiber alignment.

Kovar mount

Figure 12. Configuration of test sample subjected to temperature cycling.

OJ -0

V1 V1

co

COl o c .- :.= - Cl.. a :J -> 0 Q) u

0

3 2 1

D--1

-2 -3

1

Temp_ Cye! ing (-45~ .eo'C)

10 Cycle

100 1000

E ..3

Figure 13(a). Variations in coupling loss for test samples during temperature cycling test.

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340

Results of storage tests at 60 and 80"C are also shown In Fig. 13(b). with only a slight change in coupling loss with time. These results coincide with the reported data that a creep phenomenon in eutectic solder joints between optical components is not critical in a high reliability laser module [9]. [10].

10 100 1000 Storage time (hI

Figure 13(b). Variations in coupl ing loss for test samples during high­temperature storage tests.

4.2 High-Temperature Storage Test

The difference in thermal expansion coefficients between components assembled in a package is a primary cause of mechanical strain. Since a crystal fiber has the lowest thermal expansion coefficient (3.5 X 10- 7

lIdegree). care must be taken to absorb mechanical strain in the axial direction of the fiber. For this. the section of fiber inside the pack­age was slightly bent as a means of absorbing mechanical strain (see Fig. 10).

As an in i tial temperature storage test condi tion. temperature character is tic (5 - 80 'C) of tota 1 insert ion loss was measured for a complete module. and the result is shown in Fig. 14. Deviations were found to be within ±1 dB. The result of a 60"C storage test is shown in Fig. 15. indicating a monotonic change in coupling loss with a rate higher than those shown in Fig. 13(b).

3 2

CD 1 .:E? • c a • . 2 • •• • • • -0 -1 • . ~

-2 0

-3 a 50 100

Temperature (oGI

Figure 14. Temperature dependence of total insertion los for the module.

Page 344: Semiconductor Device Reliability

co "0

U'l U'l

c:~

c:0\ .2 :§ -- a.. a ::J .s; 0 III u 0

3 2 1 0

-1

-2

-d 1 10

Storage time (h)

60 OC

100

341

Figure 15. Variation in total insertion loss of the module during 60\: storage tes t.

To gain more insight into the above results. it would necessitate to investigate the reliability of an optical switch itself. Hence. the present study has not yet reached a final conclusion because of a lack of systematic experiments concerning distinguishable degradation modes of the entire module. However. we believe that the preliminary data described so far suggest the absence of cri tical deterioration in the modules developed. which is encouraging for their practical use.

5. CONCLUSION

A novel fiber-coupling method was propos,ed for the fabrication of a module composed of an InP-based 4 X 4 polarization-independent optical switch array (OSA) aligned with single-mode fiber arrays. Fundamental characteristics of a complete module and several aspects on reliability were descr i bed.

This relatively time-saving method was found to be applicable to efficient fiber-waveguide coupling in single mode with an excess loss of less than 2 dB for a packaged vers ion. Deviations in coupling loss were controlled within ±O.2 dB for all 4 single-mode fibers.

To ensure improved mechanical stability of the fiber-waveguide joint and to examine thermal stability of the solder as adhesive for key components. temperature eye ling (- 45 - + 8 O\:) and high tempera­ture (60 and 80\:) storage tests were conducted. with promising resul ts.

Finally. we believe that the fiber-array attachment. which can align a number of fibers by truncated pyramidal through-holes. will be utilized for future large-scale optical lCs.

ACKNOWLEDGMENT

The authors are grateful to Z. Tsutsumi and Dr. M. Maeda for their en­couragement throughout this work. They wish to express their apprecia­tion to F. Yuuki for his active assistance in the experiment.

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REFERENCES

1. Raner, O. G. (1981) 'Single-mode fiber-to-channel waveguide coupl ing,' J. Opt. Commun., 2, 122-127.

2. Voges, E. (1981) 'Coupling techniques: Prism, grating and end fire coupl ing,' in S. Martellucci and A. N. Chester (eds.), Integrated

Optics: Physics and Applications, Plenum, New York, pp. 323-333. 3. Bogert, G. A., Murphy, E. J., and Ku R. T. (1986) 'Low crosstalk 4

X 4 Ti:LiNb0 3 optical switch with permanently attached polarization maintaining fiber array.' J. Lightwave Technol., LT-4, 1542-1545.

4. Neyer, A •• Mevenkamp, W., and Kretchmann, B. (1986) • Nonblocking 4 X 4 switch array with sixteen X-switches in Ti :LiNb03,' in Proc. IGWO '86, Atlanta, GA, paper WAA2.

5. Granstrand, P., Stoltz, B., Thylen, L., Bergvall, K .• Doeldissen. W., Heinrich. H., and Hoffmann. D. (1986) 'Strictly nonblocking 8X 8 integrated optical switch matrix,' Electron. Lett., 22, 816-818.

6. Inoue, H., Nakamura, H., Morosawa, K., Sasaki, Y., Katsuyama, T., and Chinone, N. (1988) 'An 8 mm length nonblocking 4 X 4 optical swi tch array,' IEEE J. Select. Areas Commun., SAS-6, 1262-1266.

7. Murphy, E. J. and Rice, T. C. (1986) 'Self-al ignment technique for fiber attachment to guided wave devices,' IEEE J. Quantum Electron., QE-22, 928-932.

8. Sakai, J.and Kimura, T. (1980) 'Design of a miniature lens for semi­conductor laser to single-mode fiber coupling,' IEEE J. Quantum

Electron., QE-16, 1059-1066. 9. Mizuishi, K. and Adachi, E., 'l. 3-um wavelength laser diode module,'

unpublished. 10. Mitomi 0., Nozawa T., and Kawano K. (1984) 'Effect of solder creep

on optical component reliability,' in Proc. 1st IEEE CHMT Symp., Tokyo, 198-204.

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MODELLING THE EFFECTS OF DEGRADATION ON THE SPECTRAL STABILITY OF DISTRIBUTED FEEDBACK LASERS

A.R. GOODWIN, J.E.A. WHITEAWAY STC Technology Ltd London Road Harlow, Essex CMl7 9NA United Kingdom

R.H. MURPHY STC Submarine Systems Ltd Christchurch Way Greenwich London SEIO OAG United Kingdom

ABSTRACT. Modelling is used to simUlate lhe effects of degradation on lhe drive current and spectral characteristics of DFB lasers. As an example, calculations are presented of the .effecls on uniform grating and ~/4 phase shift DFB lasers of changes made in localised injected current density and in lifetime of carriers for linear non-radiative recombination. The aim of the work is to evaluate modelling as a technique for comparing the susceptibility of different laser designs to spectral instability, with a view to selecting designs of lhe greatest stability.

1. INTRODUCTION

For error-free operation of optical links using dispersive fibre it is essential that the laser source emits in a single frequency mode and never hops or changes to another frequency during ils operational life.

Mode hopping due to degradation is a new reliability hazard peculiar to single frequency lasers. Degradation has been reduced to low levels by worldwide investigations of reliability and several laboratories are now predicting 1 ,2 operating times in excess of 25 years on Fabry Perot lasers. Nevertheless, some residual chip degradation is expecled.

Degradation in general may be eilher uniform or localised in some part of the chip. Residual chip degradation will change the injected carrier density, which will perturb the eff.~ctive refractive index and aller the optical pitch of the grating. For localised degradation this in turn will inlroduce an additional phase shifl inlo lhe original laser design which if sufficiently large will cause mode hopping.

DFB lasers have been developed3and lifetest results are good. The spectra, side mode suppression and drive current show good stability

343

11. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 343-352. @ 1990 Kluwer Academic Publishers.

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344

even at l2S oC. Assurance of spectral reliability at end of life is now needed. The objective of the present work is to evaluale computer modelling to simulate degradation as a means of enhancing information on the spectral behaviour of lasers at end of life. Experimentally, this can be achieved by overstressing the lasers to cause degradalion and then measuring the speclra3 . Additionally, lhe degradation can be theoretically modelled by solving for the speclral modes of a DFB laser wilh deliberate changes made to recombination parameters to simUlate degradation. The purpose of this paper is lo describe a theoretical model to do this. The model is illustrated by reference to two examples of 1.55 ~ DFB lasers designed for optical fibre communications, one using a uniform grating and the olher a ~/4 phase shift grating.

The uniform graling laser with perfecl anti-reflection coated facets is theoretically degenerate al threshold, lasing in two modes located just oulside the two edges of lhe stopband. Asymmetric facel reflectivity in general results in the seleclion of one of lhese modes. Useful yields of single frequency lasers can be achieved using one as-cleaved facet and one anti-refleclion coaled facel. The phase of the facet reflection relative to the grating ~ is critical. f'igure l(a) shows the spontaneous emission speclrum of such a uniform DFB laser just above threshold. Single mode seleclion is not strong.

f'or 60 <I> 1400 , the laser emi ts single frequency in mode c. Outside these limits adjacent modes are also exciled and the oulput is no longer single frequency. The lasing and spontaneous modes and threshold current density values are illustrated as a function of <I> in Figures 2(a) & (b). The value of ~ chosen for this example is 1000 , which is close to optimum. In praclice, facet cleaving will give randomly distributed values of ~ from chip to chip and frequency selection will be weaker than for ~ ~ 1000 . The example using <I> - 1000 is therefore a best case.

In contrast the ~/4 phase shift grating DFB laser with two anti-reflecting facets emits in only one mode (0) centred at the Bragg wavelength (Figure l(b».

A priori the ~/4 phase shifl DFB is expected to be superior to the uniform laser in resisting mode hops and wavelength changes due to degradation. This modelling aims to evaluate this expectation quanti tati vely.

2. M~;THOD

Modelling of non-uniformly injected DFB lasers is carded out. as follows. The model used is described elsewhere 4 and consist.s of three nested loops which iterate the longit.udinal carrier, mode intensity and refractive index distributions to reach a self-consistent solution. The model takes account of multimode operation and longitUdinal mode spalial hole burning.

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345

The linear, bi-molecular and Au~er recombinalion coefficienls can be specified as well as the gain-carrier densily relalionship. These values were laken from lhe lileralures. The laser lenglh is divided inlo seclions so thal designs wilh non-uniform current densily, and carrier recombination or gain-carrier density characteristics can be delermined.

To demonstrate the technique, the examples are worked for two arbilrarily selecled lypes of degradation mechanism, one uniform and one localised.

3. R£o:SULTS

3.1 Uniform non radiative recombination

Uniform or non-localised degradation was simulated by inlroducing linear non- radiative carrier recombination at all points in the active re~ion. Values of non-radiative recombination lifetime ranging from 1 to 5 ns were used in t.he t.wo examples of laser design. The uniform grating DrB laser design selected used a first-order ~rating of repeat distance 0.24 ).Ul\, coupling fact.or K of 40 cm- 1 and cavity length 300 ).Ul\ and the value of the facet phase was 1000 . This value is close to the optimumG for greatest spectral stability. The ~/4 phase shift grating design selected used a first-order grating of repeat di~~tance 0.24 ).Ul\, coupling faclor K of 70 cm- 1 and cavity len~lh of 380 ~m.

It was found that reducing the non-radialive carrier recombination lifetime value to 1 ns caused the threshold to increase lo respeclively 3.4 and 3.5 times the value without non-radiative l"ecomb i na lion for the case of t.he un i form gra l.i ng DF'S laGer (Figure 3(a» and ~/4 phase shift DrB (Figure 3(b». Despite these lar~e threshold increases neither example showed any sign of mode hopping. This is reassuring because degradation of this lype would therefore be flagged by the rising threshold current long before there was any risk of mode hopping.

3.2 Localised injected current loss

Part of the laser cavity was driven al 50~ of the nominal current density at which the rest of the cavity was driven. The parlially pumped region length ~ was located al the reflecling facel for the uniform grating example since this location is the most crilical. The spontaneous side modes (dotted) and laser modes (full line) were then calculated as functions of ~ and J and the results are plotted in Figure 4(a) for J • 4000 A cm- 2 (corresponding to 1.4 x threshold at ~ = 0). For small values of ~ the laser emits in the mode on the long wavelength side of the stopband (c). ¥'or ~ >40 ).Ul\ it hops to the mode on t.he short wavelenglh side of the st.opband (b).

The ~/4 graling laser was partially pumped in the centre section since this design is more critical t.o partial pumping in t.he centre than at the ends. The spontaneous side modes are plotted as a

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346

function of ~ for J ~ 3500 A cm- 2 in Figure 4(b). For values of ~ <95 ~ the laser spectrum emits in mode (0). For ~ >95 ~ it emits in mode (-1) on the short wavelength side of the stopband. The effect of this partial pumping on laser threshold is shown in Figure 4(c). In the case of the ~/4 phase shifted grating DFB laser the value of Jt increased by 50~ at the critical value of ~ for mode hopping whereas the comparable figure for the uniform grating DFB laser is 6~. The value of ~ at which mode hopping occurred is dependent on the value of J. In the case of the ~/4 phase shift design the value reduced from 95 lIJII at 3500 A cm- 2 to 50 lIJII at 6000 A cm- 2 •

In the case of the uniform grating design the value reduced from 40 lIJII at 4000 A cm- 2 to 30 lIJII at 3200 A cm- 2 . The performance of the uniform grating DFB example is a best case because the value of the reflector to grating phase ~ was set at the optimum value. In practice lasers with a range of values of ~ can be expected to meet selection criteria, but they will be less resistant to mode hopping.

This type of degradation, if present, would be a serious hazard to system operation because mode hopping can occur with litLle threshold increase to flag that degradation has occurred.

The results are summarised in Table 1.

4. CONCLUSIONS

The specific values of partial pumped length calculated should be treated with caution since values had to be assumed for a number of modelling parameters. However, the general conclusions can be drawn that uniform degradation is much less likely to cause mode hopping than localised degradation. The modelling also confirms that, overall, the ~/4 phase-shiH grating DFB laser is likely to resist mode hopping betLer than the uniform grating DFB laser.

The work demonstrates that modelling of degradation is a powerful technique for comparing the susceptibility of different DFB laser designs to mode hopping caused by degradation, leading to enhanced knowledge of degradation hazards in lasers. Laser designs can be screened for susceptibility to mode hopping and designs of the greatest resistance lo mode hopping due to degradation selected, resulting in improved confidence that reliability targets can be met.

ACKNOWL~DGEKENTS

The authors acknowledge the valuable contribution to this paper made by Dr. G.H.B. Thompson of STL through technical discussions, and thank the Directors of STL for permission to publish.

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REFI!:RENCES

1. Goodwin, A.R., Davies, I.G.A., Gibb, R.M. and Murphy, R.H. (1988) 'The design and realisation of a high reliability semiconductor laser for single-·mode fibre optic conununication links', IEEE J. Lightwave Technology, Vol. 6, No.9, pp. 1428-1435.

2. Hakki, B.W., Fraley, P.E. and Ettringham, T.F. (1985) '1.3 ~ laser reliability determination for submarine cable systems', Bell Systems Technical Journal, March 1985, pp. 771-807.

3. Davies, I.G.A., Goodwin, A.R., Rashid, A., Murphy, R.H. and stockton, T. (1988) 'Reliability of distributed feedback lasers emitting at 1.55 ~', Proc. CLEO 88, Anaheim, IEEE.

4. Whiteaway, J.E.A., Thompson, G.B.H., Collar, A.J. and Armistead, C.J. (1987) 'The design and assessment of ~/4 phase shifted DFB laser structures'. Accepted for June 1989 IEEE J. Quantum Electronics special issue for 11th IEEE International Semiconductor Laser Conference.

5. Amann, M-C (1987) 'Polarisation control in ridge waveguide laser diode', App. Phys. Lett. Vol. 50, No. 16, pp. 1038-1040, April 1987.

6. Kojima, K., Kyuma, K., Nakayama, T. (1985) 'Analysis of the spectral linewidth of distributed feedback laser diodes', IEEE J. Lightwave Technology LT-3, p. 1048.

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TABLE 1. The effect of uniform and localised degradation on the spectra and threshold of D'B lasers

Laser Design

Uniform

(best case)

K2. 1.2

).../4 grating

K2. = 2.7

Parameter

Spectra

Threshold Current

Spectra

Threshold Current

Degradation Mechanism

Uniform Non-radi ati ve Recombination

Stable Stable Stable

Large Increase

Stable Stable Stable

Large Increase

Localised Partial Injection

Stable, then hops

51.

Stable, then hops

Significant Increase

Page 352: Semiconductor Device Reliability

103 103.---------~---------r

C

102 b Relative

emission intensity 101

a d

(a) l()O

10-1 1.562 1.566 1.570

Wavelength/microns

Relative emission intensity

(b)

102

101

1.564 1.568 Wavelength/microns

Fig. I Simulated spontaneous emission spectra just above threshold from uniform and phase- shifted orB lasers: (a) Uniform DFB with one anti-reflectin~ facet and one as-cleaved facet with grating phase of 1000 ;

(b) ~/4 phase shifL DFB laser with two anti-reflection coated facets

InGaAsP 4000 A cm-2

• • • • •

1.568 • d • (!) • • 0 • •

0

0 c

<;) A (flm) 1.566 0

• • o • •

0 b • (!)

• • • • •

1.564 •

t a • • • Selected

1.562L---------~--------~-----------L----------L------o 40 80 120 160

Grating/facet phase ",0

Fig. 2(a) Emission wavelength of uniform grating laser with one as-·cleaved facet and one arc facet (K ~ 40 cm· l , 2. = 300 lUll). Open circles indicate laser action

349

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350

3500

J threshold (A cm-2)

2500

c

o 40 80

c c c,b

120

Gratinglfacet phase",·

b

160 200·

Fig_ 2(b) Threshold current density vs grating/facet phase of uniform grating DFB laser, one as-cleaved, one arc facet (K = 40 cm- l , ~ = 300 ~, 1.5 ~)

10,000

J threshold (A cm-2)

6000

2000

\ \ \ \

r=oo

ModeC No hops to 11,000 Acm·2

2 3 4 5

«nsec)

---------

6 7 8

Fig. 3(a) Degradation of threshold current due to reduction of linear carrier recombination time, for uniform grating DFB laser (K = 40 cm- l , ~ .~ 300 ~, with one facet are, one as-cleaved, phase 1000 )

b

9

Page 354: Semiconductor Device Reliability

J threshold (Acm-2

10,000

6000

2000 <=00

2 3 4 5 6 7

< (nsec)

Fig_ 3(b) Degradation of threshold current due to reduction of linear carrier recombination lifetime for k/4 phase-shift DFB laser (K ~ 70 em-I, i = 380 ~)

90

~------------------------------------80

c 701----------------------------------60

I!.A (AO) 50 !?-----------------------------

a ------ - -------------------- ------. 40

30

20+------.-------.------~------r_----~------~ o 20 40 60 80 100 120

Length partially pumped£p (ILm)

~'ig_ 4(a) Wavelength shift due to partial pumping for a uniform grating DFB laser (part 2000 A cm- 2 , rest 4000 A cm- 2 )

351

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352

90 +1------------ ---------___ _

80

70 ~o~-----------------------------------

60

:~----------------------50 -------------- --------------40 ----------------------------30

20

o 20 40 60 80 100 120 Length partially pumped fp (/Lm)

l"ig. 4(b) Wavelength shifL due to partial pumping for a \./4 phase shifted DFB laser (part 1750 A cm- 2 , rest 3500 A cm-2 )

3500

MOde~ Hop

I -~---

3000

2500

Mode

."./

Hop ...

l _.-'."..".. .... ,..-

20001-------.-------,------.-------.-------.------,-20 40 60 80 100 120

Length partially pumped Ip. /Lm

Fig. 4(c) Threshold current density vs length partially driven for uniform and \./4 phase shifted lasers

Page 356: Semiconductor Device Reliability

OPTOELECTRONIC COMPONENT RELIABILITY AND FAILURE ANALYSIS

P. MONTANGERO CSELT, Centro Studi e Laboratori Telecomunicazioni SpA Via G. Reiss Romoli 274 10148 Torino ITALY

ABSTRACT. This paper examines the reliability of optoeletronic devices discussing the two main aspects, the identification of the degradation mechanisms and the evaluation of the mean life. A general classification of the main degradation mechanisms, per class of component, is reported illustrating the correlation with the stresses that may be causing them and the device parameters drifts. An overview of the specific failure analysis techniques is given, and a comparison between SEM techniques and optical techniques is presented.

1. INTRODUCTION

Optoeletronic device reliability is an issue of great importance since traditional communication systems are progressively replaced by optical fibre ones. The features of these systems are strictly connected to the performance and reliability of the optoelectronic devices they contain.

Optoelectronic devices are critical, from the reliability point of view, because the semiconductor materials they are made are newer and less studied than silicon, and because the related technology is still developing and not yet stabilized [1].

This paper discusses the reliability of lasers and photodetectors giving a general classification of the main degradation mechanisms per class of component, an est i mate of thei r expected mean 1 i fe and an overview of specific failure analysis techniques.

2. LASER DEGRADATION MECHANISMS

Laser technology has meant a continuous growth in the number of different structures which are increasingly more sophisticated. Some of them are manufactured by the one company, which makes an overall reliability study quite difficult. In fact, degradation mechanisms may be specific either to the structure or to the manufacturing process of a given company. Therefore we focus on general degradation mechanisms shared by all lasers, whatever the details of their technological

353

A. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 353-362. @ 1990 Kluwer Academic Publishers.

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354

process. Degradation processes are studied because of their direct or

indirect effect on the drift of electro-optic parameters. Understanding these processes is the first necessary step to improve re 1 i abi 1 i ty, modifying device design or process.

The degradation mechanisms we consider can be grouped in five classes:

formation/development of defective areas in the semiconductor material (laser and Led) mirror damage (for Fabry-Perot laser) die-attach deterioration (mainly for laser) gold diffusion within semiconductors (laser and Led) electrical transient damage. A1GaAs/GaAs and InGaAsP/InP emitter devices have different

criticalities and will be therefore listed in different groups.

2.1 Formation and development of defective areas

The presence of defects in the active area is undoubtedly one of the main causes behind parameter drift or emitter manfunctioning. These areas may be a 1 ready present in the substrate or form dur i ng the epitaxial growth of the structure or during the manufacturing of the device. Lastly they may also develop following thermoelectric stimulations in the course of the operative life of the device [2].

Although not exhaustive, the following table summarises the main defects for A1GaAs/GaAs and InGaAsP/InP components, as well as giving the origin and the impact on the electro-optical parameters of the device.

DEFECT ORIGIN A1GaAs/GaAs Threading Cl imbing dislocations Substrate 11 reduced

dislocation Dislocation Climbing networks Process stress 11 reduced

Operat ive 1 He stress

Dislocation LEC**-single clusters crystal no Misfit LPE*-mismatch dislocations epi/substrate no

Edge growth In-inclusions LPE-melt

carry-over no

liquid phase epitaxy * LPE ** LEC liquid encapsulation Czochralski

InGaAsP/InP

no effect

no effect

11 reduced Jth increase 11 reaucea Jth increase

11 reduced Shunt,unsta-ble I-V P-I

The first two defects are typical of GaAs based components and will not be treated more in depth.

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355

Dislocation cluster

The InP substrate qual ity has been improved tremendously in recent years, nonetheless some problem may still be due to defects present in the substrate. InP is universally grown using the LEC technique with boron oxide as the encapsulant. If the boron oxide is not thermally treated, water inside it may react with the InP melt to produce gaseous products. The stress generated by these gases is released creating dislocation loops along the <110> directions [3]. These clusters may be up to 50-100 Mm in size.

When the heterostructure is grown on substrates with one or more clusters, dislocations may cross several layers and hillocks may be found up to the surface.

Misfit dislocations

The growth of heterostructures becomes possible when the lattice parameters of two bordering layers are equal [4]. Thanks to the thickness of the quaternary layer (0.1-0.2 Mm), the quaternary InP mi smatch is usua 11 y not cr it ica 1 for standard lasers wi th LPE grown material. However, if 'edge growth" is present, local significant composition variations are possible. This means higher interface mismatching with subsequent formation of edge dislocations along the <110> crystallographic directions. These lines follow the characteristic pattern with parallel lines often at an equal distance from each other [5].

Figures 1 and 2 illustrate a case of misfit dislocation formation in a InGaAsP/lnP laser. Figure 1 shows the p-side of the laser after metal removal. Figure 2 shows an EBIC of the surface where the pattern of parallel lines described above can be observed.

In terms of devi ce performance, the presence of dislocations has meant increasing threshold current in conditions and greater sensitivity to temperature as shown values of To (43 K).

misfit pulsed

by low

GaAs devices are virtually dislocation misfit-free because of the smaller degree of lattice parameter variability of the A1GaAs ternary composition. Moreover the lattice thermal expansion parameter is only slightly different from that of GaAs.

Melt-carryover: In-rich inclusions

To perform the LPE growth of the heterostructure the substrate is carried over from one well to the other in the crucible. When the separating septum is scratched Indium residues may be left on the surface and then segregated within subsequently grown layers. This phenomenon is kwown as "melt carry-over" [6]. These inclusions may act as current preferential paths.

2.2 Mirror damage

Facet reflectivity is important as far as reliability is concerned to

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356

ensure a stable performance over a period of time, especially for Fabry Perot lasers. For this reason it is imperative to preserve the physical integrity of the mirrors.

Fabry-Perot laser mirrors are usually obtained by simply cleaving the semiconductor crystal along specific crystallographic planes. The surface thus obtained is a "defect" from a crystallographic point of view because the surface atoms present a series of dang1 ing bonds. These may associate with impurities and generate a high density of surface states [7].

A1GaAs/GaAs lasers are more sensitive than InGaAsP/InP lasers to degradation of the mirrors. The higher thermal conductivity, the lower surface recombination rate and the lower energy of the photons in InGaAsP/InP Lasers may explain this situation. In A1GaAs/GaAs lasers the problem is overcome coating the facets with protective dielectric layers.

In InGaAsP/InP lasers, mirror damage is often due to a wrong In operation (excessive forward current or temperature) or to electrical transients.

2.3 Die-attach deterioration

Indium is often used as a die-attach because of its low melting temperature (156°C) which means the chip would not suffer any thermal stress. Currently this choice is being questioned especially as indium tends to form intermetallic compounds with gold employed both as a coating for the copper heat-sink and in the metallization.

The In-Au interdiffusion with formation of voids and In-Au intermetal1ic phases is held to be responsible for the increased thermal resistance and has also been observed in devices which operate at room temperature. It is evident that an increase in thermal resistance 'will produce an increase in junction temperature and an increase in threshold current, increasing the operative stress of the device.

Indium is also responsible for another failure mechanism, other than that mentioned above. It causes sudden irreparable faults [8] due to indium whisker growth. This growth is caused by indium thermo­migration on the surface of the laser mirrors. In the standard p-side down assembly the indium whiskers can reach the active layer and short­circuit the p-n junction.

A solution to these problems is to use different die-attach as Au/Sn or Sn/Pb. Another solution is to mount the chip laser up-side up" ("epy-up"), and this is possible with low threshold current devices.

2.4 Gold diffusion from p-contact

Metallization, particularly p-side, is a critical point in emitters and is important in terms of technology. The geometry of the contact requires it to be small (the size of the contact stripe being from 2 to 10 ~m) to confine current in a satisfactory way while offering low contact resistivity (10-5+1O-6 Ohm cm2) to minimize heat dissipation due to the Joule effect. This is why metallizations have to date always

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been gold based, i.e. CrAu, AuZnAu, TiAu and so on. However though gold means a good contact from an electrical point

of view, it has been identified as a potential cause of emitter degradation due to the high diffusion coefficient it has in III-V materials (0=10- 16 cm2 sec- 1 for GaAs). This means that in working conditions when there is a current density of the order of KAcm- 2 it may migrate to the active layer, only a few microns from the contact, by thermo-electromigration, producing localized metallic precipitates. These will first of all reduce radiative efficiency.

Diffusion is not just a uniform process and it may take place along particular directions when the crystal shows defects such as dislocations. In these cases the crystallographic defect acts as a preferential channel where gold may diffuse more rapidly. Accumulation and precipitation (decoration of dislocations) may also take place. Figure 3 for instance shows an EBIC images from the p side of a degraded laser [9].

Gold diffusion takes place regardless of whether the emitter is a Led or a laser, which is why the problem has to tackled and overcome rapidly. Current trends favour multilayer metallizations such as TiPtAu where Pt acts as blocking layer thus preventing gold diffusion. In this instance there are Schottky contacts and a Zn diffusion in the top layer in contact with the metallization is carried out.

2.5 Electrical transient damage

ESD and surge damages have always been considered one of the possible causes of laser failures but only recently more attention to these problems have been paid. The trend toward low threshold current and fast laser devices has meant a growth of different structures with reduced active area and very small RC figures. This has also meant a reduction in the amount of spike current: they can withstand and a greater susceptivity to ESD phenomena.

Damages from spikes or ESD can cause either sudden cathastrophic device fai lure, eletro-optic parameter shifts or device weaknesses. It is difficult to evidence the physical effects of such damages, because, generally, the interested areas are very small (for example a localized melted point or a localized leak in a junction) especially when the damage has not caused a complete failure.

All laser structures can suffer damages from electrical transients but the level they can withstand can be different. In particular buried structures confined with reverse biased junctions seem to be more affected by these problems.

3. QUANTITATIVE MEASUREMENT OF LASER RELIABILITY

It is always cri t ica 1 to predict device mean 1 ife, that is fa il ure rate, which is what users often wish to know. This is especially true for photoemitters where technology is sti 11 in a phase of rapid evolution and there are still few field data.

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Accelerated laboratory life tests are often the only source of information, though not altogether satisfactory: component overstressing can trigger degradation processes absent in normal operating conditions or viceversa other aspects present under these conditions - such as humidity, mechanical stress, etc - might not be considered.

To evaluate laser mean life it is necessary to: a) identify the one or more significant parameters; b) define a failure criterion, that is the maximum admissable

variation of one or more parameters c) have a population of devices that may be considered equivalent in

order to perform a statistical analysis of the test results. As far as transmission systems are concerned, a general

malfunctioning criterion can be defined as follows: "the inability" of the laser to supply the amount of stimulated power and/of the quality of the optical signal required to maintain an error rate below pre­established values, usually 10-9 bit/sec." Such a definition involved several parameters which vary in relation to degradation in device performance. These include the increase of threshold current, a decrease in differential quantum efficiency, the increase of leakage current, the triggering of higher order modes or variaHons in the front/back power ratio controlling the signal stability. This is why the parameters should be selected so that they do not require an excessive number of tests but shoul be able to describe the "good performance" of the device.

Now as a consequence of the first point we have to define a failure criterion. Usually threshold current is the first parameter to be checked and hence the first constraint one introduces is a limit to the amount it can be increased. However, its priority must not be taken for granted as L-I linearity in the working zone is just as important. However in this case a quantitative criterion is not easily introduced; for instance a qual itative criterion might be the absence of kinks. Another criterion could be the non-excitation of higher order modes.

With reference to point c) it is necessary to notice that often, the manufacturing processes are not sufficiently well establ ished to produce "equivalent" devices. Screening and purging will help to provide a better population uniformity. Anyway, when reliability requirements are very strict the followed approach is to assess each device in order to include their specific behaviour patterns. A 1 GaAs/GaAs 1 aser mean 1 ite has improved from the few hours of the early devices to 106 hours of the current devices. As far as InGaAsP/InP laser devices are concerned, we lack assessments based on long term field observations. However, 104 107 values have been given. The wide variance is due to both the marked diversification of structures and the fact that often the only available data comes from the manufacturers.

4. PHOTODETECTOR DEGRADATION MECHANISMS

Unlike laser, where malfunctioning may be attributed to the degradation of several electrical/optical characteristics, there is an general

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consensus for accepting the dark current as the one critical parameter for photodetectors. This is true whatever is the semiconductor material used (silicon, germanium or III-V), and the kind and structure they are. For this reason photodetector reliability focuses on the physical phenomena responsible for dark current and on the factors that can cause this parameter to increase during the operative 1 ite of the device.

Dark current comprises several components and we expect the component which increase the most to be different according to the structure.

A brief summary might read as follows:

STRUCTURE COMPONENT FAILURE Planar I bulk Junction diffused degradation APD/Pin Localized

breakdown (microplasmas)

Mesa I surface Oxide contaminations

Microplasmas appear to be the main cause of the increase of Ibulk. From the electric point of view a microplasma at the junction is a

site where breakdown voltage is below the average value referring to the junction as a whole.

It can be identified when the characteristic I-V has a 1 inear slope, which may at times be negative. This is interpreted as the triggering of resistive paths for carriers, which may saturate [9]. The presence of these paths will produce an increase of the leakage current.

The APD multipl ication factor is enhanced by the presence of microplasmas. In fact it has an exponential relationship with the carrier ionization coefficient which in turn depends on the electric field, which is higher at microplasmas sites than in the remaining junction depleted zone.

Microplasmas can be found in devices showing anomalous junction profiles due to defects in the semiconductor material or to a not well executed technological step [10].

4.1 Oxide contamination

Mobile impurities trapped in passivating oxides and the degradation of the surface, due to external agents (02' H20) or to stress at the interface are held responsible for the increase of the surface component of dark current.

In the first case positive ions such as Na+ or K+ may move towards semicondutor-oxide interface. They may attract electrons from the semi conductor that in turn wi 11 cause an increase in the number of occupied interface states near the conduction band. As a result generation - recombination processes will increase, as will the leakage current surface component [11].

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5. QUANTITATIVE MEASUREMENTS OF PHOTODETECTOR RELIABILITY

Photodetectors are simpler than lasers and dark current is the first and most important parameter to define correct functioning. Laboratory life tests are therefore planned for a forced increase, possibly activating impurities in oxide or stressing the weak points of the junction.

This is why bias voltage and temperature are used jointly. since they are the device degradation acceleration factors.

An increase of leakage current is taken as a failure criterion. Its entity depends on the predicted component use, and can vary ten­fold from its initial value to 1 ~A.

The mean life of Si and Ge detectors falls somewhere between 106-108 hrs while III-V material detectors have a 105-106 hour mean life.

6. FAILURE ANALYSIS TECHNIQUES

Excluding intermittent failures (faulty contacts, leakage current due to impurity migration in oxide coatings, etc) all degradation mechanisms end up with permanent changes in the device. This is why failure analysis of a degraded component is performed with the aim to highlight the induced modification~ responsible for the anomalous device behaviour.

Due to the very small sizes of components, failure analysis relies on microanalytical techniques. The most valuable features of these technique, for this application, are high sensitivity, high spatial resolution, easy and fast sample preparation and the fact of being non destructive or contaminant.

The microanalytical techniques more frequently used in failure analysis are SEM technique, optical techniques, AES and SIMS. The latter two are mainly used in the determination of elemental depth profiles (doping anomalies, contact diffusion, etc), and, generally are employed to give an answer to specific problems.

Of the SEM operation modes the most specific for failure analysis are the EBIC and cathodoluminescence signal both extremely useful in the detection of crystal defects, junction damages etc. EBIC generally has a better signal noise ratio than cathodoluminescence, due to the easier and high collection efficiency of the junction present in the observed speciment. To improve the CL signal noise ratio it is common to use lock - in technique and to strongly cool the sample. In this case the required equipment is more expensive and complicated than the one necessary to operate the EBIC mode.

EBrc and CL have a direct correspondance in the two optical techniques of OBIC and photoluminescence. The lateral resolution of all these techniques is in principle equal, being mainly dependent on generated carrier diffusion length.

The main difference between electronic and photonic excitation of these signals is related to the different interaction volumes involved. In particular, when the photons energy employed in the optical techniques is greater than the band gap energy of the analyzed

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semiconductor speciment, the optical signals are more sensitive to surface feature than their electrons analogues.

Optical techniques offer a unique features compared to SEM, that is the possibility to selectively excite the signals also in a deeply buried semiconductor layer when the burying material has a greater band gap energy than the buried layer. This strange request is in fact a normal feature of all InP/InGaAs(P) devices, like optoelectronic components for the 1.3, 1.55 j.lm regions. This opportunity offer the advantage, in several cases, to extremely simplify the sample preparation procedure prior to analysis. In fact it is possible to examine the specimen from the "back" i.e. penetrating the thick InP substrate using photons of lower energy than the InP band gap. It is evident the impossibility to perform the same analysis in a SEM where the interaction volume will always stay close to the surface exposed to the electron beam.

To succesfully complete a failure analysis it is generally necessary to collect informations from several sources, reaching a synergy from the different techniques. For this reason optical and SEM approach must not be considered competitive but complementary.

REFERENCES

[1] P. Montangero, A. Piccirillo, "Reliability of optoelectronic components", in Microelectronic Reliability Vol. 2: Integrity Assessment and Assurance, E. Pollino Editor, Artech House Inc. Norwood MA (USA) , 1989 [2] A.K. Chin, "Journal of crystal growth", 1984, Vol. 70, pp. 582-596 [3] B. Cockayne, G. T. Brown and W.R. MacEwan, "Journal of crystal growth", 1981, Vol. 51, pp. 461-469 [4] K. Nakajima, S. Yamazaki, S. Komiya and K. Akita, "Jap. Appl. Physics", 1981, Vol. 52(7), pp. 4575-4582 [5] S. Yamazaki, Y. Kishi, K. Nakajima, A. Yamagouchi and K. Akita, "Jap. Appl. Physics", 1982, Vol. 53(7), pp. 4761-4766 [6] G. Fornuto and C. Papuzza, "Materials Chemistry and Physics", 1986, Vol. 16, pp. 45-52 [7] C.H. Henry, P.M. Petroff, R.A. logan and F.R. Merrit, "J. Appl. Physics", 1979, Vol. 50, pp. 3721-3732 [8] K. Mizuishi, "J. Appl. Phys.", 1984, Vol. 55(2), pp. 289-295 [9] R. De Franceschi, M. liberatore, P. Montangero and A. Piccirillo, "Proceedings of 17th ESSDERC", 1987, Bologna, Italia [10) T.P. Pearsall, "Proceedings of 4th ECOC, 1978 [11] A.K. Chin, F.S. Chen and F. Ermanis, "J. Appl. Phys.", Vol. 55, No.6, 1984, pp. 1596-1606 [12] J.F. Vermey, "Proceedings of Conf. on Insulating Films on Semiconductors", Durham, 1979, pp. 62-74

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Figure 1 - Side view of a laser after metal removal. Misfit dislo­cations are clearly visible

Figure 2 - Same laser of Figure 1. EBIC image

Figure 3 - EBIC image of a degrad­ed laser after metal removal. The anomalous dark region crossing the stripe is attributed to a local gold diffusion

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TEMPERATURE CYCLING TESTS OF LASER MODULES

P. Su and B.A. Unger Bellcore Navesink Research and Engineering Center 331 Newman Springs Road Red Bank, New Jersey 07701-7020 USA

ABSTRACT. Eight laser module package designs from six manufacturers were subjected to temperature cycling tests from -40' C to +70' C for 500 cycles. This is an extended cycling test intended to reveal weakness in packages designed for central office installations. Bellcore's cri­teria for central office qualification is satisfactory performance after 100 cycles with the perfor­mance after 500 cycles for information only, and not to be used as a qualification criterion. Laser packages intended Cor distribution loop applications were also part oC this test sequence, although their qualification requirements are 500 cycles from -40' C to +85' C. Most of these tests were conducted with the laser module unpowered. However, some devices designed for sub­scriber loop distribution were cycled while the devices were powered. We report here the results of these temperature cycling tests, including the comparison of power-on versus power-off dur­ing temperature cycling and an analysis of the packages that failed during this program.

1. Introduction

Laser modules from six manufacturers were subjected to a temperature cycling qualification test of Bellcore's document TA-TSY-000468.! The document states that laser modules intended to be used in the uncontrolled environment (such as the local distribution loop or fiber to the home) shall be qualified by 500 cycles from -40' C to +85' C. The criteria for central office qualification requires satisCactory performance after 100 cycles from -40' C to +70' C, with the performance aCter 500 cycles Cor information only, and not to be used as a qualification cri­terion. In our experiment, we kept the temperature extremes from -40' C to +70' C to compare t,he designs power-on versus power-off results under the same temperature cycling conditions. The modules tested all contained laser chips and rear-facet monitors in hermetically sealed packages. Thermoelectric coolers (TECs) and thermisters are commonly used in laser modules intended for central office installations. They maintain the laser at a constant temperature that results in more uniform laser performance and better reliability. Thermoelectric coolers

Bellcore Technical Advisory TA-TSY-000468 Issue 2, dated July 1988, is titled "Reliability Assurance Practices For Opt.oelectronic Devices." This document states Bellcore's view of minimum generic relia.bility assurance requirements which are appropriate ror optoelectronic devices to be used in products and equipment for the network of a typical divested Bell Opera.ting Compa.ny.

363

fl. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 363-378. G;l 1990 Kluwer Academic Publishers.

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are generally not incorporated in modules for loop or fiber to the home applications because of cost and circuit complexity considerations. Lenses are sometimes used in both applications for better coupling efficiency and stability. All the laser modules tested, except one type which has a laser diode and a rear facet monitor hermetically enclosed in an optical connector, had fiber pigtails and Bellcore installed biconic connectors.

2. Test Sequence

The temperature cycling was conducted in a Tenney Corp. two chamber cycling system where the device was physically transferred between a +70 0 C hot and a _40 0 C cold chamber. The elapsed time in each chamber was 30 minutes. The modules took less than 20 minutes to equilibrate in temperature after a temperature change. Each module therefore had at least a 10 minute soak at each temperature. In tests on unpowered devices, the modules were periodi­cally removed from the cycling chamber and tested for parametric shifts after permitting a half hour stabilization period at room temperature. Power on temperature cycling tests were con­ducted at constant optical output power. The drive current was continually monitored. Thorough characterization was done after failure occurred or at the completion of the 500 cycles.

3. Test Results & Failure Analysis

Many manufacturers have unique approaches in their laser module designs. The important features of the samples tested are summarized in Table 1, along with some specifications. It should be noted that some of these packages were stressed at temperatures that exceeded the manufacturers' stated operating and storage temperatures. The methods to lock the fiber, test­ing conditions, and results are summarized in Table 2.

3.1 MANUFACTURER A

Both laser modules from manufacturer A failed to complete the 500 cycles because of a sudden optical power drop. One failed between 150 to 250 cycles, and the other failed between 300 and 350 cycles. After the failure of the first module, determined during a 100 cycle test inter­val, the periodic testing interval was reduced to 50 cycles.

After the lids were removed from the two failed devices from manufacturer A, broken fibers were found in both laser modules. The fiber, coated with nickel and gold, penetrates the wall of the module through a ferrule and is soldered at Point A (Figure 1) to maintain the her­meticity and at Point B to retain the alignment with the laser. In one device (Figure 1), the fiber was broken near the solder lock (Point B). The fiber breakage occurred between Points A and B in the other device, however, closer to the solder lock than the module wall (Figure 2). In both devices, there is about 2 mm of extra fiber length inside the package. External to the package, the glass fiber is protected with a nylon jacket. The nylon jacket is retained at both ends; one end is held by the connector and the other end is secured with epoxy in the ferrule to the package. The failure of the fiber inside the package was traced to the differential thermal expansion of the glass fiber and the nylon jacket. The nylon jacket, although outside of the package, created sufficient force due to the thermal expansion mismatch to cause the solder bond/ferrule to fail where the fiber enters the module.

The linear dimensional change of the nylon jacket due to a temperature change has two distinct characteristics; a reversible temperature expansion/contraction and a non­reversible linear change. The reversible expansion/contraction property for nylon is

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approximately 0.01%/' C. With a typical 1 meter long fiber pigtail, a -40/+70' C temperature cycle would create an expansion/contraction linear dimensional change of -6.5 mm to +4.5 mm around a 25' C ambient. The nylon jacket is not physically bonded to the glass fiber. The glass has negligible thermal expansion over this cycling range. With the nylon jacket held at the connector and the module end, any differential expansion/contraction of the system will translate through the glass fiber into a linear push/pull forc:e on the solder joint used to bond and seal the penetration hole where the fiber enters the package wall. In addition, the nylon exhibits a property such that it tends to restore itself to its original unstressed dimensional stat,) if heated above its "deflection temperature." The deflection temperature of nylon is about 50' C. This is the non-reversible expansion/contraction characteristic mentioned above. During the coating of the plastic jacket on the glass fiber, the tendency is to put the jacket in tension as it cools and during thermal cycling where the deflection temperature is approached or exceeded, the nylon will tend to shrink or revert to its unstressed state. In so doing, addi­tional compressive force is transmitted to the solder joint, tending to fracture the bond and push the fiber into the module and/or the connector. This is a non-elastic force that adds to the elastic force resulting from the differential expansion of 1.he fiber/jacket system. Tensile and compressive forces on the fiber are developed during the thermal cycling program. As the tem­perature rises, the plastic jacket begins to expand and then contracts as the deflection tem­perature is exceeded. At the low temperature, the jacket shrinks and pulls the fixed ends with it; this in turn pushes the fiber to the fixed ends, in the same direction and added to the non­elastic force. This is called "pistoning" and pictorially shown in Figure 3. This forces the glass fiber to intrude into the package, break the solder bond whe:re the fiber enters the package, and accumulate excessive fiber in the package (between points A and B in Figure 1 and Figure 2) and eventually causes the fiber to break. The solder seal around the fiber at the ferrule inside one laser module showed a visible crack (Figure 4.)

The location of the fiber break in the package provided a clue as to the conditions of the solder bonds and the fiber. A long slender column with both ends rigidly fixed develops its maximum stress at the fixed ends, with higher stress at the end where the fiber is more rigidly held. And a slender column with both ends able to move, acting as hinges, will develop its max­imum stress near midspan and fracture at that point. The solder to fiber bond near the laser diode in Figure 1 appeared to be more rigidly held so that the maximum stress was developed at this end, resulting in a break near the bond. The presence of flaws or imperfections can reduce the breaking strength of a glass fiber from almost 1 mega psi to ten thousand psi or less. In cases where faults exist, the fiber would probably break at the location of the fault. Appen­dix A provides some calculations of the forces that must have been developed within the module.

Figure 5 provides data on the non-reversible expansion/contraction characteristics of two lots of fiber with nylon jackets, labeled A-I and A-2 over a temperature cycling range of -40/+70' C, along with the characteristic of a polyester jacket labeled Type B. The differential lengths for nylon range from 0.02 to 0.3 mm while that for polyester is close to zero. The forces transmitted by the fiber to the solder bond on the package due to non-reversible shrinkage of the jacket together with the reversible differential contraction forces eventually caused the bond fatigue and failure, and the fiber to fail in bending within the module package. The data showed that the actual differential length is quite dependent on the manufacturing lot, but that the extra 2 mm of fiber in the failed modules is consistent with the numbers pro­vided here. It is noted that the data shows the differential length almost stops increasing after 20 cycles.

The results of these tests are consistent with the above explanation with respect to a non-reversible length shortening during the temperature cycling. However, in these tests the devices failed after 150 cycles instead of 20 cycles. The temperature cycling numbers for device failures are higher, probably because the fiber is bonded in the module instead of free to move as was the case in Figure 5. Consequently, it takes more cycles to cause the bond to fail and

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then to permit the differential fiber length to penetrate the package. Manufacturer A replaced the nylon jacket with a polyester one in their newer product.

The thermal properties, deflection temperature and coefficient of linear thermal expansion of polyester are similar to those of nylon although the performance shown in Figure 5 indicates it is better than nylon. One possible reason suggested for the better performance of the polyester jacket is that the adhesion force of polyester to the primary coating of the fiber (uv cured acrylic) is strong enough to hold the polyester from shrinking at temperatures higher than the deflection temperature. Changing to polyester would therefore make devices less sensitive to temperature cycling between -40/+70· C.

3.2 MANUFACTURER B

Neither of manufacturer B's laser modules showed any observable change in the electrical/optical characteristics from the bare fiber pigtail after 500 temperature cycles. How­ever, connectors installed on the fiber pigtails in test samples failed in less than 100 cycles. The failures were fiber failures within the biconic connectors. Some of these connectors were replaced, only to fail again.

The fiber in the laser module of manufacturer B also used nylon as the secondary coat­ing, but this fiber was produced by a different supplier. Although the fiber to module bond with­stood 500 temperature cycles indicating a secure bond, the fiber in the optic connector did not. The fiber failures within the connectors were originally attributed to poor installation of the connectors. It is now clear that these failures were also caused by the differential expansion/contraction of the fiber/jacket system in a manner similar to the failure discussed previously. Inside a connector (Figure 6), the fiber was stripped to glass from Point B to Point D and held by epoxy at Point C. The nylon coating, terminated at Point B, was held by epoxy at Point A. During the assembly process some epoxy coating was provided between points A and C but it did not completely fill this space. The glass fiber was pushed into the space between Points Band C when the coating shrank. The excessive fiber caused the breakage just as it occurred inside the package. Since the mixing of epoxy and air bubbles between Points B and C was not controllable, the tolerance to temperature cycling was not reproducible as we observed failures occurring from about 20 to 300 cycles. These failures occurred at the connec­torized end since this was the weaker joint in this assembly design. The fiber breakage in the connectors helped to release the force in the fiber; preempting any fiber failures in the package. After the connector failures had occurred, the temperature cycling tests were continued without connectors. It was then observed that the nylon jacket contracted, leaving a small length of bare glass fiber after temperature cycling. This is the same "pistoning" effect as described in the previous section.

The failure mechanism described above may not be unique to the laser module with a biconic connector. As we explained earlier, the force originating from the glass fiber with plastic jacket may be transferred to other parts in the system. This stress could result in failures in laser modules with other types of optical connectors.

3.3 MANUFACTURER C

One device of Manufacturer C (designated as C-a1) actually showed improved performance after cycling. The optical power from the front connector at 50mA drive current increased by 4.7% after 100 cycles, 9.2% after 250 cycles and 12.6% after 500 cycles. This is probably caused by the movement of the fiber towards a more optimized position, or closer to the laser active region after temperature cycling.

Three devices of another type from Manufacturer C (Type b) were divided for tempera­ture cycling tests; two devices (C-b1 & C-b2) were used for power-off and the third device (C­b3) for a power-on test. After 50 cycles, C-b1 degraded. The power from the front connector dropped from 225/lW to 1.5/lW when the laser was driven by 50mA of current. Since the rear­facet monitor photo current also dropped from 1.37mA to 1.7/lA, the failure is more likely to be

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the laser diode itself. Additional temperature cycling did not degrade the device any further. The failure mode is under study now.

Devices C-b2 and C-b3 were not degraded after 500 cycles of temperature cycling.

3.4 MANUFACTURER D

One device from this manufacturer was tested in the power-off mode. Some degradation from the front connector was observed after 100 cycles; The external quantum efficiency dropped 10% when measured at room temperature. The threshold current and the rear-facet monitor photo current were stable. It did not degrade after an additional 150 temperature cycles. How­ever, the external quantum efficiency dropped another 10% after 500 cycles. These changes appeared to be the fiber movement induced by the stress during temperature cycling tests. Since we did not know the original position of the fiber, we could not measure the misalignment due to fiber movement. However, we are currently developing a technique to examine the align­ment during temperature cycling.

3.5 MANUFACTURER E

Five devices from Manufacturer E Type "a" were tested; 3 were powered and 2 were not. They all showed no observable degradation after 500 temperaturE! cycles.

Two devices of Type "b" were also tested. The one tested with no power-on during the temperature cycling showed significant degradation; the power from the optical connector dropped by 5 orders of magnitude after 100 cycles while the threshold current and rear-facet monitor photo current did not show changes. Temperature cycling to 500 cycles caused an additional 75% power drop. The second device was powered during the test and also showed significant optical power drop (more than 50%) between 350 and 500 cycles without rear-facet current change. The degradation in these two devices resulted from fiber movement.

3 6 MANUFACTURER F

Power-on temperature cycling tests failed two out of the four modules tested. Both were caused by TEC failures in less than 10 cycles. All TEC failures were open circuit.

Optical microscope and SEM examination (FigurE! 7) showed that thermoelectric ele­ments were severely damaged; either cracked, split or lifted up. The damage was particularly severe on the p-type elements. The elemental analysis did not indicate any diffusion or migra­tion of foreign chemicals to cause the cracks or damage. We conclude that the thermal mismatch of the copper heat sink with the thermal conducting top, usually aluminum oxide, caused the crack or split during the temperature cycling;. The thermistor indicated that the TEC was progressively failing during temperature cycling. The cooler required continually more current in an attempt to maintain the laser at 2.5 0 C until it completely failed. This occurred even though the TEC current was limited to 1 amp maximum, which was within the TEC specifications.

One device was tested without power-on and passed without observable degradation.

4. Conclusion

The temperature cycling tests showed that laser module/fiber pigtail/connector assemblies are susceptible to failures by forces due to the differential thermal expansion/contraction of the fiber/coating system. The degradation that we observed revealed a fundamental problem with designs that use fiber coated with low deflection temperature, low adhesion force materials, with large differences in coating to fiber thermal characteristics. The force can cause fiber breakage when the glass fiber and the jacket are held fixed at any two points; breakage can o.:cur inside the package, in the ferrule, or in the optic connector. The same force can also

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move the fiber to change the coupling efficiency of the light when the fiber lock is loosened. There were no clear indications that power-on or power-off conditions contributed to

laser failures. However, it did point out that the devices using TECs have to be tested with TECs powered on. The occurrence of TEC failures within 10 cycles indicated that the screening with TEC powered during temperature cycling needs to be emphasized.

Finally, this series of experiments did provide a degree of confidence in and confirmation of the validity of the temperature cycling requirements in TA-TSY-000468.

REFERENCES

1. Osamu Mitomi, et aI., "Reliability of Optical Components for Use in Submarine Optical Fiber Transmission Systems", in J. of Lightwave Technology, Vol. LT-5, No.6 (June 1987), pp. 838-847

2. Sim, S. P., et aI., "Reliability Testing of Opto-Electronic Components," in Br. Telecom Techno!. J., Vol. 4 (April 1986), pp. 104-113

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APPENDIX A - Calculation of Fiber Stress

Two methods are used to calculate the stress in the fiber prior to fracture. In both cases, the calculated bending stress in the fiber was determined to be in the order of 105 psi. This stress is within the breaking strength of glass fiber which ranges from 104 psi to 106 psi.

After Broken:

~t.l,..·

<C .•.•••••••••••••••••••••••••••••••••• I .................................... 2>

Before Broken:

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Method I

Considering the fiber as a long slender column, the stress in the fiber column can be expressed by Euler's formula:

where n=4 if fixed at both ends (=2 if pivoted one end)

E=1.1x107 psi - Young's modulus for glass

r=75j.lm - fiber radius including glass and metal coating (see Figure 4)

1=1.Icm - fiber length in the package when broken

Hence

stress = 1.6IX105 psi

Method II

The distance between the two fixed points in the package is lOmm and the extra fiber found in the package after failure is Imm. The arc angle (¢) immediately prior to fiber failure was calculated to be 0.55 (about 32 0

) and the radius (R) was 11.88mm.

stress = deformation X Young's modulus

= ¢ r E/R

Hence

stress = 3.17X105 psi

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TABLE 1. Temperature Cycling Test Samples

DEVICE PACKAGE(l) OPERATION(2) STORAGE(3) TEC(4) LENS(S)

A-al a2 Rectanl!:ular -20/+65' C -20/+70' C Yes No B-al a2 Rectangular -40/+70' C -40/+70' C Yes No C-al Rectangular -40L+65'C -40/+85' C Yes No C-bl b2 b3 Cylindrical -40/+85 'C -40/+85' C No Yes D-al Rectangular -20/+65' C -40/+70'C Yes Yes E-al a2 a3 a4 as Cylindrical -20/+70' C -30/+70' C No Yes E-bl b2 Cylindrical 0/+50'C -30/+70' C No Yes F-al a2 a3 a4 Rectangular -20/+60' C -40j+70' C Yes No

1. Rectangular: devices are in pigtailed SIP or DIP packages Cylindrical: devices are in cylindrical can with or without pigtails

2. Operating temperature in the data sheet

3. Storage temperature in the data sheet

4. Using thermoelectric cooler to maintain the laser diode temperature

5. Using additional optical lenses between the laser active region and the coupling fiber other than the SELFOC lens at the fiber tip

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TABLE 2. Temperature Cycling Test Results

DEVICE FIBER LOCK(l) TEST(2) RESULTS(3)

A-al Solder Power Off Failed - fiber broken in package 250

A-a2 Solder Power Off Failed - fiber broken in package 350

B-al Solder Power Off Failed - fiber broken in biconic 30

B-a2 Solder Power Off Failed - fiber broken in biconic 20

C-al Solder Power Off Passed

C-bl Laser Welding Power On Failed - LD degraded 50

C-bZ Laser Welding Power Off Passed C-b3 Laser Welding Power On Passed D-al Solder Power Off Failed - fiber movement 500

E-al (4) Power On Passed

E-aZ (4) Power Off Passed

E-a3 (11. Power On Passed E-a4 (4) Power On Passed

E-a5 (4) Power Off Passed E-bl Solder Power Off Failed - fiber movement 100 E-bZ Solder Power On Failed - fiber movement 500 F-al Laser Welding Power On Passed F-aZ Laser Welding Power Off Passed F-a3 Laser Welding Power On Failed - TEC failed 10

F-a4 Laser Welding Power On Failed - TEC failed 10

1. The mechanism to lock the fiber aligned to the laser active region

2. Power On: Laser module is powered at a constant optical output power as in normal operation during temperature cycling Power Off: Laser module is not powered during temperature cycling

3. Failed if showing >10% change after certain number of temperature cycling

4. LD is packaged in an optical connector

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FIGURE 1. Fiber Broken Near Laser Diode

FIGURE 2. Fiber Broken In The i\1iddle

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FIGURE 3. Lasr Module Fiber Pig-Tail System

z Ci5 w a:

g a..W W....J ~ a: a: w u..

w Cl o is

ffi-~

Cl Z

~

Cl W

~ o c..>

~

z z o c..>

a:---1lTI W

~

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375

FIGURE 4. Cracked Solder in Laser Module From Manufacturer A

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FIGURE 5. Fiber Piston Due To Fiber Coating Shrinkage

t

('I)

ei

I « UJ a.. ~

~

C\l ei

C\l I «

UJ 0..

~ ~ i;; j ,

~ ,~ .

r- o ei

(ww) 1'7 H18N31 Tv'11N383.:l.:lla

CO UJ a.. >-I-

0 ......

o CO

o LO

(j)

o~­"<:tO~

>-0 0 ...... Ll..+

000 ('I) -a::: 0

Wo COO

O ~"'T ::::>­C\lz

o r-

o

Page 380: Semiconductor Device Reliability

FIGURE 6. Biconic Optical Connector

UJ z 2 0..

T5

g 0.. UJ

377

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378

FIGURE 7. TEO Failures

Page 382: Semiconductor Device Reliability

AN EXPERIMENTAL AND THEORETICAL INVESTIGATION OF DEGRADATION IN SEMICONDUCTOR LASERS RESULTING FROM ELECTROSTATIC DISCHARGE

LOUIS F. DECHIARO, CARMEN D. BRICK-RODRIGUEZ, and ROBERT G. CHEMELLI Bell Communications Research 331 Newman Springs Road Red Bank. NJ. USA 07701

JOHN W. KRUPSKyl South Central Bell P.O. Box 771 Birmingham. AL. USA 35201

ABSTRACT. Human Body Model (HBM) electrostatic discharge (ESD) step stressing has been applied to commercial, 1.3 micron Fabry-Perot semiconductor lasers. ESD failure voltages varied by a factor of 5 among the commercial products tested. The static L-I data for each longitudinal mode exhibit larger changes with ESD stress than the total L-I data. In addition, the modal L-I data show a clear trend of degradation at stress levels well below the failure voltage. The total and modal L- [ characteristics were numerically modeled using a rate equation analysis, including third order gain suppression and a linear change in peak gain wavelength with drive current. Theoretical results indicate that the modal L-I relations are much more sensitive than the total L-I to the simulated ESD stress, in agreement with the experimental data. The dynamic rate equations were numerically solved for a step change in drive current and predict that the individual mode dynamics are more sensitive to the simulated ESD stress than the total output. Implications of these findings upon the dispersion penalty for optical communications systems are discussed.

1. Introduction

During the past 15 years, the state of optical communications technology has rapidly advanced. Modern semiconductor lasers are capable of being modulated at speeds in excess of 10 GHz. Single frequency devices can be rapidly tuned over a relatively broad range of wavelengths and are presently being studied for use in coherent communications applications. The more mature multi-frequency technologies are appearing in large device numbers in central office switching and transmission equipment throughout the world. Manufacturing engineers, working in conjunction with reliability investigators, have succeeded in producing lasers in high volume with threshold currents and quantum

1 This work was performed as part of a Bellcore internship.

379

A. Christou and B. A. Unger (eds.), Semiconductor Device Reliability. 379-41l. © 1990 Kluwer Academic Publishers.

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efficiencies that are relatively stable for more than a thousand hours of accelerated aging. One is led to conclude that the time-dependent failure mechanisms of multi-frequency semiconductor lasers are relatively well understood.

Until the mid 1980s, however, little had been done to study the impact of event­dependent failure mechanisms, such as electrostatic discharge (ESD), upon the performance or reliability of semiconductor lasers. The historical reasons for this are clear. Older 0.8 micron AIGaAs lasers were often designed with junction areas measuring in the hundreds of thousands of square microns. Although the large junction areas usually rendered the devices slow by modern standards, the same factor also afforded a large measure of ESD immunity. Human Body Model (HBM) ESD failure voltages of 8000 volts or more were not unusual for such devices. Consequently, there was little economic incentive to support ESD studies of these components. Modern lasers, however, typically contain junction areas measuring only in the hundreds of square microns. These junction areas are com­parable to those of ESD-sensitive silicon integrated circuits. Consequently, HBM failure voltages on modern, high speed lasers can measure less than 1000 volts, a level sufficiently low to justify both ESD-preventive handling procedures and detailed studies of the laser response to ESD stress.

A comprehensive review of the initial studies of catastrophic and gradual degradation in semiconductor lasers can be found in Casey and Panish[l]. Some of the first Japanese studies of high volume production GaAIAs lasers[2] described facet damage resulting from ESD and promoted the use of Zener diode-bearing protection networks. A definitive ESD study on semiconductor lasers was published by Sim et al[3] who applied square, high current pulses to 0.8 micron oxide-isolated AlGa As lasers and characterized the effects of polarity and pulse width upon failure voltages. Their cathodoluminescence results clearly indicate that ESD stress can cause crystallographic damage in the active region sufficiently intense to quench the luminescence. In addition, their results demonstrate that ESD damage is not necessarily confined to the facets, especially in the case of reverse biased stress.

This work was undertaken to answer several outstanding questions regarding the ESD response of 1.3 micron semiconductor lasers. First, which laser parameters show evidence of degradation at ESD stress levels well below the failure voltage? Second, what is the difference in the inherent ESD sensitivities of the several types of laser structures? Third, how do the various laser parameters change during the course of ESD stressing? Fourth, how sensitive are semiconductor lasers to the location of the damage site? Finally, is the existing base of theoretical work adequate to account for the changes within a semiconductor laser caused by ESD stress? Section 2 describes the various types of lasers used in this study, while Section 3 contains information on the experimental apparatus and procedures. Section 4 presents the experimental results for the aggregate (summed over all longitudinal modes) laser characteristics such as total light output versus drive current and current versus voltage data. Section 5 contains our experimental results on light output versus drive current for each separate longitudinal mode and describes how the modal patterns vary with ESD stress. Section 6 describes the experimental variation in the dominant longitudinal mode number with drive current and ambient temperature. Section 7 discusses a simple two-mode laser model above threshold, elaborating on the work of Hori et al[4], and explains the connection between the model and certain results from Catastrophe Theory. Section 8 presents results from a detailed numerical model of a multimode laser based upon the rate equation work of Yamada and Suematsu[5] and Asada and Suematsu[6] in which we study the effect of localized, ESD-induced gain changes upon the modal power distribution. Section 9 presents our theoretical plots of dominant longitudinal mode number

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versus current and temperature, and Section 10 contains our dynamical rate equation results. Sections 11 and 12 respectively contain a discussion of our results and state our major conclusions.

2. Laser Structures Studied

The lasers used in this study are Fabry-Perot InGaAsP lasers with operating wavelengths near 1.3 microns. Submounts were used to enable far field measurement and to minimize the probability of reflections from the near fiber end which can occur with laser modules. The commercial lasers were designed for use in direct modulation optical communication systems. The Bellcore lasers are experimental devices fabricated by the Applied Research Area. Structures and active layer growth technology are given in Table l.

Table 1. Structure and active region growth technology for the lasers in this study.

Growth Vendor Structure Technology

A BH LPE

B BH MOVPE

C Unknown MOCVD

0 VSBH LPE

Bellcore BC LPE

3. Experimental Apparatus and Procedure

This section describes the experimental apparatus and procedure used to collect data from the lasers in this study. Wrist straps were used in handling all lasers to avoid unintentional exposure to ESD stress. In addition, materials which tend to create large amounts of triboelectric charge (styrofoam, for example) were avoided. The lasers were received from the vendors in antistatic packaging, and the lasers were protected by such packaging when not installed in the apparatus.

ESD stress was applied with an IMCS Model 2400C stressing set which was modified to ensure an HBM waveform with minimal leading edge transients[7) and essentially no recharge transients. During a typical stressing sequence, five pulses at a desired voltage were applied in the reverse biased direction, after which the laser was tested and the data stored on disk. Reverse biased stressing was used beca.use initial tests indicated that the worst case failure voltage was always observed in the reverse direction. If catastrophic failure was not observed after stressing at a given level, the voltage was incremented to the next higher level and the stressing protocol repeated. A typical starting voltage was 100 - 200 volts, and typical increments were 100 volts. Starting voltages ranged as high as 1000 volts for those laser structures known to have high failure voltages. Stressing was continued at least until the laser exhibited a large (typically a 100 %) increase in threshold current. A number of lasers were stressed beyond this point for the purpose of observing the response to continued stress.

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Total light output versus forward current versus forward voltage (L-I-V) and reverse-biased voltage versus current (R-I-V) data acquisition was performed by an HP 4145A Semiconductor Parameter Analyzer which was controlled over the IEEE-488 (GPIB) bus by an IBM PC/XT style computer equipped with a National Instruments GPIB controller card. All applications programming was done in the ASYST language. The lasers were mounted in a locally-fabricated TEC-cooled holder whose temperature was controlled to within 0.50 C of the desired value with a locally-fabricated closed-loop controller. Total light output was measured with a Hitachi HRllOI PIN diode operated at zero bias voltage. The cold end of the photodiode was returned to a voltage source on the 4145A for the purpose of providing a virtual ground and decoupling the photodiode from the laser current. This arrangement enabled the measurement of photocurrents as low as 10 picoamps when using the medium integration time of the 4145A. A typical scan consisted of 151 data points with a drive current resolution of approximately 0.3 mao Laser spectra were observed with a SPEX 1.25 meter monochromator, controlled by a SPEX Datamate computer. Light from one laser facet was focused onto the detector, while light from the other facet was directed into the monochromator entrance slit by microscope objectives ranging in mag­nification from lOX to 40X. During the collection of modal L-I data, the longitudinal modes were separated by setting the monochromator exit slit width to 750 microns. This width provided excellent discrimination against neighboring modes, while ensuring that the desired mode remained within the instrumental bandpass over a laser drive current range of 45 mao The entrance slit was typically set near 100 microns to avoid preamplifier saturation and was left at a constant setting for the duration of stressing with each laser. Light emerging from the monochromator exit slit was detected with a large area germanium detector and a locally-fabricated operational preamplifier. Reflections were minimized by placing a 20 db attenuating neutral density filter between the microscope objective and the entrance slit of the monochromator. All of the optical elements were placed on or secured to a Newport optics table which was mounted on active, pneumatic legs to minimize vibrations.

4. Total L-J-V Data

This section describes our experimental results for the aggregate characteristics of the lasers under stress. Total L-I-V and R-I-V data were collected from the test lasers at each ESD stressing voltage. Figure I shows plots of total L-I characteristics for one laser after stressing at several different voltages. In Figure lA, the L-I characteristics at 1200 volts and below are essentially identical. At 1300 volts and higher, significant increases are observed in the threshold current (determined from the peak in d2L/dI2), and decreases are observed in the slope efficiency. Catastrophic failure was arbitrarily defined as the stressing voltage at which the threshold current exhibited a 50% increase over its unstressed value. A plot of threshold current and slope efficiency versus stress voltage is shown in Figure lB. The general trend for the parameters is monotonic, however a number of voltages were observed at which the laser characteristics exhibited a temporary improvement before continuing to degrade at higher voltages. The changes in L-I data associated with these improvements are considerably larger than the experimental uncertainty and are thus not attributable to systematic error.

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383

-:l c.. -:l

A 0 -.r:. Ol

--.J

00 10 20 30 40 50 60 70 Drive Current (mA)

60 Slope

l... Efficiency (j) 40 -(j)

8 c 0 l...

0 20 i (L

Threshold

00 0.5 1.0 1.5 2.0 2.5 Stress Voltage (kV)

Figure 1. A. Plot of L-I data after stressing at various voltages. B. Plot of threshold current and slope efficiency versus ESD stressing voltages.

Figure 2 shows the L-I data from another laser plotted on a logarithmic light scale. The data show that the spontaneous emission increases sharply at zero forward current for all stressing voltages below the catastrophic failure point. However, the current "threshold" for spontaneous emission increases abruptly at the catastrophic failure voltage.

+- 101 :l c.. -:l o ::.c 10- 1 Ol

--.J

103~O __ ~~~~~~ __ ~ __ 7 o 12 24 36 48 60

Drive Current (mA)

.'igure 2. Typical plot of laser L-I data on a logarithmic light scale.

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384

The existence of a nonzero current "threshold" for spontaneous emission implies the possibility of a leakage path around or through the active region. Figure 3 shows reverse biased I-V data for a typical laser at several values of stressing voltage. It is apparent that the reverse biased I-V data indeed show the existence of a leakage path whose impedance abruptly drops when catastrophic failure occurs. One further comment is indicated regarding the rate of degradation with stress. The lasers used in this study generally exhibited poor consistency in the rate of degradation of characteristics after catastrophic failure occurred. The parameters shown in Figures I and 3 degrade slowly after the initial change at catastrophic failure. Other supposedly identical lasers man­ufactured by the same vendor exhibited much faster degradation with stress. The reason for this difference in post-failure degradation rates is not currently understood.

Reverse Voltage

Figure 3. Reverse biased I-V characteristics at several ESD stress levels.

Figure 4 shows dL/dI results (from a different laser than shown in Figures I and 3) versus ESD stress. The changes below catastrophic failure are fairly subtle except for the appearance of a kink at 1200 volts of stress. The derivatives were computed by a simple difference of neighboring points algorithm. After the differencing calculation, the derivative array was subjected to Blackman window low pass filtering to remove high frequency noise. The high pass cutoff frequency was manually set at 0.5 cycles per point, the largest value allowed by the ASYST programming language. This was done to minimize distortion of the data while providing some attenuation of unwanted noise. After removing the high frequency noise, some underlying low frequency structure can be discerned, and this structure appears to exhibit some change at stress voltages below the catastrophic failure point. The structure does not show the periodicity with drive current that is known to occur when reflection problems exist. However, the percentage change in these characteristics is sufficiently small that it is difficult to rule out system noise or quantum fluctuations as the source. In a later section, it will be shown that such subtle changes in the low frequency component of the dL/dI with ESD stress can be expected on theoretical grounds. However, in our opinion, the magnitude of the low frequency structure contained in the data is not sufficiently large to enable an unambiguous determination of ESD stress as the only likely cause of the changes shown in Figure 4.

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100.--------------------,

80

-u 60 "-....J -u 40

20

OL..---~-----'------'-------l

10 20 30 40 Drive Current (mA)

50

385

Figure 4. Plot of experimental dL/dI versus drive current at two values of ESD stress.

We conclude this section by listing the overall ESD stressing results by vendor. Table 2 contains the mean and standard deviations of the ESD failure voltages for the lasers in this study.

Table 2. Mean and standard deviation ESD failure voltages by vendor.

Mean Fail Standard Vendor Voltage Deviation

A 1800 ---B 1325 150

C 1400 100

D 4400 800

Bellcore 1750 150

The laser with the highest failure voltage was a vendor D laser, which failed at 5200 volts. The lasers with the smallest failure voltages are not included in the table. Two lasers from vendor B exhibited failure voltages between 500 and 1000 volts. The vendor B distribution is therefore bimodal, and it appears that the lower peak of the distribution represents devices that were in some sense defective. In order to give a more accurate representation of the main population, the "freak" data were censored.

5. Modal L-I Data

As reported in the previous section, the total L-I characteristics of the majority of the lasers in this study did not exhibit significant change (with the single exception of occasional kinks appearing in the dL/dI at some stressing voltages) until the ESD level became sufficiently high to cause laser failure. It is desirable to identify parameters which exhibit change in all lasers at stresses well below the catastrophic level. This section presents our

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experimental results on modal L-I data versus laser structure and ESO stress and indicates that the modal L-I characteristics are considerably more sensitive than the total L-I to the effects of ESO stress.

Figure 5 shows L-I data for three longitudinal modes in a typical unstressed laser. The data show single or multiple peak structures, and one can discern a negative correlation among the neighboring modes. For example, mode -2 decays rapidly as mode 0 grows, and mode 0 decays as mode 3 grows. However, this laser also shows some evidence of a positive correlation between two modes sufficiently separated in wavelength. A small peak appears in the L-I characteristic of mode -2 as mode +3 grows. This suggests that as mode 0 decreases in strength, most of the power appears in mode +3, but some appears in mode -2. The magnitude of this effect as well as the shape of the modal L-I characteristics showed considerable variation among the lasers studied.

4 Unstressed +3

3 "" « :J

'--" 2 .-Q)

'U

°10 20 Drive Current

Figure S. Plot of experimental L-I characteristics for 3 longitudinal modes in an unstressed laser.

Figure 6 shows typical L-I data for one longitudinal mode of a multi-mode laser recorded after ESO stressing at several voltages. The laser failed at 1300 volts, however, the L-I data indicate evidence of change at stress levels as low as 500 volts. The changes occur primarily in two areas. First, the shape of the modal L-I characteristic can change with ESO stress. In general, the modal data contain one or more peaks, separated by local minima in which the modal intensity may drop to less than 25% of the peak value. ESO stress can cause a peak to disappear, to merge with a neighboring peak, or to split into two peaks. Second, in those cases for which the overall shape of the modal L-I is invariant under stress, ESO can cause large changes in the currents associated with modal features. For example, in Figure 6, the ESO stress evidently caused changes in the currents associated with the local maxima of the modal L- I. These effects can result in large changes in the distribution of power among the several longitudinal modes without necessarily yielding a correspondingly large change in the total L-I characteristics.

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387

8 Mode +2

6 '" <{

::J '--" 4 -+- 1200 V (J)

"U

2

0 20 30 40 50

Drive Current (mA)

Figure 6. Experimental L-I plot for one longitudinal mode of a typical laser after ESD stressing at 500, IIQO, and 1200 volts.

One may define a mode transition current as the value of forward current at which the first derivative of the modal L-I data reaches a local maximum in absolute value. Figure 7 shows a plot of the mode transition currents versus ESD stress level for one of the lasers used in this study. The failure voltage for this laser was 1200 volts; however the transition currents show significant change at stress levels well below the failure voltage.

X+l0.----------------------.-----. -2-- 0 Laser Fails 1 ........ '., __ .~.~ 1 0 ____________

...... -.. \ ........................... . ] '''''-_ ..... '''', '- '-; " ' ..... -3 -"0 () X+5 ... __ " X=30

' ..... _--'" ..... ------

Threshold

X=10

"

XOL---~O~.3~--O~.~6--~Ou.9~--1~.2~--~1.5

ESD Stress (kV)

Figure 7. Experimental plots of threshold and longitudinal mode transition currents in a typical laser versus ESD stress. The vertical axis covers a range of 10 rna. The vertical scale ranges from 10-20 rna for the threshold current and the -2 -> 0 modal transition, 30-40 rna for the -3 -> 0 modal transition, and 40-50 rna for the 0 -> +1 modal transition.

In addition to or in place of the changes in mode transition currents, some lasers may exhibit a change in the maximum light power associated with a given peak in the modal L-I characteristic. For example, Figure 8 shows the peak modal power versus stressing voltage for three modes of a laser which failed at 1200 volts. The change in the distribution of power among the modes is evident at stressing voltages as low as 25% of the failure voltage.

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10

'-\I) 8 ~ 0

CL 6

0

" 0 :::!: 4 .:;{.

0 \I) 2 CL

---------....

Mode 1 ............ ...... _"" , ,

'\ \i :\

Mode -1 ~,/ \ ............................ _--.. -.... _-_ ...... - ... - ,

0.3 0.6 0.9 1.2 ESD Stress (kV)

Loser fails

1.5

Figure 8. Experimental plot of peak modal power versus stress voltage for three longitudinal modes. Note the increasing slope as the failure voltage is approached.

Another effect of ESD is the creation of current regions in which the modal charac­teristics exhibit bistability and hysteresis. Figure 9 shows L-I data for one mode resulting from upward and downward current scans. The pre-stressing data show good agreement between the upward and downward current scans; the small differences are attributable to quantum noise effects resulting from the interaction of electrons and photons in the active region of the laser. The post-stressing data clearly show a region of hysteresis at about 28 rna of forward current. In fact, the hysteresis effects are present at stressing voltages as low as 1100 volts.

4r-----------~~~-----------.

1700

,.-....3 <t: Mode -1 :::l

-----up •••••••.•••••••••••. Down

o~~~-~---~---~ 20 25 30 35

Drive Current (mA) Figure 9. Experimental, bidirectional L-I plots for one mode before stressing and after stressing at 1700 volts. The upward and downward scans essentially agree in the unstressed case. However, evidence of hysteresis is visible in the post-stressing data.

The data indicate that the hysteresis effects are not confined to one mode. Figure 10 shows bidirectional L-I scans for two modes separated by approximately 2.5 nanometers (three longitudinal mode spacings) in wavelength. The area inside the hysteresis loop is

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389

considerably larger for mode -I, however a small loop is discernable even on mode 2. In fact, all modes show evidence of well defined hysteresis loops in the same forward current range.

4.-----------~~--------__,

..... 2 Q)

"U

Mode

----up ••••••••••••••••••••. Dow n

25 30 Drive Current (rnA)

0.2

0.1

Figure 10. Experimental, bidirectional L-I plots for two modes of a laser after ESD stress at 1700 volts. Note the hysteresis occurring between 28 and 29 ma of forward current in both modes.

The changes in modal L-I characteristics of the lasers in this study did not appear to follow a common pattern. In fact, two lasers from the same vendor often exhibited large differences both in the unstressed, modal L-I characteristics and in the stress-induced changes of those characteristics. Because the modal L-I data may be affected by reflections, it is significant that the ESD stressing was performed in situ and that steps were taken to minimize the amplitude of any reflections. Although the changes in the modal L-I data with ESD stress do not suggest a universal, pass/fail criterion, their sensitivity to changes at low stress levels indicates their usefulness as a measure of change in the active region of the laser. In the following sections, a rate equation analysis will show that the types of changes observed in modal L-I characteristics with stress can be theoretically explained by assuming changes in the spatial distribution of gain within the active region.

6. Modal Transitions Vs. Temperature and ESD Stress

The phenomenon of mode hopping in Fabry-Perot lasers has been experimentally studied by M. Ohtsu et all8], who characterized lasers by plotting the distinct regions of modal behavior in the current-temperature (1-T) plane. This analysis is also useful in our study of multi-mode lasers. During our stressing sequence, modal L-I characteristics were periodically measured at temperatures from 200 through 300 Celsius. The longitudinal mode with the highest output power was determined at each value of forward current and temperature. Contour plots were then generated to show the boundaries of the regions in the 1-T plane within which a given mode dominated the laser field spectrum. Data below threshold were rejected due to system noise. In addition, the effects of quantum noise above threshold were minimized by applying Blackman window filtering in the frequency domain at each temperature. Figure II shows typical Ohtsu plots generated by this procedure for a given laser before stress and after stressing at 1700 volts. This laser exhibited catastrophic failure at 1800 volts.

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390

30.----rr--~----~------~

U'28

OJ Q) 26

Ae a. 24 E Q) t- 22

20 20

30

---. 28 u

:ir 26 Be a. 24 E ~ 22

:'2 0

.<: Vl ., '-

.<: I-

~ ..'e ., C)

23 26 29 32 35 38 41 Drive Current (mA)

Drive Current

+5

+3

Figure 11. Experimental Ohtsu plots for one laser before ESD stress (A) and after step stressing at 1700 volts (B). Note the displacement of the modal regions toward the upper right in plot B.

A number of features are evident from these plots. First, the constant mode regions of the stressed laser were displaced to the upper right, indicating that the stress caused a measurable change in operating wavelength. Changes of several nanometers in operating wavelength with ESD stress prior to catastrophic failure were not uncommon. Second, the shape of the constant mode regions experienced some deformation with ESD stress. Some of this deformation is obviously attributable to the constraints on the low current side of the region imposed by the threshold condition (see the left boundary of the mode -I region, for example). On the other hand, some of the boundaries away from the laser threshold limit also experienced some change with stress (such as the boundary between modes 0 and +1). Third, the boundaries between some of the modal regions are roughly hyperbolic in shape. This implies that as the region is displaced by ESD stress, the width along the current axis of the region dominated by a given mode can change. Fourth, the width of the regions varies substantially among the various modes. The mode +2 regions, for example, are considerably more narrow than those for modes +1 and O. It should also be mentioned that the hyperbolic pattern shown in Figure II was not observed for all lasers. In some cases, a small region within which mode +1 dominates may be surrounded on all sides by a larger mode 0 region. These patterns appear to show some consistency among the lasers supplied by anyone vendor, but considerably less consistency among the several vendors.

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7. Catastrophe Theory and the Multimode Rate Equations

The experimental data presented above contain a number of distinctive features, particularly the variation in modal L-I characteristics with ESD stress. In most cases, the modal power changes with drive current in a continuous fashion. However for some lasers, there exist a small number of currents at which some of the modal powers exhibit large, discontinuous changes and even show evidence of bistability and hysteresis. Catastrophe theory is a relatively new branch of mathematics developed to describe systems which occasionally exhibit discontinuous responses from continuously varying stimuli. For reasons of brevity, we shall use a number of results from this theory without detailed proof; the interested reader is referred to any of the numerous books[9] covering the topic in depth. This section describes a simplified mathematical model of a two-mode laser at currents well above threshold and interprets the salient features of the model in the context of catastrophe theory. With these simplifying assumptions, one can analytically derive a number of important characteristics of the system and set the stage for the more detailed numerical calculations to be presented in the following sections.

To fully utilize catastrophe theory, one requires a potential energy function, from which the equilibrium operating point of the laser may be derived. For a two mode laser in static equilibrium, the potential function is given by the solution of the time independent Fokker-Planck equation[lO] and may be written as follows:

(1)

where Sj (i=I,2) is the photon density associated with the ith longitudinal mode, aj is the first order (linear) gain of the ith mode, ~, is the self suppression coefficient for the ith mode, and 9 '2 is the cross suppression coefficient which controls the strength of the intermodal coupling. In this case, the coefficients aj, ~ I , and 9 '2 represent the input variables, while the photon densities Sj are the output variables. The input and output variables form a 7 dimensional phase space within which the operating conditions of the laser can be represented as I point. Expressions for the equilibrium surfaces in phase space are obtained by computing the gradient of (I) with respect to Sj and setting the result to zero, which yields the following:

(2)

(3)

These will be recognized as the static rate equations whose solutions give the values of Sj for any desired combination of input variables. Catastrophe theory states that given a well behaved potential function such as (I), the output variables will be continuous functions of the control (input) variables at all points in phase space with the possible exception of a unique subset known as the bifurcation set. If this set is non empty for a given potential function and if the control trajectory crosses through it, the output variables mayor may not exhibit discontinuous jumps, depending upon the direction of approach to the bifurcation set and the state of the system. The type of potential function shown in (I) yields what is known as a double cusp catastrophe. The geometrical shape of the bifurcation set in phase space resembles a pair of cusps touching at the tips. An analytical expression for the bifurcation set may be obtained by computing the Hessian matrix of the Fokker-Planck potential function, setting its determinant to zero, and solving the resultant

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392

equation simultaneously with the rate equations by eliminating the output variables. In other words, the bifurcation set consists of the locus of all points in phase space which both satisfy the equilibrium conditions (the static rate equations) and yield a zero determinant of the Hessian matrix. The elements of the Hessian matrix are the second partial derivatives of the Fokker-Planck potential with respect to the output variables Si'

(4)

When the determinant of (4) is set equal to zero and (2) and (3) are substituted into it to eliminate Si' we obtain the following expression for the bifurcation set:

0= (U 2 _V 2 )(W 2 + 1 +t)-w{2u 2 +2v 2 +t(U 2 +v 2 +2uv)}

where we have defined the auxiliary variables

al- a 2 V=---

2 ' o

t=-. 13,

(5)

(6)

In the limit of t -4 0 this reduces to the expression derived by Hori et al[4] from stability considerations on the solutions of the steady state rate equations. A plot of the bifurcation set in the v-w plane showing the various regions of phase space is given in Figure 12. The two cusps of the bifurcation set are evident, and they meet at a value Wo which approaches I as t -4 O. For large values of lvi, the laser gain is very unevenly distributed between the two modes, yielding steady state operation in only one mode. For values of Ivl near zero and for w<wo, Hori et al[4] predict a region of multi mode operation characterized by mode competition noise. Finally, for small Ivl and w>wo, we expect a region of bistabiIity and hysteresis. Since w is a ratio of the self and cross suppression terms from the rate equations, its value is independent of the overall strength of the gain suppression terms. In the simplified analysis presented in this section, the behavior of the system is relatively independent of the absolute strength of the nonlinear terms in (2) and (3). This is not true for the more general, numerical analysis to be presented in the following sections. The case w>wo implies that the off diagonal coefficient of the nonlinear interaction is larger than the diagonal coefficient. In the next section, we shall see that the numerical solutions to the nonlinear rate equations give rise to bistability and hysteresis in precisely this region.

Page 396: Semiconductor Device Reliability

5 r----------------,

4

3: 3

2

t = 0.5 u = 20

Bistability /Hysteresis

o ~--~----~----~----~----~ -10 -6 -2 2 6 10

v

393

Figure 12. Computed plot of bifurcation set of the Fokker-Planck potential. Note the double cusps, joined at the apexes.

To understand the behavior of the laser modes in this phase space, we examine the surfaces of constant Fokker-Planck potential in a three dimensional S1-v-w space. The steady state rate equations (2) and (3) may be substituted into (1) to eliminate S2 yielding an expression in S1 and the control parameters: '

12 {I W}I 12 X=-y +y --(u+u)--O --(u-u)O+-O 4 2 2 2 4'

(7)

where we have defined the variables

u(w-I)+u(w+ I) 0- 2 ' w -1

(8)

x = f3 I U and Y = f3 I S ~. Recognizing the lack of a cubic or linear term in S1> it is evident that this is simply a quadratic equation in Y whose solutions are given by the usual expression.

Plots of the solutions for Yare shown in Figure 13. In the single mode regions of phase space, the square of one of the modal photon densities is complex while the other is real and positive, thus accounting for the single mode nature of those regions. In the regions of mode competition noise, we have two real roots for S12. However, one of these real roots is generally negative, yielding only one real root for 51' In the bistability /hysteresis region, one also finds two real roots that are usually both positive. Therefore, two stable values will exist for each modal intensity, and the value actually observed will depend upon the direction of entry into the bistable region. For some values of the potential however, there will exist subsets of this region in which the smaller of the real roots is negative. Physically, this corresponds to a disappearance of one mode in that respective subset of phase space, in qualitative agreement with some recent, unpublished observations of Suo

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100

30

100 ~

lOV' Mode ~'" Imaginary

~ 1 2 ~" Sl /' I \ .... ,,;

on Y \, .......... -----......... / , "//

\ ;' \ I I I 'I 1I ' , ': \,

W=2.1

....

0.1

0.01~ ____ ~ __ ~~ ____ -7L-__ ~ -10 -5 0 5 10

V

Figure 13. Plots of IYI (proportional to S12) versus v in the region w>wo. In plot A, two positive roots for Y exist in the entire bistable region, indicating the existence of two stable solutions. However, plot B shows a subset of the bistable region in which the smaller root for Y becomes negative, indicating that only I stable solution exists in that subset.

8. Rate Equation Theory: Static L-I Calculations

The experimental effects discussed in the previous sections were modeled using the rate equations of Yamada and Suematsu[5] and Asada and Suematsu[6] (hereafter called the YAS rate equations). These equations arise from a density matrix calculation, originally applied to semiconductor lasers with undoped active regions. However, they have been found useful in describing the behavior of lasers with heavily doped active regions as well. The Y AS equations contain third-order gain suppression terms, which involve an N by N matrix (N being the number of longitudinal modes under consideration). These equations bear some resemblance to the simplified rate equations presented in the previous section. However, the nonlinear term contains the square of the photon densities in the YAS equations, while the photon densities are raised to the third power in the previous section. As a result, it is not as convenient to write the associated Fokker-Planck potential in closed form. In general, all the elements of the gain suppression matrix are nonzero; therefore all the longitudinal modes are explicitly coupled in the photon rate equations as well as via the customary modal sum that appears in the electron rate equation. The Y AS equations are stated as follows:

Page 398: Semiconductor Device Reliability

dS.. C ( (I) K ,,(3) S) COIN ---- am -a l,,- lLalJ'tll w • It S +--dt n"" • .. 1:,

dN I, N c" ( (I) K ,,(3) S) -==-----L am - lLamnW,. It S dt eV "t, n"".. • ..

395

(9)

(10)

where Sm is the spatially averaged photon density of the mth longitudinal mode, N is the spatially averaged electron density within the active region, and c, e, and neq have their usual meanings. If is the forward drive current, Kl gives the strength of the third order gain suppression term, while Cm is the average probability of spontaneous emission into the mth longitudinal mode. V is the volume of the active region, and a.h represents the distributed cavity losses. The parameter w. is the angular frequency for the nth longitudinal mode, while 1:, is the radiative recombination lifetime. The quantity a~)is the first order gain of the mth longitudinal mode at wavelength Am and is given by

(11 )

where N~I) is the electron density required for positive, first order gain, Ao is the carrier density coefficient of gain, y is the parabolic gain curvature parameter, and 'kp is the wavelength corresponding to maximum first order gain. One important feature of this analysis, attributable to Hori et al[4], is the explicit assumption that thermal and carrier density effects cause a linear variation in 'kp with forward current, expressed as

( 12)

where 0, is the drive current coefficient of peak gain wavelength, 0 I is the temperature coefficient of peak gain wavelength, T is the junction temperature, and 'kpo is the peak gain wavelength at T=Oo Celsius and 0 drive current. The third order gain suppression matrix elements a!,;'~ are given by

(13)

where N~3)is the electron density required for positive, third order gain suppression and 'k". and A n are the wavelengths of the mth and nth longitudinal modes, respectively. The parameter 1: I is the intraband relaxation time for electrons in the conduction band. The parameter Wpo is the angular frequency associated with the wavelength 'k po • The quantity <R~h> is the mean square dipole moment formed between an electron and a heavy hole in the conduction band. For the 1.3 micron laser materials, we use the value 4.1 X 10-67

coul2m2• The coefficient arrays a~)M and a!,;'r represent spatial averages of the active region gain, weighted by the spatially-varying intensities of the modal electric fields as follows:

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396

f CCr) 1 E mer) 12 d 3 r a(l)M _ =---:-_____ _

m flEmcr)12d3r (14)

f C(r)IEm(r)1 2IE.(r)1 2 d3r a(3)M _ "--,..--________ _

m. f IEmCr)12IE.er)12d3r (15)

The function Cer) is the normalized gain as a function of position within the active region (C(r) - 1 at all points free of defects), and E mer) is the electric field associated with the mth longitudinal mode. The integration is performed over the volume of the active region. Since the thickness and width of the active regions in many high speed laser structures are comparable to or less than the characteristic diffusion length for carriers, the integration reduces to a single dimension parallel to the optic axis. This is the mechanism we use to simulate defects caused by ESD. The procedure was inspired by the results of Sim et al[3], who report that ESD stress induces regions of nonradiative recombination in which the gain is either locally reduced or rendered negative. We find that this procedure allows spatial inhomogeneities in the laser gain to perturb the gain vs. wavelength characteristics via the matrix elements given in equations (14) and (15). This yields significant departures from the parabolic gain profile of the mathematically-perfect laser.

Figure 14. Axonometric plots of third order, gain suppression matrix from Equation (15) (plotted on vertical axis) versus matrix indices (plotted on horizontal plane). Both plots were calculated using the same sets of laser parameters, except for the spatial distribution of defects in the active region. The upper plot was generated by placing all the defects near one facet, while the lower plot was generated by placing the defects within the active region in such a way as to selectively attenuate modes 4, 5, and 6. Each defect is approximately 0.1 microns in length and locally reduces the spatial gain by 10%.

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397

Figure 14 shows axonometric plots of (l~JM versus matrix indices m and n for two cases which exhibit approximately the same average gain but different spatial distributions of gain within the active region. Since this matrix appears as a factor in (13), it is evident that the laser spectrum will be a sensitive function of the spatial gain distribution.

Equations (9) - (IS) form a set of coupled, implicit, nonlinear differential equations. They were numerically solved in the static case by a modified Newton's method the details of which are given in Appendix I. For the limiting case in which the third order gain suppression (K1) and thermally-induced peak wavelength shift (" ,) vanish, we obtain results identical to those published by Lee et al[ll]. In the general case, however, both of these effects considerably modify the spectrum at all currents above threshold. For example, Figure IS shows theoretical, modal L-I results for two lasers with identical parameters except for the values of (l~JM , which are given by Figure 14. It is evident that the spatial distribution of defects within the active region exerts considerable influence upon the shape of the modal L-I characteristics.

7.-----------------------, Defect at facets

6

-s 5 0.. 8 -S 4

A 0

8

:i: 3 0">

::J 2 2

.... ::l

.e-::l

0 .... ..c 0">

::J

1

°0~--~10~~2~0~~3~0~~4~0~·~50 Drive Current (mA)

10 Defects in interior

8 8

6

4

2

00 //

10 20 30 40 50 Drive Current (mA)

Figure 15. Computed, modal L-I relations for two lasers with identical parameters except for (l~r , which are given in Figure 14 above. Modes 4, 5, and 6 in plot B are about a factor of 100 below the peak amplitude of mode 7. Note the distorted shape, the increased peak width, and the steeper transition between modes 3 and 7 of plot B. This distribution of defects produces a laser with two mode groups for drive currents in the 20-30 rna range.

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398

One can observe many similarities with the overall behavior of the experimental data given in Figure 5. In general, the first order rise and fall of the modal L-Is is driven by the current-dependence of "- p' However, this trend is strongly affected by the intermodal coupling contained in the gain suppression term of the photon rate equations. In the limiting case of large 1:, relative to "-po/w, the values of «~1 drop rapidly as one departs from the main diagonal of the matrix. This yields an approximately diagonal «(3) matrix which effectively decouples the modes in the photon rate equations and is mathematically equivalent to the gain suppression terms used in the dynamic rate equation work of MiIler[12]. For small (10-13 sec or less) values of 1:, , the modes are strongly coupled in the photon rate equations, and the modal L-I characteristics can develop multiple peaks, plateaus, shoulders, and other complex features very similar to those of our data. Efforts to calculate an optimum set of laser parameters and matrix elements yielding a best fit to our experimental data are currently in progress.

Figure 16 shows calculated values of total dL/dl versus I for the same two lasers. It is evIdent that the strong differences in modal behavior appearing in Figure 15 nearly cancel when one sums over the modes to produce the total L-I and its derivatives. Significant differences between the two plots did not become apparent until the vertical scale of the flat part of the plots above threshold was magnified by a factor of about 200. The features appearing in the magnified dL/dl above threshold are not artifacts of the numerical algorithm but are instead remnants of the modal behavior that did not quite sum to zero when the total L-I was computed. These features are similar to the residual features seen in the dL/dl data of Figure 4 after the high frequency noise is removed. Nevertheless, it is apparent that the modal L-I results for the two lasers show a much larger difference than the aggregate characteristics, which is in good agreement with the trend exhibited by the ESD stressing data of the previous sections. In other words, the experimental and theoretical results are both consistent with the hypothesis that subdamage stressing perturbs the spatial distribution of gain in the active region and produces large changes in the modal L-I characteristics but usually smaller changes in the total L-I and its first derivative.

12

-0 10 "--1 8 -0

-0 <P 6 "0 :i 4 ~ 0 () 2 10.6815 20 45

00 10 20 30 40 50 Drive Current (rnA)

Figure 16. Computed plots of total dL/dl versus I for the same two lasers. The derivative characteristics appear to be identical in the main plot. However, when the vertical sensitivity is increased by a factor of 200 as shown in the inset plot, one can readily discern the differences. The sudden increase in dL/dI at 28 ma is associated with the transition between modes 3 and 7.

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399

The computed value of dL/dI generally declines with increasing current above threshold, except for the abrupt increases that occur near the longitudinal mode transition currents. This decline is mathematically attributable to the third order gain suppression term. The negative slope in dL/dI above threshold is a direct function of the value of K1• It should be emphasized that this effect is purely a function of the photon density and operates on the same time scale over which the photon densities change. While our data almost certainly contain such effects, the experimental dL/dI above threshold is also affected by a thermal degradation in photon lifetime which operates over a much longer time scale. For this reason, comparisons between experimental and theoretical dL/dI would not be meaningful and were not attempted.

14

12

:; 10 .e- 8

A ::l 0

:E 6 0> ~ 4

2

00

10'9

10'8 '" =u

B ~ld7 '" "'0

ld 6

Tolo I l-I ---------.. ,t; i

6

2 /8 30 50

2.70

2.69 ~ 'iii

2.68~ ...

2.67·~ ... 0

U

2.66 .....-- Threshold

10 20 30 40 502 .65

Drive Current (mA)

Figure 17. A. Computed plot of total L-I and modal L-I for modes 2 through 8 of a 10 mode laser. This laser is essentially a single mode laser due to the large side mode suppression ratio, however, it becomes double-moded at the gain crossing currents. B. Computed plots of total d2L/dI2 and carrier density versus drive current. A small, positive constant was added to the second derivative to enable its illustration on a logarithmic scale. Note the peaks that occur in the second derivative at the mode transition currents and the cusps that occur in the carrier density at the same values.

When relatively large values of Kl (implying a strong nonlinearity) and large y(implying a short cavity) are used, the longitudinal mode transitions become very steep. Figure 17 A shows a composite plot of the total and modal L-I characteristics for such a laser, while Figure 17B shows the calculated d2L/dI2 and carrier density versus If. The large peak in the second derivative is the usual peak occurring at threshold. However, the smaller

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400

peaks above threshold are associated with the longitudinal mode transitions and occur at the same currents. Below threshold, the carrier density (N) exhibits the usual linear dependence upon Ir. However, with the nonlinear gain suppression term added to the rate equations, N no longer saturates at threshold, but rather continues to increase (although at a lower rate than below threshold). The carrier density also exhibits cusp-like behavior at the longitudinal mode transition currents.

In order to explore the possibility of bistability and hysteresis contained in the data of Section 5 and also observed by Nakamura et al[l3], calculations were performed with several sets of a~r. The use of large "t, relative to "'po/m ensures (in the absence of defects) that the diagonal elements a~~)M are larger than their off diagonal nearest neighbors. This corresponds to the w<wo case of Hori et al[4], in which they predict that no bistability or hysteresis will occur. Our results are in agreement with this prediction. However, unlike Hori et ai, we did not observe any regions of laser parameter space in which perfectly-single mode operation was obtained. The most likely reason for this is that our analysis also includes spontaneous emission terms, which have the mathematical effect of spreading the power among many longitudinal modes. In addition, our analysis includes both the photon rate equations and the carrier density equation, while Hori et al focused upon the photon rate equations, which removes one degree of intermodal coupling. With moderate values of "t, and an appropriate structure to a~,.>M , the more interesting case of w>wo was also investigated. In this region, Hori et al predict bistability and hysteresis for the ideal two mode laser. Our results are shown in Figure 18.

We report regions of bistability and hysteresis whose width is a direct function of the off diagonal to diagonal matrix element ratio, as shown in the above figure. Given a pair of modes for which the corresponding w exceeds Wo (or equivalently, a~~)M < 1 ), a bist­ability/hysteresis region occurs in the current range for which the gains of the modes are approximately equal. However, due to the intermodal coupling, the abrupt jumps in modal intensity affect not only the two modes involved in the gain crossing but also all of the remaining modes. The relative size of the intensity shift appears to be an inverse function of the wavelength separation. That is, the two modes directly associated with the gain crossing exhibit the largest intensity jumps, while modes further separated in wavelength from the gain crossing experience a smaller percentage change in intensity. This effect is similar to that shown in the data of Figure 10. The cusp-shaped plot of Figure 18B is analogous to a subset of the bifurcation set plotted in Figure 12. The quantity a~~)M is analogous to the reciprocal of the variable w in Figure 12. Furthermore, while a variation in laser drive current affects the total laser gain (the variable u from Hori et al[4]), its largest effect is upon v, the difference in gain between two neighboring modes. Thus the bistable region of Figure 18B corresponds to the bistable (w>wo) region in Figure 12, and the boundaries of the bistable region of Figure 18B are equivalent to the upper two branches of the bifurcation set of Figure 12. The two mode analysis presented above therefore provides direct insight into the numerical results.

Page 404: Semiconductor Device Reliability

1021r---------------~~------, Mode 6

+-

E-102o Mode ::J

4/~\ ! 1 A 0

.,/ \

....•.... /..... ~ .. \\

.. ; ......... .. ! .. - ....... - .... - ........

1d8~.~!~~~~~~~~~~~--~ 10 25 30 35 40 45

Drive Current (rnA)

32.-----------------------. Bifurcation Point

C28 B t

::J u26 Q)

> ;§24

Monostable Region

22~-L~~ __ ~~~~~ __ ~ 0.6 0.7 0.8 0.9

()((3)M 66

401

Figure 18. A. Computed plots of bidirectional, modal L-I characteristics for two longitudinal modes. Mode 6 exchanges power with a neighboring mode at the borders of the bistable region, while mode 4 is separated in wavelength from the mode transition. The bistability & hysteresis were created by reducing the value of (l~~)M. B. Computed plot of boundaries of bistable region versus (l~~)M. This parameter is equivalent to the reciprocal of w. The upper and lower boundaries meet in a cusp at (l~~)M = 0.94.

These abrupt jumps in modal intensity appear in the total dL/dI as a kink precisely at the longitudinal mode transition current, as shown in Figure 19. The size of the kink is a direct function of the matrix elements and shrinks to zero as the local w drops below woo It is significant that Chinone et al[14] reported the experimental observation of kinks in the dL/dI characteristics of MCSP AlGaAs lasers precisely at the drive currents cor­responding to mode hopping events and nowhere else. Although they explained their results with a saturable absorber model, in our opinion the mathematical essential is a nonlinear element in the modal kinematics. Such nonlinear terms will modify the expressions for the associated Fokker-Planck potential in such a way as to create a nonempty bifurcation set and the possibility of modal catastrophes. The abrupt changes shown in Figure 19 illustrate a well known difficulty with the heavy filtering or smoothing of dL/dI data to reduce noise. In addition, these same considerations justify the use of a minimum size current step in the discrete sampling measurement of an L-I characteristic. Small current steps will render a kink more visible, provided that one does not use heavy spatial averaging ( ego a four or more point algorithm) to compute the derivative.

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402

13r---------------------.

12

1 1

1.0 0.9 0.8

Versus CX(3)M 66

10 ( 10 20 30

Drive Current (mA)

40

Figure 19. Computed plot of total dL/dI versus drive current above threshold for three values of o:~~)M. The case of o:~~)M < 1 is equivalent to w>wo in the two mode theory of the previous section. The bistability and hysteresis associated with this case can be accompanied by kinks in the dL/dI characteristic.

One final feature of the static, theoretical analysis warrants inclusion in this discussion. The Catastrophe Theory results mentioned above state that a nonempty bifurcation set will exist if and only if the determinant of the Hessian matrix vanishes in some subset of phase space. This provided a means to calculate an expression for the bifurcation set of the simplified two-mode case given above. Although the Fokker-Planck potential function associated with the YAS equations cannot be conveniently written in closed form, its Hessian is exactly given by the Jacobian matrix of the Y AS equations, which one must compute to solve the YAS equations by the modified Newton's method. Therefore, with a small additional expenditure of computer time, we calculated the Hessian determinant as a function of drive current, with typical results shown in Figure 20.

10 29

10 9 -c 10 25 0

c

E 10 21 .... Q)

CD 10 17 Cl

c 30.1 0 10 13 rn rn Q)

10 9 :r:

10 5 0 10 40 50

Drive Current (rnA)

Figure 20. Computed plot of determinant of Hessian matrix versus forward drive current. Note the sharp drop at threshold and the local minima at the longitudinal mode transition currents. The inset shows an expanded view of the sharp drop toward zero at a mode catastrophe.

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403

We find that the determinant is largest at zero forward current and drops at threshold. Furthermore, it contains local minima at each noncatastrophic, longitudinal mode transition current. Mathematically, this implies that the Hessian determinant does not have real roots at the more gradual mode transition events (ie. those for which the local w parameter is less than wo). As predicted by Catastrophe Theory, it drops toward zero and exhibits a real root at the boundary of the bistable regions.

The large changes in the Hessian determinant affect the computer time required for the calculations. The convergence rate of the algorithm is a direct function of the Hessian determinant. Consequently, below threshold, the algorithm typically achieves a fractional error of 10-10 in 3 or 4 iterations. As the calculation proceeds through threshold or through a gradual mode transition event, the number of iterations required for the same accuracy may double or triple. However, as the calculation passes through a longitudinal mode catastrophe and out of a bistable region, the Hessian determinant passes through a zero, and the required number of iterations may exceed 100.. To further complicate matters, the discontinuity of the solution to the Y AS equations at the mode catastrophe is usually larger than the radius of convergence, causing the algorithm to wander aimlessly through phase space. To avoid this problem, correctional procedures were developed to detect mode catastrophes and predict an improved starting point, as covered in the Appendix. The changes in convergence rate at threshold and at thl~ mode transition currents bear a direct analogy to the critical slowdown of convergence in certain types of Monte Carlo simulations[l5] of physical systems. Such simulations generally exhibit a drastic increase in the computer time required to reach thermal equilibrium as one passes through a thermodynamic phase transition. In fact, parallels have been drawn between thermodynamic phase transitions and the onset of bistability in lasers (See Hioe and Singh[lO]). This work suggests that such parallels are accurately drawn, particularly in the case of longitudinal mode kinematics of semiconductor lasers

9. Rate Equation Theory: Ohtsu Plots

The VAS rate equations were also used to construct theoretical Ohtsu plots by taking advantage of the explicit temperature and current dependence of x. p contained in (12). For a given set of laser parameters, the Y AS equations were used to generate theoretical, modal L-I characteristics at several temperatures. The regions of the 1-T plane dominated by the various longitudinal modes were then isolated by the same procedure given above for the experimental results. Two such theoretical Ohttsu plots are given in Figure 21. These were generated with sets of laser parameters that were identical except for the defect bearing arrays (l~)M and (l~JM defined in (14) and (15).

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404

30~--~-------r----rr-..-----~

____ 28

u

~26 Cl ........ 0.24 E Q) I-

22

30~~-.--------------------~

----.28 u

~26 Cl ........ 6

20~~--~--~2~5~~3~O--~3~5~~40~

Drive Current (rnA)

Figure 21. Theoretical Ohtsu plots for two lasers with identical parameters but different spatial distribution of defects in the active regions.

The modal regions are shaped roughly like parallel bands running diagonally across the plot. The slope of these regions is determined by the ratio (J,I (J I. It should also be mentioned that the shape of the plots is caused by the ratio y / K 1 used to generate the plot. When the gain suppression term is dominant, as in Figure 21, the shape of the modal regions is very sensitive to the defect bearing arrays a~)M and a~~M. One can then observe two or more geometrically distinct regions in which a given mode dominates the spectrum. The deformation of the constant modal regions due to the laser threshold condition is clearly visible. In addition, however, one can also discern the effects of the differing defect distribution. Figure 21B shows a much smaller width for mode 4 and a much larger width for mode 6 than Figure 21A. This is purely due to the spatial distribution of defects, which was specifically designed to change the modal weights in the L-I characteristics. In fact, with a slight change in the distribution, no regions in the 1-T plane would exist in which either mode 4 or mode 6 dominate the L-I results. Such "missing modes" have been reported by Ohtsu, and our work suggests that this observation can be explained by the distribution of defects or gain perturbations within the active region.

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405

10. Rate Equation Theory: Dynamic L-T Calculations

Having observed the strong effect of the spatial gain distribution upon the static, modal L-I characteristics, it is worthwhile to explore the effects of spatial gain upon the modal dynamics during pulse modulation. This section presents a limited analysis of these effects for the purpose of opening a theoretical inquiry into the changes in performance and reliability as lasers degrade.

The dynamic solution of (9)-(15) was generated by starting with a point on the static L-I characteristics reported in a previous section and using the fourth order Runge Kutta algorithm to integrate the VAS equations assuming a step function change in forward current. As in the work of Miller[l2], the time step was dynamically controlled to limit the maximum change per step in the modal intensities to 0.5%. In addition, an independent upper limit of 2.0 picoseconds was placed upon the size of the time step. It was found that this procedure ensured stability of the algorithm. Although the time scale over which the modal quantities changes was much slower than 2 picoseconds, a small time step was necessary to ensure numerical stability due to the "stiffness" of the rate equations. This work also used an expression for peak gain wavelength A. p that follows the current and yields an instantaneous change with the current step. This effect is weaker in real lasers, because some of the current dependence of A. p is thermal in origin and some is driven by the carrier density. Therefore, the thermally-induced portion of the A. p variations will respond to changes in If over a much longer time scale (microseconds or longer) than we consider in this work, while the carrier density portion will change over time frames comparable to the ones in this simulation. Integration of the VAS equations for I microsecond at a time step of I picosecond would obviously require I million iterations. Even a fourth order algorithm cannot avoid a prohibitive accumulation of numerical errors after I million iterations. For this reason, among others, the thermal portion of the response of A. p to the step change in If was accelerated to permit an exploration of the effects of the spatial gain function upon the dynamic, modal response.

Our results for total light output versus time (L-T) and gain suppression strength (K1)

agree well with the results of Miller[l2]. The amplitude and decay time constant of the leading edge ringing are sensitive functions of Kh and much of the ringing was suppressed when the size of the nonlinear term was a few percent of the linear terms in the VAS equations. Since the leading edge ringing typically observed is considerably less than that obtained when we neglect Kh our dynamic results enabhl us to estimate that the minimum probable value for Kl is about 5.0E-25 m6kg/farad sec.

For the purposes of this study, the most significant parameters that affect the modal dynamics are the defect-bearing arrays a~,.>M and a~)M., The primary quantity we wish to explore in this section is the effect of environmental stress upon the modal dynamics. Accordingly, the dynamic rate equations were solved with several sets of parameters that were identical except for the spatial gain function. Results are shown in Figure 22.

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406

1022r-------------------------.

.... :::J

E-1020 :::J o :L:1019 0>

::::i 1018

No Defects

\',//~ / J

I --- All Modes ~/ ; .--------- Mode 7

On~ / 17 Defect. ___ ~/

10 10- 12 10- 11 10-10 10-9 10-8 10-7

Time (Sec)

Figure 22. Calculated light output versus time for two lasers, one free of defects and one with a defect introduced near a facet. The plot shows both the total power output and the output from mode 7. In each case, a current step from 10 to 30.5 rna was applied at time O.

The dynamic results contain three dominant parameters, all of which have been affected by the introduction of the defect. First, it is evident that the turn-on delay for the degraded laser is substantially larger than that of the defect-free laser. The reason for this is that the degraded laser threshold is slightly larger than the pre-step current of 10 rna, while the defect-free laser threshold is slightly smaller than 10 rna. Consequently, the defect caused a small threshold increase, which produced a large change in turn-on delay. Second, it is clear that the leading edge ringing frequency is somewhat higher in the defective laser. Third, the slower overshoot on the defect-free laser has essentially disappeared in the defective laser, implying that the defect has changed the mode com­petition dynamics on the nanosecond time scale as well as on the leading edge. The steady-state total power output and the mode 7 power at 30.5 rna do not show large changes resulting from the introduction of the defect. The static modal L-I characteristics however, exhibit large changes resulting from the defect.

11. Discussion

The large variations in modal L-I characteristics observed even among the lasers from one supplier suggest that the modal L- I data can be envisioned as a type of "fingerprint" which may be associated with a particular laser at a particular point in its lifetime. Furthermore, the large changes in modal L-I data that occur with ESD stress and the well-known spectral changes that occur with aging indicate that laser degradation is a complex physical process and that the modal behavior is a sensitive probe into that process. The overwhelming weight of experimental evidence indicates that environmental stress affects semiconductor lasers primarily by inducing the nucleation or growth of several types of defects, either within the active region or at the facets. Our data, particularly those shown in Figures 7,8, and 10 support the hypothesis that reverse-bias ESD stress produces effects that are nonuniform among the longitudinal modes. The direction of wavelength shift with ESD suggest that a TE/TM mode shift is not a likely effect of the stress. In addition, our observations of the far field pattern and the correlations between the L-I-V and R-I-V data do not suggest that catastrophic failure is caused by a transition to a higher order

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transverse mode. While we cannot dismiss the possibility of a small admixture of a higher transverse mode field pattern, the far field appears to be dominated by the lowest order transverse mode. The hypothesis most consistent with our data is that the ESD stress induces nucleation or growth of defects within which the local gain is reduced.

The magnitude of the wavelength shifts at catastrophic failure should also be mentioned. Figures 8 and II both show evidence of peak wavelength shift with stress. Typical shifts below the catastrophic failure voltage are 1-2 nm. However, in passing through the failure voltage, shifts as large as 20 nm are observed. Essentially all of the commercial lasers continue to lase after being stressed above the failure voltage. Although the operating current will increase substantially at the failure voltage, the system driver may still be able to operate the laser at an acceptable output power (See the 1400 volt curve from Figure I for an example.) Laser drive current alarm levels in the system may be set as high as 5-10 times the laser threshold current. Thus the laser of Figure I may not trigger an alarm after stressing at 1400 volts. However, after suffering a shift in the tens of nanometers, the laser wavelength may change to a value for which the fiber dispersion has substantially increased, leading to an unacceptably high bit error rate. This potential problem will be exacerbated at higher bit rates and could be especially severe in transmission equipment. Even at stress levels below the failure voltage, one may expect some changes in the bit error rate. The dynamic rate equation work strongly implies that a variation in the spatial gain function will change the topography of the arrays given in equations (14) and (15). This, in turn, will change the modal dynamics during modulation with a possibly harmful effect upon the bit error rate.

We unintentionally observed some evidence of latency in approximately 5% of the lasers studied. Within 5 to 10 minutes after stressing at a voltage 10-20% below the expected failure voltage, some of the lasers spontaneously failed during DC drive at about I.S times the threshold current. These lasers had exhibited acceptable total L-I-V data prior to spontaneous failure and after the most recent ESD stress event. A harbinger of this type of stress response was observed in 0.8 micron lasers by Sim et al[3], who reported a substantial increase in the rate of degradation with aging in some of their lasers after receiving a square pulse stress event. Further experiments to investigate this effect are currently in progress.

The Y AS rate equations take account of spatial inhomogeneities in the active region and are well suited to model the effects of environmental stress upon semiconductor lasers. We have explored several hundred sets of laser parameters in order to investigate their effect upon the theoretical, modal L-I relations. In general, the static Y AS equations can be least-square fitted to a given set of experimental, modal L-I data and can duplicate all of the features of the data not associated with dynamical effects (eg. mode hopping). Furthermore, the Y AS equations encompass a wide variety of anomalous, modal behavior by choosing parameters in an appropriate region of phase space. For example, we observed well-defined regions of phase space in which bistability, hysteresis, and kink phenomena occurred. These regions are directly analogous to equivalent regions in the phase space of the simplified, two mode laser model. A comparison of Figures 12 and 18B suggests that the bifurcation set of the Y AS equations is similar in shape to the upper cusp of the two-mode bifurcation set. The single factor with the most influence upon the shape of the static VAS solutions is the geometry of the arrays a~r and a~)M. These arrays contain the information about the spatial correlation between the local gain function and the electric field distributions of the various longitudinal modes. Placing arrays of small, shallow defects at the nodes of a given longitudinal mode field distribution will suppress all other modes, converting the laser into a single mode device. On the other hand, placing the same defects at the antinodes of the modal electric field will suppress that mode only. If one places a single, large (10 microns in length) defect near a facet and calculates the

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modal L-I relations as the gain within the defect drops and becomes negative, one can begin to observe bistability and kinks in a laser that was previously free of those phenomena. This compares favorably with the experimental development of those phenomena during stressing as shown in Figures 4 and 10.

The results of Section 10 suggest that the growth of defects during the lifetime of a laser or during ESD stress can exert a large impact upon the dynamic response to a current step. The changes induced by the defect growth are nonuniform among the various longitudinal modes. The settling time increased for some modes and decreased for others as the defect was added. In a transmission application, it is plausible that these changing mode dynamics would influence the bit error rate in a manner that would be highly dependent upon the individual characteristics of the defect distribution.

12. Conclusions

Human Body Model (HBM) ESD stressing has been applied to commercial, 1.3 micron, Fabry-Perot semiconductor lasers for the purpose of investigating the degradation of the various laser parameters with stress. Failure voltages varied by a factor of about 5 among the four types of commercial lasers tested. Total L-I-V data generally show little change with stress until the failure voltage is reached, at which point the laser threshold typically increases by 50-100%, and the quantum efficiency drops by 20% or more. Some lasers developed kinks within the operating current range during the stressing. The static L-I characteristics for each longitudinal mode exhibit significant changes in both the amplitude and drive current associated with the various peaks and valleys at stress levels well below the failure voltage. In addition, some lasers exhibited bistability and hysteresis in the individual L-l characteristics of each longitudinal mode after stress. A small percentage of our lasers spontaneously failed after 5-10 minutes of post-stress, DC biased operation at 50% above threshold. Modal plots in the temperature-current plane exhibited significant change with ESD stress below the failure voltage. Some of these changes are attributable to wavelength shifts, which became as large as tens of nanometers at the failure voltage. However, deformation of the modal regions was also observed, indicating a change in the power distribution among the modes with stress.

The laser characteristics were modeled by a rate equation analysis, including the effects of explicit modal coupling and gain suppression induced by a finite intra band relaxation time. Laser degradation with ESD stress was modeled as localized regions of reduced gain, which enter the rate equation analysis through spatial correlations with the modal electric field distribution. Static L-I results for a 10 mode laser successfully emulated the features of the modal L-I data. The analysis predicts that the addition of defects to the laser below the catastrophic failure level induces large changes in the modal L-I characteristics but small changes in the total L-I-V results, in good agreement with the experimental data. Bistability, hysteresis, and kinks were observed in the numerical results under certain mathematical conditions and interpreted within the context of Catastrophe Theory and the steady-state Fokker-Planck potential. The bifurcation set of the nonlinear rate equations was calculated and shows cusp-like geometry, in agreement with the predictions of a simplified, two-mode laser model. The dynamic rate equation calculations suggest that the introduction of defects will change both the modal dynamics and the total laser step response in a fashion that is strongly dependent upon the physical size and location of the defects.

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Acknowledgements

We wish to thank P. Su, R.S. Koelbl, T.P. Lee, S.E. Miller, M.M. Choy, R. Fagerstrom, P.W. Smith, P.W. Shumate, and S.G. Menocal for helpful discussions. In addition, we extend our appreciation to B.A. Unger and P.A. Link for their strong and unflagging support and inspiration.

Appendix: Solution of Y AS Equations Via Modified Newton's Method

Newton's Method consists of an iterative procedure for finding the roots of a general, nonlinear equation. The method may be easily extended to multidimensional systems of equations and works well, provided that the original trial solution is sufficiently close to the actual solution and that the system of equations is reasonably well behaved. Let us write the system of equations as follows:

i= I, N (A I)

If Wn is the trial solution after n iterations, then the value of Wnd is given by

(A2)

where Y n is the solution vector to the linear system

(A3)

f is the vector whose components are given in (AI), and J is the Jacobian matrix of the equation set (AI). The superscript (n) indicates that the Jacobian matrix and f. are evaluated using the trial solution at the nth iteration to predict the correction term Y n •

The elements of this matrix are simply the first partial derivatives of the f. with respect to the dependent variables. For a 10 mode laser, the II dependent variables are the 10 modal intensities (Sj) and the carrier density (N). The f. are the right hand sides of the VAS rate equations given in (9) and (10). The implicit N-dependence of the first and third order gain parameters a~)and a~1must be considered in computing the derivatives of the Y AS equations. A unique solution to (A3) will exist unless the determinant of J vanishes. This limitation presents difficulties only on the bifurcation set of the Y AS equations, where the determinant does, in fact, vanish. In practice, if there is any separation, however small, between the specified drive current and the current associated with the zero of J, the algorithm will converge (albeit slowly). The iterative process is terminated when the largest component of I Yn1w.1 drops below 10-10. The modal L-I calculations are initiated by solving the Y AS equations at a point where the rate and radius of convergence are both maximal, this point being located near zero forward current. With one solution point in memory, the first solution point is used as the initial trial solution at the next value of forward current, and the entire array of solution points is computed by this procedure.

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Special attention is required to circumvent a number of computational problems that may arise in practice. It is possible for the algorithm to enter the mathematically acceptable but physically unrealistic region in which one or more of the modal photon densities is negative. The most common cause for this is an excessively large value of N. To avoid this problem, we test the sign of the photon densities after each iteration. If any are negative, we decrement N by 5 to 10% and return to the original trial photon densities. A somewhat more difficult problem may arise if the Jacobian matrix becomes iU­conditioned. In this case, the Gaussian Elimination algorithm used to solve (A3) produces large errors. This problem was eliminated by substituting the computed Y n back into (A3) and calculating the fractional error between the computed f and the actual value of f. If excessive errors are encountered, the value of Y n is corrected by repeating an iterative procedure developed by Jacobi until the error is within acceptable bounds. A third problem that can arise is the trapping of the algorithm in a self -perpetuating oscillation between two or more points in phase space. One can recover from this problem when it occurs by keeping a history of the fractional errors. A properly-functioning algorithm should yield an error that is a monotonic decreasing function of the iteration number. If an oscillation develops, the error will instead be a periodic function of the iteration number. This is easily identified, and a different trial solution is then used. Our most difficult numerical problem was encountered when the control trajectory crosses the bifurcation set of the Y AS equations. In this case, the difference between the solution values on either side of the bifurcation set is usually much larger than the radius of convergence of the algorithm. The mode catastrophe at the bifurcation set is always accompanied by a rapid increase in the power of one mode and the rapid decrease of another. Our solution to this problem consists of identifying the two modes that are exchanging power and extrapolating an initial trial solution from the previous solution point by adjusting the powers of the exchanging modes with a suitable multiplicative factor. A moderate number of iterations are attempted, and if convergence is not forthcoming, another factor is tried. This procedure has been found to be successful in about 90% of the cases and has enabled us to solve the Y AS equations through violent discontinuities in modal power.

References

l. Casey, H.C. and Panish, M.B., HeterostructllTe Lasers, Chapter 8.

2. Kumada, S., Shimizu, H., and Itoh, K., "Lifetimes of 800 nm-Wavelength GaAIAs Semiconductor Lasers", International Reliability Physics Symposium Proceedings 21, 153-9 (1983).

3. Sim, S.P., Robertson, M.J., and Plumb, R.G., "Catastrophic and Latent Damage in GaAIAs Lasers Caused by Electrical Transients", J. Appl. Phys. 55, 3950-5, (1984).

4. Hori, R., Endo, K., Kono, E., and Sakurai, T., "Mode-Transition Characteristics and Tunability of an AIGaAs Laser", J. Appl. Phys. 60, 2231-7, (1986).

5. Yamada, M. and Suematsu, Y., "Analysis of Gain Suppression in Undoped Injection Lasers", J. Appl. Phys. 52, 2653-64, (1981).

6. Asada, M. and Suematsu, Y., "Density-Matrix Theory of Semiconductor Lasers with Relaxation Broadening Model - Gain and Gain-Suppression in Semiconductor Lasers", IEEE J. Quant. Electr. QE-21, 434-42, (1985).

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7. Chemelli, R.G. and DeChiaro, L.F., "The Characterization and Control of Leading Edge Transients From Human Body Model ESD Simulators", EOS/ESD Symposium Proceedings, EOS-7, 155-62, (1985).

8. Ohtsu, M., Otsuka, Y., and Teramachi, Y., "Precise Measurements and Computer Simulations of Mode-Hopping Phenomena in Semiconductor Lasers", Appl. Phys. Lett. 46, 108-10, (1985). See also Ohtsu, M., Teramachi, Y., Otsuka, Y., and Osaki, A., "Analyses of Mode-Hopping Phenomena in an AIGaAs Laser", IEEE J. Quant. Electr. QE-22, 535-43, (1986).

9. For example, see Saunders, P.T., An Introduction to Catastrophe Theory, Cambridge University Press, (1980).

10. Hioe, F.T. and Singh, S., "Correlations, Transients, Bistability, and Phase-Transition Analogy in Two-Mode Lasers", Phys. Rev. A 24, 2050-·74, (1981).

II. Lee, T.P., Burrus, C.A., Copeland, J.A., Dentai, A.G., and Marcuse, D., "Short-Cavity InGaAsP Injection Lasers: Dependence of Mode Spectra and Single-Longitudinal-Mode Power on Cavity Length", IEEE J. Quant. Electr. QE-18, 1101-13, (1982).

12. Miller, S.E., "On Fluctuations and Transients in Injection Lasers", IEEE J. Quant. Electr. QE-20, 1032-44, (1984).

13. Nakamura, M., Aiki, K., Chinone, N., Ito, R. and Umeda, J., "Longitudinal-Mode Behaviors of Mode-Stabilized AlxGal_xAs Injection Lasers", J. Appl. Phys. 49, 4644-8, (1978).

14. Chinone, N., Kuroda, T., Ohtoshi, T., Takahashi, T. and Kajimura, T., "Mode-Hopping Noise in Index-Guided Semiconductor Lasers and its Reduction by Saturable Absorbers", IEEE J. Quant. Electr. QE-21, 1264-70, (1985).

15. DeChiaro, L.F., An Experimental And Theoretical Inyestigation of Magnetic Ordering In Yttrium Iron Garnet, Dissertation, Stevens Institute of Technology, (1979).

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RELIABILITY TESTING OF PLANAR InGaAs AVALANCHE PHOTODIODES

MASAHIRO KOBAYASHI and TAKAO KANEDA Fuj itsu Limited Compound Semiconductor Division 1015 Kamikodanaka. Nakahara-ku. Kawasaki 211 Japan

ABSTRACT. Accelerated high temperature aging tests have been conducted to investigate a reliability of planar InGaAs avalanche photodiodes for long wavelength optical transmission systems. A burn-in screening at 200 deg.C has been found to be effective on removing weak population. From aging tests at 175 deg.C and 200 deg.C wear-out distribution due to degradation of dark current was observed and the activation energy was 1.0 eV. The estimated median life at an ambient temperature of 50 deg.C exceeds 100 millions hours. Total device hour of 750 thousands hours has been achieved without any failure at test temperatures of 150 deg.C and 125 deg.C. which indicate a small random failure rate.

1. INTRODUCTION.

InP/InGaAs avalanche photodiodes CAPDs) have been widely utilized in the front-end of receivers of most long-haul high-bit-rate optical transmission systems operated at 1.3-um or 1.55-um.

Reliability of InP/InGaAs APDs is one of the most important points for actual use. To assure electrical stability and long durability. the device is substantially required to be a planar configuration having an effective guard ring structure. We have developed planar "buried structure" InP/lnGaAs APDs by using two-step liquid phase epitaxy CLPE) on a (111) A faced InP substrate [1J-[3J. The "buried structure" provides a large breakdown voltage tolerance of the guard ring and thus gives an excellent performance.

In this paper. we will report a result of a comprehensive reliability testing of the buried structure InP/InGaAs APDs. The test is composed of two steps. In the first step. life test had been carried out for investigating failure mechanism and failure distribution and determining an appropriate burn-in condition. The second reliability testing was conducted to verify long-term stability of the APDs.

413

A. Christou and B. A. Unger (eds.). Semiconductor Device Reliability. 413-421. © 1990 Kluwer Academic Publishers.

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In the following section the device structure and the fabrication process are briefly described. Results of the first step of reliability test are shown in Section 3. Discussion on the failure mechanism is given based on the failure analysis in Section 4. Development of burn­in screening and the results of the second-step life-test for screened devices are also presented in that section.

2. DEVICE STRUCTURE AND FABRICATION.

Two types of devices with different photosensitive areas (50um and SOurn in diameter) have been used in this study. The first step of the reliability testing was conducted for SO-urn-diameter APDs. Since the fabrication technologies and the device structure are all the same with only exception of the photosensitive area diameter, the results are considered to be equivalent and adaptable to 50-urn-diameter devices. In the second-step test the reliability was confirmed by using both 50-um­diameter and SO-urn-diameter devices.

A cross sectional view of the planar buried structure InP/InGaAs APD is shown in Fig.l. The two-step LPE technique enables a complete embedment of the n-InP multiplication layer into the low carrier concentration InP layers. Moreover, the periphery of the active p-n junction (abrupt junction) is covered by the guard ring p-n junction formed by ion inplantation (graded junction). A combined effect of difference in carrier concentration and difference in p-n junction profile brings large breakdown voltage tolerance of the guard ring region to the active region.

In the first LPE growth, n-InGaAs light absorption layer (carrier concentration of 5xIO-15/cc and thickness of 3.0um), n-InGaAsP intermediate bandgap layer (5xlO-15/cc, O.4um), and n-InP multiplication layer (2.5xlO-167cc, 2.5um) are grown on a (lll)A faced InP substrate. The n-InP layer is chemically etched into a mesa shape with a diameter of about SO-urn. At the second growth a low carrier concentration InP layer is overgrown onto the mesa after a slight melt-back procedure. A flat surface of the epitaxial wafer after the growth can be achieved by a proper growth condition.

Cadmium (Cd) thermal diffusion and beryllium (Be) ion implantation are used to make the active and the guard ring p-n junction, respectively. A silicon-nitride (SiNx) film deposited by a plasma enhanced CVD (P-CVD) is used for a diffusion mask and the film is retained on the InP surface for passivation. AR-coating film is also formed by P-CVD SiNx film.

Ti/Pt/Au electrode was used for the p-type contact material. The n-type electrode is formed by Au-Ge. The APD chip is hermetically sealed into a precision packge in dry nytrogen ambient.

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Electrode (TI/PtJAu) p+-lnP Guard ring

~ l---l, L ! : r-------~I I if J • I I

_D=_IDf'_.l

ySINX

_ n- - InP j2nd Epi. ....--n--lnP

-n - InGaAsP 1st E i. -n -lnGaAs p

-n - InP Buffer

_(III) A n+ -lnP Sub.

Fig.l. Cross section of the buried-structure InP/InGaAs APD.

3. LIFE TEST.

415

For the first step of the reliability testing, aging test at three elevated temperatures had been conducted. The objective of the test was to investigate failure mode, failure distribution and consequently to determine the burn-in screening condition. In this section, the result of the first-step-test is described.

3.1. Test Conditions.

Accelerated high temperature aging test had been performed at three temperature levels (200 deg.C, 175 deg,C, and 150 deg.C). 41 samples of 80-um-diameter devices were used in this step. All of them were selected from the same wafer after initial measurements of optical and electrical characteristics.

At the elevated temperature levels, the samples were operated under breakdown conditoins which were achieved by driving APDs with constant reverse current of 100uA. The test conditions are summarized in Table.l. During the tests, breakdown voltage and dark current were measured at room temperature. These two parameters are considered to be the most sensitive ones to observe device degradation.

Table.l. 1st-step life-test condition.

Temperature Current Sample Test time ==============================================

200deg.C 175deg.C 150deg.C

100uA 100uA 100uA

16 10 15

1000 hrs. 4000 hrs. 6000 hrs.

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3.2. Test Results.

Figure 2 shows the time dependence of dark current for APDs tested at 200 deg.C. Dark current were measured at 90% of the initial breakdown voltage. so change of dark current at exactly the same reverse voltage had been monitored during the test.

The time-to-failure versus percent of cumulative failures for three temperature levels are plotted in Fig.3 on a log-normal graph. The end-of-life is defined as the time where the dark current exceeds 200nA or the breakdown voltage changes more than 1 volts from the initial data. A week population is observed at an early stage of the aging test and is followed by a main population. At 200 deg.C and 175 deg.C, the main population of failures is composed of the devices that showed gradual increase of dark current. They show relatively good obedience to the log-normal distribution with a standard deviation of about 0.5. The main population at these temperatures are consequently considered to be a wear-out failure. Median lives at 200 deg.C and at 175 deg.C are estimated to be 750-hours and 3500-hours, respectively. At 150 deg.C, although two devices failed at an early stage, remained devices showed good stability within the test period of 6000 hours.

Median lives are plotted against reciprocal temperature as shown in Fig.4. From an interpolation of the median lives obtained from 200 deg.C and 175 deg.C tests, the thermal activation energy of wear-out failure is tentatively estimated to be about 1.15 eV. The extrapolated median life to the actual operating temperature, for example at 50 deg.C, exceeds 100 millions hours.

10 5

<' 10 4 .s m >

10 3 C1I ci -'" C

10 2 ~ 5 u

~ 10' '" C

10 0 0 500 1000 1500

Test time (hrs.)

Fig.2. Dark current (measured at 0.9VB) variations during the 200 deg.C aging test.

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~

99'-~T~(ft.OCM)~"N-----'-------'--------'

- 95

~ 90

• 200 16 "'175 10 0150 15

t!! .a 'iij

70 -CI) 50

> :;:: 30 as :; E 10 ~

___ - __ -o=t>

150"C

0 5

1 10 10' 10' 10' 10'

Time to failure (hours)

Fig.3. Log-normal plot of time-to-failure versus cumulative failures for APDs tested at 200. 175, and 150 deg.C.

Temperature (Oe)

10' ,---'=2'T'00'-----'1:r50"--_---';10"'-0_-, 10·' ,--------------,

Ea=1.15 eV

5 10' .c:

'li' o Worst case plot -

initial

417

10' 2.0 2.5 50 100

Reciprocal temperature (10'/K)

Fig.4. Arrhenius-plot of median lives from 1st-step life-test. Median life of 150 deg.C test is the worst case value estimated by sigma=0.5.

Reverse bias (V)

Fig.5. Change of I-V characteristics as a function of aging time for the device tested at 200 deg.C.

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4. FAILURE MODE ANALYSIS AND DISCUSSION.

4.1. Early Failure.

The devices of week population showed a "sudden failure" characteristics with respect to dark current and some of them appeared a shift (decrease) of breakdown voltage at the failure. Only one device that failed at 200 deg.C test within 10 hours showed an evidence of a dielectric breakdown of the SiNx film at the outer edge of Ti/Pt/Au electrode.

Although any defect couldn't be visually detected after removal of the passivation film and slight etching of the surface of the InP layer, dark current of the degraded sample was almost recovered to the initial value after the etching treatment. This experiment suggest that the failure was originated at the surface of InP layer.

For all early-failed devices vibration of dark current were distinctively observed at the initial measurement. Degree of the vibration was only a few nano-Amps at 0.9VB of reverse bias and increased at higher reverse voltage. The behavior was considered to be correlated with a microplasma that initially existed and localized at the periphery of the guard ring junction.

Chin et. al. [5J reported the failure mechanism initiated by a microplasma in a planar p-i-n photodiode. They concluded that overstress by temperature and reverse bias accelerated the degradation and shortened the p-n junction resulting in a sudden increase of dark current and a shift of breakdown voltage. The same degradation mechanism can be presumed for the early failure. We consider that a higher electric field of APDs due to a larger bias strongly trigger the degradation and the failure is observed in the early stage of the aging test.

4.2. Failure Analysis for Main Population.

The failure mode of the main population can be classified into surface failure as well as the early failure mode because only degradation mode observed was an increase of dark current. Even after the device degradation, changes in the multiplication characteristics were not detected and, for some sample devices, the multiplication noise was examined but no change was also found within the measurement uncertanty.

Dark current characteristics as a function of aging time is illustrated in Fig.5 for a degraded APD at 200 deg.C test (ID was degraded to 800nA after 1000 hours of aging). Dark current at 0.9VB remains nearly constant for 300 hours while the dark current at low-bias region gradually increases. After 500 hours, the dark current increased in the wide range of reverse bias. Since the vibration phenomenon of dark current as measured in the weak devices was not observed even after 500 hours of aging, we exclude the microplasma initiated failure mode. The possible mechanism of the increase of the dark current is an accelerated degradation of the interface between InP and SiNx at the periphery of the guard ring. As reported by Tashiro et.al.[5J, hot hole

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injection into the SiNx film is considered to deteriolate the surface. MIS diodes were prepared by using the same passivation process and

the same structured n-type wafer. Bias-temperature (B-T) stress of 150 deg.C and -60V (metal electrode was negatively biased to the wafer) was applied for 100 hours to the MIS diode. We confirmed not only positive charge transfer into the SiNx but also increase of interface state density from the C-V measurement after the B-T test.

The dark current characteristics was also measured at elevated temperature range before and after the aging. The dark current at 20V and 0.9VB as a function of reciprocal temperature is plotted to distinguish the component of the dark current. The result is shown in Fig.6. At the initial measurement the activation energy of the dark current at 20V is estimated to be 0.68eV (half of the band-gap of InP) which indicates the InP surface generation-recombination (g-r) current at low-bias region. After 1000 hours of the aging test the activation energy changes to about 0.20eV. The dark current at 0.9VB shows the same activation energy. The fact can be linked to the I-V characteristics at 1000 hours shown in Fig.5. where the dark current was increased in the whole range of the reverse bias. Another APD showing comparatively slight degradation (ID was increased to 300nA) also showed a lower activation energy of dark current at 20V.

The results indicate that an interface state is induced by the hot hole injection and it becomes a dominant source of the increased dark current.

Temperature (OC)

10 • .--__ 1,5.;;..0 __ 1,0.:....0 __ -=5;=-0 __ --,

Ea = after 1000 hrs.

0.20~ n""D

0.45e~ ~ 20 V

10·"l..------''-------'------' 2.0 2.5 3.0 3.5

Reciprocal temperature (10 3/K)

Fig.6. Arrhenius-plot of dark current at 20V and 0.9VB before and after 1000-hours aging at 200 deg.C. (The same device as shown in Fig.5)

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4.3. Development of Burn-in Screening and 2nd-step Life-test.

Though the thermal acceleration for the early failure is not clear from the first-step test. the proportion of week population is about 15% at each temperature test. We can estimate a burn-in screening condition at 200 deg.C for 48 hours (2 days) for eliminating the week devices (see Fig.2).

To further examine the burn-in screening condition. we additionally tested 73 pieces of 80-um-diameter APDs at 200 deg.C and 100uA. The change of dark current after 48 hours of burn-in exhibited a distinct distribution of acceptable devices. The change of dark current of these devices were almost within 5nA. The maximum allowable change of dark current was then determined to be 10nA from the result.

The second step of the reliability test was conducted by using the screened devices to confirm the effectiveness of the burn-in screening and the long-term stability. 54 pieces of 80-um-diameter APD and 105 of 50-urn-diameter devices had been tested at 150 deg.C or 125 deg.C. The test results are listed in Table.2. Total device hour of 750 thousands hours has been achieved without any failure. We can predict a small failure rate of the buried-structure InP/InGaAs APDs.

Table.2 Summary of 2nd-step life-test.

Device Test condition Type Lot Temp. IR

80-um- A diam. B

C D

50-um- E diam. F

5. CONCLUSION.

G H I

150deg.C 100uA 150deg.C 100uA 150deg.C 100uA l50deg.C 100uA

150deg.C 100uA 150deg.C 100uA l25deg.C 100uA 150deg.C 100uA 125deg.C 100uA

Sample Test time Number of size (hrs.) failures

13 13 10 18

13 30 30 15 15

2000 hrs. 2000 hrs. 2000 hrs. 3000 hrs.

2000 hrs. 7000 hrs. 7000 hrs. 6000 hrs. 6000 hrs.

o o o o o o o o o

Accelarated high temperature aging tests of planar buried-structure I nP/InGaAs APDs were conducted in two steps to examine the device reliability. Two failure modes were observed at the first-step life­test. Both failure modes were classified into surface failure. Micro­plasma site which initially existed at the periphery of the p-n junction was considered to be the source of early failure. The wear-out failure was predicted to relate to the InP/SiNx interface degradation and to be arised by hot hole injection under a high electric field.

Page 423: Semiconductor Device Reliability

421

The burn-in screening at 200 deg.C was shown to be effective to remove early failure and to achieve long-term stability. From the second-step life-test we have achieved 750 thousands hours of device hour without any failure and have demonstrated a high reliability of the planar buried-structure InP/InGaAs APDs.

ACKNOWLEGMENT.

The autors would like to thank T. Shirai, H. Machida, and K. Satoh for thier helpful discussions and assistance.

References

[1J Yasuda,K., Kishi,Y., Yamazaki,S., Nakajima,K., and Kaneda,T. (1984) 'InP/InGaAs buried-structure avalanche photodiodes', Electron. Lett., vol.20, no.4, 165-166.

[2J Kobayashi,M., Yamazaki,S., and Kaneda, T. (1984) 'Planar InP /InGaAsP/ InGaAs buried-structure avalanche photodiode', Appl. Phys. Lett., vol.45, no.7, 759-761.

[3J Kobayashi,M., Machida,H., Shirai,T., Kishi,Y., Takagi,N., and Kaneda, T. (1987) 'An optimized GalnAs avalanche photodiode with low noise and large gain-bandwidth product', in OFC/IOOC'87 Tech. Dig., 36.

[4J Chin,A.K., Chen,F.S., and Ermanis,F. (1984) 'Failure mode analy­sis of planar zinc-diffused InO.53GaO.47As p-i-n photodiodes' , J. Appl. Phys., vo1.55, no.6, 1596-1606.

[5J Tashiro,Y., Taguchi,K., Sugimoto,Y. ,Torikai,T., and Nishida,K., (1983) 'Degradation mode in planar structure InO.53GaO.47As photo­detectors', J. Lightwave Techno., vol.LT-l, no.1, 269-272.

Page 424: Semiconductor Device Reliability

STATUS OF COMPOUND SEMICONDUCTOR DEVICE RELIABILITY

W. T. ANDERSON AND A. CHRISTOU Naval Research Laboratory Washington, DC 20375

ABSTRACT. A review is made of compound semiconductor device reliability from the period 1980 to the present. Emphasis is placed on technology based on field effect transistors (FETs). Many reliability studies were made of small signal GaAs FETs in the 1970s and of GaAs power FETs in the 1980's; a substantial reliability base exists for these devices. How­ever, there remains a lack of reliability data for GaAs devices such as digital ICs, MMICs, and heterojunction transistors (HEMTs, HBTs). Future directions for high reliability lie in device designs to reduce channel and junction temperatures, reduction in interdiffusion and ion migration between metal/semiconductor layers and between semiconductor layers, and in the development of high temperature stable Schottky barrier metallizations and Ohmic con­tacts.

1.0 INTRODUCTION

A comprehensive review of compound semiconductor device reliability was published in 1981 [1]. Since then a number of reviews have appeared including GaAs FET reliability at Bell Telephone Laboratories [2], various GaAs device and IC problems [3], and subsurface burnout mechanisms [4]. The present contribution is intended to serve as an update, with emphasis on life test results. A number of published results of high temperature storage relia­bility studies have appeared, but there is evidence that these can give overly optimistic relia­bility predictions and such studies will not be included. As has been pointed out [2], it is important in reliability life testing to stress the devices as near the actual operating conditions as possible and to measure the degradation in the important figures of merit of the device. Obvious examples of bias dependent failure mechanisms are electromigration, field assisted ionic migration, and subsurface burnout. Particularly for high power devices, it is important to stress the devices under high frequency operation and to measure the degradation of a high frequency figure of merit because it has been found that DC and RF degradation are not always correlated [2].

2.0 LIFETEST RELIABILITY STATUS

Recently published reliability studies will be discussed below including small signal GaAs FETs, GaAs power FETs, monolithic microwave integrated circuits (MMICs), digital

423

A. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 423-437. If) 1990 Kluwer Academic Publishers.

Page 425: Semiconductor Device Reliability

424

ICs, and heterojunction devices. A number of as yet unpublished reliability results from our laboratory and from the ESPRIT Program will also be included. Other increasingly important reliability aspects such as radiation effects [5-7], electrostatic discharge (ESD) [8,9], high power pulse [10], and high humidity [2,11] are beyond the scope of this paper.

2.1 Small Signal GaAs FETs

A reliability study of Al gate GaAs FETs was made at Bell Telephone Laboratories which used a total of 1500 FETs and included high humidity effects [12]. Because of the renewed interest in Al metallization by GaAs IC manufacturers to use "proven Si-like fabrication methods," this work continues to provide much useful information. Accelerated high temperature reliability life tests were carried out with and without bias at the tempera­tures 80, 180, 220, 250, 275°C. The results are shown in Table 1. Two types of failure mechanisms were discovered, both of which were related to the Al gate: 1) Au-AI phase for­mation, 2) Al electromigration. Both types of failure mechanisms were bias sensitive and aging without bias resulted in an overly optimistic lifetime prediction. The long term degra­dation in both DC and RF characteristics were measured and these were found not always to be correlated. Thus, basing lifetime predictions on an easily measured DC parameter, e.g., drain current, can lead to erroneously long lifetime predictions in the RF parameters that are important in applications, e.g., gain or noise figure. As shown in Table 1, the median time before failure (MTBF) at a channel temperature, (Tch ) of 60°C was 1 X 107 hours for those devices that failed by Au-AI phase formation ano 4 X 107 hours if the failure was by AI elec­tromigration. For both failure mechanisms the activation energy was 0.8 eV. The lifetime prediction was made at Tch = 60°C because the expected application for these devices was in a radio relay module where the ambient temperature was expected to be 50°C. In other applications, and particularly for power devices, the channel temperature during normal operation is expected to be in the range of 120 to 130°C.

In a more recent study of low power GaAs FETs intended for digital applications [13], devices with Ti/Pd/Au gates were aged under DC bias at channel temperatures of 245, 260, 275, 290, and 310°C. Degradation was evident in a decrease in the drain current at zero gate bias, iDSS , a decrease in the pinchoff voltage, Vp ' and an increase in drain to source resis­tance, RDS ' These changes were more rapid compared to devices stored at the same tempera­tures unbiased. As shown in Table 1, the MTBF at a channel temperature of 100°C was found to be 2 X 109 h based on a 20% decrease in iDSS ' DLTS revealed no new traps intro­duced by high temperature bias stressing but the carrier concentration was found to have decreased. It was concluded the failure mechanism was gate interdiffussion into the active channel, i.e., a "sinking gate," in that the edge of the depletion region follows the implant profIle deeper into the active channel during high temperature aging under bias. The activa­tion energy for this process was measured as 1.6 eV.

2.2 GaAs Power FETs

As part of a power FET development program at Bell Telephone Laboratories, devices were DC bias stressed at channel temperatures of 210°C and 250°C [14]. Degradation was observed in the drain current and gain of the devices with failure defined as a 5 % decrease in output power. Based on these two temperature points a worst case MTBF of 8 X 106 hours was predicted at a channel temperature of 110°C. Degradation was attributed to decrease in mobility and saturated velocity.

Page 426: Semiconductor Device Reliability

Dev

ice

MT

BF

(ho

urs)

1 C

hann

el t

emp.

(0C

)

AI

gate

GaA

s F

ET

1-

4 X

10

7/6

0

GaA

s di

gita

l IC

FE

T

2 X

10

911

00

Ti/

Pd/

Au

gate

GaA

s P

ower

FE

T

8 X

10

6/1

10

GaA

s P

ower

FE

T

1 X

10

6/1

30

AI

gate

GaA

s P

ower

FE

T

1.4

X

106/1

30

Til

Al/

Ti

gate

GaA

s P

ower

FE

T

1 X

10

7/1

30

Ti/

Ai

GaA

s P

ower

FE

T

6 X

10

"'/12

5 I

x 10

7/8

0

GaA

s P

ower

FE

T

2 x

10711

25

GaA

s P

ower

FE

T

8 x

1~/1

25

GaA

s M

MIC

2

x H

Y'/1

25

Til

Pt/

Au

gate

0.7

,an

gat

e 9

x 1~

/120

G

aAs

HE

MT

0.3

,an

gat

e (1

.0 e

V)

3 x

HY

'112

0 G

aAs

HE

MT

0.3/

Lm

gat

e 2

x 10

"'/12

0 G

aAs

HE

MT

0.3

,an

gat

e 3

x 10

"'/12

0 ~aA-,HEM'I'

. ---

Tab

le 1

. G

aAs

Dev

ice

Rel

iabi

lity

Stud

ies

Tes

t co

ndit

ions

F

ailu

re m

echa

nism

s (E

a)

Au-

AI

phas

e fo

rmat

ion,

AI

elec

trom

igra

tion

, D

C b

ias

(0.8

eV

)

DC

bia

s si

nkin

g ga

te (

1.6

eV)

Tch

=

245

, 26

0, 2

75,

290,

310

°C

DC

bia

s m

obil

ity

and

satu

rate

d ve

loci

ty d

ecre

ase

Tch

=

210

, 25

0°C

(1

.2 e

V)

DC

bia

s A

I ga

te o

pen

and

burn

out

(BO

) (1

.0 e

V)

Tch

=

240

, 27

0, 3

00

°C

DC

bia

s 30

% d

egra

dati

on i

n B

V G

D an

d B

O

Tch

=

240

, 27

0, 3

00

°C

Ti,

AlG

aAs

inte

ract

ion

(1.0

eV

)

DC

bia

s bu

rnou

t (1

.0 e

V)

Tch

=

240

, 27

0, 3

00

°C

RF

at2

W

Die

att

ach,

gat

e vo

idin

g (1

.5 e

V)

Tch

= I

SO,

190,

225

°C

burn

out

RF

at

0.2

W

AI

gate

dif

fusi

on i

nto

GaA

s T

ch =

210

, 23

0, 2

50°C

le

adin

g to

bur

nout

(1.

2 eV

)

RF

at4

W

AI

gate

dif

fusi

on i

nto

GaA

s T

ch =

210

, 23

0, 2

50°C

le

adin

g to

bur

nout

(1.

2 eV

)

RF

at

1 dB

com

pres

sion

re

duce

d ch

anne

l is

olat

ion,

SID

voi

ding

, Tc

h =

228

, 27

3°C

an

d B

O (

0.5

eV)

DC

bia

s st

ress

ind

uced

tra

ps o

r si

nkin

g ga

te (

1. 5

e V

) TB

=

200

, 22

5°C

unbi

ased

st

ress

ind

uced

tra

ps o

r si

nkin

g ga

te (

1. 0

e V

) 20

0, 2

25,

250°

C

DC

bia

s st

ress

ind

uced

tra

ps o

r si

nkin

g ga

te (

1.1

e V)

TB =

ISO

, 17

5, 2

00°C

RF

at

1 dB

com

pres

sion

st

ress

ind

uced

tra

ps o

r si

nkin

g ga

te 0

.0 e

V)

T8

= 1

75,

200,

25

5°C

Ref

. (y

ear)

12 (

1978

)

13 (

1986

)

14 (

1982

)

15 (

1984

)

15 (

1984

)

15 (

1984

)

16 (

1986

)

17 (

1987

)

17 (

1987

)

Thi

s pa

per

(198

9)

22 (

1988

)

22 (

1988

)

22 (

1988

)

22 (

1988

)

.l>­

N

'-"

Page 427: Semiconductor Device Reliability

426

A number of different gate metallizations were investigated at NEC [15], including AI, Ti/AIITi, and Ti/AI gates. Devices with 0.5 ILm gate lengths were accelerated tested at chan­nel temperatures of 240, 270, and 300°C under DC bias. Failure was defined as a 30% decrease in the gate to drain reverse breakdown voltage, BVGv . The predominant failure mechanism depended on the type of metallization, as shown in Table 1, but all mechanisms had an activation energy of 1.0 eV. Ti/AI was found to be the most reliable gate metalliza­tion with an MTBF of 1 x 107 h at a channel temperature of 130°C.

In the first report of RF accelerated high temperature stressing [16], it was found that compared to devices stressed under the same conditions except with DC bias only without RF input, the DC stressed devices had longer lifetimes. Based on the failure criterion of a 1 dBm decrease in output power, the MTBF was predicted to be 6 X 1 if at a channel temperature of 125°C when operating at a power level of 2 W. An activation energy of 1.5 eV was deduced from the data for the two most common failures mechanisms of loss of die attach and gate voiding. However, many of the failures were by catastrophic burnout, another difference compared to DC stressed devices where nearly all devices fail by gradual degradation.

In fact in a similar study of 0.2 W and 4 W power FETs [17] at channel temperatures of 210, 230, and 250°C all the devices subjected to high temperature accelerated stressing under RF drive failed by burnout. The failure mechanism appeared to be Al gate diffusion into GaAs leading to catastrophic failure. Extrapolated MTBF values at a channel temperature of 125°C were 2 X 107 h for the 200 mW device and 8 X 106 h for the 4 W device, with an activation energy of 1.2 eV.

2.3 GaAs MMICs

There have as yet been no published results of MMIC reliability studies. To our knowledge the reliability test data taken at other laboratories has been taken under DC condi­tions only and with the failure criterion for gradual degradation defined in terms of a DC parameter. At NRL a limited study was made of the Texas Instruments two stage medium power MMIC type EG8014, that was a deliverable on a previous NRL manufacturing technol­ogy program. These devices were fabricated by Si ion implantation into lightly Cr-doped semi-insulating GaAs with 0.5 fLm long Ti/Pt/Au gates defined bye-beam lithography. The study was limited to a population of 7 devices, at each temperature, which were operated under 1 dB compression RF conditions at 170°C and 215°C base plate temperatures.

When high temperature stressed under these conditions, it was found there was a strong temperature dependence in the output power , Po, which decreased rapidly as the temperature increased. A typical example is shown in Figure 1 which shows the temperature dependence of the degradation in the total drain current, Iv, and Po following RF accelerated high tem­perature life testing at a base plate temperature, TB , of 215°C. The failure criterion adopted for these devices was a 20% or greater decrease in output power within the temperature range -55 to + 125°C. If, under DC life testing, only drain current degradation had been used as a failure criterion, the device would not have been judged to fail. In fact, at the accelerated stress temperature of 215°C the device might have been judged to be improving by bum-in to a higher current. However, the RF measurements show the device was rapidly degrading in output power. As the drain current had not degraded significantly out to 310 h, this indicates a large decrease in efficiency with the drain current beginning to take leakage paths. The

Page 428: Semiconductor Device Reliability

360 ,----;;:--------------, 460

340 10 -"AFTER 310h 440

320 AT 215"C 420

300 400 - ~~ ~ 260 INITIAL 360 g g~ -~ ~= =~ ffi 200 300 ~ ~ 180 280 i3 a.. 160 260z

5 140 240~ ~ 0 ~ 120 220...J

o 100 200g

80 TI MMIC EG 8014-34 180 >-60 P(=50mW,9.0GHz 160 40 Vo =6.0V,VG=-1.0V

20

140

120

00:--"--:":40:-'--::870 --'--c1~20::-'-C-:16~0-'--::2::0'0:-'-2::C470 -'--::2-::-:80=-' 100

BASE PLATE TEMPERATURE, T6 (0C)

427

Figure 1. Temperature dependence of drain current, ID , and Po degradation following RF accelerated high temperature life testing at TB = 215°C, failure by gradual degradation of Po by 31 % at 125°C.

degradation of this device is shown as a function of exposure time, Ie' in Figure 2. An increase in drain current and decrease in output power at the stressing temperature is typical of devices that failed by gradual degradation. Life test results for the 14 TI MMIC EG8014 are shown in Figure 3. All but three of the devices were held at ± 1 °C of the base plate tem­perature of 170°C or 215°C. The other three had varied as much as ±3°C from the planned temperature because of technical problems, but not for a significant amount of time, and this amount of temperature drift does not appear to have given rise to the scatter in the data in Figure 3. Approximately 50% of the devices failed by burnout while under high temperature RF life testing with the other 50% failing by gradual degradation Po by 20% within the tem­perature range of -55°C to 125°C. Median time before failure values were approximately 600h at 170°C and 220h at 215°C, assuming a lognormal distribution. Actual channel tem­peratures have not yet been measured, but based on the measured channel temperature rise above ambient in [16] for similar devices, the channel temperature is estimated to be 58°C above TB . An Arrhenius plot for these two data points (Tch = 228°C and 273°C) is shown in Figure 4. Under DC bias at room temperature the devices heat to TB = 50°C, Tch = 108°C. Extrapolation to Tch = 125°C results in the prediction of an MTBF of 2 X 104 h under RF drive in a module operating 17°C above room temperature. The corresponding activation energy is 0.50 eV. Failure analysis is not yet complete, but preliminary SEM micrographs and energy dispersive x-ray analysis indicate electromigration of AuGe ohmic contact metallization in the case of MMICs that degraded by a 20% power loss. The decrease in efficiency also indicates a decrease in channel isolation and consequent drain current leak­age paths. These results, although based on a small population and only two temperatures, are expected to be confirmed, to at least the same magnitude, when larger populations are tested later. However, the MTBF values and activation energy may change by as much as a factor of two or three when the channel temperatures are accurately measured. These meas­urements are considered to represent a worst case result.

Page 429: Semiconductor Device Reliability

428

5oo.---------------------------------,500

§" 400

S ~=--==-----~~--__ 0.0

rL 300

~ t-----------------__ a. 200 TI MMIC EG 8014-34 I- P, = 50mW, 9.0GHz ~ VD=6V, VG= -1.0V

o 100t-________________________ .:..:Po~" 215D C

« 400S

~ 300 ~

a:: ~ U

200 ~ ~ C ..J

100 ~ 12

°O~·~------~,O----------~,O~O---------,~OO~

'e' EXPOSURE TIME (H)

Figure 2. Degradation in ID and Po as a function of exposure time, te, following RF accelerated high temperature life testing at TB = 215°C, failure by gradual degradation of Po by 31 % at 125°C.

105

104

~ 103 oS w II: ::J ...J

~ 102

0 t-W ::;; F

10'

100

Te =170°C

.5 1 2 5 10 20 40 60 80 90 95 98 99.5

FAILURES (Cum %)

8

7

6

5

4

3

2

0

Figure 3. Time to failure vs cumulative failures for TI MMIC EG8014 RF accelerated stress life tested at base plate temperatures, TB , of 170°C and 215°C, assuming a lognormal distri­bution.

Page 430: Semiconductor Device Reliability

~ >--

0.5 - 4.0 SCALE, EA 0.2 - 0.5 SCALE, EA

400,-------+"----------'-+'------------,

350

300

250

200

150

100

50

25~~~~~~~~~~~~~~=L~~

.5

.4

.3

.2

102 103 104 105 106 10' 10· 109

TIME (hi

429

4.0 3.0

2.0 ., w

1.5 -' > .!!!->-

1.0 ~ 0.9 ~

w 0.8 z

0 0.7 ~

> ;:: 0.6 ~

0.5

Figure 4. Arrhenius plot of MTBF vs. channel temperature, Tch , for TI EG8014 MMICs accelerated stress life tested under RF operating conditions at Tch = 228°C and 273 °C, corresponding to an activation energy of EA = 0.50 eV.

2.4 Digital ICs

The only reliability life test results on digital integrated circuits that has appeared is a study by Giga Bit Logic [18]. FETs and ICs were subjected to DC bum-in at a channel tem­perature of 150°C and l000h wafer storage tests at 250°C. Because of the mild accelerated conditions used, in order to stay below temperatures where failure mechanisms may change, little degradation was observed. Thus activation energies and MTBF values were not meas­ured and the data was used to determine if there were any limiting reliability problems with the production methods used. It was concluded that no such reliability limitations exist for production of digital ICs for the commercial market.

2.5 Heterojunction Devices

2.5.1 HEMT Reliability Issues. In order to assess the present status of HEMT reliability, a universal plot has been made of mean time to failure (MTF) (20% decrease in IDss) as a func­tion of device channel temperature. Shown in Figure 5 is a summary of the discrete HEMT (or MODFET) reliability life tests [19]. Above a channel temperature of 200°C, the data shows a clear separation between depletion mode and enhancement mode structures. The extrapolated MTFs for enhancement mode HEMTs are of the order of 104 hours at a channel temperature of 110°C, while for depletion mode HEMTs, the extrapolated MTF is of the order of 105 hours. Above 200°C a different failur{: mechanism appears to be operating.

The difference in MTF between enhancemenlt mode and depletion mode HEMTs can only be due to the AlGaAs thickness and must be related to the degradation of the AIGaAs -GaAs interface. The integrity of the AlGaAs - GaAs interface and the degradation of such interface as it affects the reliability of such structures is shown in the reliability comparison between HEMTs and FETs. Figure 6 shows the MTF comparison of FET and HEMT relia­bility taken from controlled experiments [19]. The HEMT and the FET inverters consisted of

Page 431: Semiconductor Device Reliability

430

10' r--r--,--,----,---.,-----,

e " o =10' w II:

3 ~ 10'

12 w ::!l i= 10' z ~ ::!l

'0

.... NRL SAG-MODFElS ENHANCEMENT MODE

~CNETTESTS

o THOMSON CSF ENHANCEMENT MODE

• GOULD-DEPLETION MODE

o NRL SAG-MODFETS DEPLETION MODE

~~3Q~-~~-ZQ~-~1~~--~100~--~~

DEVICE CHANNEL TEMPERATURE ('CI

Figure 5. Discrete HEMT Reliability Life Test Results [19].

/

10

/ /

/ 0"

" " 0/

0" /

" ,P

6NRl HEMT INVERTERS DIE MODE

ONRl FET INVERTERS DIE MODE

Figure 6. Comparison of FET ICs with HEMT ICs [19].

exactly the same geometry and the depletion - enhancement mode inverters were of equivalent cross-sections. Shown in Figure 6 is a one order of magnitude difference in MTF between HEMT and FET inverters. The primary reason for the reliability difference must be the loca­tion of the two-dimensional electron gas (2-DEG) channel and the integrity of the AlGaAs­GaAs interface.

2.5.2 HEMT Reliability Materials Issues. A number of material changes occur in HEMT structures as a result of accelerated life testing. These changes have been assessed as part of an ESPRIT program [19] and will be discussed in the present paper. In terms of buffer layer quality, a broadening of the photoluminescence spectra has been observed as well as a build up of the MBE defect region as shown in Figure 7 [19]. This shows a comparison between high quality HEMT buffer layers and those after a 200°C - 24 hour accelerated life test. The build up of the MBE defect region may be the result of trap generation or donor migration into the buffer layer. Both phenomena would result in a decrease of transconductance. The second phenomenon which occurs is a decrease in sheet carrier concentration. Figure 8 shows the variation of sheet carrier concentration with gate voltage of depletion mode HEMTs [19J. There is a dependence on the spacer layer thickness and conduction band offset degra­dation on sheet carrier concentration. During accelerated life testing the degradation of the AlGaAs-GaAs interfacial quality results in deconfmement and a decrease in sheet carrier con­centration.

2.5.3 Modeling of HEMT Reliability. Theoretical calculations of the AlGaAs/GaAs heterojunc­tion [20J and calculated changes [21J based on the charge control model [22] are shown in Fig. 9. During accelerated life testing, the energy bands in AlGaAs may be lowered resulting in deconfmement. Once degradation of the AIGaAs-GaAs interface occurs, shallow donor states must be included in GaAs that increase conduction in GaAs. The reduction of the

Page 432: Semiconductor Device Reliability

2.06E 04,---------;;---------------, HIGH QUALITY GaAs

1. SPLITTING OF AD(e_h} 2. SHARP DOle_h) J. LOW INTENSITY M BE DEFECT

F.E.

I 1.9K M8E 79

FREQUENCY (em"'"

• BUILD UP OF ··MBE DEFECT·· WITH TEMPERATURE AND TIME

• BROADENING OF P.L. SPECTRA

431

Figure 7. Photoluminescent intensity vs wavenumber for HEMT buffer layers "as deposited" and after 200°C for 24 h [19].

x10tl

10r--'---'--~---'--------r---'

~ .£ ~ 8 2: o !i ~ 6 w CJ 2:

8 4 II: W a: II:

tS 2 t;; w l: rJ)

D·HEMT

Ndepl = 5x1010cm-Z

x=O.3 AT 12 K

Wsp=

OA

......,. ___ .. 75.1.

GATE VOLTAGE Vgs (V,

• SPACER LAYER THICKNESS DEPENDENCE

• EFFECT OF flEe DEGRADATION OF SHEET CARRIER CONCENTRATION

Figure 8. 2-DEG sheet carrier concentration vs gate voltage for D-mode HEMT before and after high temperature exposure [19].

Page 433: Semiconductor Device Reliability

432

Alx Ga1_xAs Ix < 0.31

~oo 200

1. ENERGY BANDS IN AIGaA. ARE LOWERED

100

2. SHALLOW DONOR STATES MUST BE INCLUDED IN GaA.

GaAs

Ns "" 5x10"cm-2

Ndepl"" 5xl01°cm-2

-- VARIATIONAL ........ NUMERICAL

200

3. WAVE FUNCTION PENETRATION INCREASES

400

Figure 9. Calculated energy band vs distance, Z, from AlxGal_xAs/GaAs interface before [20] and shift (- - -) after 200°C/24 h exposure [21].

AIGaAs energy bands results in wave function penetration into the AIGaAs donor layer through the spacer layer. Figure 9 shows the results of calculations using Fang-Howard wave functions [20] and the calculated [21] shallow donor state shifts, increase in wavefunction extent, and reduction of energy bands in the AIGaAs. This model would explain the MTF difference between enhancement mode and depletion mode HEMTs. Similarly, a charge con­trol model has also been applied to the HEMT in order to show the effectiveness of charge transfer during biasing [22].

2.5.4 Varian HEMT Reliability Study. In a study of HEMT reliability by Varian [23] 0.7 /Lm and 0.3 /Lm gate devices were accelerated life tested under a number of conditions including, RF operation, D.C. biased, and unbiased. The results are shown in Table 1 and it can be seen that the 0.3 /Lm gate device had a much shorter MTBF than the longer gate device indi­cating short channel effects may be present, because basically the same methods were used to fabricate the devices.

Failure analyses were performed on these HEMTs at NRL which included capacitance and conductance deep level transient spectroscopy (DLTS) measurements [24]. Degradation of HEMT during high temperature stress was evident in a reduction in drain current, pinchoff voltage, and gain accompanied by an increase in noise figure. Figure 10 shows a cross­section of one type of HEMT that was studied. The degradation of the DC drain current pro­duced by RF stressing a HEMT is illustrated in Fig. 11 where the temperature dependence of the drain current is shown for an unstressed and a stressed device. The stressed devices have a lower drain current than unstressed devices, and they have a different temperature depen­dence. For low gate biases, the drain current of an unstressed device increases as the tem­perature is lowered. This is consistent with what may be expected for a 2 DEG system as the

Page 434: Semiconductor Device Reliability

GATE 0.7 ~m

SOURCE 0 DRAIN

~_/~_--'-C_ ----''''-..IL------............ 500 A GaAs 7XIOIB

-400 A Al.26Ga.74As 2XlO18 ==;:::=======-50 )\ Al.26Ga.74As (undoped spacer)

"'- 2 D.E.G -O.B ~m GoAs (undoped)

:========::~AlAslGaAs Superlattice ..,/'1000 A GoAs (undoped)

--------SEMI-INSULATING SUBSTRATE

Figure 10. Cross-section of 0.7 pm Varian HEMT [23].

9.0 r--------------,

5.5 ~05V ~~O~T!~~~ED vGS 0 ~5C

·0.1

~~3----------------__ (a)

~ ~(b)

2.5 o

433

50 T(K) 450 50 T(K) 450

Figure 11. Drain current, IDS, vs temperature, T, of a 0.7 Jtm Varian HEMT before and after high temperature RF stress [24].

mobility increases as the temperature decreases. The drain current for a stressed device is more like that for the unstressed devices with a large:r gate bias where the 2 DEG is not well confined.

Current and capacitance DLTS techniques w(~re both used to study the background defect spectra of unstressed devices and to compare the merits of the two methods. All the data were recorded so that DLTS lines which point downward represent majority carrier traps. The data presented in Fig. 12 indicate that both current and capacitance DLTS reveal a single prominent majority carrier trap line near 220 K in unstressed HEMT devices. In addi­tion, the current DLTS for some samples contained a small positive going line near 320 K, which was not detected in the capacitance DLTS. The properties of the defect at 220 K indi­cate that it is the "DX" center which is normally found in AlxGa1_xAs. The signal to noise ratio for the current DLTS is higher than that for the capacitance DLTS, which indicates that the current technique is more sensitive than the capacitance method.

Current DLTS measurements on stressed devices revealed a new spectral feature not found in the unstressed samples as shown by the comparison in Fig. 13. While both devices shown here contain the "DX" trap, the RF stressed sample contains an additional feature. Since the peak goes in a positive direction, it would normally be identified as being due to a

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0.2 (a)

c:.J 6 8 0

~ <-0

-0.9

50

0.4 (b) UNSTRESSED

C"I CURRENT DLTS

6 ,....,

0 VGS=-0.3V >-< ;:::. <-0

-3.0

T(K) 450 50 T(K)

Figure 12. DLTS spectra of a 0.7 /tm Varian HEMT [24].

50 T(K)

VGS=-0.3V

CURRENT DLTS RF STRESSED 300 h at 225 C

450

450

Figure 13. Current DLTS spectra of 0.7 /tm Varian HEMT before and after high temperature RF stress [24].

minority trap, but it should not be possible to detect minority carrier traps, as minority car­riers are not injected during the filling pulse. The full nature of this center needs to be exam­ined, and for the present paper, it will be referred to as a "minority-trap-like feature." Simi­lar results have been observed in current DL TS studies of GaAs MESFET devices.

Capacitance DLTS measurements were made on the stressed devices to determine if they would also reveal the minority-trap-like feature. A comparison of the current and capacitance DLTS on a stressed device is shown in Fig. 14, which clearly indicates that the minority­trap-like feature is only found in the current DLTS. Since the capacitance DLTS is primarily

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435

1.5 0.1

Cal (b)

VGS=·O.3V N C\J

6 6 8 8 0 0

5 s <.0

<.0

-0.4 -0.7

50 T(K) 450 50 T(K) 450

Figure 14. Comparison of DLTS spectra of a 0.7 /LID Varian HEMT after high temperature RF stress [24].

sensitive to the area under the gate, while the current DLTS is sensitive to the entire channel between the source and drain, this comparison indicates that the minority-trap-like feature is associated with the portion of the channel not under the gate. Surface traps that are located between the gate and either the source or the drain c:ould capture and emit charge as a result of the bias applied to the gate, thus affecting the channel's conductivity, and thereby the result is a current signal. From the data taken to the present time, stress induced surface electron traps appear to explain the DL TS results and degradation of the devices better than an alterna­tive explanation of hole traps created at the AIGaAs/GaAs interface.

3.0 CONCLUSIONS

Two general conclusions can be made from the reliability data in Table 1: 1) RF stressed high temperature reliability tests result in lower MTBF predictions than either DC biased or unbiased reliability testing, and the number of burnout failures is much larger, and 2) HEMT reliability problems are real and solutions are needed if 10 year lifetimes can be relied upon at useful channel temperatures. Of course, much longer lifetimes can be expected for low temperature applications. Solutions should take the form of designing in reliability to reduce channel and junction temperatures. High temperature stable metallizations are needed for Schottky barriers and Ohmic contacts to reduct: interdiffusion and ion migration. It is unlikely that VLSI and ULSI circuits will be able to utilize the Au/Ge alloyed Ohmic contact. Therefore, non-alloyed contacts are needed as device dimensions shrink below 0.5 /Lm. A number of types of these contacts have been developed but their reliability has not yet been established.

REFERENCES

1. Davey, I.E. and Christou, A. (1981), "Reliability and Degradation of Active TIl-V Sem­iconductor Devices," in Reliability and Degradation, Semiconductor Devices and Cir­cuits, Howes, M.J. and Morgan, D.V., Eds. (Wiley, New York, 1981).

2. Irwin, J.C., (1982), "The Reliability of GaAs FETs," in GaAs FET Principles and Technology, DiLorenzo, J.V. and Khandelwal, D.D., Eds. (Artech House, Dedham, MA, 1982), pp. 353-399.

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436

3. Christou, A. (1989), "Reliability Problems in State of the Art GaAs Devices and Cir­cuits," Quality and Reliability Engineering International, 5, p. 37.

4. Anderson, W.T., Morgan, D.V., Buot, F.A., and Christou, A., (1988), "Subsurface Burnout Mechanisms in GaAs Devices," Quality and Reliability Engineering Interna­tional, Vol. 4, pp. 255-268.

5. Zuleeg, R., (1985), "Radiation Effects in GaAs Integrated Circuits," in VLSI Elec­troncis Microstructure Science, Vol. 11, GaAs Microelectronics, Einspruch, N.G., and Wisseman, W.R., Eds., (Acadamic Press, NY, 1985), pp. 391-436.

6. Anderson, W.T., Meulenberg, A., Beall, J.M., Kazi, H., Harrison, R.C., Gerdes, J., and Mittleman, S.D., (1987), "Radiation Induced Displacement Damage in GaAs Dev­ices," in Gallium Arsenide and Related Compounds, 1987, Christou, A. and Rupprecht, H.S. Eds., (Inst. of Physics, Bristol, 1988), pp. 471-474).

7. Anderson, W.T., Simons, M., Tseng, W.F., Herb, J.A., and Bandy, S. (1987), "Tran­sient Radiation Effects in AIGaAs/GaAs MODFETs," IEEE Trans. on Nucl Sci., NS-34, pp. 1669-1675.

8. Huang, C.L., Kwan, F., Wang, S., Galle, P., and Barrera, J. (1979), "Reliability Aspects of Small Signal GaAs FETs," Microwave J., 22, pp. 34-43.

9. Anderson, W.T. and Chase, E.W. (1987), "Electrostatic Discharge Effects in GaAs FETs and MODFETs," 1987 Electrical Overstress/Electrostatic Discharge Symposium Proceedings, pp. 205-207.

10. Anderson, W.T., Buot, F.A., Christou, A., and Amand, Y., (1986), "High Power Pulse Reliability of GaAs Power FETs," 24th Proc. 1986 Internat. Reliability Physics Symp., (IEEE, N.Y.) pp. 144-149.

11. Anderson, Jr., W.T. and Christou, A., (1980), "GaAs FET Failure Mechanism Result­ing from Exposure to High Humidity and Ionic Contamination," IEEE Trans. on Relia­bility, R29, pp. 222-231.

12. Irwin, J.C. and Loya, A. (1978), "Failure Mechanisms and Reliability of Low-Noise GaAs FETs," Bell Sys. Tech. J., 57, pp. 2823-2846.

13. Ogbonnah, D. and Fraser, A. (1986), "Reliability Investigation of 1 Micron Depletion Mode IC MESFETs," 24th Proc. 1986 Internat. Reliability Physics Symp. (IEEE, NY), pp. 132-137.

14. Fukui, H., Wemple, S.H., Irwin, J.C., Nichaus, W.C., Hwang, J.C.M., Cox, H.M., Schlosser, W.O., and DiLorenzo, J.V., (1982), "Reliability of Power GaAs Field Effect Transistors," IEEE Trans. on Electron Devices, ED-29, pp. 395-401.

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15. Katsukawa, K., Kose, Y., Kanamori, M., and Sando, S., (1984), "Reliability of Gate Metallization in Power GaAs MESFETs," 22nd Proc. 1984 Internat. Reliability Physics Symp., (IEEE, NY) pp. 59-62.

16. Russel, K.J. and Dhiman, J.K., (1986), "Power GaAs FET RF Life Test Using Temperature-compensated Electrical Stressing," 24th Proc. 1986 Internat. Reliability Physics Symp. (IEEE, NY) pp. 150-156.

17. Kashiwagi, S., Takase, S., Usui, T., and Ohono, T., (1987), "Reliability of High Fre­quency High Power GaAs MESFETs," 25th Proc. 1987 Internat. Reliability Physics Symp., (IEEE, NY), pp. 97-101.

18. Venkataraman, R. and Schaefer, J., (1986), "GaAs IC Reliability and Quality Assurance Handbook," (Giga Bit Logic, Inc., Newbury Park, CA).

19. ESPRIT 1270 Program (1988).

20. Ando, T. (1982), "Self-Consistent Results for a GaAs/AlxGa1_xAs Heterojunction: II. Low Temperature Mobility," J. of the Phys. Soc. Japan, 51, pp. 3900-3907.

21. ESPRIT 1270 Technical Memorandum (1988).

22. Halkias, G., Christou, A., and Dumas, J.M., (1989), "Charge Control in a Laser Pro­cessed Superiattice High Electron Mobility Transistor (LPHEMT), " Solid State Elec­tronics (to be published).

23. Varian Associates Inc. Final Report, (1988), "Reliability Study," Naval Research Laboratory Contract No. NOOO14-86-C-2547, Oct. 1986 - March 1988.

24. Magno, R., Shelby, R., and Anderson, W.T., (1989), "A DLTS Study of HEMTs Sub­jected to Lifetime Stress Tests," J. Appl. Physics (submitted).

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INVESTIGATION INTO MOLECULAR BEAM EPITAXY-GROWN FETs AND HEMTs

S. MOTTET and J. M. DUMAS Centre NationaL d'Etudes des TeLecomunications BP 40, 22300 Lannion France

ABSTRACT. An investigation into molecular beam epitaxy-grown FETs and HEMTs has been carried-out. Reliability life-tests have been driven on both AIGaAs/GaAs conventional and AIAs/GaAs superlattice HEMTs. Power MESFETs including an AIGaAs undoped buffer layer for electron confinement in the channel have been also studied. For all these devices the influence of laser desorption during the MBE growth process has been assessed in terms of performance improvements and stability of FET structures. Moreover, the main parasitic effects penalizing this large scale integration of HEMT-based ICs have been experimentally characterized and investigated together with the related modelling.

1. Introduction

Results presented in this report have been extracted from ESPRIT contract n° 1270 issues. This ESPRIT contract links FORTH, PLESSEY Res, UNIVERSITY OF WALES in Cardiff, ELLTEC S.A. and CNET. The presently studied MBE-grown devices (including Laser Processing) have been developped inside the abovementioned consortium.

It is of evidence that the future generation of both analog and digital integrated circuits will be based on high electron mobility transistor structures (HEMT). Consequently, parasitic effets penalizing the integration of such structure have to be comprehensively understood. Two major ambient temperature parasitics (kink and backgating effects) together with the collapse at low temperature are experimentally characterized.

Among the target of the consorsium, elimination of DX centers (responsible for the collapse) has been carried-out by developping a multiquantum wells donor layer. The laser process and the FET structures have been used to avoid, as well, kink and backgating effects. Moreover lifetest have been driven on the devices in order to validate the technological choises during operation.

2. Parasitic effects

Classical high electron mobility transistors (HEMT) present kink

439

A. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 439-453. © 1990 Kluwer Academic Publishers.

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effect. This effect also appears during ageing. The kipk effect is enhanced under back-biasing the substrate (figure 1). This experimental result let us to conclude this effect is related to the interaction of the epitaxial layers with the semi-insulating substrate. In a simpliest way, the same type of interaction is responsible for the kink effect in MESFETs [1].

oCt E

'" 40 ..F

30

20

10

o 2 3 4 5

Vos (V)

Figure 1. REMT drain current IDS versus drain-to-source voltage VDS and gate-to-source voltage VGS characteristics for two different substrate­-to-source VSUB voltages.

In the case of MESFET it has been demonstrated that the origin of the phenomenom is due to the modulation of the active layer thickness induced by the variations of the extension of the space charge region between active layer and semi-insulating substrate : larger is the drain-to-substrate bias, larger is the space charge region extend. Moreover, modelling and experimental results have shown that this extention could disappear when minority carriers are injected in the channel, this minority carrier injection being due to majority carrier impact ionization: this correspond to the kink effect. For drain to source voltage VDS > VDSC the IDS current increases and becomes independent of the backgate voltage and simultaneously the gate current increases due to the generation of minority carriers in the channel by impact ionization. Owing to our experimental results the same phenomenon occurs into HEMT structure: but in the present case the two­dimensional-electron-gaz (2DEG) density is modulated instead of the channel thickness. This has been confirmed by numerical simulation of the structure.

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441

2.1. NUMERICAL MODEL

The numerical model used the general set of equations describing heterostructures steady state conduction

---+ div (E • grad 10) q. (n -

p - el } ---+

1 --+ , n·Pn·grad Ern - -·div I n - U with the currents --+

q ---+

1 --+ Jp p·pp·grad Er1' -·div Jp - U q

The drift-diffusion conduction currents in isothermal heterojunction are expressed, independently of the statistics [2]. As HEMT AZGaAs/GaAs heterostructures present a spike, the carrier densities must be necessarily described using Fermi-Dirac statistics :

where ~4 is the ~ order Fermi integral function. The standard Schokley-Hall-Read generation-recombination term U is

generalized to Fermi-Dirac statistics. For most of the materials doped by shallow impurities, C only depends

on the impurity density. In the present case the substrate is undoped semi-insulating GaAs in which the compensation of the residual shallow acceptors is obtained by partial ionization of the midgap EL2 deep donor level [3]. The fixed charge density local expression is :

Cp·p - Cn·n l

C =~(ND + N~) with N~ = N~and ND = ND·~~----~--~--~----~ C1' · (p + Pl) + Cn · (n + nl )

in which n l = n.exp [EL2 - Ern] and k·T

Cn and Cp are the electron and hole capture coefficients. The abovementionned set of equations is numerically solved using

finite differences method.

2.2. RESULTS AND DISCUSSION

The one-dimension simulated structure is representative of an HEMT under-drain cross section.

The room temperature physical parameters used are those currently admitted. Concerning the semi-insulating material, the values of the energy level in the band gap and the ratio of capture coefficients are Ec- EL?= .72 eV and Cn/Cp = 10 which have been deduce from a previous study l4].

The HEMT structure, described in table 1 corresponds to the epilayers growth sequence of the measured devices. Starting from these values a study of the sensitivity of each of the parameters to backgating has been carried-out. The results of simulation of the backgating

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442

sensitivity of HEMT structures are presented in terms of variations of the 2DEG density.

TABLE 1. Parameter values for the different layers of the standard HEMT structure.

material thickness doping level

Al. 3Ga. 7As 0.2 J.IlTl ND= 1018 cm- 3

Al. 3Ga. 7As 1014 cm- 3 50 'A ND=

spacer

GaAs 1J.1lTl N;"= 1015 cm- 3

undoped

GaAs N;"= 5 1015 cm- 3

undoped 10 J.IlTl S.l. ND= 5 1016 cm- 3 (EL2 )

Backgate-voltags (V)

Figure 2. Electron gas surfacic density versus substrat-to-drain voltage amplitude, as a function of the GaAs buffer layer residual doping density.

• GaAs buffer layer residual doping influence. The p-type of the GaAs MBE-grown undoped buffer layer is now established. The residual doping level ranges from 10 15 to 2. 10 16 cm -3 which corresponds to the

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443

effective range of density we measured. Figure 2 illustrates the 2 DEG density versus backgate-voltage, as a function of this residual doping. The AIGaAs layers and the semi-insulating material are fixed to the standard values. This figure clearly shows the buffer layer doping level influence on the backgating effect. It must be noted that the variation values correspond to the I DSS current variations experimentally measured.

• AlGaAs layer doping influence. The AlGaAs donor layer doping level has a direct influence on the 2 DEG density. The question is : does also the AlGaAs doping level have an influence on the backgating ? The simulations performed as a function of the doping level of the AlGaAs donor layer verify that the 2 DEG density increases with the doping level but the backgating amplitude is not affected at all.

1E+12

N I e u

9E+ 11 >. .. .. t: 0.51-' Il

"C 8E+ 11 0.2p I.? 1pm L.I c N 7E+ 11

2pm

6E+ll

5(+11 0 2 4 6 B Ie 12

Backgate-voltage (V)

Figure 3. Electron gas surfacic density versus substrate-to-drain voltage aTTrp Li tude, as a function of the GaAs buffer layer thickness. The GaAs residual doping density is fixed to 1015 cm- 3 .

• GaAs buffer layer thickness influence. Figure 3 illustrates the 2 DEG density versus backgate-voltage as a function of the buffer layer thickness. The GaAs buffer layer doping is supposed to be uniform and fixed at 10 15 cm -3. The thickness ranges from .2 to 2 ~. The figure shows that the zero-backgate-voltage 2 DEG value and its variation are both affected by the thickness of the layer.

• Semi-insulating material influence. The standard undoped semi-insulating substrate, used in the previous simulation, is sUfPosed to be the result of 5 1015 cm- 3 acceptors compensated by 5. 101 cm- 3

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444

lE+12

N ! e u

9E+ll >. .. .. c u 8E+ll "t:I

C) W C

N 7E+ll

6E+ll

5E+ll EI 4 6 a lEI 12

Sackgate-voltage (V)

Figure 4. Electron gas sur/acic density versus substrate-to-drain voltage amplitude as a /Unction 01 the compensation 01 the semi­-insulating material. The residual acceptor doping density is lixed to 5 1015cm- 3 and the EL2 density is the variable parameter.

EL2 deep donors. In fact this material is non-intentionally doped and these values are residual densities. They may vary from a wafer to the other. Moreover variations exist over a wafer.

From the simulations it appears that for a given compensation ratio, ND(EL2)/N~, the backgating is independent of the effective concentrations of acceptors and EL2 . On the contrary the backgating strongly depends on the compensation ratio. In figure 4, is shown the influence of the EL2 concentration, N~ being fixed to 5. 1015 cm- 3 . A strong backgate-effect appears when the EL2 concentration decreases to reach the acceptor concentration. Increasing the EL2 concentration decreases the backgate-effect ; but this behavior saturates when the EL2 concentration becomes very large in regard to the acceptor one's.

2.3. MODELLING CONCLUSIONS

From these numerical simulation results, it appears clearly that the backgating effect is closely related to the equilibrium between the GaAs buffer layer and the semi-insulating material. Thus, backgating strongly depends on the GaAs buffer layer thickness together with the residuals of each of these materials. Among the results the sensitivity to the semi-insulating substrate residual concentrations could be critical since the undoped semi-insulating material is known to present non­uniformities.

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3. Low noise HEMTs

3.1. LASER PROCESSED HEMTs

High electron mobility transistors have been limited by the existence of an inefficient charge transfer from the n+ ALGaAs to the triangular potential well of the ALGaAs/GaAs heterojunction. The charge transfer and the presence of the DX centers has been found to depend on the aluminium mole fraction, the spacer layer thickness and the total donor concentration. These effects have resulted in collapse of current voltage characteristics at low temperatures. An optimization of the structure has been performed by means of a novel laser assisted processing technology and a superlattice donor layer of 4 nm GaAs/ALAs periods j the GaAs wells being spiked doped. The laser assisted processing consists of in-situ laser desorption at 248 nm of the GaAs substrate in order to attain an arsenic stabilized growth surface. The laser assisted growth is used to achieved a high resistivity buffer layer with a minimum of incorporated acceptors in order to minimize backgating effect.

s D G

/ \ n+ GaAs 50 nm

( u: GaAs 4n m

( SUPERLATTICE n: GaAslu: AlAs

7 PERIODS 4nml4nm

/ u: AfxGal_xAs x-0.27 '\ 10 nrn \

GaAs BUFFER LAYER [ 1

S.I. GaAs SUBSTRATE ) ) \

Figure 5. LPHEMT structure.

The structure of the laser processed HEMT (LPHEMT) is shown in figure 5. The LPHEMTs consist of 4 ~ thick buffer layer followed by a 10 nm ALGaAs spacer layer. On the spacer layer is grown a seven period superlattice ALAs/GaAs where the the top layer is a 4 nm undoped GaAs layer. Each GaAs layer in the superlattice is spike-doped. The LPHEMT consists of a 0.75 ~ gate with a 200 ~ total gate width. The gate metallization is the typical TiPtAu. The ohmic contacts consist of

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446

AuGeNi which are laser annealed. The current voltage characteristics are shown in figure 6 and indicate

no characteristics looping or collapse. Moreover the LPHEMT does not exhibit the characteristic kink effect which is correlated to backgating effect sensitivity.

50

40

~ E 30 Vi -0

20

10

Vgs step = - 0.2V

r ~ ~o3 -:.::-. ,. ---..... . ....

.. , .... .... -----0~~~'~~'~~'~~~=~~'~~"'~":~~~~~~'~~"'~~~~==3

2 3 4 5

Vds(V)

Figure 6. LPHEMT drain current IDS versus drain-to-source voLtage VDS and gate-to-source voltage VGS characteristics.

3.2 RELIABILITY STUDY OF LPHEMTs

The ageing behavior of the LPHEMT structure have been compared to two classical HEMT structures: A SONY structure grown by MOCVD with a 0.7 ~ gate length and a MITSUBISHI stucture grown by MBE with a 0.5 ~ gate length. The ageing test have been performed on 20 samples under the following ageing conditions :

• VDS = 2 V and IDS = 10 mA (operating point for a low-noise operation) .

• Two channel temperatures, Te , have been used which are respectively 180 ·C and 210 ·C.

The major parameters are automatically scanned with computered failure criteria and subsequent computered switch-off of power supply facilities. Periodic measurements are performed at room temperature.

The evolutions of the IDS currents of the three structures are shown in figure 7 for a channel ageing temperature of 180 ·C. The figures 8 and 9 respectively show the evolutions of the associated gains, Ga, and the noise figures. NF. measured at 11 GHz for the same channel ageing temperature of 180 ·C.

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447

12

a: E 11

UJ 0 H lfil

9

8 0 LPHEMT

7 A SONY

6 MITSUBISHI "V'

5 1 fil 1 1 fil2 1 fil3 1 fil4

time (hours)

Figure 7. Evolution 01 the IDS currents lor a channel ageing temperature 01 180 ·C.

11

~ lfil

9

8

7

o FORTH

A SONY

'<7 MITSUBISHI

~r------------40

time (hours)

Figure 8. Evolution 01 the associated gains, measured at 11 GHz, lor a channel ageing temperature 01 180 ·C.

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448

2

!II -a

It.. Z

1. 5 f-

o FORTH A SONY 'V MITSUBISHI

-

-

time (hours)

Figure 9. Evolution 01 the noise ligures, measured at 11 GHz, lor a channel ageing temperature 01 180 ·C.

12

a: E

11

to 0

10 H

9

8 0 FORTH

7 SONY A

6 MITSUBISHI 'V

5

10 1

Figure 10. EVolution 01 temperature 01 210 ·C.

10 2 10 3

time (hours)

the Ins currents lor a channel ageing

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449

1 1

II:l -0

fd 10 ~ -

---- =:::::::% -=

9 _

~ 0 FORTH

-

8 A SONY - -"V MITSUBISHI

time (hours)

Figure 11. Evolution of the associated Grains, measured at 11 GHz, for a channel ageing temperature of 210 ·C.

2

II:l -0

u.. z 1.5 -

o FORTH A SONY "V MITSUBISHI

-

-

time (hours)

Figure 12. Evolution of the noise figures, measured at 11 GHz, for a channel ageing temperature of 210 'C.

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450

In figures 10, 11 and 12 are parameters, respectively IDS' Ga temperature of 210 ·C.

plotted the evolutions of the same and NF, for a channel ageing

From these ageing tests, performed up to 2000 h at two temperatures, it can be observed that :

• The measured drifts on IDS of the LPHEMTs of FORTH are comparable to those of classical HEMTs under same ageing conditions .

• A degradation seems to appear at 210 ·C on the LPHEMTs according to our margin of error : ~F ~ ± 0.2 dB and ~a ~ ± 0.5 dB at 11 GHz.

Our priliminary conclusion, after 2000 h ageing under DC bias conditions, is that the reliability level of LPHEMTs and classical HEMTs is identical to up-to-date commercially available GaAs MESFETs

4. Power MEDFETs

4.1. CHANNEL DOPED STRUCTURE (MEDFET)

The description of the layers for the MEDFET structure is given in table 2. The MEDFET consists of a GaAs buffer layer grown on the GaAs semi-insulating substrate followed by a ten period AlGaAs!GaAs superlattice to getter impurities from GaAs substrate and buffer, in order to improve the quality of next growths. The upper layer of the superlattice is an undoped GaAs layer. On the superlattice, the AlGaAs undoped grown high band-gap layer permits the confinement of electrons in the channel. This layer is followed by the n doped GaAs active layer. The upper n+ GaAs layer is grown for the source and drain ohmic contacts.

The ohmic contacts are AuGeNi. Gate metallization together with over­layers are TiPtAu. The gate is recessed. Adjacent source pads are connected with TiPtAu air bridges. The chip surface passivation is insured by a SiN film. The gate dimensions are 2.8 mm width and ~ 1 ~ length.

TABLE 2. Parameter values for the different layers of the MEDFET structure.

material thickness doping level

GaAs 1000 A n+ 1018 cm- 3

GaAs 2500 A n 1017 cm- 3

AlGaAs 5000 A undoped GaAs 80 A undoped

10 periods : AlGaAs 80 A undoped

GaAs 80 A GaAs Ipm undoped GaAs

undoped S.l.

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451

4.2. AGEING RESULTS

It is obvious that the n GaAs-AlGaAs interface stability versus operating time has to be investigated. 2 sets of devices have been aged under the following conditions :

• VDS = 4 V; I Dss ~ 100 mA : this value has been choosen instead of IDss/2 = 300 mAo It drives the device near pinch-off condition, with a relatively high gate-to-drain voltage. As a consequence, the space charge layer spreads deeply into the channel, stressing the n GaAs/ALGaAs interface.

• Ambient temperature are 175 and 215·C. Taking into account the thermal resistance (~ 20·C/W) and the power dissipation (0.4 W), the channel temperatures are respectively 190·C and 230·C.

Four parameters are automatically scanned during ageing: VDS ' IDS' VGS and IGS . If one of these parameters increases (or decreases) over (under) a memorized value (failure criteria), the device power supply is automatically switched-off. This prevents any burn-out and consequently allows a failure analysis. Periodic measurements are also made at room temperature, especially RF parameters.

E' 31

III "C

30

-I 29

0 0-

28

o Tc ~ 190 • C 27

CI Tc ~ 230 • C 26

25 10 I

time (hours)

Figure 13. Po(-l), 1 dB gain compression output po~er evoLutions at 8 GHz for channeL ageing temperatures of 190 ·C and 230 ·C.

No metallurgy-induced of surface-induced defects have been detected in terms of parameters drifts after 4000 hours.

In figure 13 are plotted the 1 dB gain compression output power evolutions, Po(-l), in figure 14 are shown the evolutions of the linear gain, GL, at 8 GHz for both ageing temperatures. The results lead to the following conclusions:

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7

5

0 Tc ~ 190 ·C 4

Q Tc ~ 230 ·C

3

10 1 10 2 10 3 10 4

time (hours)

Figure 14. Linear gain, Gl, evolutions at 8 GHz for channel ageing temperatures of 190 ·C and 230 ·C .

• Whatever the ageing conditions the 1 dB gain compression power shows the same behavior for degradation. No drifts are observable on classical DC parameters such as l Dss and the gate-to-drain breakdown voltage BVDGO

No gate lag appears during ageing. However a dramatic increase of lGS is measured near the pinch-off conditions (lGSO??).

• No decrease on linear gain appears according to our marging of error, ~l ~ ± 0.7 - 0.8 dB.

A correlation between the increase of l GSO?? and Po(-l) has to be made. It may indicate an in-bulk degradation of the n GaAs active layer interface with the undoped AlGaAs layer leading to an increase of the reverse current of the gate. A degradation of the carrier lifetime can be hypothetized in the AlGaAs at the interface region.

5. Conclusion

After 2000 hours ageing conventional and superlattice HEMTs compare favourably with up-to-date commercially avialable GaAs MESFET. However the use of an AlGaAs buffer layer introduces a degradation on the leakage current of power MEDFETs. The backgating effect and correlated kink effect which have been characterized an modellized on conventional HEMTs are strongly dependent on the structure type and the grown layer quality. The magnitude of these effects is drastically reduced in the studied laser-desorbed structures.

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6. References

[lJ Mottet, S. and Le Mouellic, C. (1984) tlGaAs MESFET anomaLies related to minority carrier injection into semi-insulating substrate" in D. C. Look and J. S. Blakemore (Eds.), Semi-Insulating III-V Materials, Shiva Publishing Ltd England, 406-409

[2J Viallet, J.E. and Mottet, S. (1985) tlHeterojunction under Fermi­Dirac statistics: general set of equations and steady state numerical methods" in J.J.H. Miller (Ed.), Proceedings of the Fourth International Conference on the Numerical Analysis of Semiconductor Devices and Integrated Circuits, Boole Press ltd. Ireland, 530-535

[3J Mottet, S. and Viallet, J.E. (1986) "Simulation of III-V device semi-insulating material" in K. Board and D.R.J. Owen (Eds.), Simulation of Semiconductor Devices and Processes, Vol. 2, Pineridge Press G.B, 494-507

[4J Zebbar, N. (1987) tlEffet du substrat semi-isolant GaAs sur Ie comportement des transistors MESFET a l'arseniure de gallium", These de doctorat, USTHB, Alger

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RELIABILITY OF GaAs MESFETs

B. Ricco', F. Fantini"·, F. Magistrali'*', P. Brambilla**'

Abstract

* University of Bologna, Italy ** S. S. S. U. P. S. Anna, Italy

*** Telettra Spa, Italy

The paper presents new data on the reliability of GaAs MESFETs for microwave telecommunications obtained from the analysis of fleld repairs and accelerated tests. This work represents a systematic investigation of devices in the context of real applications, thus providing a significative contribution to the state of the art in the field.

1. Introd uction

With the growing use of discrete devices (for low- noise and power applications) and, more recently, of (analog as well as digital) integrated circuits the field of GaAs compo­nents has already reached dimensions and importance requiring sound assessments of part reliability.

This is particularly true for radio- frequency (RF) power transistors used in telecom transmission equipments and microwave analog circuits (J\fMICs), together representing the main undisputed area of GaAs devices, because very tight requirements make the circuits critically sensitive to parametric MESFETs degradations, thus giving rise to sophisticated reliability problems.

For these reasons, most of the data available in the literature refer to analog RF components, but they have also been assumed to represent a starting point for the case of digital ICs, although such an extrapolation must be regarded with great caution because of the significant differences in fabrication technology.

The considerable effort devoted to the subject has produced substantial results in that the most important failure mechanisms and their main dependence on technological parameters and operative conditions have been substantially identified [1- 7]. In spite of these important qualitative results, however, the data available in the literature are still rather scarse, particularly as far as real "field" applications are concerned.

This work intends to provide a contribution in this sense presenting new data obtained from devices (both commercial and captive) for RF telecom applications.

The rest of the paper is organized as follows. In the next section we present data col­lected from field repairs; in section 3 the technique used for accelerated testing is described while the obtained results are presented and discussed in section 4. Conclusions are finally drawn in section 5 where a brief discussion of the case of simple MMICs is also given.

2. Field results

Only recently the Military Handbook (MIL fIDBI( 217E) has introduced a new model [8] for the reliability of GaAs .MESFETs (ICs are not yet considered). In particular, starting

Work partially supported by CNR under the MADESS Project

455

A. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 455-469. © 1990 Kluwer Academic Publishers.

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from the classical formula for transistors

(1)

where: Ap and Ab are the failure rate of the device and a base value (to account for operating temperature, junction heating and electrical stress), respectively; lIE and lIe represent device independent factors describing (at a macroscopic level) enviromental conditions and the effects of the interactions with other transistors within the same package, respectively; finally, lIQ denotes the quality factor and IIA a parameter accounting for the effects of the type of circuit where the MESFET is to be used.

For the MESFET applications of interest for this work realistic values of such pa­rameters are: lIE = 4 (for operating conditions not featuring air conditioning); TIc = 1; TIQ = 0.24 (for devices that passed a burn- in test of 168 hours at 12S0C); 11" A = 0.7 or SO for low- noise or driver applications, respectively.

Considering typical ambient temperatures ranging from -SoC to 4SoC to be increased by 10 -;- lSoC because of the lleating of the whole equipment incorporating the MESFET under normal operating conditions, a reasonable value for the reference ambient temper­ature is 30 -;- 3SoC. In this case, avoiding high electric stresses, the base value Ab ranges between 20 and S2 FITs, consequently the overall failures rate can be estimated between 13 and 2400 FITs (the rather large dispersion being due to the possible options about the factor TIA)'

This estimate can be compared with data obtained from field repairs by means of a dynamic data base for system monitoring and surveillance. The results of a study of this type are summarized in fig. 1 showing MESFET failure rates calculated from field repairs collected over the last S years (the number of considered "device - hours" assures a level of confidence better than 90% for each point). The data reported in fig 1 represent a removal rate taking into account all the substituted parts, but extensive failure analysis are performed whenever the number of collected cases exceeds a critical threshold in order to discriminate extrinsic from intrinsic (i.e. component- related) failures. In this way it has been verified that the data presented here are not significatively affected by artefacts due to wrong applications or to the collection procedure.

The results of fig. 1 are in substantial agreement with the estimate provided by the MIL HDBK formula, particularly considering that they also include failures occuring during the system start- up, strictly speaking not to be considered as real reliability problems. Furthermore they show the classical effect due to the "learning curve", even though after 1986 no saturation is present. This last point can be explained considering that the field of power devices is still growing significantly so that the effect of a maturing technology is partially compensated by the introduction of devices for ever higher power applications featuring higher failure rate (essentially due to device heating).

3. Accelerated life tests

Accelerated tests are intended to provide estimates of device reliability in time much shorter than those required to prod uce a significant number of failures under normal oper­ating conditions. To achieve this result, the tests must stress the largest possible number of devices in a controlled manner without introducing artefacts (Le. unrealistic failure modes).

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The choice of factor used to accelerate device aging must be necessarily based on the expectation and modeling of the relevant failure mechanisms [9]. In the case of power MES­FETs for RF telecom applications, the accelerated tests normally used are the following.

a) High Temperature Storage (HTS) without applied bias. For these tests only one refer­ence value of temperature (250°C) has been generally applied because the experiments do not give unique answers, although they are useful to accelerate diffusion processes active at the metal/ semiconductor and dielectric- semiconductor interfaces [10,11].

b) High Temperature Operating Life Tests (HTOL): different temperatures are considered in conjunction with electrical conditions similar to those experienced by the device during normal operations with the purpose to study the combined effects of thermal and electrical stresses [12].

c) High Forward Gate Current Tests (HFGC): the gate is forward biased in order to investigate the effects of high current densities (at high temperatures) [13].

d) High Temperature Reverse Bias Tests (HTRB): the gate is biased close to breakdown to observe the cumulative effects of high electric fields and temperatures.

e) Temperature Humidity Bias Tests (THB) and Highly Accelerated Stress Tests (HAST). In these type of experiments the gate is reverse biased to analyse the effects of humidity directly on the chip and the protection capability of the package [14]. The effectiveness of all these tests in characterizing the various MESFETs failure

mechanisms is summarized in table I (and fig. 2 to be used as a reference). The most delicate problems arise from the HTOL experiments requiring critical choices

between static and dynamic life tests as well as static and dynamic parameter monitoring. Obviously, dynamic parameters should be extracted under real operating conditions,

however, since RF measurements are not compatible with the text fixtures used for relia­bility tests, suitable extrapolations are mandatory. At this regard, we have found a good correlation between RF and DC parameters [9]. Fig. 3 shows the correlation found in the particular case of I Dss and POUT.

For this reason, rather than developing a sophisticated and critical RF measuring sys­tem, we have concentrated our efforts toward a reliable automatic DC equipment allowing easy monitoring of parametric drifts. Obviously, in the procedure adopted for device char­acterization RF measurements are performed before, at selected times during the DC tests and at the end of the experiments to check and monitor the MESFETs RF performance.

In all the tests mentioned above, measurement repeatibility is of course essential, particularly when device reliability is high and lifetime must be inferred from parametric degradations since a significant number offailures cannot be produced in a reasonable time.

The automatic measurement set- up mentioned above operates on the following pa­rameters.

a) IDss, gm and Vp (where I Dss is the saturation current measured with Vcs = 0, gm and Vp are the transconductance a,nd pinch- off voltage, respectively) to be calculated from device trans- characteristics.

b) Ideality factor (n) and saturation current (Is) extracted from the I-V curve of the gate- source diode under forward bias (to study interfacial degradation of Schottky contacts [13])'.

c) Breakdown voltages of the gate- source (and gate- drain) junctions (to observe surface degradation [10]).

d) Resistance of the active device channel (Ro) and those in series with the source (Rs),

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drain (RD) and gate (RG). Rs and RD allow to monitor the degradation of ohmic contacts, Ro is used to characterize the interaction between the gate and the semi­conductor in the channel region, while RG provides interesting information about electromigration of the metal lines [15). The determination of the resistances mentioned above is not trivial, particularly in

power devices where they can be as low as 0.2 - 0.411. The main difficulties arise when trying to separate out the various contributions from the measured total resistance (RON = Ro + Rs + RD). To this regard, the only method so far suggested in the literature is that of Ref. 16 that can be used for device characterization (even if repeatibility is not really satisfactory), but is hard to apply to monitor device aging because critically dependent on fitting parameters that change considerably with device degradation.

Table II reports the measured electrical parameters together with some interesting results coming from statistical evaluations. The repeatibility of all parameters (except Ro) is better than 1%, thus ruling out any possibility of data misinterpretation.

As for the way used to stress the devices, we have also chosen to operate in DC because it is obviously much easier and, on the other hand, RF operations do not seem to introduce extra failure modes (apart from the catastrophic destruction induced by RF spikes that, however, is more a problem of robustness than of reliability).

Furthermore, working under DC conditions, it is possible to develop tests addressed to single failure mechanisms (as shown in table I), while both results and acceleration factors are easier to analyze and to monitor. On the contrary, dynamic life tests normally involve different failure mechanisms occurring at the same time and leading to complete burn- out of the devices.

The control of stress conditions in order to avoid burn- out represents the most critical aspect also for DC tests and to this regard our automatic set- up features [12):

1) control of the stability of the operating point; 2) protection against spikes during onl off switching sequences; 3) limitation of extra- currents; 4) precaution against the possibility of forward gate conduction; 5) oscillation quelling at high as well as low frequencies. Furthermore the set- up enables to explore a wide range of temperatures (up to 200°C)

and to measure different type of MESFETs. Fig. 4 shows the mentioned automatic test equipment, while fig. 5 illustrates its

effectiveness in avoiding undesired device destruction. In particular, fig. 5a and 5b show a device stressed without and with the precautions of the set- up, respectively.

4. Results and discussion

The most effective test for lifetime prediction is the HTOL essentially because it in­volves conditions close to those experienced by the device during its real life.

As for the analysis of the data, the most widely used lognormal distribution [17) is supported by substantial experimental evidence ill the case of GaAs discrete MESFETs and ICs [18,19).

For this reason, the analysis to be presented is based on the assumption of lognormal distribution (checked by means of experiments continued until reaching the failureof all the devices in order to explore the widest possible ranges).

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The results refer to medium- power MESFETs fabricated with standard gold- based technology (all the sample came from the same lot). Fig. 6 shows the cumulative failure distribution obtained in 4 life tests performed at ambient temperature in the range 700 e -125°e for nearly 2 104 hours.

By means of electrical measurements and physical examination, the failure mode was found to be an increase in the gate leakage current eventually leading to a localized short circuit similar to that shown in fig. 5b. The origin of the leakage is probably in the defective areas at the semiconductor surface (passivated with PECVD silicon- nitride) or in protrusions in the metallizations (possibly due to the lift- off process).

The presence of a defect- related phenomenon is also confirmed by the large dispersion (0" ~ 2) of the lifetimes found in all tests that contrasts with the tight value (0" ~ 0.5) typical of wearout mechanisms in homogeneous samples. (Accurate failure analysis enables to rule out the possibility that the large value of 0" is due to the cumulative effects of different failure mechanisms).

As for reliable data extrapolation a unique value of 0" is mandatory, all our data have been suitably fitted in order to obtain a common optimum of such a paramenter.

The choice of the temperature used to accelerate device failure comes from a trade- off between the needs to make the experiments conveniently short and to have small uncer­tainities when extrapolating the data at real operating conditions (besides purely geometric considerations, the use of very high temperature has to be avoided also to prevent the in­surgence of specific failure mechanisms not relevant for real applications).

To deal with these problems, we selected a temperature range close to real operating conditions, even though this inevitably leads to very long tests.

As shown in fig. 7, our data allow to extrapolate a value of MTF ~ 1.8 108 hat 300 e with an activation energy EA ~ 1.6e V, in excellent agreement with recent results even though the failure mechanisms seem to be different [5].

The rather high value of EA is not unexpected in GaAs devices (see Table III), and it is also important that it has been obtained from experiments performed at lower temperatures than in previous works, thus resulting particularly reliable.

In spite of all these precautions, the possibility that the real activation energy at room temperature is lower than the extrapolated value cannot be completely ruled out. In fact, our data suggest that the Arrhenius plot might present two different slopes with the p;u·t at lower temperatures exhibiting an activation energy ~ 0.5eV. If this was the case, a conservative prediction of MTF at 300 e can be obtained in the range of 9 105 hours.

From these extrapolations, the expected failure rate under normal operating conditions can be easily calculated. As shown in fig. 8, we obtain a maximum value < 10 FITs in 25 years using EA = 1.6eV and < 2 103 FITs for the most conservative case featuring two activation energies. This latter case is in good agreement with the value provided by the MIL HDBK model (represented by the shaded area in fig. 8).

In the second example of tests considered here, humidity is used as acceleration factor. To this purpose two experimental conditions have been chosen (with the gate diode reverse biased), namely 125°e, 85% relative humidity (RlI) and 85°e, 85% RlI, respectively.

Fig. 9 shows the results obtained with the same devices used in the previous sections that are here compared with samples fabricated with a different, Al- based technology (all transistors are unpackaged).

In these experiments, although the result is to be taken with some caution because

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coming from only two points, we obtain EA = 0.3 and 0.4 eV for AI- and Au- based devices, respectively. Not surprisingly (because in the humidity tests metallizations play the main role) these values are almost the same as those found with silicon devices using similar metal technology.

As for failure mechanisms, Al corrosion (where present) was found to be the most rapid one, while in the other cases the main phenomenon is humidity- assisted degradation of ohmic contacts (in particular due to Ni extrusion leading to short circuits [14]).

As a final comment about THB and HAST tests, it is worth mentioning that, since from a quantitative point of view the values of the extrapolated activation energies are not reliable, their most practical use is to compare the robustness of different technologies with regard to humidity.

5. Conclusions

In this work a comprehensive approach to MESFETs reliability has been presented that, based on new data coming from field rcpairs, provides a quantitative assessmcnt for the case of descrete devices intended for low- noise and power applications.

The results, particularly significative as accelerated experiments have been performed at conditions close to those encountered in real applications, are in substantial agreement with published data and with the predictions of existing models.

The approach of this work is also suitable for direct extention to the case of MMICs that are rapidly becoming more and more important in telecom applications. In fact, we have just started to work but do not have enough results to present here.

In general, however, MMICs reliability data are rather scarse in the literature and the situation is largely unsatisfactory, particularly compared with the case of the much more mature Si technology. However, because of the very rapid growth of the field, the problem is becoming progressively more important and significant improvements are in sight. From this point of view, in fact, considerable help comes from the substantial knowledge acquired with discrete power devices. Such an advantage, without counterpart in the silicon world, is definitely much more significant in the case of Ml\HCs than for their digital counterparts because of the similarity in the used technology and of the fact that IC reliability is largely dominated by transistor faults.

The integration of several devices on the same chip, however, introduces also some new phenomena, such as possible undesired interactions of neighboring parassitic structures and, at least in the case of MMICs, also the failures mechanisms that are specific of passive components (in particular capacitors). Furthermore, the fabrication of complex lCs requires the introduction of suitable protections (particularly against ESD) at the I/0 pins whose drawbacks (and effectivness) are still to be carefully evaluated.

References

1) J. E. Davey, A. Christou; in "Reliability and Degradation" edited by M. J. Howes, D. V. Morgan, Wiley, NY 1981, p. 237.

2) J. C. Irvin; in "GaAs FET Principles and Technology" edited by J. V. Di Lorenzo, D. D. Khandelwal, Artech House, Dedham 1982, p. 283.

3) J. M. Dumas, et al.; l' Echo des Reserches 123, p. 35, 1986. 4) A. Christou; Tutorial 3 at the Inter. ReI. Phys. Symp., 1986 (unpublished).

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5) W. J. Roesch; Tutorial 1 at the Inter. ReI. Phys. Symp., 1988 (unpublished). 6) A. Christou; Quality and Reliability Engineering InternationalS, p. 37, 1989. 7) J. M. Dumas; Proc. 4th Int. Conf. "Quality in Electronic Components", p. 120, 1989. 8) "Reliability Prediction of Electronic Equipments", Military Handbook 217E, U.S. Depart­

ment of Defence, 1986. 9) P. Brambilla, et aL; Alta Frequenza, LV 3, p. 181, 1986.

10) C. Canali, et aL; Electronics Letters, 21, p. 600, 1986. 11) C. Canali, et aL; IEEE Electron Device Letters, EDL 7, p.18.5, 1986. 12) C. Canali, et aL; Microelectronics and Reliability, 27, p. 897,1987. 13) C. Canali, et aL; IEEE Trans. Electron Dev., ED 44, p. 205, 1987. 14) F. Magistrali, et aL; to be published on the Proceedings of ISTFA 1989. 15) C. Canali, et al.; Electronics Letters, 23, p. 364, 1987. 16) H. Fukui; Bell System Tech, Jour., 58, p. 771, 1979. 17) F. H. Reynolds; in "Large Scale Integrated Circuits Technology: State of the Art and

Prospects" edited by 1. Esaki and G. Soncini; Nijhoff, The Hague, 1982, p. 517. 18) A. S. Jordan, T. D. 0' Snllivan; Microelectronics and Reliability, 24, p. 125, 1984. 19) W. J. Roesch, M. F. Peters; Proc. of GaAs IC Symp., p. 27,1987. 20) D. A. Abbott, J. A. Turner; IEEE Trans. Micr. Theory and Tech., MTT 24, p. 317, 1976. 21) T. Irie, et al.; IEEE Trans. Oil Micr. Theory and Tech., MTT 24, p. 321, 1976. 22) M. Omori; Proc. IRPS 15, p. 232, 1977. 23) R. E. Lundgren, G. O. Ladd; Proc. IRPS 16, p. 25.5, 1978. 24) P. M. White, et aL; Proc. European Microwave Conr. 1978, p. 405. 25) J. C. Irvin, A. Loya; Bell System Tech Jour., 57, p. 2823,1978. 26) M. Benedeck, B. S. Hewitt; IEDM Tech. Digest 1978, p. 385. 27) I. Drukier, J. F. Silcox Jr.; Proc. IRPS 17, p. 150,1979. 28) K. Mizuishi, et aL; IEEE Trans. Electron Dev., ED 26, p. 1008, 1979. 29) M. Omori, et al.; Proc. IRPS 18, p. 134, 1980. 30) H. Fukui, et aL; Proc. IRPS 18, p. 151, 1980. 31) A. Christou, et aL; Proc. IRPS 19, p. 182, 1981. 32) E. D. Cohen, et al.; IEEE Trans. Micr. Theory and Tech., MTT 29, 1981. 33) 1. S. Bowman, W. H. Tarn; Proc. ISTFA 1981, p. 69. 34) W. J. Slusark Jr., et al.; Proc. IRPS 21, p. 211,1983. 35) G. M. Brydon, B. G. Caplen; Proc. IRPS 21, p. 302, 1983. 36) K. Katsukawa, et aL; NEC Res. Dev. Jour., 71, p.82, 1983. 37) W. Wilhelmsen, T. Zee; Proc. ISTFA 1984, p. 163. 38) J. F. Bresse; Microelectronics and reliability, 25, p. 411, 1985. 39) S. Mizugashira, E. Sakaguchi; 15th Symp. on Reliability and Maintainability 1985, p. 53. 40) M. F. Millea; Proc. IRPS 24, p. 125, 1986. 41) K. J. Russel, J. K. Dhiman; Proc. IRPS 24, p. 150,1986. 42) S. Kashiwagi, et al.; Proc. IRPS 25, p. 97,1987. 43) A. Fraser, D. Ogbounah; Proc. GaAs Symp. 1985, p. 161. 44) K. Katsukawa, et al.; Proc. MMMC Symp. 1987, p. 57. 45) M. Spector, G. A. Dodson; Proc. GaAa IC Symp. 1987, p. 19.

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1···· ...... · .. ·1 ........ ·· .... ·1 .. ·· ...... · .... 1· ........ · ...... ··1·· ........ ··· .... ·1 ................ 1 .... ····· .. 1 I MECHANISM I GaAs surface I Ohmic contact I Ohmic Contact I Shottky junction I Gate I Metal I ITEST I degradation I degradation I Electromigration I and enaMel lelectromigrationl corrosion I I··························· .. ························· .......................................................... .. 1 1 1 1 1 1 1 1 1 HTS 1 1 1 1 1 1 1 I·· .. ············ ................................................................................................. . 1 1 1 1 1 I 1 I 1 HTOl 1 1 1 1 1 1 I I············ ..................................................................................................... . 1 1 1 1 1 1 I I 1 HTRB 1 I 1 1 1 1 I I········ .. ·················· .. ···· .. ···················· ......................................................... . 1 1 1 1 1 1 1 1 1 HFGC 1 1 1 1 1 1 1 I························· .. ··· .. ······················· ......................................................... . 1 1 1 1 1 1 1 1 1 THL/HAST 1 1 1 1 1 1 1 I·············· .. ········ .. ··· .. ····················· .. ··· ....................................................... .

TABLE J: e"FFECTtVENESS OF ACCELERATED TESTS (* = effective, "'* very effective)

1 ============ 1 ========== 1 =========== 1 ============ 1 1 PARAMETERS 1 MEAN 1 DISP. 1% VARIATION 1

1 ============ 1 ========== 1 =========== 1 ============ 1 1 Ron (Ohm) 1 0.6051 1 0.00142 1 0.23608 1 1············1··········1···········1············1 1 Rdend (Ohm) 1 0.2931 1 0.00118 1 0.40463 1 I··'··'··'·· ·1··········1···· •••••• ·1··· ••• '··'··1 1 Rsend (Ohm) 1 0.2888 1 0.00081 1 0.27986 1 I··· ....... '·1· •••.• ····1·········· ·1· ••••••• ····1 1 Ro (Ohm) 1 0.1335 1 0.00125 1 0.941171 I·· ··········1· •••••••• ·1· ··········1· ..••.• ·····1

1 n 1 1.1904 1 0.00115 1 0.09715 1 1············1··········1···········1············1 1 Is (A) 1 1.82E·ll 19.382E·13·1 5.15531 1 1············1··········1···········1············1 1 Ibrk (A) 1 5.38E·5 1 .00000025 1 0.4m9 1 1············1··········1···········1············1 1 Idss (A) 1 1.4278 1 0.00123 1 0.08673 1 1············1··········1···········1············1 1 Gm (S) 1 0.5682 1 0.00114 1 0.20122 1 1············1··········1···········1············1 1 Vp (V) 1 ·2.7051 1 0.00129 1 0.04801 1 1············1··········1···········1············1 1 Rd LS (Ohm) 1 0.2067 1 0.00151 1 0.73347 1 1············1··········1···········1············1 1 Rs LS (Ohm) 1 0.2025 1 0.00141 1 0.69345 1 1············1··········1···········1············1 1 Rg LS (Ohm), 1.2822 1 0.02071 1 1.61577'

,============, ========== ,=========== ,============ ,

TABLE II:

STATISTICAL ANALYSIS ON AUTOMATIC SYSTEM MEASUREMENTS (on 211 sa...,les)

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Table III.

Device Type Temp. Range Failure Mechanism EA Ref.

small signal 200°C metal migration at ohmic contacts 1 eV [20]

small signal 150-295°C increase of ohmic contact resistance 1.8eV [21]

diodes 275-325°C ohmic contacts degradation 2.3 eV [22]

low-noise 230-270°C increase of ohmic contact resistance 1.5eV [23]

power 120-220°C An-AI 2 eV [24]

low-noise 88-275°C RF parameter degradation 0.8 eV [25] Au-AI 0.5 eV

low-noise and 170-250°C Schottky-metal AI: 0.93 eV [26] power interaction with substrate Au: 1.53 1.74 eV

power 140-200°C gate pad inter diffusion 1 eV [27] drain electromigration 1.85 eV

low-noise 175-275°C illterdiffllsioll at ohmic contacts 1 eV [28]

low-noise 230-300°C contact stability 1.05 eV [29]

power 175-250°C gradual degradation 1.2-1.8 eV [30] channel compensation 1.5eV

power 180-220°C electromigration in ohmic contacts 1.1 eV [31] Ti oxidation and As outdiffnsion 1.8eV

power 137-197°C high gate resistance 0.9 eV [32] surface contamination 2.3 eV

low-noise 200-260°C Au-AI 1.5 1.9 eV [33]

power 190-215°C Al electromigration 0.61 eV [34]

low-noise 170-220°C electromigr at ion 0.8 eV [35]

power 240-337°C Al voids 1 eV [36] ohmic contact degradation 1.8eV

low-noise 225-275°C electromigration 1.3eV [37]

no-bias / bias low-noise 100-275°C Au-Cr interdiffusion 0.64 0.10 eV [38]

Ga and As outdiffusion 0.92 0.32 eV Ni diffusion 0.76 0.60 eV Ge diffusion 0.50 1.96 eV

low-noise and 180-337°C Au-AI 1.1 eV [39] power ohmic contact degradation 1.5eV

low-noise and 200-300°C ohmic contact degradation 1.8eV [3] power Au-AI with !barrier 1.2eV

surface oxidation 0.7 eV low-noise 100-200°C ohmic contact degradation 0.7 eV [40]

power 150-225°C gate voids 1.5eV [41]

power 210-250°C AI-GaAs interdiffusion 1.15 eV [42]

MMIC 175-31O°C gate channell interdiffusion 1.6eV [43] NiCr resistor degradation 0.8 eV

MMIC 180-337°C ohmic contact degradation 1.4eV [41] surfa.ce degradation 1.4 eV

IC amplifier 150-235°C 1.1 eV [45]

Page 463: Semiconductor Device Reliability

464

RITs

1000

800

600

400

200

1983

\ \ Low No I s .. FETs , ,

-------F~

1984 1985 1986 1987 1988 1989

Fig. 1 Removal rate of low- noise and power MESFETs.

s G o

, / I ' . ; ,/ I B n-epi !/ C , ____ ~_...L ____ _

5\- GaAs

Quant I ty (a. u. )

Fig. 2: Sketch of the MESFET showing the localization of the main failure mechanisms.

Page 464: Semiconductor Device Reliability

loss % VARIATION 0

\ \ A

- 10 ~--e.. .... ......

- 20 ..". "-

" "-- 30 " , , ,. - 40 's._ B

.... - --e

-50

TA = 17SoC

o 2 4 6 8 10 (khours)

POUT VARIATION (dBm)

+1~ o • •

-1 ..... --&_-~~ A

'\ - 2

-3

-4

- 5

o 2 4

" '"

6

" ~ " B

" 8 10

t ( khours)

465

Fig. 3: Degradation of IDss and RF power gain in a device subject to HTOL stress.

Page 465: Semiconductor Device Reliability

466

Fig.4: a) Test fixture for a single FET

b) Overall view of a lifetest oven with the FET control circuits

Page 466: Semiconductor Device Reliability

a)

b)

Fig. 5 a) SEM picture of a burn· out MESFET; b) SEM picture of a device made to fail under controlled conditions.

467

Page 467: Semiconductor Device Reliability

468

CU~UL. F AlLURES X 99.9 99.

95

90

80

70

80

50 40

30

20

10

I

0.5

0.2

0

0

O.! -'--·~-·~~~"'T' ~i6n-b,r-

o

125 C

i "1k'

105 C

/"

/" /" /"

/"

/" 70 C

~ Gl&R

90 C

/"

I • 10k' I , I iook' _n -r---'---'~i(

T 1me (hours)

Fig. 6: Lognormal plot of c.umulative failure distribution obtained in 4 HTOL experiments with medium- power MESFETs.

MTF (hrsl Ie 09 500

1e 08 5e 07

Ie 07 58 DB

1e 08 500

1e 05 50 04

18 04 50 03

1e 03 500

1e 02 50 01

/ /

_1£:--_-- /:r

/ /

/

/ /

One Slope Extrapolation

~TF (aO CI. L a* I o~our.

--r --- Two Slopes Extrapolation

~TF (aO CI. 9. 1'105Hours

125 C 105 C 90 C 70 C aD C le2~~I---=-2.-::5:r---=-2.-::8:r-- ·~2:".7,.'-"":":-2--.8"'---:-2-.9:T'---3:r'---::3-.'I'---::3:--.:::12'-- 3.~-~- 'i-41

remp. (IDOO/KI

Fig. 7: Arrhenius plot derived from the data of fig. 6. The full and dashed lines represent calculations assuming a single (E.4 = 1.6eV) and two different values of activation energy.

Page 468: Semiconductor Device Reliability

" f-H

U.

lEee

! 19 y.ars I I 2.5 y .... r ..

L-l--.J......L! I [I lEas! I J' [ ! I I II

Fig 8' F 'I Time (h ) : ' al ure rates at 300 r s

mdlcates the MILHDBI' C :~culated assuming E -\. preructlOn range, A - 1.6 and O,5eV, The shaded area

95

90

80

70

30

20

10

1 10

o

AI-gate devices

H~ST

H~ST THB

THB

o o

o

GOLD-gate devices

--------r----,--" '!SOOI j , • i I lk

F' 9 Time (hours)

Ig : Lognormal plot of c ' expenments, umulatlve failure rust 'b ' n utlOH obtamed with HAST d an HBT

469

Page 469: Semiconductor Device Reliability

HYDROGEN EFFECTS ON RELIABILITY OF GaAs MMICs

WILLIAM O. CAMP, Jr., RANDALL LASATER, VINCENT GENOVA, ROBERT HUME

IBM Systems Integration Division (SID) Owego. NY 13827-1298

USA

ABSTRACT. A series of investigations into unexplained RF gain changes versus time during life tests have lead to the conclusion that hydrogen gas in quantities as small as 0.5% of ambient atmosphere can cause significant performance degradation in as little as 168 hours at elevated temperatures (125°C). This amount of hydrogen has been readily observed in Kovar hermetic packages with 0.1 cc internal volume.

The apparent mechanism for this degradation is the conversion of gaseous hydrogen into atomic hydrogen in Pt metallization, with subsequent doping compensation due to the atomic hydrogen. The doping compensation leads directly to lower transcon­ductance, and lower RF gain. A change in the Schottky diode characteristics is also noted.

1.0 Experiment

Multiple stages of experiments were required to determine the mechanism of this effect and appropriate corrective actions. First, it had to be determined that hydrogen gas at elevated temperature was the factor causing RF gain degradation. Residual Gas Anal­ysis (RGA) was done on selected samples of packaged MMIC amplifiers showing a variety of RF gain loss from 0 to 5 dB per 30 dB of total gain after 168 hours at 125°C. Then, unpackaged amplifiers and individual FETs were put in a furnace with 100% hydrogen atmosphere for 4 hours at 150°C. This became the "standard" hydrogen exposure for all future experiments.

RF gain of amplifiers, drain current and transconductance versus gate bias of FETs, and gate I-V curves of FETs were measured before and after the standard hydrogen exposure. This set of measurements became the "standard" measurements. A control group of devices was subjected to the same temperatures but in ordinary atmosphere.

Second, a set of experiments was conducted t.o determine the extent of this effect. MMIC amplifiers from four vendors were subjected to the standard hydrogen expo­sure. The standard measurements were made before and after exposure. This exper­iment was repeated for a large number of wafers from two vendors, and for a large number of die across several wafers from one vendor. It should be noted that one of the vendors was ourselves, with MMIC devices made at our facility.

Third, the exact FET structure causing the degradation had to be localized. At this point, we restrict ourselves to MMIC amplifiers and FETs made in our own fabrication facility, because we make use of process changes as part of the experiment to determine

471

A. Christou and B. A. Unger (eds,), Semiconductor Device Reliability, 471-477. © 1990 Kluwer Academic Publishers.

Page 470: Semiconductor Device Reliability

472

the location and mechanism of the degradation. A process monitor device consisting of three gateless FETs with varying source-drain spacing was exposed to r.ydrogen to determine if either the ohmic contacts were degraded or the n-GaAs channel was affected. Then, FETs were made with the following gate metallizations:

• Ti/Au-ISOO/4000 • Ti - 600

Numbers after elements are thicknesses in angstroms. The objective was to see if the degradation was associated with any particular metal in the gate metallization struc­ture. Tests were also conducted with silicon nitride added to see if it would reduce the effect.

Fourth, the mechanism of degradation had to be learned. At this point, the results of the above experiments suggest the gate structure as the location and the presence of Pt as a contributing factor. Auger analysis was performed to test for migration of the Pt layer into the GaAs channel, as proposed in [1].

An alternate hypothesis is that the gaseous hydrogen is dissociated into atomic hydrogen in the Pt layer, diffuses into the GaAs forming a neutralizing complex with the Si donors, and results in loss of electrical activity and a modified interface between the metal and semiconductor [2]. Testing for this failure mechanism is accomplished by using an Automatic Network Analyzer (ANA) to measure capacitance as a function of voltage of FETs with I micron gate length (as opposed to large area dots) to determine the change in doping concentrations under the gate after hydrogen exposure. This hypothesis also implies that the degradation should be reversible by an amount dependent on temperature. Thus, devices that had been exposed to hydrogen and degraded were then exposed to 168°C and reevaluated.

The results of these experiments then lead to the further remaining questions: How does the atomic hydrogen reach the GaAs? Is this an effect that happens only at the periphery of the gate? A large area FET (commonly called a FA TFET) was made with just the Ti and Pt layers from the baseline process and exposed to hydrogen. It was reasoned that the hydrogen would have direct access to all of the area of the gate and would produce the normal change if it was conducted throughout the entire area to the GaAs. A negative result would mean that either the Pt must touch the GaAs to conduct the hydrogen to the GaAs, or that the hydrogen was blocked from going through the Ti layer but could be conducted along its outer surface.

2.0 Discussion

The first results were from RGA analysis of the sealed packages contammg GaAs MMICs that had been subjected to 168 hours at 12SOC. There was 100% correlation between amplifiers that showed some loss in R F gain and those packages that did not leak to the atmosphere and correspondingly had a measurable amount of hydrogen present. RGA anaylsis showed that hydrogen in the range of O.S to 2% by volume produced measure able RF gain degradation on GaAs MMIC amplifiers. Figure I and Figure 2 show the change in drain current and transconductance for an FET subjected

Page 471: Semiconductor Device Reliability

473

to the standard hydrogen exposure. A uniform gain drop of 4 dB was seen when biased at 50% Ids and is attributable to the drop in transconductance. Gate current as a function of voltage (I-V) curves are shown in later figures, and are used as a quick way to determine whether hydrogen is causing a change: .

-1.5 ~2.S -3

Gille Voltage (V)

.----------------------------------, 100

i 60

j

o BeIore H2 EKpoBure

i- Afll!I" H2 Exposure

! ~h-. ~~~~~ .~~H>-<H>~ ~.S ~1 -2,5 -3

Gate Voltage (V)

Figure I. Degradation of FET drain-source current Figure 2. Degradation of FET transconductance (Ids) aller H. exposure (Vendor A). (Gm) aller 112 exposure (Vendor A).

Table 1 shows the results of tests conducted on MMIC amplifiers from four vendors. At least three devices from each vendor were subjected to the standard hydrogen exposure, and the change in RF gain was observed. Note that devices from two of the vendors are not susceptible to the RF gain loss due to hydrogen ambient. Information about passivation and gate structure is included for each vendor. Addi­tional devices from multiple wafers from Vendor A were also subjected to the test. This data is shown in Table 2. Note the wide variation in effect from wafer to wafer and even within a wafer. Vendor B is the IBM facility in Owego.

Table I. Data on MMIC amplifier degradation Table 2. Data on MMIC amplifier degradation for four vendors. for mUltiple wafers from Vendor A.

Vendor MMIC Device SiN? Gale Siruclure Wafer MMIC Amplifier Device Number Amp Gain (A) Avg. (dB) 1 2 3 4 5

of As 1 ·0.1 -0.2 (dB)

2 ·3.3 -3.9 A -3.0 12.5 Yes Ti/PtiAu (?I?I?)

3 ·2.0 ·1.9 B ·3.0 13.0 No TilPl/Au

(600/200/4000) 4 ·5.0 -4.5

C <0.02 8.0 Yes Ti/Pd/Au (?I?I?) 5 ·4.9 ·4.6

D <±0.02 9.0 Yes TIlPtiAu 6 ·2.9 -4.4

(1500/50017) 7 ·2.6 -2.9

8 -4.1 ·4.1

9 +1.4 +1.6

10 +1.6 +1.1

11 ·4.1 ·4.2 ·4.0 -5.7 -4.6

Page 472: Semiconductor Device Reliability

474

The experiment with gateless FETs showed no change in the ohmic contact resist­ance or in the n-GaAs channel properties after exposure to hydrogen. This result points to the gate as the location of the degradation. Silicon nitride was deposited on FETs from Vendor R to see if that particular form of passivation may account for the negative results seen on devices from Vendors C and D in Table l. The silicon nitride did not prevent the hydrogen from causing degradation. In fact, some degradation could be seen immediately after the silicon nitride was deposited. This is expected, since the Plasma Enhanced Chemical Vapor Deposition (PECVD) process generates atomic hydrogen during deposition.

The experiments with different gate metallizations yield the clue to the cause of the failure mechanism. The next four figures show the drain current and transconductance as a function of gate voltage before and after exposure to hydrogen for two gate struc­tures lacking Pt. In Figure 3 and Figure 4, we see no change in either parameter due to hydrogen. In Figure 5 and Figure 6, with Ti/Au gate, the change in drain current is very slight at pinch off, and the change in transconductance is negligible. The gate forward bias I-V curves showed no change for the Ti/Au gate and a small change for the Ti gate. For comparison, Figure 7 shows the transconductance change for the standard process Ti/Pt/Au (600/200/4000 A) gate before and after hydrogen. The large change after exposure to hydrogen confirms that it is the presence of Pt that correlates with the degradation in transconductance. For this case, the gate forward bias I-V curve has decreased by 80 mV after hydrogen exposure.

50

o Before H2 Exposure

+ After H2 ExpOSUre

D~O----~O~2----~O~.4----~D~'--~-~O~.8----' Gale Voltage (~V)

,----------------------------.

i .. r= ...... --~ o Before H2 Exposure + Arler H2 Exposure

f wj

~2:L~-.~~-~~~~ o 0.2 0.6 0.8

Gate VOltage (-V)

Filture 3. FET drain current, before and after I h Figure 4. FET transconductance, before and after exposure, Ti gate. I h exposure, Ti gate.

Now, questions arise about the exact nature of the contribution of the Pt layer to this effect. Is the Pt diffusing through the Ti layer as is suggested by Canali [1], Ersland [3], and Roesch [4]7 Auger analysis of the Ti/Pt structure does not show any movement of the Pt into or through the Ti layer. It does show the Ti layer to contain about 15% oxygen. Canali [I] states that Ti with greater than 4% oxygen is a good barrier to gold, so it might also be effective to Pt. This analysis seems to rule out the concept of "sinking gate" as discussed in [IJ, [3J, and [4].

Paccagnella [5J, Aspnes [6J, and Lundstrom [7J give some insight into the mech­anism. It is postulated here that the Pt is a catalyst for converting the gaseous

Page 473: Semiconductor Device Reliability

475

hydrogen into atomic hydrogen that then migrates into the n-GaAs channel. The carrier concentration is reduced as the Si donors are compensated. The drain current and the transconductance, varying with doping and square root of doping, respectively, each degrade. Reference [2] also gives details of the effects of atomic hydrogen on the interface between the metal and semiconductor. It reduces the diode ideality factor and reduces charge effects that can keep the barrier artificially high, thus explaining why the barrier is seen to drop.

16

14

112 110 u .~

o Before H2 Exposure

+ After H2 Exposure

B

4°1 o Before H2 Exposure + Afler H2 Exposure

i '" to

°

d

~L'-'-------'-----i ~il o 0,2 0.4 0,6 ° 0.2 0.4 0.6

Gate Voltage I-V) Gate VoHage (-V)

Figure 5. FET drain current, before and aller 1-12 Figure 7. FET transconductance, before and aller

40

.. 30

.s w u c JlI u 20 , -g 0 lli c ~

'" 10

0 0

exposure, Til Au gate. If 2 exposure, Ti/Pt/ Au gate.

0,2

[] Before H2 Exposure + After H2 Exposure

0,4

Gate Voltage I-V)

0,6

o Before H2 Exposure + After H2 Exposure 1 ¢ 36h@168°C

'E ~ 2 8 c

~

+ +

0,40 0,45 o,so Gale Voltage (V)

o

0,55

Figure 6. FET transconductance, before and oller Figure 8. FET gate I-V curve aller H2 exposure, H2 exposure, Ti/Au gate. then heated to 168°C in atm. (no H2).

I f this hypothesis is correct, then two tests should give positive results:

1. Heating the FETs in the absence of hydrogen (atmosphere) should cause the silicon to release an amount of hydrogen depending on the time and temperature [2]. This removal of hydrogen should be accompanied by recovery in gain, transconductance, and diode barrier height. Partial recovery is seen in Figure 8 if heated to 168°C for 36 hours. The fact that there is not full recovery may indicate that a secondary (and

Page 474: Semiconductor Device Reliability

476

irreversible) change in the gate metal semiconductor interface occurs via another mechanism. This is further supported by several results that simultaneously show an increase in drain current (due to reduced depletion layer thickness), decrease in transconductance (due to reduced carrier concentration), and reduced Schottky gate diode barrier height. This secondary process may not require the conversion to atomic hydrogen, however.

2. Doping concentration as indicated by capacitance as a function of FET gate voltage should show a drop. Figure 9 shows just such a decrease in apparent doping after exposure to hydrogen.

Now, the remaining question is, does the hydrogen pass through the Ti layer or must the Pt be in contact with the n-GaAs? The experiment with the FA TFET showed a shift in the gate forward J -V characteristic (Figure 10) of 0.1 times the average shift for a narrow gate FET. This result is interpreted to mean that the atomic hydrogen does not pass through the Ti, and that the failure mechanism is active only at the periphery of the gate structure. Because the minimum dimension of the FA TFET is ISO microns, and we assume that the ratio of J-V shift is equal to the ratio of areas affected, we infer that the diffusion in from the edge is approximately 7.5 microns.

Auger analysis of our Ti layer shows 15% oxygen content, which is well known to decorate the grain boundaries and prevent the passage of many species through the layer [1], and may well be preventing the passage of the atomic hydrogen formed in the Pt layer. It is not known whether the hydrogen is conducted along the outer surface of the Ti to the GaAs or a slight amount of Pt overlaps the Ti and directly touches the GaAs. Experiments which attempted to reduce this possibility of overlap by changes in the photoresist stencil were inconclusive.

o Before H2 Exposure

+ After H2 Exposure

o+---~--~--~----._--~--~ 0.08 0.1 0.12 0.14 0.16 0.18 0.2

Depth [urn)

,----------------------------,

1.2

« .s 0.8

~ <3 0.6

0.4

0.2

o Before H2 Exposure

+ After H2 Exposure

0.2

Voltage (V)

0.4

Figure 9. Doping concentration of channel below Figure 10. Change in gate forward bias I-V curve of gate before and after H 2 exposure. a FA TFET TifPt gate exposed to II2.

Page 475: Semiconductor Device Reliability

477

3.0 Conclusions

Gaseous hydrogen and moderately elevated temperatures of 150°C can lead to degrada­t.ion of transconductance and RF gain in GaAs FETs and MMICs. The failure mech­anism is the conversion of gaseous hydrogen into atomic hydrogen in the Pt layer of the gate metallization, and the subsequent doping compensation and carrier removal from the active channel as the atomic hydrogen diffuses into the channel. This failure mechanism can be averted by eliminating the Pt layer if the Ti layer has sufficient oxygen content (15% appears to work) to prevent Au from diffusing through to the GaAs.

A secondary failure mechanism appears to be hydrogen (form unknown) affecting the interfacial layer between the gate metal and GaAs, reducing the effective diode barrier height. This mechanism itself does not appear to either affect the carrier con­centration in the channel or the transconductance of the FET.

4.0 Acknowledgements

The authors would like to acknowledge the help of L. Rathbun for the Auger analysis, P. Schuessler for the RGA anaylsis, and A. Callegari, T . .Iackson, and T. I-lickmott.

5.0 References

1. Canali, c., F. Castaldo, F. Fantini, D. Ogliari, L. Umena, E. Zanoni, "Gate Metallization 'Sinking' into the Active Channel in TijWjAu Metallized Power MESFET's," IEEE Elect. Dev. Let., Vol. EDL-7, No.3, March 1986.

2. Chevalier, .I., w.c. Dautremont-Smith, C.W. Tu, S . .I. Pearton, "Donor Neutralization in GaAs(Si) by Atomic IIydrogen," Appl. Phys. Lett., Vol. 47, No. 2, .Iuly 15, 1985.

3. Ersland, P., .I. Lanteri, "GaAs FET MMIC Switch Reliability," GaAs IC Sympo­sium, 1988.

4. Roesch, W . .T., "Thermo-Reliability Relationships of GaAs ICs," GaAs IC Sympo­sium, 1988.

5. Paccagnella, A., A. Callegari, E. Latta, M. Gasser, "Schottky Diodes on Hydrogen Plasma Treated n-GaAs Surfaces," to be published.

6. Aspnes, D.E., A. Heller, "Barrier Height and Leakage Reduction in n-GaAs-Pt Group Metal Schottky Barriers upon Exposurc to lIydrogen," .I. Vac. Scr. Techno!. B., Vol. 1, No.3, .Iuly-Sept, 1983.

7. Lundstrom, I, M. Armgarth, L. Peterson, "Physics with Catalytic Metal Gate Chemical Sensors," CRC Critical Reviews in Solid State and Materials Sciences, Vol 15, Issue 3,1989.

Page 476: Semiconductor Device Reliability

TEMPERATURE DISTRIBUTION ON GaAs MESFETs: THERMAL MODELING AND EXPERIMENTAL RESULTS

G. CLERICO TITINET - P. M. SCALAFIOTTI CSELT, Centro Studi e Laboratori Telecomunicazioni SpA via G. Reiss Romoli, 274 10148 Torino ITALY

ABSTRACT. Median life forecasts of GaAs devices are usually obtained from accelerated 1 ite tests where temperature is the accelerating factor; for this reason they are strongly dependent upon the accuracy with which the temperature of the device is known. A computer model allowing the temperature mapping of the chip surface is proposed and simulation and measurement results on commercial FETs with different layouts and power levels are compared. The three methods used to measure the channel temperature based on diode voltage drop, infrared emission and liquid crystals are also discussed.

1. INTRODUCTION

There are several reasons to keep cool a semiconductor device during operat ion; these are ma i n ly re lated to performance and re li abil i ty considerations. Since GaAs exhibits a thermal conductivity which is about one third of Si, one expects that GaAs devices should run hotter than Si ones, thus requiring a more careful thermal design.

Temperature greatly affects the electrical performance of a MESFET because it reduces the electron drift velocity thus reducing the gain and slowing down the device. Moreover', thinking about Monolithic Microwave Integrated Circuits (MMICs) where low-noise devices are often integrated with power ones, one should be aware that noise increases when the FETs become hotter.

As far as reliability is concerned commonly reported failure mechanisms such as interditfusion at ohmic contacts, activation of traps and defects, electromigration, exhibit activation energies ranging from 0.9 to 1.8 eV (1],(2]. The higher the activation energy, the greater the accelerating effect of temperature on the failure mechanism. This fact has two consequences: first, as a general rule, keeping cool the device will certainly improve its reliability and second, it we want to obtain median 1 i fe forecasts with reasonable accuracy from acce 1 erated 1 i fe tests, we need to know the actua 1 channel temperature of the FET.

479

A. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 479-489. © 1990 Kluwer Academic Publishers.

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480

This paper is organized as follows: in section 1 we present a simplified but accurate model in order to obtain the temperature map of a MESFET, section 2 will review the three most widely used methods to measure the channel temperature of a device whi 1e in section 3 some calculations obtained with our simulation program will be compared with experimental results.

2. THERMAL ANALYSIS OF MESFETs

2.1 The Problem

Basically a MESFET consists of two ohmic contacts, called Source and Drain, and of a Schottky contact, called Gate. The extension of the depletion region associated to the Schottky junction, fixed by the voltage applied to the Gate, determines the cross sectional area available for conduction thus modulating the electron flow from Source to Drain. The active area of a GaAs FET is only a few tens of a micron thick on a chip at least 100 times thicker and usually contains several of these unit cells in parallel. Heat is generated by Joule effect within the active region where current flows and then is generally removed from the other side of the chip which is soldered to a heat­sink.

The rigorous treatment of heat flow in a MESFET requires therefore the solution of a three-dimensional problem.

As has been widely reported the true temperature distribution in a MESFET satisfies the following nonlinear equation

V·k VT = 0 ( 1 )

where the thermal conductivity k is temperature dependant and, in the range of usual operation of these devices, can be approximated by

k(T) = 1.08 T-0.26 (2)

However, using the Kirchoff transform technique described in [3], one can solve equation (1) keeping k constant and then find the exact values of T with the following transform

t 1 ko

T f k(T) dT

To (3)

where To and Ko refer to the heat sink temperature and to the corresponding GaAs thermal conductivity value, while t is the temperature calculated under the constant k condition. The integration of eqt. (3) becomes very simp 1 e us i ng the approx i mat ion given by eqt. (2) •

The papers pub1 ished to date about the problem of simulating the thermal behaviour of GaAs FETs can be roughly divided into two

Page 478: Semiconductor Device Reliability

481

cathegories. To the first group belong a certain number of simplified models that generally treat the problem in terms of thermal resistance, defined as the ratio between the difference in temperature from channel to heat-sink and the corresponding dissipated power.

Since the channel temperature can be defined either as the value at the hottest point or as the average over all gates, this formulation may lead to quite different results in multi-gate devices, as we will see later. Simple relationships between thermal resistance and geometrical parameters of the device were derived by Fukui [4] from measurements carried out essentially with the electrical method.

An accurate evaluation of the thE~rmal resistance can also be obtained from equivalent electrical circuits: table 1 summarizes the equivalences between electrical and thermal quantities.

Electrical Quantities Thermal Quantities

Quantity Symbol Unit Quantity Symbol Unit

Electric Q Coulomb Heat Qt Joule charlie quantity

Electric V Volt Temperature T -C potential

Current I=6.Q/At Ampere PowE,r P= l:l Qt/ D. t Watt

Ohmic R=V/I ohm Thermal Rth=LT/bI -C/W resistance resistance

Electrical C=6. Q/ b V Farad Thermal C.~t/6 T J/-C capacitance cape,ci ty

Time T=RC sec. Time T=Rth.CK sec constant constant

Table I - Equivalence between electrical and thermal quantities

The heat flow in a multi-gate device is usually treated as analogous to the capacitances of multiple, coupled transmission lines since, after some manipulation, the e'quations describing the two systems are formally the same. A clear eX;Cimple of this technique can be found in [5].

The main limitation of these methods is that they can only provide the average temperature over all the active area of the device.

To the second group belong the so called physical models, usually based upon the solution of a system including the Poisson and the current continuity equations to model the electrical behaviour of the MESFET and the previously cited heat equation in order to account for temperature effects. The three unknowns are therefore the charge density, the electrical potential and the lattice temperature at any point of the simulated region. The dramatically high computational effort required by this approach led many authors to simpl ified two­dimensional solutions where the simulated region approximately

Page 479: Semiconductor Device Reliability

482

corresponds to a cross section of the active area or is slightly wider [6).

Though this is probably the best way to account for temperature effects on the electrical characteristics of a MESFET (a typical example is represented by the negative resistance region in the Drain current vs. Ora i n vo ltage curves for low Gate vo ltages), there are some disadvantages if one is mainly interested at the temperature distribution on the device.

In fact the two-dimensional approach is generally limited to a single unit cell thus neglecting temperature interactions between adjacent gate fingers in multi-gate structures; moreover a two­dimensional solution cannot obviously handle a relevant phenomenon that takes place along the third dimension, that is the end cooling of the gates. In addition to these drawbacks a physical model requires as input data the doping and the mobility profiles which can be measured with the necessary accuracy only from appropriate test patterns on the wafer and not from the actual device.

2.2 Model Description

In order to obtain a fully three-dimensional solution while keeping the computational effort reasonable, we divided the MESFET into unit cells, each one centered on a gate finger. This situation is schematically represented in Fig.' for a device with two unit cells.

I I

m Figure , - The superposition of the contributions of each unit cell gives the final temperature distribution in a two gate fingers device

Simulations obtained from physical models have shown that the heating area is roughly a semi-cylinder whose axis lays along the Drain edge of the Gate stripe and whose diameter is approximately the Gate-Drain spacing; it can therefore be treated, as shown in [7), as a rectangular heating element, whose shorter dimensions is twice the semi-cylinder diameter.

Our unit cell has to be wide enough to contain every other Gate stripe or at least the closer ones, in order to use the superposition principle thus accounting for thermal interactions between near Gates. Under the hypothesis that the top and lateral surfaces of the chip are

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483

adjabatic, except for the rectangular heating element where a constant heat flux is present, and that the bottom of the chip is an isothermal surface, the temperature at each point of the chip can be calculated in terms of a double Fourier series [8]: tlhe greater the number of terms in the series, the better the accuracy of the result.

The hypothesis of adjabatic surfaces is in most cases reasonable, since the heat removed through convection and radiation processes is negl igible. Sometimes however there is a considerable cool ing effect due to heat conduction through the bonding wires: a typical gold wire used to interconnect the device with a 25 ~m diameter and 200 ~m long has in fact a thermal resistance of about 1300 °CjW. The temperature distribution on a device with several bonding wires may therefore be significantly affected by this conduction mechanism.

If necessary this phenomenon can be taken into account by simply using unit cells slightly bigger than the actual device, as can be seen in Fig.2.

r---_----I------T"- -, I I

HEAT FLUX I I I I I I I I

a} b)

Figure 2 - Depending on device geometry a considerable amount of heat is extracted through the bonding wires (a); this effect can be taken into account using unit cells wider that the actual device (b)

3. EXPERIMENTAL METHODS FOR TEMPERATURE MI:ASUREMENTS ON GaAs FETs

This section briefly reviews the three methods we used during our experiments to determine the channel temperature of the devices under test, the aim being to point out advantages and disadvantages of each measurement technique.

3.1 Liquid Crystal Measurement Technique

Unlike most materials that have one temperature which separates solid and liquid states, nematic liquid crysta'ls show an intermediate phase between liquid and crystalline state which is called nematic phase.

In this phase all the molecules are aligned along the same direction and a thin film of liquid crystal can act as a polarizer; above a certain temperature which depends on their chemical composition the molecules become randomly oriented corresponding to the isotropic phase of the liquid crystal which loses this optical property. Since the transition between these two states, the so called clearing point, is abrupt it is well suited as a temperature indicator of the surface

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under the liquid crystal film. The measurement procedure is the fo llowi ng: the device to be

characterized is coated with a thin film of liquid crystal, mounted in its test fixture and observed under a microscope illuminated with polarized light. The light reflected from the chip surface is observed through a rotating analyzer; when the analyzer is crossed with the polarization axis of incident light the regions not covered by the liquid crystal will appear dark, but the active area of the device will be visible since the liquid crystal film acts as a third polarizer.

When the MESFET is powered up heat is generated on its surface and the regions within the active area where temperature exceeds the clearing point become dark; moving up and down the Drain voltage makes the dark region blink and become clearly visible.

The thermal resistance of the device can be easily calculated monitoring the temperature of the test fixture and the bias point. The best way to document these measurements is to use a color TV camera connected to the microscope and a video recorder.

This is probably the most precise technique because the clearing point of the liquid crystal can be determined with an error less than 0.2 GC, and the spatial resolution is very high.

However this method can not be appl ied to hermetically sealed devices, to flip-chip mounted FETs and to FETs employing an air bridge crossover that hides the active area.

Moreover the accuracy of the measurement depends on the uniformity of the liquid crystal film which is not always easy to apply, especially when the bonding wires are very close to the region to be observed.

3.2 Electrical Measurement Technique

The idea to use the temperature dependance of an electrical parameter as an indicator of the device temperature has been widely used to characterize snicon in.tegrated circuits, where the substrate diode is usually chosen as the temperature sensitive element. Fukui was the first to report an appl ication of this technique on GaAs FETs [4]; since then many different versions of the measuring circuit have been developed and some of these are now commercially available.

In the case of MESFETs the electrical characteristic used is the forward Gate voltage at a fixed current value, which decreases almost linearly with temperature at a rate of about 1.3 mV/GC.

This coefficient is strongly dependant on the metal used for the Schottky junction, so the first thing to do is to calibrate the system, that is to obtain the forward Gate voltage versus temperature relationship. After calibration the FET is biased at the desired operating point and the bias level is kept constant except for a very short interval during which the Drain voltage is removed, the Gate is switched to the constant current source and the corresponding forward voltage is measured through a sample and hold circuit.

Comparing the measured voltage with the calibration curve previously obtained gives the channel temperature of the device.

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The temperature measured is of cours,e an average value between the different gate fingers so it is impossible either to detect hot spots or to obtain any further information about temperature distribution on the chip. However this is a very fast and easy to use method which is suitable for every kind of MESFET independently on the device layout or on how the ch i pis mounted ins i de the pacikage.

In fig.3a and 3b are reported the main waveforms in the circuit developed in CSELT for these measurements [9].

Figure 3 Waveforms in the circuit for thermal resistance measurements: (1) Gate forward voltage pulse when the channel is cold (2) Sample and hold triggering signal (3) Drain bias (4) Gate forward voltage pulse when the channel is hot

3.3 Infrared Measurement Technique

Every body at a temperature above the absolute zero emits an infrared radiation (IR) whose intensity depends on the temperature, the surface conditions and the constituent material. In the range of MESFET operating temperatures the wavelenght spectrum lays between 2 and 30 microns. The lower part of this spectrum can therefore be observed with a usual sol id state detector (based on PbS, HgCdTe or InSb) and used as an indicator of surface temperature.

Also in this case it is necessary to calibrate the measuring system in order to account for the different emissivities of the materials present on the chip surface. Modern commercial instruments however are completely computer controlled so the great number of data to handle during calibration and measurements are no longer a limiting factor. Moreover the device is held tightly under the objective lens instead of being mechanically scanned, with a significant increase in accuracy over older measurement systems.

The main drawback of this technique is the spatial resolution which is physically limited by the wavelenght to be detected and can be up to 10 or 20 times the minimum geometry of the MESFET.

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4. EXPERIMENTAL RESULTS

In order to validate our model we simulated the thermal behaviour of three commercial devices intentionally chosen with completely different layouts and power handling capabilities. A sample of each device was microsectioned in order to precisely measure the chip thickness and the geometrical parameters of Source, Gate and Drain electrodes.

Temperature maps were obtained with the IR system commercially available from Barnes Inc. (USA).

The first device was a typical low-noise FET with a 0.5 /lm Gate lenght suitable for operation up to 18 GHz. The chip thickness was 120 /lm. Measurements were carried out between 100 and 150 mW of dissipated power.

Fig.4a reports the schematic layout of the device, while fig.5a shows the temperature profi le along the Gate stripe. The agreement between simulation (thin line) and measurement is good: the difference at the hottest point is about 1 ·C with a 2% relative error and the profile shape obtained from the model, with the three peaks and the two valleys, fairly fits the experimental results.

The two other devices simulated had the interdigitated structure schematically represented in fig.4b. The medium power MESFET had 14 Gate fingers half a micron long and was 125 /lm thick; the saturation current was 150 mA and the maximum Drain to Source voltage was 7 V.

a) b)

Figure 4 - Schematic layouts of the low-noise MESFET (a) and of the power ones (b)

This device is suitable for operation up to 12 GHz. Thermal characterization was done at about half a Watt of dissipated power. As can be seen in fig.5b the temperature profile obtained from the model is about 15 ·C higher than the measured one. We have to consider that in the measured profile the peaks are invisible due to the limited resolution of the instrument so a meaningful information can be obtained only comparing the average values. The relative error is 10%

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46

U 44

~ 42

UI II: :J I- 40 « II: UI 11. 38 :E UI I-

36

34 a 100 200 300

a) X AXIS ( ~m)

180

170 U ~ UI

160 II: :J

150 I-« II: UI

140 11. :E UI I-

130

120 -40 0 40 80 120 160 200

b) X AXIS ( ~m)

60

U 55

~ UI 50 II: :J

~ 45 II: UI 11. 40 :E UI I-

35

30 a 100 200 300 400 500 600

c) X AXIS ().lm)

Figure 5 - Comparison between the temp~~rature profi les obtained from simulation (thinner Hnes) and experimental results obtained with IR measurements for the low-noise FET (a), for the medium power FET (b) and for the power FET (e)

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so in this case the model doesn't seem to work very well. However we must consider that the device is bonded inside the package with five gold wires (2 Source wires about 400 Mm long, a Gate wire and 2 Drain wires about 500 Mm long) which represent a parallel thermal resistance of about 600 °C/W.

If we combine this term with the calculated thermal resistance of the chip which was 165 °C/W we obtain a value very close to the 130 °C/W resulting from IR observations. This confirms that the number of bonding wires and their placement can significantly affect the thermal resistance of the device.

The third MESFET we examined was a power device able to deliver 1 W at 12 GHz; it had 40 Gate fingers and the die was thinned down to 35 Mm. The saturation current was 400 rnA and the maximun Drain to Source voltage was 15 V. This device was tested at a power level of 1.5 W. The thermal resistance of this device was also measured with the electrical method and the result was 14.9 °C/W which is, as one can expect, lower than the value deduced from IR observations (16.3 °C/W). Also in this case the values obtained by simulation are in excellent agreement with experiment as far as the shape of the temperature profile is concerned, but the simulated curve appears to be shifted up of about 7 °C which means a 15% relative error (fig.5c).

This happens because Source electrodes are connected to the rear side of the chip by means of via-holes which, in addition to the wires, provide to the heat flux a preferential path towards the heat-sink. It should be pointed out that even if we had carried out the simulation with a more complicated and time consuming physical model the calculated temperature profile would have been over-estimated. Once again we notice that not only the geometrical parameters playa key role in the determination of MESFETs thermal behaviour.

5. CONCLUSIONS

A simpl ified but accurate model has been developed which allows the temperature mapping of GaAs FETs. The comparisons made between simulations and measurements for three different commercial devices have confirmed the validity of our model. In the near future this will be a useful tool to investigate from the thermal point of view more complicated GaAs devices such as MMICs.

ACKNOWLEDGEMENTS

The authors wish to thank M. Muschitiello and M. Stucchi of CSATA laboratories (Bari) for their help in IR measurements.

REFERENCES

[1] Clerico Titinet G., and Riva D. E. (1989), 'Reliability of Compound Semiconductor Microwave Field Effect Devices', in Microeletronic

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Re 1 iabil i ty voL 2: Integri ty Assessment and Assurance, E. Poll i no Editor, Artech House Inc., Norwood MA (USA). [2] Roesch W. J. (1988). 'Thermo Reliability Relationships of GaAs ICs', Proc. of GaAs IC Symposium, Nashville Tennessee, (USA). [3] Joyce W. D. (1975), 'Thermal Resistance of Heat Sinks with Temperature Dependent Conductivity', Solid State Electronics, Vol. 18, p. 321. [4] Fukui H. (1980), 'Thermal Resistance of GaAs Field Effect Transistor', IEEE International Electron Devices Meeting Digest, p. 180. [5] Cooke H. F. (1986), 'Precise technique finds FET thermal resistance', Microwaves and RF, n. 8 p. 85. [6] Ghione G., Golzio P., and Naldi C. U. (1988), 'Self-Consistent Therma 1 Mode 11 i ng of GaAs MESFETs: A Comparat i ve Ana 1 ys i s of Power Device Mountings', Alta Frequenza, Vol. LVII n. 7 p. 311. [7] Wemple S. H., and Huang H. (1982), 'Thermal Design of Power GaAs FETs' in GaAs FET Principles and Technology, J. V. Dilorenzo Editor, Artech House Inc., Norwood MA (USA). [8] lindsted R. D., and Surty R. J. (1971), 'Steady-State Junction Temperatures of Semiconductor Chips', IEEE Trans., Vol EO-19 n. 1 p. 41. [9] Clerico Titinet G., and Manzone G. (1988), 'Thermal Resistance Measurements and Reliability of GaAs Power MESFETs', paper presented at 12th Workshop on Compound Semiconductor Devices and Integrated Circuits, lugano (Switzerland).

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"High Speed IC ReliabUity

A.A. lliadis FO.R.T.H. / Univ. of Maryland Electrical Engineering Dept. College Park, MD 20742

Abstract

Concerns and Advances"

A review of some of the main reliability problems, associated with electromigration and stress in interconnects in high speed Si digital IC' s and interdiffusion of the gate metallizations in GaAs IC' s is given. Some reliability concerns with InGaAs/InP heterojunction structures, inherent to these materials are pointed out. Possible solutions to eliviate such problems are discussed.

I. Introduction.

As the dimensions of high speed integrated curcuits continue to decrease, they impose severe requirements to the size of metal interconnects and the integrity of contact metallizations. As a result, reliability probelms associated with electromigration, stress and structural or chemical instabilities are becoming more and more pronounced, limiting the reliability of these circuits. Furthermore, advances in processing, the introduction of new metal combinations, and novel passivation and dielectric application techniques, aiming towards improving circuit performance, may also result in new degradation mechanisms and additional reliability issues.

In this review some of the main reliability issues of 5i and GaAs based digital integrated circuits will be addressed and in particular issues associated with the formation of voids in interconnects due to electromigration or stress in Si IC' s, the degradation of the gate-channel system in GaAs devices and premature breakdown problems in the InGaAs/InP heterojunction system due to intrinsic mechanisms inherent to these structures.

II. Metal interconnects in SI Integrated circuits

AI and AI-Si (1 %wt) have been the preferred interconnect metallizations

491

A. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 491-506. © 1990 Kluwer Academic Publishers.

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for many years in high speed integrated circuits and their electromigration (EM) properties have been studied in detail [1], [2]. However, as the dimensions decrease to submicron levels, the current density requirements become more stringent and metallization failures become unacceptably high. When an electric current passes through the conductor line, a flux of electromigrating ions is formed. This electromigration occurs primarily along the grain boundaries in the conductor and the atomic flux is strongly dependent on current density and temperature [3]. The flux of atoms forms voids and hillocks which eventually lead to electromigration - induced failure by void open in the conductor line or extrusion short between adjacent lines. In the Al based single-layer interconnects, the microstructure of the layers affects the EM properties. In general the EM lifetime in this alloy system depends on grain size, grain distribution and film orientation. In order to improve the EM properties of Al-Si interconnects, (0.1-1 %) Cu has been added [4], [5] and found to suppress the formation of voids and increase the lifetime substantially. However, the addition of Cu in the AI-Si metallization increases the corrosion susceptibility of these interconnects, reduces the heat transfer [6] with the Si substrates, and presents serious difficulties to plasma dry etching when submicron line definition is needed.

A viable alternative to Cu in single-layer interconnects has been reported to be Ti doping [6]. AI-Si-Ti (0.15% wt) interconnects showed a lifetime after stress at T=1500C and J=lx1()6Ncm2, of 3200 h which was very close to that of Al-Si-Cu, but without the drawbacks of Cu and with a better heat transfer rate by a factor of 1.5 (Table I). Higher concentrations of Ti (0.2 - 1.2% wt) have been reported [7] to markedly increase the activation energy for mass transport, E A' between the binary Al-Ti (EA..=0.55eV) and the ternary Al-Si-TI (EA=0.7eV for Ti ~ 0.6% wt). This increase in EA was linked to the formation of precipitates at the grain boundaries that reduce grain boundary diffusion and present an additional barrier to EM.

Although the lifetimes of Ti doped alloys are comparable to those of Cu doped alloys, the major disadvantage is the substantially increased resistivities, which depend on temperature and eventually can affect the high speed performance of the circuit resulting in a premature functional failure.

Furthermore, when single layer inteconnects are passivated by SiN or PSG, an additional problem of mechanical stress-induced void formation due to the mismatch of the two layers, has to be taken into account. In Al-Si layers passivated with SiN, two types of stress induced voids have been reported [8] : a "slit-like" void and a "wedge-shaped" void. Void-open failure (catastrophic) was found to be accelarated by the increasing thickness of the SiN fIlm, and the decreasing width and thickness of the interconnect, consistent with the induced mechanical stress in the interconnect given by [8] :

(1) 6 AI = 6S1N • t (2/W + 1ff)

where 6 AI = internal stress in interconnect (tensile)

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6SiN = internal stress in SiN (tensile) t = thickness of SiN T = thickness of interconnect W = width of interconnect

The addition of as little as 0.1 % wt eu was shown [8] to reduce the percentage of open failures by one order of magnitude. It was concluded that the formation of the "slit-like" void, which is primarily responsible for the open failures, is inhibited by the presence of Cu atoms at grain boundaries that getter the vacancies and make them inmobile. The "wedge-shaped" voids were found to be formed primarily by grain boundary diffusion. The two mechanisms are shown schematically in figure l(a) and (b).

In order to avoid catastrophic failures from void-opens, multilayered metallizations consisting of an overlayer of Al alloy and an underlayer of a refractory metal, are often used in advanced VLSI systems, due to their advantages in step coverage continuity and EM properties. In this type of intecOlmect, the refractory metals may react at elevated temperatures with the Al-Si layer causing a gradual increase in resistivity but the catastrophic open failure is avoided by diverting the current through the refractory metal conductor whenever a void appears in the Al-Si layers. The time dependence [9] under temperature stress for several typical individual samples of single-layer, two layer and three layer metallizations are shown in figure 2. The slow increase in resistance is evident in the multilayered fIlms, while in the signle-Iayer film failure is precipitous.

As the resistance increase is gradual it is hard to select a suitable failure criterion for these int.~rconnects, such as for example, the cracking of the passivating overlayer or the high speed perfomance of the circuit. As the tolerances of performance vary for each application, the best failure criterion for multilayered metal interconnects is still an open question and a topic for research, but a certain percentage of resistance increase for a standard size line may be a suitable criterion for this case.

Such a failure criterion of 20% increase in line resistance has been suggested [10] and used to det.~rmine the EM performance and mean time to failure (MTF) of Ti:W/Al-Si and Ti/W/Al-Si films for various annealing temperatures (350-5500C). Based on this criterion, a significant improvement in EM performance was demonstrated [10] for both films, for annealing temperatures between 450 and 5000C. The increase in resistivity and activation energy (EA) for EM was associated with the formation of intermetallic compounds such as AlI2 W and Ak W that produced a more stable, EM resistant interface between the A1-Si and the Ti : W or Ti/W layers. The importance of a standard criterion for these interconnects was demonstrated by varying the failure criteria. It was shown [11] that the effective activation energy EA, varies with the failure criterion as shown in figure 3. It was concludeCl that due to the instability observed in the resistance after extensive voiding and healing due to local heating at the voids, the activation energy is more

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accurately detennined for failure criteria of less than 40% in resistance increase.

However, in view of the possibility for functional failure of the circuit at this level of resistance increase, the 20% failure criterion appears to be the best suited so far for high speed IC reliability assesment.

In summary, a number of areas of reliability concerns in single and multilayered interconnect metallizations to Si IC's, have been addressed. In single-layer interconnects, Ti doping appears to be the promissing one. The increase of interconnect thickness may be considered in order to compensate for the increased resistivity of the films, but a compromise has to be achieved to avoid mechanical stress-induced damage from the passivating layers. The ultimate size of the lines will be decided by stress-induced void formation phenomena. When two or three layer interconnects are used, the lack of catastrophic open failure, necessitates the use of percentage resistance increase failure criterion, which is suggested to be in the region of 20%.

The standard thermal annealing of these interconnects increases the MTF dramatically (2000 h) and can be replaced by laser assisted rapid thermal annealing for improved interlaces and EM perlormance. Although these systems are significantly more tolerant to stress than single layered structures, optimization of the thickness and quality of the passivating oxides/nitrides, and the thickness and width of the interconnects, is essential for improved reliability, Furthermore, the use of other refractory metals like Mo and silicides like TiSix may be benefiCial, in spite the higher resistances.

III. Gate Metallizations for GaAs IC's

GaAs IC technology is rapidly approaching high volume manufacturing and it has become increasingly important to demonstrate highly reliable operation of GaAs based high speed IC's.

One of the main areas of concern is the reliability of the MESFET components, and one of the main requirements in GaAs MESFET technology is the thermal, structural and chemical stability of the gate matallizations. Reliability tests have shown a significant decrease in saturation current loss, threshold voltage, Vp and channel resistance RCH [12], [13], consistent with gate metal intermixing with the GaAs active layer. Common metallizations used, are based on a combination of refractory metals like Ti, TI/Pt, Ti/W, Ti/Pd and an overlayer of Au. Ti/PdlAu gates on implanted n-channel GaAs FET's have been reported [13] to have a MTF of two million hours at 1000C, where the failure criterion was a decrease in IDSS~O%. However, accelerated life tests at 2900C for 100 h showea a fuss decrease of 35%, a Vp decrease of 20%, an increase in RCH of 40% and a decrease in transconductance gm of 5%. TiW/Au gates were reported [12] to degrade similarly, with loss decreasing by as much as 50% and V p decreasing by 48% at temperatures between 2300C and 275°C. Increase in the on-resistance and decrease in IDSS and Vp has also been reported [14] for the Ti/Pt/Au system. The aegradation was attributed to the indiffusion of Au through the Pt layer into the active region of the device.

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The degradation mechanisms consistent with the observed changes in the gate parameters, are :

(a) indiffusion of the gate metal, primarily Au, that moves the metal-semiconductor interface further into the channel thus reducing the channel thickness [15].

(b) indiffusion of compensating impurities from the gate that reduce the doping of the channel. Au has been reported to be a compensating impurity in GaAs [16]. Furthermore, other inadvertent contaminants like Cr, Fe, Mg, Mn, may be present.

(c) outdiffusion of dopant atoms (Si, S) from the active layer to the gate metal. Ti is known to be a gettering agent for many other atoms.

The indiffusion of Au through the refractory metal has been reported in TVW/Au gates [15] after RF testing at channel temperatures of 185°C for 1()()()() h, IUld in Ti/Pt/Au gates [14]. High temperature reverse bias (HTRB) tests and high forward gate current (HFGC) tests showed degradation in ID.s.s' Vp and ReH, consistent with channel reduction. Auger analyses l14], [15] Clearly showed the penetration of Au into the active layers. It is therefore, clear that a diffusion barrier to Au will improve the degradation of the gates. Silicides may be promising in this area of concern. WSix has been reported to produce good contacts with cIV=O.75 eV and n=1.15 [17]. The system was found not to react with the GaAs layer during high temperature annealng at 8000C for 20 minutes, although Ga and As outdiffusion was observed. It was concluded that the WSi045 system can be a good indiffusion barrier, but the difficulty in ·ac magnetron codeposition produced a significant contamination of mostly Zn and also Cu, Cr, Fe and V that impaired the performance of these gates. Other ~mbinations of silicides like MoSix and TiSix, may be more appropnate.

IV. Reliability Concerns of Heterojunction FET's

III-V semiconductor heterojunction FET's based on InGaAs and InP, are attracting considerable attention for high speed digital applications due to their higher peak electron velocities, higher electron mobilities, improved thermal conductivity, and better confinement of the 2D electron gas at the heterojunction interface. Heterojunctions based on these materials have been reported to demonstrate high performance with transconductances over 300 mS/mm for und0ped layers [18] and over 1000 mS/mm for modulation doped stru,*ures, but systematic reliability studies to define the stability and lifetime of these devices are yet to be done. Although some of the reliability problems of these materials are expected to be of similar nature with those of GaAs, some problems are inherent to these structures and have to be dealt with separately.

InP' which is the high energy gap semiconductor in these structures, has a very low Schottky barrier height (<I>b~.5 eV) and for

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this reason insulated gates using Si02 or SiN are the most common way of fabricating these transistors.

However, high densities of interface states at the Si02/InP interface [19] can cause serious gate current drift problems and special processing and surface passivation has to be developed to improve the long term stability of the gates. In spite of their high speed performance, these structures usually show significantly lower breakdown voltages than expected, which represents another area of reliability concern. For GaAs, breakdown fields are of the order of 4xl<P V/cm, for InP the fields are even higher 6xl<P V/cm and for InGaAs EB=2-3xl<P V/cm. Therefore, in GaAs MESFET's a reasonable breakdown voltage, V BO' is expected to be between 60 and 80 V for a 6 !AID source-drain separation. In InP MISFET a V Bo~40 V for 4 !AID separation is expected. However, devices based on the InGaAs/InP heterojunction appear to breakdown at voltages of less than one-tenth of the expected drain-source voltage, which corresponds to at least one order of magnitude lower breakdown fields, as shown in Figure 4. Typically the breakdown is catastrophiC, resulting in the formation of a current filament between source and drain and the destruction of the device. As seen in Figure 4, the lowest breakdown values are for the InAlAs/lnGaAs/InP and InAlAs/InP/lnGaAs structures and the highest for the Si0zLInP/lnGaAs structure.

Two mechanisms for premature breakdown are proposed : (a) surface-states assisted avalanche and (b) wide to narrow band gap hot-electron-induced impact-ionization avalanche breakdown.

The influence of surface states on breakdown voltage is well known for both GaAs MESFET's and III-V photodetectors [20], [21]. This effect was observed [22] by testing ungated InGaAs/InP structures (Figure 5) and shifting the breakdown voltage by applying different surface treatments and passivating layers. Etching-off the native oxides was found to reduce the breakdown voltage in most cases, while the deposition of a Si02 passivating layer was found to improve the breakdown voltage.

The second breakdown mechanism is an intrinsic mechanism based on the band structure alignment of the InP and InGaAs layers, as shown in Figure 6. Assuming a conduction band discontinuity DEc=0.25 eV between the InP and InGaAs, then the L and X valleys of IriP are very close in energy to the ionization energy EL of InGaAs. Therefore, under high electric fields when these sattelite valleys are populated, the high kinetic energy electrons (hot) can be launched into InGaAs and produce ionization. This can be taken as an apparent reduction in the effective ionization energy of the semiconductor and consequently a reduction in the breakdown voltage. This is consistent with the one order of magnitude reduction in the breakdown field ES observed in these heterojunction structures. The reduction of the ioruzation energy has been reported for InGaAs/InP superlattice photodetectors [23], but this is the first time it is linked with the premature breakdown of heterojunction FET's.

In summary, some reliability concerns related to the low breakdown voltages of InGaAs/InP based heterojunction FET's have been pointed out. Such reliability problems may limit the applications of these high performance devices in digital IC's.

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17. AG. Lahav, C.S. Wu and F.A Baiocchi, J. Vac. Sci. Tech. B6, p.1785 (1988).

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Table I [6)

INTERCONNECT Al-Si AI-Si-Cu Al-Si-Ti

PARAMETER

MTF (h)

106 A/em2 156 3620 3200

1500C

P (llQ em) 0.2 0.3-0.6 0.7

h (Wem-2r J) 70 100

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500

\!I; vacancy

.!1!:BXi=: R~ \ \

Wedge Shaped Void Silt-like Void

Figure 1 (a) Formation mechanism of " wedge-shaped" void under tensile stress.

Cu Atom Cu Precipitates

F - F -Wedge Shaped Void

(b) Formation mechanism of "slit-like" void under tensile stress [8]

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501

'.1 AI-SI

1.6

1.5

1.4 TiW-alloy/AI-SI

!2 ~ 1.3 -~

'.2 l-

,.,1 1.0

0.9 0 200 400 600 1000

t(hOlJrs)

Figure 2 Normalized resistance versus time for test samples of single-layer and multilayer Al-Si (1%) metal interconnects [9].

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502

"> .55 .!2

~ .50 cz:: .... z ..... 45 z Q .... ... = .40 .... ... u c .35

I 2 J-1XI0 A/ci

D-tI Ti/II/Al-lISi

..... Ti: II/Al-1ISi

.300L-~5~~10--~15---2~0---2~5--~3~0--~375--~4~0--~45~~5·0 PERCENT RESISTANCE INCREASE

Figure 3 Activation energy versus failure criterion for two and three-layer metal interconnects [11]

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Table II [22)

MATERIAL GaAs InP InGaAs PARAMETER

EBn (V /em) 4 x 105 6 x 105 2-3 x 105

VBn (V) 60 - 80 40 - 50 20 - 30 Expected (6 lim) (4 pm) (4 pm)

VBn (V) 30 - 35 8 - 10 4 - 6 Observed

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504

20.0

16.0

12.0

8.0

4.0

0.0

Undoped SiOdInP (InGaAs

SiOdp+InP (u-InGaAs GaAS/ AIGaAs

InAlAs/InP /InGaAs InAlAs /InGaAs

4 ........... ....

e =3.2 x 10 .....

........................ 4

_ .. ······e=2.3x10 ....•.... . ......... .

............................. . .......... . ......... . ....... .

...... ",'

" ; ...... '''' ................... . ...... .

................. . ...... . .... ;::::: ::: .......... .

... ~~~~"

e = 1.3 x 104

0.0 1.0 2.0 3.0 4.0 5.0 6.0

Source-Drain Separation (microns)

Figure 4 Breakdown voltage versus the source drain separation of undoped InGaAs/InP and InAlAs/InGaAs/InP structures. The electic field associated with the slope of each line is given as a parameter.

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Figure 5 Micrographs show the damage resulting from filament formation between the source and drain of epitaxial layers (ungated). Filaments were formed mesa edge (top) or on the surface (bottom).

505

current InGaAs at the

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I nP InGoAs

i Ex E;

j EL t 0 8 eV

t 0.55 eV 1 0

Er " to 25 eV

~ ·Ec

1 .35 eV 0 75

1 Ev ~ Ev

Figure 6 Energy band-diagram for the InP/InGaAs heterojunction system, including the ionization energy of the InGaAs and the energies of the L and X satellite minima of InP.

eV

eV

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RELIABILITY OF SHORT CHANNEL SILICON AND SOl VLSI DEVICES AND CmCUITS

Dimitris E. Ioannou Electrical Engineering Department University of Maryland College Park, MD 20742

ABSTRACT. This is a review of hot electroJl induced degradation in state-of­the-art MOS silicon devices. First the various hot electron processes and resulting currents are defined, and the device degradation symptoms are established. Ap­proaches to model the device reliability and to characterize the degradation are then reviewed. FinaJ.ly device designs for enhanced reliability are introduced, and it is shown in particular how silicon-on-insulator (SOl) technology may reduced hot electron degradation.

1. Introduction

The most important reliability concerns in VLSI MOS technology are currently hot carrier, radiation, and electromigration induced degradation, and thin oxide tun­nelling and breakdown. Particularly chaJ.lenging are problems due to hot carriers in submicron devices [1,2]. During the operation of such transistors high electric fields may exist in the channel and carriers may gain sufficient energy 80 that in­jection into the gate oxide becomes possible. Injected carriers may be trapped in the oxide and/or generate interface traps in the region next to the drain junction. This results in threshold voltage shifts, mobility and transconductance degradation and increased subthreshold currents. Moreover, hot carrier induced impact ioniza­tion results in gate currents, causing input impedance drop, and substrate currents, which are responsible for capacitance discharge and latch-up effects.

This review deals with the following main issues of hot carrier research: (a) degrada­tion mechanisms and localization effects, (b) characterization techniques and related measurements, and (c) device and circuit design optimization for hot carrier degra­dation suppression. Recent experimental and theoretical results from the literature will be discussed to clarify these issues. It will be shown how Silicon-On-Insulator (SOl) technology may reduce hot carrier induced degradation and in particular how very thin SOl substrates can be used to fabricate circuits of improved reliability with many remarkable properties.

2. Hot Electron Processes and Currents

Electrons become hot when they absorb energy from large electric fields more quickly than they lose energy due to collisions with the lattice. Their energy in­creases until greater electron random motion gives rise to larger phonon collision

507

A. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 507-516. © 1990 Kluwer Academic Publishers.

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rates, resulting in a more rapid rate of energy loss. Eventua.lly this larger energy emission rate balances the energy absorption rate from the electric field, leading to a steady-state at which the electron temperature, or random motion, exceeds that of the lattice. The electrons are then said to be hot. It should be noted at this point that similarly to electrons, holes may also become hot. However, hot holes seem to have much sma.ller mean-free-path between collisions [3]. They are thus much less hot than electrons in the same electric field, and therefore are less effective in degrading the device. Several hot electron related phenomena occur in semiconductor devices, and those important to MOSFET's are shown in Fig. 1 below: [4,5]

Figure 1: Hot-Electron Processes in a MOSFET [Ref. 4]

proce$$ 1: electrons enter the oxide layer creating interface traps, filling oxide traps, or passing through the oxide to produce a gate current la.

proce$$ !: avalanche electron-hole pair production near the drain, where the electric field is larger.

proceu 9: avalanche-generated holes (process 2) are collected by the substrate and create a drift component of substrate current.

proceu -I: electrons are injected into the substrate from the source due to forward bias caused by process 3.

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proceu 5: Some of the injected electrons by process 4 are collected by the drain as in a npn transistor resulting in more avalanche-generated earners.

509

The various currents produced in MOSFET's by the above hot electron processes are shown in Fig. 2: [6]

(SUB

VSUBT

Figure 2: Hole-Electron Induced Currents in a MOSFET [Ref. 6]

ISUB, ""b"trate current, resulting from the hole generation by channel hot electrons through avalanch ionization.

la, gate leakage current, resulting from hot electrons injected into the gate.

IN, minority carrier current, is released into the substrate from a MOSFET operating in the saturation region. It is due to carrier generation by photons produced by hot channel electrons and/or minority carrier injection from the source, if it becomes forward-biased.

ICOL, e:cceu leakage current. Once the minority carriers giving rise to current IN above are deposited in the substrate, by either mechanism, they may be collected by nearby nodes as excess leakage current.

The above hot electron phenomena are detrimental to device and circuit opera­tion in several different ways. Oxide and interface charge causes threshold voltage

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shifts, mobility and transconductance degradation, and increased subthreshold cur­rent. Gate leakage current causes impedance drop. Substrate current ~uses supply voltage sag, capacitance discharges, and lach-up. Finally leakage currents IcoLL are known to cause DRAM refresh-time degradation.

3. Modeling Degradation

Hot electron degradation phenomena occur fairly f'ast. To get an idea of' the time rates involved [5], consider a typical case of' a short channel MOSFET under stress with gate oxide thickness Zo~ = 30nm, where a gate current of' one nA is measured. Assume that this current flows through a section 0.2 by 10 pm near the drain end of' the channel, and that one in every 1()6 injected electrons is trapped in the oxide at an average distance of' 0.2 Zo~ from the silicon surface. The result is that the threshold voltage in the damaged region will be increased by 0.1 V in about 0.25 sec.

Methods of'varying accuracy, extending from the rigorous, but costly Monte Carlo approach to the totally empirical and simplified lucky electron model are used to predict degradation. Between these extremes in complexity, the energy transport­llichardson's equation method gives a qualitative description of oxide degradation in MOSFET's.

i) Luclcg Electron Model{6, 7/

The lucky electron model states that some electrons acquire enough energy to de­grade the device-surmount the oxide barrier or create an electron-hole pair- by accelerating in the electric field while escaping all collisions; such electrons are designed as "lucky". The probability that an electron becomes lucky and then contributes to gate current is given by an exponential with the aid of' a f'ew fitting parameters:

IG = A up(- 4Jo~ ) qAE

where Ia is gate current, A is an adjustable coefficient , A is an adjustable mean free path, 4JO% is the oxide barrier height which is taken to be between 2.5 to 3.2 e V, and E is the electric field.

ii) Monte Carlo Calculatio,,", {8/

Monte Carlo calculation are used to predict gate leakage currents and impact ion­ization. In general, the phonon scattering frequency is proportional to the density of' states. At high energy the band structure is nonparabolic and the resulting density of states may be complicated. Under these conditions, numerical forms for the density of states have been used. With such calculations the complete electron

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distribution function can be determined. By knowing the quantity and velocity of channel electrons striking the gate oxide, the current through it can be calculated.

iii) Energy 7hnuport - RiehAnUon', EqUAtion {9}

The energy transport-Richardson equation method is an improvement upon the lucky electron model; however, although efficient, it does not provide nearly as much information as the Monte Carlo techniqul~. By solving the energy transport equation the electron average energy and temperature are obtained. These are then substituted into Richardson's equation for thennonic emission to calculate the gate current. From the gate current, oxide charges and hence threshold voltage shifts can be determined.

The above techniques are chiefly used to predict the hot electron produced damage in the oxide and at the interface. Modeling is also needed and done in order to establish the nature of the damage and its location, i.e. oxide charges VB. interface traps, donor traps vs. acceptor traps, and the extend of the damage localization near the drain end of the channel. Moreover, modeling is done in order to ascertain the impact of the damage on the device operation and characteristics. Several work­ers have performed both one dimensional and two dimensional modeling to clarify these issues and it is now known that the most important form of hot electron pro­duced damage is acceptor interface traps located near the drain end of the channel [10,11,12]. Typical procedures in such modeling have as program input parameters the channel length, doping concentration, oxide thickness, junction depth, applied voltages, defect type and density, and extension and location of damaged region. The output gives the two dimensional potential distribution, threshold voltage, channel conductance, and transconductance.

Simpler, analytical models also exist in order to facilitate the interpretation of experimental data. One such model regards the damaged transistor as composed of two regions of different conductancies, the wldamaged region, and the damaged region near the drain. Transistor parameters describing these two regions may be defined and can be fitted to experimental data. Considering the simplicity of this model, it is surprising how good the fit can be, as can be shown by the more advanced numerical models.

4. Degradation Characterization Challenges

Several important challenges exist in measuring and characterizing hot electron damage. The defects are inhomogeneously distributed along the channel, within the oxide, and within the energy gap. Only a few defects need be present per device in order to degrade its performance. For instance 1010 defects/cm2 of damaged region, which would be considered sufficient to alter the device characteristics, means just one defect present in a 0.1 x O.lpm damaged region. Nevertheless techniques for the measurement of hot electron induced damage do exist, and in general are stan­dard characterization techniques appropriately modified for hot electron studies.

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These interface characterization techniques include charge pumping [13,14,15,16J, dynamic conductance and transconductance [17,18J, l/f noise and OLTS [19,20J measurements. Useful information is extracted from the application of these tech­niques by making the measurements both in the normal and in the reverse mode, by intercharging the roles of the source and the drain [21J. During the measure­ment the drain voltage is gradually increased until the entire zone of defects lies within the space charge region of the drain junction. The drain voltage at which this occurs is determined by monitoring the evolution of the measurement signal while increasing the drain voltage, until the signal is equal to its predegradation value. Usually, the transconductance and l/f noise are measured in the saturation region for both the normal mode and the reverse mode of operation. In the reverse mode of operation the measurement signal is always constant and different from its value before degradation. In the normal mode it either decreases or increases (de­pending on the technique at hand) with increasing drain voltage until all damage is included in the expanding drains depletion region. The extent aL of the damage localization from the drain is taken to be equal to the extension of the depletion region, calculated at the relevant drain bias [12,21J.

5. Design of MOS Technology for Suppressed Hot Electron Degradation

Several novel features have been incorporated in traditional MOS device designs in order to suppress the hot electron induced degradation. The burried-channel structure [22] and the lightly doped drain (LOO) structure [23,24J are two notable such approaches. The first mainly moves the source of hot electrons further from the oxide, whereas in the LOO structure appropriate double implants are used to adjust the doping profile such that the value of the maximum channel electric field Em,.., near the drain is reduced.

New opportunities for suppressing hot electron effects in MOS structures are offered by recent advancements in Silicon-on-Insula.tor (SOl) technology [25]. A typical SOl MOSFET is shown in Fig. 3. This particula.r transistor was fabricated on a SIMOX (Separation by Implantation of Oxygen) 501 substrate, but several other techniques to produce SOl substrates are also available: Silicon-Qn-Sapphire (SOS), Zone Melting-Recrystallization (Z'MR), Full Isolation by Porous Oxidized Silicon (FIPOS) and Bond-and-Etch-Back. Oue to important advances in SOl technologies in recent years, ultrathin SOl films of excellent quality are DOW routinely produced by several methods, the most successful one been the SIMOX technology. Ouring the operation of transistors fabricated in such thin SOl films, the film will be par­tially depleted (PO) or even fully depleted (FO). In the case of PO structures [25J, the electric field distribution is very similar to bulk structures with positively biased substrate, due to the Boating SOl substrate. But positive substrate bias in bulk MOSFET's reduces the threshold voltage and this increases the drain saturation voltage. This, in tum, decreases the maximum drain electric field. There is thus a

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built-in feedback loop in PO SOl transistors which reduces hot electron degradation. In FO SOl transistors the drain saturation voltage is higher than in PO ones.

GATE OXIDE

BURIED OXIDE

SUBSTRATE

Figure 3: Typical SOl MOSFET Structure

In particular, it has been shown [26] that the drain saturation voltage increases when a transistor is turned from the partially depleted mode into the fully depleted mode, by appropriate substrate biasing. Because of tbis increased saturation voltage, the hot electron degradation is less in fully depleted SOl transistors.

6. Conclusions

Hot electron degradation simulation and characterization are challenging problems. Progress has been made in both fields, and good modeling procedures as well as characterization techniques for hot electron degradation measurements do exist. A simple two-piece analytical model of the degraded device has been reported which is a great help to the interpretation of results obtained by the various characterization methods.

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I am very greatful to my colleagues Drs. Sorin Cristoloveanu and Neil Goldsman for many useful di8CU88ions.

References

[1] Ning, T.H., Cook, P.W., Denard, R.H., Osburn, C.M., Shuster, S.E., and Yu, H.N. (1979), "1 I'm MOSFET VLSI Technology: Part IV-Hot-Electron Design Constraints," IEEE Trans. Electron Devices, ED-26, pp. 346-353.

[2] Hu, C., Tam, S.C., Hau, F.-C., Ko, P.-K., Chan, T.-Y., and Terrill, K.W. (1985), "Hot-Electron-Induced MOSFET Degradation-Model, Monitor, and Improvement," IEEE Trans. Electron Devices, ED-32, pp. 375-385.

[3] Takeda, E., Shimizu, A., and Hogiwara, T. (1983), "Role of Hot-Hole Injection in Hot-Carrier Effects and the Small Degraded Channel Region in MOSFET's," IEEE Electron Device Lett., EDL-4, pp. 329-331.

[4] Hsu, F.-C., Ko, P.-K., Tam, S., Hu, C., and Muller, R.S. (1982), "An Analyt­ical Breakdown Model for Short-Channel MOSFET's," IEEE Trans. Electron Devices, ED-29, pp. 1735-1740.

[5] Muller, R.S. and Kamins, T.I. (1986), "Device Electronics for Integrated Cir­cuits," 2nd ed., Willey, pp. 490-495.

[6] Hu, C. (1983), "Hot-Electron mects in MOSFET's," IEEE-IEDM '83, pp. 176-181.

[7] Shockley, W. (1961), "Problems Related to p - n Junctions in Silicon," Solid State Electron., 2, pp. 35-67.

[8] Jacoboni, C. and Reggia.ni, L. (1983), "Monte Carlo Method for the Solution of Charge Transport in Semiconductors with Applications to Covalent Materials," Review of Modern Physics, 55, pp. 645-705.

[9] Frey, J. and Goldsman, N. (1985), "Tradeoffs and Electron Temperature Cal­culations in Lightly Doped Drain Structures," IEEE Electron Device Lett., EDL-6, pp. 28-30.

[10] Maes, H.E. and Groeseneken, G. (1982), "Determination of Spatial Surface State Density Distribution in MOS and CMOS Transistors After Channel Hot Electron Injection," Electron. Lett., 18, pp. 372-373.

[11] Hau, F.C. and Tam, S. (1984), "Relationship Between MOSFET Degradation and Hot Electron-Induced Interface State Generation," IEEE Electron Device Lett., EDL-5, pp. 50-51.

[12] Haddar&, H. and Cristoloveanu, S. (1987)~ "Two-Dimensional Modeling of ~ cally Damaged Short-Channel MOSFET's Operating in the Linear Region," IEEE Trans. Electron Devices, ED-34, pp. 378-385.

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[11] Hsu, F.C. and Tam, S. (1984), "Relationship Between MOSFET Degradation and Hot Electron-Induced Interface State Generation," IEEE Electron Device Lett., EDL-5, pp. 50-51.

[12] Haddara, H. and Cristoloveanu, S. (1987), "Two-Dimensional Modeling of L0-cally Damaged Short-Channel MOSFET's Operating in the Linear Region," IEEE Trans. Electron Devices, ED-34, pp. 378-385.

[13] Groeseneken, G., Maes, H.E., Beltran, N., and De Keersmaecker, R.F. (1984), "A Reliable Approach to Charge-Pumping Measurements in MOS Transistors," IEEE Trans. Electron Devices, ED-31, pp.42-53.

[14] Heremans, P., Maes, H.E., and Saks, N. (1986), "Evaluation of Hot Carrier Degradation of n-Channel MOSFET's witb the Charge Pumping Technique," IEEE Electron Device Lett., EDL-7, pp. 42:8-430.

[15] Bellens, R., Heremans, P., Groeseneken, G., and Maes, H.E. (1988), "Analysis of Mechanisms for Enhanced Degradation During AC Hot Carrier Stress of MOSFET's," IEEE-IEDM88, pp. 212-215.

(16] Hadara, H. and Cristoloveanu, S. (1986), "Profiling of Stress Induced Inter­face States in Short Channel MOSFET's Using a Composite Charge Pumping Technique," Solid State Electron., 29, pp. 767-772.

[17] Hadara, H., Elewa, T., and CristoloveanllL, S. (1988), "Static and Dynamic Transconductance Model for Depletion-Mode Transistors: A New Characteri­zation Method for Silicon-on-Insulator Materials," IEEE Electron Device Lett., EDL-9, pp. 35-37.

[18] Fang, Z.H., Cristoloveanu, S., and Chovet, A. (1986), "Analysis of Hot-Carrier­Induced Aging from l/f Noise in Short-Channel MOSFET's," IEEE Electron Device Lett., EDL-7, pp. 371-373.

[19] McLarty, P.K., Ioannou, D.E., and Hughes, H.L. (1988), "Deep States in Silicon-on-Insulator Substrates Prepared by Oxygen Implantation Using Cur­rent Deep Level Transient Spectroscopy," Appl. Phys. Lett., 53, pp. 871-873.

[20] McLarty, P.K., Ioannou, D.E., and Colinge, J.-P. (1988), "Bulk Traps in Ul­trathin SIMOX MOSFET's by Current DLTS," IEEE Electron Device Lett., EDL-9, pp. 545-547.

[21] Haddara, H. and Cristoloveanu, S. (1988), "Parameter Extraction Method for Inhomogeneous MOSFET's Locally Damaged by Hot Carrier Injection," Solid State Electron., 31, pp. 1573-1581.

[22] Takeda, E., Kume, H., Touabe, T., and Asai, S. (1982) "Submicrometer MOS­FET Structure for Minimizing Hot-Carrier Generation," IEEE Trans. Electron Devices, ED-29, pp. 611-618.

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[23] Tsang, P.J., Walker, W.W., Shepard, J.F., and Critchlow, D.L. (1982), "Fab­rication of High-Performance LDDFET's with Oxide Sidewal-Spacer Technol­ogy," IEEE Trans. Electron Devices, ED-29, pp. 590-596.

[24) Yoshida, A. and Ushiku, Y. (1987), "Hot Carrier Induced Degradation Mode Depending on the LDD Structure in n MOSFET's," IEEE-IEDM87, pp. 42-45.

[25] IEEE Circuits and Devices Magazine, Special Issues on SOl Technology, vol. 3, No.4 (July '87) and No.6 (November '87).

[26] Colinge, J. P. (1987), "Hot-Electron Effects in Silicon-on-Insulator n-Channel MOSFET's," IEEE Trans. Electron Devices, ED-34, pp. 2173-2177.

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;PECIAL RELIABILITY ISSUES AND RADIATION EFFECTS OF HIGH SPEED I.C. s

G. J. PAPAIOANNOU Solid State Physics Section University of Athens 104 Solonos St. Athens 106 80 Greece

ABSTRACT. A review of special reliability issues related to radiation effects of hi~h speed integrated circuits is presented. The radiation induced de~radation of the basic building blocks is initially discussed and further related to the I.C. performance. The analvsis includes the material properties and substrate structure. Both particle and elec­tromagnetic radiations are considered.

1. INTRODUCTION

Solid state semiconduct.or devices are nowadays commonplace items finding applications in complex electronic systems. The use of silicon for these devices is pre-eminent and it seems likely that its use will continue to be almost univer­sal except for a few special applications where gallium arsenide and other III-V semiconductor devices are in ascen­dency. The advantages of silicon for all other aspects are low cost and a well founded technology. Large numbers of high speed I.C.s are marketed finding applications in military and space environments or in nuclear industrial fields where radiation is encountered. The effects of nuclear radiation in all these cases can be disastrous. Unprotected bipolar sys­tems slow down, decay in gains and come to halt with some hope of recovery, perhaps in hours or days. Unprotected CMOS systems can lose stored data and potentialy burn out. Thus one of the most important issues is dealin~ with the ability of I.C.s to survive the effects of nuclear and space radia­tion.

The subject of radiation effects in semiconductor devi­ces is complex because several types of radiation, radiation damage, and semiconductor devices must be considered. Elec­tronic circuits are affected by gamma, alpha, beta and X-rays as well as neutrons, protons and electrons. These radiation

517

A. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 517-544. © 1990 Kluwer Academic Publishers.

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ty?es induce displacement of atoms from their lattice sites, ionization of atoms and internal energy changes. For semi­conductor material the effects of radiation are generally devided into four cate~ories: neutron effects, total ionizin~ dose, transient ionizing dose and single event upset (SEU).

The study of radiation effects on high speed I.C.s is well documented in relevant literature rl-6]. This paper presens a survey of the degradation and failure mechanisms found in silicon devices and integrated circuits, and of the reliability problems encountered in high speed rcs.

Section 2 describes the two basic damage mechanisms, the displacement and the ionization. The effects of permanent damage resulting from cumulative exposure to fast neutrons are analysed in section 3 while the total dose and dose rate effects are treated in sections 4 and 5 respectively. SEU phenomena like soft errors and possible latchup are analysed in section 6 and the substrate and material consideration i.e. SOS, sor and GaAs are discussed in section 7. Finally the summary and conclusions are presented in section 8.

1.1 Radiation stress testing

In order to investigate the degradation of devices, they are artificially "aged" using radiation stress testing procedures to determine the sources of failure which would curtail the operating life [19-231. Generally these tests may take such forms as, for example:

(i) Total radiation dose which must be also related to the dose rate used under test. The last is necessary since a fast annealing device can absorb more radiation when it is tested at slow dose rates. This test is determinative for the design of devices suitable for space applications, where the dose rate encountered is relatively low - in many cases less than one rad per second - or weapon environment, where the dose rate can be orders of magnitude higher.

(ii) Irradiation under bias or not. If a device is unbiased during irradiation, it can withstand significantly hi~her levels of radiation than if it were biased. It must be noted that for an unbiased device no latchup occurs.

(iii) Temperature level in the radiation chamber. Lack of temperature control while irradiating a device may also allow the device to anneal more rapidly. skewing the test results. On the other hand vulnerability to latchup increases with temperature due to increase of leakage currents and thus the decrease of critical charge for upset (21].

(iv) Testing in situ or iteratively. In the iterative

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method the device is irradiated to a particular level then physically removed from the chamber for electrical measure­ments. This process continues until the device fails fun­ctionally or parametric limits are reached. When tested in situ the device is monitored electrically being irradiated. Parametric measurements are more difficult to make in situ and the device may not stressed in the worst-case condiiton. In either case. there can be significant differences in final test results.

The failed devices are further analysed to determine the modes and mechanisms of the failures. The undersanding of the mechanisms of the failures enables the device design and processing to be improved. and aids the determination of which build-in procedures are effective in improving the device reliability.

The failure mechanisms in silicon devices may rise from either displacement radiation or ionizing one. The damage mechanism of each radiation will be examined separatelly.

2. DAMAGE MECHANISMS

2.1. Displacement

Radiation generates defects in the crystal lattice by displacing lattice constituents. Recoil atom so created possesses enough energy to collide with other lattice atoms and to induce other displacements in cascade during its slowing down [7]. Thus additional energy states are intro­duced in the energy band gap of the semiconducting material. These defects act as recombination centers which reduce the minority carrier lifetime. This mechanism is effective in bipolar transistor operation but is negligible for the FETs. On the other hand displacement defects. as already mentioned. introducing additional fixed charges have the same effect as doping and reduce the mobility and the carrier concentration.

The effects of displaced atoms in a silicon lattice are due to the creation of simple defects and defect clusters (fig.!). The components of defect complex are charged during the defect complex formation [8J. As a result anything that changes the charge state during formation can change the probability of formation of specific defects. thus altering the competitive nature of the defect formation. Therefore if irradiation is performed under zero bias conditions the damage effects are fairly consinstent while a variation of the injection level or temperature during or after irradia­tion can substantially alter the damage effects.

Displacement damage is often ignored in total dose testing because surface effects are usually the dominant mechanism although it can be very significant for structures used in linear designes. Displacement defects are introduced

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by particle radiation like neutrons. alpha and beta particles and protons. Electroma~netic radiation can also introduce displacement damage by compton electrons.

1OOr--..,.--r--,.--r--,---,

•. L"':----',--:'.I .. ~-~. ---:':::--. -=-~ ... DISTMU "'" .... IIITI. Ol.-al" II)

2.2. Ionization

Fig.l Defect .;enera­tion picture of a typical re­coil atom track

In contrast to neutron irradiation. where the energy loss occurs mainly by displacement of lattice constituents. the energy loss of charged bombarding particles (27) and of high energy photons such as gamma rays is mainly due to ioniza­tion. In the case of hij;l;h energy photons free electrons are generated directly or not accordin~ to three tYpes of inter­actions: photoelectric. compton effect and pair production. The Fig. 2 shows the importance of the three types of photon interactions in function of absorbing material and photon energy.

Electronic disturbances lead to macroscopic effects the more important of which are the build up of a positive charge in the oxides and specially in the Si02 layers and the crea­tion. during ionization, of positive and negative charge car­riers into semiconductor which can move by diffuison or con­duction to induce photocurrents. Further trapping of car­riers. followed by thermal reemisson, can result in currents that persist long after termination of the radiation pulse.

The electron-hole pairs thus generated cause primary and secondary currents. So if all excess carriers generated, for example, by gamma rays were collected by the electrodes, a primary photocurrent would result. In addition to the primary photocurrent, a secondary photocurent can originate within device structures [9] by the following mechanisms:

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120 Photoelectric Effect Pair Production Dominant

100 ... OJ .0 80 ... 0 In

~ 60 ... 0

40 N

20

0.5 50 100 hv in MeV

Fig.2 Relative importance of the three types of photon interactions in function of absorbing material and photon energy.

521

(i) conductivity modulation wi thin the substrate. (i i) altered potent ial distribution on wi thin the device structure and (iii) changes in the extension of the depletion volume and the charge distribution on assoc:Lated with the .iunction of the gate and channel substrate, respectively [10].

Transient ionizing radiation may generate photo-currents in all semiconductor regions that can result in changes in logic states. circuit ringing. .;unction break.down. latchup and/or burnout. Finally a single ionizing particle can give rise to a single event upset. A 5EU creates a bit flip or soft error. In a soft error the device is not damaged except if latchup occurs resulting in burnout and/or massive functional failure.

3. NEUTRON EFFECTS

3.1. Electronic induced effects

Neutrons are characterized by their energy spectrum ( > 10KeV ) and their total fluence measured in n/cmA2. The interaction of a fast neutron with most materials is domina­ted by elastic nuclear scattering. Neutrons themselves pro­duce no ionization but are capable of producing structural damage in solids by direct energy transfer to lattice atoms if their kinetic energy is in excess of about a hundred eV. The displacement of a silicon atom from its lattice position requires about 25eV. So after an elastic collision the dis­placed atom and incident neutron can displace again other a.toms if their energies are still sufficient. As already mentioned the effects of displaced atoms in a silicon lattice are due to creation of simple defects and defect clusters (fig.1) which act as carrier recombination centers. therefore

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modifyin~ the material properties. The ma:jor effects of neutron displacements, that is the minority carrier lifetime [15] and majority carrier mobility and concentration can be approximated by simple equations.

The relation between neutron fluence (<ll) and minority carrier lifetime is

where Co and c are the preirradiated and postirradiated li­fetimes and KT the lifetime dama~e constant which depend on many parameters like the type and impurity concentration. in­jection level. neutron spectrum e.t.c. An average value of KT for Si is about 5E-6 cm~2/n sec [11J

The neutron-produced changes in carrier concentration can be characterized empirically [12-14] by the folowing equations

O.77W N = No exp{ - 1

444No

O.77<ll P = Po exp{ - 1

387Po

The semiconductor mobility is determined by both the scattering on phonons and ionized impurities. Thus the ma~o­rity carrier mobility decreases upon neutron irradiation due to introduction of ionized defects. The following relation approximates the change of mobility on the radiation fluence

1/1J. = 1/1J.0 + K... <P

where K ... = lE-19 sec/V n Displacement damage is produced also by gamma ray expo­

sure through the resultant compton electrons. For all prac­tical purposes the ~amma ray-induced displacement damage effects are negligible compared to the long-term ionization effects. High-energy ions lose energy in two ways: 1) ionization, which as already mentioned is the dominant energy loss mechanism and 2) energetic Rutherford scattering which give rise to displacement damage and is more rare. In the case of high energy protons the nature of displacement damage is found to be essentially the same with that of neutrons although protons are found to be more damaging than neutrons [26].

3.2. Neutron effects on MOS transistors and Ies

The effect of neutron radiation on diffused resistors and MOS

Page 519: Semiconductor Device Reliability

11 10

TECHNOLOGY

"-was Bulk Si-Gata CMOS

CommercIal Hardened

51-Gate CMOS/SaS Comm .... clal Harder.lld

1 I 2

Junctlo"l-iaolated BIpolar TTl. lo ... -Powa ... m Eel

Oxide-Separated Bipolar Analog Bipolar

12 10

~ -I ~

13 10

~ 1 ~

14 15 16 10 10 10

~I 2 l~ITDl =

= = I ~

=

= c=::::::;:;::I

=====1.

Neut:-on F'1uence. n/cm2, 1 MeV equivalent

" '.'

523

Page 520: Semiconductor Device Reliability

524

transistors is twofold. It both decreases the majority car­rier mobility and minority carrier lifetime thus increasing the device resistivity and leakage current [161. These effects result into a decrease of the circuit speed and increase of power dissipation. Changes in the threshold voltage and the transconductance are expected since both depend on the mobility and substrate doping level respective­ly. As a result MOS transistors begin to show changes in their electrical performance for neutron fluences above lE14n/cmA2 [16] (fig.3).

3.3. Neutron effects on bipolar transistors and ICs

Neutron failure levels for bipolar microcircuit technology (fig.3) reflect the sensitivity of circuit performance to the dominant degradation in transistor common-emitter gain. as well as the evolution to transistors with higher gain-band­width products and thus lower neutron damage susceptibility r24). The degradation of transistor gain (~e) is a function of neutron fluence as [251:

1 1 1 f1 ( ) = - -- = K <I> / FT Ie

a a ~ 1 t:

o~----~----~~--~ 10'3 10'· FLUENCE - n/cm'

a .. o t:

hfeo

Ii 12 ~ . o > ~ 1 , .. -----o

::;: ~ 0.8 "'

b / / BVceo

.... , .. '

10'3 10'· FLUENCE - n/cm'

Fig.4 D.C. gain (a) and breakdown voltage (b) vs neutron fluence for a typical ECL Ie [17].

where K is the gain damage constant, FT the gain bandwidth product and Ie the emitter current. The high neutron failure levels of both junction-isolated ECL and all oxide-separated bipolar digital circuit technologies reflect the application of very high gain-bandwidth transistor elements. It must be noted that the neutron susceptibility of EeL is slightly reduced because of the trend to depend on relatively high transistor gains. The degradation of the gain of a typical

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525

ECL IC vs neutron fluence in shown in Fig.4a [171. Finally the radiation induced increase of the collector resistivity, which is proportional to the reciprocal of the concentration­mobility product (p l/N\.l) , causes the breakdown voltage and VceCsat) to increase (fig.4b). It is obvious that the increase of breakdown voltage is an improvement over the pre­irradiation value. On the other hand the corresponding increase in VceCsat) is undesirable since it is an important parameter in logic and amplifier circuitry. The D.C. gain degradation of a bipolar transistor versus particle fluence is shown in Fig.5

::l~~~--" -.~-~~, ... ---r_--T~­"",,"v--_I

60''''V--/

030 -

~';f 025

020 g ~ 015 -

~

010·

1-- PROTONS-I

00'

---- NEUTRONS -I ____ L __ .L ___ -.L ___ . ..1._~~ ___ 1._

1 Q 20 30 40 50 60 70

PARllCLE flUfNCE 1_10 13 1CM2)

Fig.5 Reciprocal gain vs. fluence for irradiation of a bipolar transistor with lMeVCSi) displacement damage equiva­lent neutrons and 60.3 and 36.7 MeV protons [26].

4.TOTAL DOSE EFFECTS OF IONIZING RADIATION

In most cases of device testing or characterization Cobalt-50 sources are used. As already mentioned ionization is produced also by high energy particles. Early reports have shown that charge recombination losses in MOS devices irradiated with higher stopping power particles, such as 1-3MeV protons and 3.4MeV alphas. are significantly larger than for Co-50 or electron sources [331 that is damage sensitivity is not equivalent to Co-50 for these particles. Also electrons appear to be more damaging than Co-60. There have been also reports proposing the low ( lOKeV) energy X-rays as alterna­tives to Co-60 [34] for effects such as interface dose enhan­cement. Finnally the dose enhancement effect must be mentioned which occurs at the interface of semiconductors wi th high-Z mater ials. Then photoelectrons are generated in the high-Z material which penetrate into Si and enhance the dose near the interface. In the following the effect of gamma rays on MOS transistors and bipolars will be examined.

Page 522: Semiconductor Device Reliability

526

4.1. MOS transistors

The exposure of metal-oxide-semiconductor (MOS) structures to ionizing radiation causes an increase in the oxide trapped charge and in SiO~ -Si interface trapped charge. In addition. there can be a change in the energy distribution of interface trapped charge.

During ionizing irradiation electron-hole pairs are generated through the oxide layer and only a fraction escape early recombination to yield free electrons and holes. Under a gate bias the mobile electrons are swept out of the SiO . Those holes generated in the bulk of the oxide eventually encounter a distribution of hole traps [291 which is located near the Si02-Si interface. Depending upon the local density and capture cross section. of the hole traps. a fraction of the holes are captured. The remainder continue into the Si and are recombined. Part of the captured holes. within a cer­tain distance from the interface. are removed by electrons tunneling from the Si [28]. Trapped holes may also recombine with electrons generated in the oxide layer and hot electrons injected from the Si substrate. The net trapped holes give rise to a positive trapped charge thus affecting the device threshold voltage. On the other hand the radiation induced interface states are primarily caused by the presence of a center at the Si-Si02 interface called the Pb defect. It has also been found that the Pb center is an amphoteric one and that the density of radiation induced interface state de­fects is equal to the number of Pb defects [3~). Finally the increase in the interface density of states is larger for thick oxide layers varying from tox~2/3 to tox~2 [32J. In N­channel MOS transistors the interface states are neutral or negative thus they can compensate the positive charge in the insulator. On the other hand in P-channel MOS transistors the interface states are neutral or positive that is they tend to add to the positive oxide charge. According to these the shift of a MOS transistor threshold voltage can be expressed in the following way:

where VNi and VNo are the contribuitons of the interface state an~ trapped charge respectivelly. Therfore an enhance­ment P-channel transistor will become gradually OFF since its threshold voltage becomes more negative with irradiation. In the case of an N-channel transistor the threshold voltage initially decreases upon irradiation turning it ON due to the positive trapped charge and further it turns gradually OFF due to the negative charge of the interface states (fig.6).

Another mechanism contributing to the failure of MOS transistors is the degradation of the channel effective mobi­lity due to the increase of interface state density upon ir-

Page 523: Semiconductor Device Reliability

527

radiation [311. The variation of normalize mobilitv. oxide

1.00 t~a 0 lOWN"

l:1 .... IGH Nit

!!-~ 0.50 -Ppr.

CIRRA~IATION-

0.00 -2 -1 ~ t I l.~h::fl~E 106 RADS lSI,

6. HiGH "it AN ot

,olLO ,OW ...

10 . ,xtO'1 o::m-2 )

ANi\

(l1.10 11 cm"21

0_ 2 -1 ot L~h~!I~E 10 6 R"OS (Sit

"LQ" '0 o LOWN" ,. A HIGH"lt

10 . °_2 _1 of L:!':

10 8 RADS Isn

Fi~.6 Normalized mobility (a), change in oxide trapped charge(b) and density of interface states (c) as a function of total ionizing dose r311.

trapped charge and density of j nterface states is Fig.6 .Mobility degradation can be fitted to the ship:

shown in relation-

1..1 =

where 1..10 is the pre-irradiation value and Q = 7E-13 for both N- and P- channel transistors over all bias conditions.

As shown above, mobility degradation is related to the buildup of interface state charge while threshld volta~e is dependent on the sum of both oxide-trapped and interface state charge. Both affect the Ie performance of fast by shifting the input and output levels and increasin~ the propagation delay (fig.7) [2J. The device failures due to increase of bias current above specification limits caused by the shift of threshold voltage (fig.B) [1].

Page 524: Semiconductor Device Reliability

528

2.0 ......,

• g? 30 > • -1.5 • •

• 20 c • •

>-1.0 • .c ~.

a • 10 • • • •

0.5 • 10 100 10 100

_30 • • (f)

2.,5 • c

'> • 20 d 2.0 • :i:: • a. •

.c • .., 10 :> b

1.5

1 10 100 10 100 krad krad

Fi~.7 Change of (a.b) input levels and (c.d)propa~ation times vs total accumulation dose for a high speed CMUS Ie fZl

4.2. Bipolar transistors and diodes

For diodes and bipolar transistors. positive charges induced into the protection oxide can invert the doping of the underlying layer, giving rise to leakage currents between the two parts of the junct ion or into the base of a transistor. This effect reduces the transistor gain. Thus the susceptibi­lity of junction isolated and oxide separated bipolar is dif­ferent (fig.S) since the failure mechanism is transistor gain degradation in the former and surface inversion under the oxide-separation. as mentioned above. in the last. The same effects determine the degradation of diffused resistors.

The dependence of the trapped charge on the device bias give rise to bias annealing effects f18J which in some cases shift the threshold voltage and cause functional failure of the MOS integrated circuit. Finally it must be noted that the oxide growth process affects significantly the device radia­tion hardness.

Page 525: Semiconductor Device Reliability

529

40 60 80

Tolal Doao, KAad. (51)

Fig.8 Dependence if bias current (lee) on total dose for a family of high speed CMOS integrated circuits which have been irradiated with a CO-60 source at a rate of 9 Krad(Si)/sec [1].

2 3 • ~ • , TECHNOLOGY ,. ,.

'0 '0 '0 '0 I I i I 2 ' , ~ I I I,

2 ,I • • , . • . , ' , "-was Bulk 51-Got. eNOS

CGmrn.rcfal Iiord_ned

51-Gat. CWOS/5OS Commercial Han::lened

JUftctlon-laolotod Bll'Okir m = I.o.-Po •• ,. m = Eel = Oxide-Separated Bipolar

Analog 81po1or

I 2 (I 2 , ?I 2 ~ i I 2 • il ,

( I , I I I I ,02 '03 , .. ,.~ ,0' '0'

Total Ionizing 00 •• , rada(SI)

Fi~.9 Estimated ranges of IC long-term ionization radiation dama~e [161.

o. DOSE RATE EFFECTS

5.1. HaS devices

The total dose response of MaS ICs can be strongly affected by the dose rate at which they are irradiated. This is caused by.as mentioned previously, the interplay of two mechanisms: trapped holes, which produce a negative threshold voltage shift in N-channel devices, and interface states, which pro­duce positive threshold voltage shifts. The threshold voltage depends on time primarily because the trapped holes anneal. although in some cases the time required for interface state formationmay also contribute to the time dependence. Thus the net sign of the threshold shift in N-channel devices will depend on dose rate. Dose rate dependence is also affected by the fundamental nature of the response mechanisms. Three different failure mechanisms occur. taking into account the total dose and the dose rate: 1) at high dose rates where the

Page 526: Semiconductor Device Reliability

530

failure occurs because of ne~ative 6V in N-channel transis­tors, 2) at moderate dose rates where failuer occurs either because of a shift in N-channel ~V (either direction) or be­cause of a ne~ative shift in P-channel ~V and 3) at low dose rates where failure occurs because positive shifts in N­channel threshold volta~e. Assuming linear behavior all cases can be reproduced in Fig.10 [221.

Total dose failure level [rad(Si)]

Region 3

1 04 ~-::-":-:---:.L---'---'7---:=--:~ 0.001 0.01 1000

00$8 rate [rad(Si)/s]

Fig.lO Dependence of the failure level on dose rate for a typical CMOS IC with linear mechanisms

5.2. Diodes and bipolar transistors

The main effects induced by an ionizln~ radiation pulse are described from the behavior of irrs.diated reverse biased PN .iunction. Under the influence of hi~h electric field in the depletion region and of the diffusion process, associated to the hiAh concentration variations near the junction, the charges are separated giving rise to a photocurrent

Ip(t) = q go Vc ~(t)

where go is the generation rate conversion factor 4e13 carriers/cm~3 rad, yet) is the radiation ener~y deposi­tion rate density in rad per second and Vc the volume from where the carriers are colected.

In the case of bipolar transistors, primary photocur­rents are generated within the depletion reAions of the collector and the emitter as well as within a few diffusion lengths of the .iunction in the base-emitter and the base­collector regions. Since the base-collector reAion is the largest in volume and reverse biased, most of the primary photocurrent ori~inates into the collector.

In integrated circuits all of the active and parasitic junctions are the source of photocurrents. Their contribution is more difficult to evaluate. The photocurrents generated in

Page 527: Semiconductor Device Reliability

531

insulators. with exception of SOS. remain weak compared to that of ~unctions.

In the case of diffused resistors two basic are induced: the conductivity modulation. which is insignificant and can be easily rendered. and the

phenomena !<enerally photocur­f351. the rent generation due to the surrounding .iunction

consequence of which essentially determine the resistor hardness.

5.3. Transient photoresponse

The transient photoresponse is the result of radiation indu­,~ed p-n .iunction photocurrents. In .iunction isolated ICs the principal effect is the sum of the substrate .iunction photocurrents and the primary/secondary photocurrents of the active or parasitic transistor elements. In other words the response is the sum of the substrate response and the circuit response. The dose-rate dependence of the substrate photores­ponse is relatively linear. but that of the circuit response 1S typically non-linear.

The effect in the IC involves the time-dependent current-noise tolerance in each logic cell as well as the overall electrical switching requirements. Transient failure l::an be either the distortion of an external logic si!<nal to an undefinite or erroneous voltage level, or an internal effect that prevents normal electrical response of the (lVerall integrated eircuit. In the case of a high speed inte!<rated circuit the transient failure occurs when the substrate photocurrents .iust exceed the current-noise margin of the logic cells [361.

~. SIN~LE EVENT UPSET AND LATCH-UP

H.t.Single event upset

Thl':: single event upsets are caused by charge collection at sensitive nodes produced by incident radiation. such as cos­mic rays and alpha particles emitted from trace elements in packagin" mat.erials. The cosmic rHY particles are 90% pro­tons; however. cosmic rays also include alpha particles and nuclei of heavier elements. i.e. heHvy ions.

Unlike totHI ionizing dose irradiations performed with lower energy gamma rays or with electrons. there is no threshold accumulation of total dose required before damage becomes unacceptable. Even one particle can cause an upset ~lthough the individual probability is low. Experiments have shown ihat the average fluence required for a sin!<le upset of a device may range from 100 heavy ions/cm-2 up to about [20]

Page 528: Semiconductor Device Reliability

532

iEiO protons/cm~2 (Ep > i5MeV) for susceptible device types. There is, however, for each device type a cri tical chan~e which must be deposited within a microscopic sensitive re~ion of the device if upset is to occur.

For hp,avy ions (Z >,. 2), two important numbers must be determined in order to obtain predictions of upset rates for operational systems. The first is the linear energy transfer threshold which is proportional to the energy (or charge) de­posited along the path length of a given incident ion spe­cies. This quantity determines which ions heavier than pro­tons are capable of depositing a sufficient dense ionization chan~e to induce upset for the particular device under test. The calculation must also include the charge that is deposi­ted along oblique particle paths by lower linear energy transfer ions that are capable of depositing an equal criti­cal charge along their tra~ectory. The second important 1l1.1I11ber is the sensitivity of the device under test to upset for a 12;iven energetic ion. this nnmher can he represented as the number of ions/cm"2 to cause a sinl2;le IlPset or bv its reciprocal. known as the device upset crossection. In some cases the numher is presented for whole device and in others it is normalized to give upsP,t rate or crossection on a per­bit hasis. For heavy ions. the device crossection is a function of the linear energy transfer,

,~

S ()

ro I

r.Ll ~0.2 c: o

'M

+' ()

rJl 0.1 Q)

'.fl

rJl ill 0 0 I-<

20 C)

"1"

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., ., ....... 9

~~ ......... ~. ............. "0"

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T(C) 100

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I r.Ll ,...;

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X ., ., ., ., "."", 0 ..... .

~.... ..... "(1' ............

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....... ~

tQ o I-<

U

O~---r---.--~.---~--~ 20 60 100

T lei

Fiit.11 Temperature riependence of SEU cross section for (a) protons and (b) :'Ilpha particles for "1" fill and "0" fill runs f381. The Ie was an NMOS resis­tive load static RAM.

Certa j n test parameters affect the SEU response of the device under test. The applied bias is important because the stored charge on the device is proportional to bias. The angle of incident beam is also important because it affects the amount of charge that is deposited within the sensitive volume of the device r20.371. On the other hand the flux has

Page 529: Semiconductor Device Reliability

533

no effect. since upsets occur at rates much too low to lead to collective effects from multiple ions present in the sample. ::.I)metimes. the initial state confi~~uration (e.~. zeroes or c'nes) of a device affects the SEU sllsceptibility and this phenomenon may depend on the linear ener):l;y transfer of the incident ion. Finally the Ie temperature increases the SEll crossection f38]. In Fi):l;. 11 is shown the temperature dependenr::e of SEU cross section. of an NMOS resistive load static RAM. for protons and alpha particles.

1: •. 2. La t c h - u p

I.1'lt"h··up arises from t.he activation of four-l.aver pnpn pat.hs that are i.nherent in some monolit.hic inte)2:rated circuit ,;t.ru(:t.llres. 111 bulk eMU:; the path is depicted in the r'ross section shown in Fip: .12a and schematically in thp lllmppd equivalent circuit shown in FiQ.12b . Lat.ch-up jnitist.inn

Voo Voo

R,+II

Rft+

R.l p-W1II1

R., ". n-Iub

",3 R •• R" R., n--epi -.~- ;;+.7ub

Rft+ "s+ Rn-t Rcn'" "ft+ ",

GNO

VOO

Voo

a b c

Filt.12 Cross sec·tion (8) of blllk CMOS strll.,tllre shnwinJ'l' a f()llt' laver Dath. (b) t.he eql] ivalent. 11.11nped C'ros:;-eoupled model Ilsed for l.at.('h-llP st.lldv and (e) the epitaxial d~vicp

1'eQllirps t.hat one nf t,he hi.polar cit'Ov1ces bee-orne bia.spd int" the act.ive mode. f,o. tf the sllbstra.t.e current i.,,, !!lade t.o fl(,w thl'Ollg:h Rs (fi.I1.12b), t.he emitt.er-basr, i Ilnr-t:i on (,f t.he lnt.p .. · ral pnp can hecome forward biased and iniect. holes into substrate. Some of t.hese will be collec·ted by t.he p·-well I.here they will provide base dri.ve to the vert.ical npn. which. when active will feed back additional base current to the pnp. A reQenerative model is attained that will result in latch-up if the feedback loop has Qreater than unitv Qain. If -::he effective loop Qain. that J;!:ain that. accounts for t.he r:urrent. division due to t.he base-emi.tter shunt. i.mpedances.

Page 530: Semiconductor Device Reliability

534

can bE' made less than one. latch-up is precluded. A first order latch-up solution involved the reduction of minority carrier lifetimes thus reducin~ the parasitic bipolar ~ains below one. This solution. however, becomes less effective as geometries become smaller Cp-wells < 6~m). An alternate solut ion employed the use of epitaxial n on n+ subst.rates (fig.12c). This structure reduces Rs by shllnting the element. with a high conductivity region thereby raising the holding current either to a level beyond the capabilities of the power sourceor to the region of current ~ain falloff with collector current such that re~eneration cannot occur f391. CMOS on epitaxial substrates has also been observed to latch for tighter design rule devices (p-wells = 2.5-3~m). Further a proper selection of layout parameters. backside contact and t.hlclmess (If epitaxial layer permits even more ti.~ht design rule devices (p-well = 1.25um) f23.401.

Latch-up paths in bipolar devices f4Jl are more complex than the latch-up paths in simple CMOS devices. This is par­ticularly true for linear circuits which use several circuit elements in series. with diferent geometries and circuit fun­ctions. Finally multiple latch-Up paths with different latch­up susceptibilities can occur in bipolar logic circuits with replicated circuit elements.

Hill t iple latch-up paths. that occur in devices which have several pnpn structures. have been observed in CMOS and advanced bipolar technolo~ies. and seem to be more prevalent as the scale of inte~ration increases. Several devices exhi­bit. latch-up in a specific range of radiation intensities (lat.ch-up window effect) [421. In some cases the width of the latchup window is quite narrow or a device may exhibit multi­ple windows. The window effect is caused either by multiple

Table 1. Summary of Experimental Techniques for Latohup

PURPOSE TEST TECHNIQUE APPLICATION LIMITATIONS

Irradiation Pulsed radiation test Screening and latchup Total dose damage

Hethods (linaa or flash X-ray) path characterization Large beam area cost

Pulsed laser test at top Location of sensitive Shadowing from surface (packaged regions. Latchup path metalization; dosimetry device) characterization accuracy

Pulsed laser test at Location of sensitive Partial removal of back side (packaged regions. Latchup path backside metalization: device) characterization special packagin~

Pulsed laser test on Screening Limited backside contsC't wafer (back side) Probe resistance too hil'lh

for IBr~e currents

Page 531: Semiconductor Device Reliability

535

latchup or by ohmic drops in metalization or substrate that cause the internal voltage to fall below the holding voltage.

Latchup can be tested by usin~ different radiation methods. Each method has its specific application and limitations which are summarized in Table I.

7. SUBSTRATE AND MATERIAL CONSIDERATION

1.1. CMOS/SOS t.echnology

The Silicon On Sapphire (SOS) t.echnolo~y allows the t.otal insulat.ion of active elements without semiconductor ~un­otions. It. leads to improve the circuit speed in reducing the parasitjc capacitances. to increase the integration density and to increase the transient radiation level. The SOS technology main point lies in the use of monocrystalline alumina substrate. about 300um thick. on top of which a thin silicon layer (O.6u.m) has been epitaxially ~rown. The first step of the processin~ consists of the creation of silicon islands where the transistors are diffused or implanted and the gate oxide is generally thermally grown (fig.13).

sapphire

FiQ.13 Typical structure and location of back-channel in a 50S transistor.

7.1.1. Total dose effects of ionizing radiation

To the creation of positive charge into the gate oxide and of the electronic states at the Si-Si0 2 interface. it is r.ecessary to add the same effects created into the sapphire substrate and at the silicon-sapphire interface. The two first effects. as mentioned previously. give rise to thre­shold voltage shifts. In addition leakage current appears which is often several orders of magnitude greater than the pre-irradiation value r431. The leakage current. otherwise

Page 532: Semiconductor Device Reliability

536

called back channel leakage current,is caused by the positive charge created in the sapphire substrate which can induce an electron inversion layer in the silicon near the silicon-sap­phire interface. thus connecting the source to drain. This current is in general independent of the gate voltage and hence cannot be turned off. Some ion implantation processes are performed to decrease this effect and to allow a good ionizing total dose level [lE6 rad (Si)] [24J. Finally the employment of Si-gates instead of AI-gates improves the electrical performances and increases the total dose level.

7.1.2. Ionizing dose rate effects

Tranflient effects into CMOS/SOS circuits are the result of the act ive .iunction photocurrents and of the induced photo­currents by the sapphire. The intrinsic .iunction photocur­rents are very small. due to the junction small area. so with the considered silicon layer thickness. the photocurrent va­lue is about 3E-13 A/rad(Si) per micron length. On the other hand all silicon stripes and aluminum interconections are biased at various bias levels thus collecting the electrons which are generated during the ionizing pulse and giving rise to photocurrents.

Recently. experiments on single event upset r441 in 1. 25~\m channel length RAMs revealed a "multiplication" effect of charge.According to that the collected charge was found to be about twice than the deposited one and the effect was attributed to parasitic phototransistor action.

7.2. CMOS/SOl technology

501 technology consi sts of growing 8i] j con layers on the top of silicon oxide or nitride layers. which are recrystal­lized by various appropriate methods. SOT technology combines the advantage of dielectric isol.ation with a standard silicon -based technology. There are severa] new SOT fabrication methods: FIPOS (ful]y isolated porolJs silicon); ZMR (zone melt recrystallization); ELO (epitaxial lateral evergrowth) and SIMOX (separation by implanted oxygen). he implantation technique (SIMOX) exhibits the most promise for producing device quality SOl material.

7.2.1. Total radiation dese effects.

Total radiation dose experiments have shown that back-channel leakage currents and edge effects resulting from irradiation exposure can be minimized for n-channel devices by applying a

Page 533: Semiconductor Device Reliability

537

negative bias to the substrate without determinally affectin~ the p-channel devices [45]. This improvement in total dose hardness with ne&;ative substrate bias is &;eneric to the SOl structures and results in an inherent advantage of sor over SOS technology. -

In SIMOX devices positive char~es trapped in the burried oxide due to ionizing radiation cause. as already mentioned above. a decrease of the threshold voltage of the n-channel back gate parasitic transistor and thus a~ increase the lea­kage current. Since the threshold voltage shift depends on the oxide thickness. the total dose hardness of the burried oxide has been improved by reducin&; the burried oxide layer thickness that is by lowering the oxygen implantation dose. S() by decreasin&; the implantation dose from 2.25E18/cm'2 to 1.4E18/cm"2 the threshold volta&;e shift decreased by about 40% at a total gamma dose of 1E6 radCSi) with the device sub­strate biased at -3Volt [461. Another approach that has been adopted to improve the total dose hardness was the add it ion of nitrogen implant to form an oxinitride layer instead of an oxide layer. Thus by implanting nitrogen at a dose of 5E16/cm-Z the threshold voltage shift decreased by about 38% r 461.

7.2.2. Transient radiation effects

The response of SOl devices to transient radiation is compa­rable to that of SOS and surpasses that of bulk CMOS. The performance of Sal MOS devices to transient radiation is limited by the parasitic bipolar phototransistor action that gives rise to photocurrents. which are .5 to 6 times greater than the expected ones for the total d iscret device vo lume. The gain of the bipolar transistor is determined by both the minority carrier lifetime and the device geometrv [451. The phototransistor action is diminished when the minority car­:rier lifetime is decreased and enhanced when the device di­mensions &;et smaller.

7.3. GaAs devices

In the field of electronic technologies GaAs is well placed. GaAs field effect transistors have demonstrated their abili­ty to work into power and frequency ranges not accessible to silicon. Some of these advantages are: (a) hi~her speed. (b) homoepitaxy with no equivalent interfacial de~radation in saturation velocity and mobility. (c) automatic dielectric isolation and small parasitic capacitance effects. (d) redu­ced radiation sensitivity to total dose due to the absence of a gate oxide. (e) the potential for adequate transient and neutron dose hardness.The effect of each radiation type will

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be examined in the following.

7.3.1 Total dose effects

Under radiation. GaAs material and devices undergo the same de~radation types than the silicon case. Displacement dama~es take place into the crystal lattice where are found the two deffects: creation of point deffects. vacancy-interstitial. pairs and damaged regions of various sizes consisting of spi­ke zones of quasi-metallic behavior. instead of deffect clus­ters which appear in silicon. Displacement dama~e decreases the carrier mobility. which effect is non-significant when the device operates in the saturaton velocity region. and the carrier concentration. which results in a change of the channel shape. Both effects lead in an increase of the para­sitic resistances.

The chan~e in the channel the device threshold vol ta.E':e. above 1E15n/cm~2 (47). and an current due to the decrease of slope [48].

shape results into a change of about 20% at neutron fluences increase of substrate leakage

the channel-substrate ~unction

The transconductance degradation for an epitaxial layer transistor upon neutron radiation can be approximated by [101

where ~ and ~ are expressed in cm~2/V sec and n/cm~2 respe­ctivelly and W andL are the device channel width and length. The device noise figure increases also for doses above r 491 1E15n/cm~2 due to the decrease of the tranconductance and increase of the source parasitic resistance.

The effect of ionizing radiation on GaAs devices has been studied extensively. The damage on GaAs devices from energetic electrons has been shown to rise very rapidly above 600 KeV [501 while the total dose for gamma ray which causes the same degradation was found to be one order of magnitude higher than that for 1 MeV electrons [50]. Up to about total dose of 1E7 rad(GaAs) the chan>1;es in the devce performance are hardly noticeable and pronounced changes appear at 1E8 rad(GaAs) rlOl. It has been shown also that the model of carrier removal. irrad iating with neutrons. protons and alphas. is consistent with the channel narrowinl'! with damage [511. Total radiation dose experiments r521 have shown also that HEMTS are superior to MESFETs under 250Mrad dose.

7.3.2. Transient radiation effects

The primary photocurrents in GaAs and Si are almost equal for the same volume and dose rate in view of the small difference

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539

in ele(;,tron-hole pair generat ion constant. Transient ionizing radiation cause also charge trapping in the semi-insulating (SI) substrate. The higher the ionizing doze. the more char~ ge trapping occurs. On the other hand backgating is an effect where negative potentials applied to the SI substrate act to deplete the channels of the transistors and saturated resis­tors. thereby the current flowing through the channels. Thus after a short radiation pulse the charge trapped in the sub­st.rate will modulate the channel conductance giving rise to an increase of the drain current. Further. since the trapped charge is thermally emitted the drain excess current will ex­hibit a tail [53]. Reduction of the long-term radiation res­ponse can be achieved by inserting a p-type layer between the channel and substrate r541. This layer reduces the backgating eff€ct and thus to increases the radiation tolerance above the theoretical and experimental upset level of lEllrad(GaAs) r 101.

Finally the HESFET exposure to alpha particle transients --400./sec for 60sec- in the gate region may lead to burnout due to the electrothermal transport mechanism rS51.

8. CONCLUDING REMARC5

The data presented in these sections demonstrate the toleran­ce of 51. Si-related and GaAs integrated circuits to fast neutrons and ionizing radiation. both under transient and cumulative conditions. The advantages and drawbacks of each material have been analysed. The outstanding performance of the silicon related SOS and SOl and the GaAs materials is obvious. The problems encountered under ionizing radiation in SOS and 501 with the back-channel effect and phototransistor action can be deminished. On the other hand long-term tran­sient radiation response in GaAs MESFETs can become negligi­ble with the addition of a p-layer under the channel. No latch-up appears in integrated circuits fabricated on these substrates. The radiation environment induced degradation in. such materials. high speed ICs can be reduced significantly and even eliminated with hardening methods. The latter are very often improvements of the basic technology.

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1~\. Srour .. J. f(, (HJ'I~i) "Stable-Damage Comparisons for Neutron·-Irradiated :;i1icon". IEEE Trans. Nuclear Sci. NS-20. 191.1-

lf3. Raymond. J. P. and Petersen. E. L. (1987) "Comparison of Neutron. Proton and Gamma Rav Effects in Semiconductor Devices". IEEE Trans. Nuclear Sci. NS-34. 1622-1628

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Daniel. M. E. and Coppa~e.

a H ilth Speed ECL NS-22. 2595-2598

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Lantz. M. D. and Galloway. K. F. (1983) Effects on Circuit Speed Measurements". Nuclear Sci. NS-3U. 4264-4269

Schwank. J. R. and Dawes. W. Silicon Gate MOS Device Bias Nuclear Sci. NS-30, 4100-4104

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20. Nicols. D. K .. Price. W. E. and Malone, C .. J. (1983) "Single Event iJpset (SEU) of ~;emiconductor Devices - A Summary of JPL Test Data".IEEE Trans. Nuclear Sci. NS-30. 4!) ~O -4 S:i5

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:22. .J ohnston. A. H. and Roeske. S. B. (1986) "Total Dose Effects at Low Dose Rates". IEEE Trans. Nuclear Sci. NS-3:3, 1487-1491

:3on.o;~, Y .. Cable. J. S .. Vu. K. N. and Witteles. (1986) "The Dependence of Latchup Sensitivity on Features in CMOS lnte>?:rated Circuits". IEEE Nuclear Sci. NS-33. 1493-1498

A. A. Layout Trans.

24. Long. D. M. (1980) "Hardness of MOS and Bipolar Integra­ted Circuits". IEEE Trans. Nuclear Sci. NS-27, 1674-1679

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:26. ~;Ilmmers. G. P .. et al (1886) "EnerJ;!V Dependence of Pro­ton Displacement DamaQe Factors For Bipolar Transistors". IEEE Trans. Nuclear Sci. N8-33. 1282-1286

'.(.7. Bethe. H. A. and Ashkin .. J. (1953) Experimental Nuclear Phvsics Vol.I. in E. Ser~e (ed.), Wiley. New York

;~8 .

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Boes~h, H. E .. McLean. F. B .. Benedetto. .J. M .. McGarri-tv. ,J . M. and Bailey, W. E. ( 1986 ) shold Volta~e Shift in MOSFET's Trans. Nuclear Sc i . NS-33. 1181-1HJ7

Witham. H. S. and Lenahan. P. M. the Deep Hole Trap in MUS Oxides". Sci. NS-34. 1141-1151

Lenahan. P. M. and Dressendorfer. structural Vari8tinl1s in Radiati.on Ohserverl Thr(Jl1~h ESR". IEEE Trans. 4RO?-413D4

"Saturation of Thre-at Hilfh Dose .. IEEE

( 1987) "The Nature of IEEE Trans. Nuclear

p V. (1983) "Micro­lia I'd and Soft Oxides

Nuelear Sci. NS-:30.

:i1. Sexton. F. W. and Sdlwank .. J. R. (1985) "C0rrelation of l:<adiation Effects in Transi.stors and IntE'ltrated Circuits' TEEE Trans. Nuclear Sci. N8-32. 39'l5-3981

:3? ~;aks. N. S .. Ancona. M. (;. and Modolo .. J. A. (1886) "Ge­neration of Interface States by Ionizin~ Radi.ation in Ve­rv Thin MC)S Oxides". IEEE Trans. Nuclear Sci. NS-33. 1185-1191

3:1. ::,tassinopoulos. E. G. et al (1983) "The Damal2:e Equiva-lence of Electrons. Protons. Alphas and Gamma Ravs in Rad-Hard MOS Devices". IEEE Trans. Nuclear Sci. NS-30. 4363-4367

::i4. Dozier. C. M. and Brown. D. B. (1983) "The Use of Low Ener~y X-Rays for Device Testinlf A Comparison with Co-SO Radiation". IEEE Trans. Nuclear Sci. NS-30. 4382-4387

::i~). Fossum. J. G .. Sander, H. H. and Gerwin. H. J. (1974) "The Effects of Ionizing Radiation on Diffused Resistors" IEEE Trans. Nuclear Sci. NS-21. 315-322

::3i). Raymond. <T. P. (1974) "MSI/LSI Radiation Response. Chara.­cteriz8.tion and Testinlf". IEEE Trans. Nuclear Sci. NS-21. 308-314

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37 Anderson. IN. T. et a1 (1987) "Experimental and Theoreti­cal Studv of Alpha Particle Induced Char~e Collection in GaAs FETs". IEEE Trans. Nuclear Sci. NS<i4. 1326-13:11

:OHi. Stapor. W. J. et a1 (1986) "SEU Dependence on Temperatu­re on an NMOS/Resistive Load Static RAM". IEEE Trans. Nuclear Sci. NS-33. 1610-1615

Ochoa. A. and Dressendorfer. P. V. of the Role of Distributed EffE'cts Trans. Nuclear Sci. NS-28. 4292-4284

(1981) "A Discussion in Latch-Up". IEEE

40. Son!?:, Y. et al (1987) "Parametric InvestiB:ation of Latch­Up Sensitivity in 1.25uM CMOS TechnolOB:V". IEEE Trans. Nuclear Sci. NS-34. 1431-1437

41.. Baze. M. P. and Johnston. A. H. (1986) "Latchup Paths in Bipolar Inte~rated Circuits". IEEE Trans. Nuclear Sci. NS-33. 1498-1.504

4:2. Baze. M. P. and Johnston, A. H. (J.987) "Testln..r Conside-

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rations for Radiation Induced Latchup". IEEE Trans. Nuclear Soi. NS-34. 17~iO-1735

K.i ar. R. A. and Pee 1. .J. (1974) Leaka~e Current in n-Channel SOS Trans. Nuclear Sci. NS-21. 208-210

"Rad iat ion J nduced Transistors". JEEE

44. Rollins, J. G., Choma. J. and Kolasinski, W. A. (1887) "Single Event Upset in SOS Inte~rated Circuits". IEEE Trans. Nuclear Sci. NS-34. 1713-1717

4::'. Davies. G. E. et al (1985) "Transient Radiation Effects in SOL Memories", IEEE Trans. Nuclear Sci. NS<l2. 4432-44~i7

46. Mao. B. Y .. Chen. C. E .. Pollack. G .. Hu~hes. H. L. and Davies, G. E. (1987) "Total Dose Harden in~ of Burr ied Insu lator in Implanted SOL Structures". IEEE Trans. Nuclear Sci. NS-34. 1682-1687

47. Borrego, J. H .. Gutman. R. J .. MOAhe. S. B. and Chudziki. M. .3. (1978) .. Ra.diation Effects on GaAs MESFETs". IEEE Trans. NucJear Sci. NS-25. 1436-1443

48. Papaioannotl. G . ..T. (19B7) "Electron Radiation Effects on GaAs MESFETs". Phys. ~.tat. Solidi (a)102. 84:3-848

49. Borre~o, ~T. M .. Gutman, R. -I. and Mo.~he, S. B. (18'19) "Radiation Effect.s on Si@:nal and Noise Characteristics of GaAs MESFET Microwave Amplifiers". IEEE Trans. NucJear

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so.

Sci. NS-26. 5092-5099

Meu lenber~. A. et. al Radi.ation Testin~ of Sci. NS-34. 1745-1750

(1887) "Dosimetrv and Total Dose GaAs Devices". IEEE Trans. Nuclear

51. Campbell. A. B. et a1 (1986) "Particle Dama~e Effects in Structures". IEEE Trans. Nuclear Sci.. GaAs JFET Test

NS-33. 1435-1441

52. Listvan. M. A .. VoId. P. J. and Arch D. K. (1987) "Ioni-zinp: Radiation Hardness of GaAs Technolo.~ies". IEEE Trans. Nuclear Sci. NS-34, 1664-1668

53. Flesner. L. D. (1984) "Transient Radiation Effects in GaAs Devices: Bulk Conduction and Cannel Modulation Phe­nomena in D-MESFET. E-JFET and n-SI-n Structures". IEEE Trans. Nuclear Sci. NS-31. 1502-1507

54. Anderson. W. T .. Simons. M .. Kin~. E. E .. Dietrich. H. B. and Lambert. R. J. ( 1982) "Reduction of Lon~-Term Tran­sient Radiation Response in ION Implanted GaAs FETs". IEEE Trans. Nuclear Sci. NS-29. 1533-1538

55. Buot. F. A .. Anderson. W. T .. Christou. A .. Campbell. A. B. and Knudson. A. R. (1885) "A Mechanism for Radiation­Induced De~rada.tion in GaAs Field Effect Transistors". J. Appl. Physics 57. 581-590

Page 541: Semiconductor Device Reliability

Reliability of High Speed HEMT Integrated Circuits and Multi-2DEG Structures

A. Christou (a) Foundation of Research and Technology - Hellas Physics Department, University of Crete Heraklion, Crete, Greece

ABSTRACT. The reliability of HEMT I.Cs indicates that the enhancement mode circuits are the weak point in the circuit' s reliability. Rapid degradation, has been observed at temperatures above 200 oc. The HEMT I.c. reliability results tend to follow the enhancement mode degradation statistics. The primary degradation mode is the confinement of the 2DEG channel and various lateral diffusion effects, which occur during circuit operation.

I. Introduction

High Electron Mobility Transistor Integrated Circuits based on III-V compound semiconductors have received wide attention recently due to their low nOise-high speed characteristics,1,2 near ballistic transport,) pico-second transit times4,5 and ability to integrate enhancement mode and depletion mode transistors. These circuits have achieved high performance as ring oscillators, dynamiC shift registers, frequency multipliers and as components for analogue circuits. In spite of the achieved results, HEMT I.C.s suffer from ohmic contact problems, threshold voltage shifts and various parasitic effects related to electron trapping and hot electron transfer from the two dimensional electron gas channel into the donor layer.

The ohmic contact degradation has been well characterized recently 6,7 and they typically suffer from random "spiking" of Au, Ge and Ni"8 to the 2DEG layer. The fabrication process requires that the alloying depth be precise enough so as to reach the 2DEG layer. Recent reports9 indicate that the mobility and electron sheet concentration degrade after sintering. The ohmic contact problems have been fully characterized and their effect on reliability has been determined. This paper will concentrate on the generic issues which affect HEMT I.C. reliability. Ufe test and 8.I:celerated stress data will also be presented for ring oscillators and dynamiC shift registers.

(a)Also Naval Research Laboratory, Washington DC

545

A. Chris/ou and B. A. Unger (eds.), Semiconductor Device Reliability. 545-556. © 1990 Kluwer Academic Publishers.

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The generic issues related to HEMT I.C. reliability are related to the stability of the 2DEG electron channel, both in the enhancement mode and depletion mode mode format. There are two generic issues which will be discussed. These two issues are : (a) confmement of the two dimensional electron and (b) trap centers in the hetero-interfaces. Related to the generic issues is the migration of such traps in a high temperature/radiation environment. The physical changes which have been identified are : 1. changes in band gap offset aEc due to aluminum diffusion, 2. changes in band-bending at the AlGaAs-GaAs interface, 3. the increase in impurity scattering in the 2DEG region. The generation of electron and hole traps are accompanied by such physical phenomenon as : 1. trap assisted tunneling and defect generation (Le. dislocations and vacancies).

II. The HEMT Integrated Circuit

The HEMT I.e. is based on depletion mode-enhancement mode transistor combination monolithically integrated on a semi-insulating GaAs substrate. The enhancement mode circuit section is formed by selectively thinning the AlGaAs doner layer up a thickness of 200-500A. The thickness is chosen so that the Schottky barrier bUilt-in potential totally depletes the electron channel so that the device is normally-off. On the other hand, the depletion mode structure consists of a thicker donor layer (600A) which allows the 2DEG channel to be normally-on. In both cases, thickness of the AlGaAs must be critically conrolled and that mode part of such a circuit is expected to be more susceptible to degradation due to the small thickness of the AlGaAs layer. Phenomenon such as alloy clustering and interface roughness is expected to affect the reliability of such circuits. Both of these phenomenon are temperature-tjrne and bias dependent and are candidates for wearout mechanisms. ll,12

In the present investigation six stage ring oscillators and dynamic shift registers were accelerated stress tested up to a channel temperature of 25()oC. The channel temperature was measured by an infra-red microscope on a 2 !UD gate length test structure subjected to the equivalent ambient temperature. The ring oscillators and dynamic shift registers consisted of 0.75 !UD HEMTs with Au-TiW gate metallizations and AuGeNi ohmic contacts. The accelerated stress temperatures were 12()oC, 15()oC, 1750 C, 2000C and 2500c. The circuits were operated dynamically at each temperature and the performance measurements were taken at room temperature. As a review, the ring oscillator is a circuit of odd number inverters (2k+1) in a cascade, with a feedback loop from the last inverter to the first inverter. Therefore the output signal is the inverted input signal.

III. Accelerated Stress Testing of HEMT I.Cs

The HEMT depletion mode-enhancement mode dynamic shift register accelerated stress results are shown in Figure 1. The MTF varies from 102 hours at 2000C to 5x103 hours at 125°C which is the maximum specified temperature. In the same figure a comparison is shown for

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547

nonnal FET DIE mode dynamic shift registers and indicates a one order of magnitude larger MTF for each temperature measured. A further comparison of FET integrated circuits with HEMT lCs is shown in Figure 2. The MTF of HEMT inverters is shown to vary between 1()Z hours at 2()()oC to 5xl03 hours at 1250 C. The equivalent FET circuits are also shown to be ten times larger than the HEMT circuits. The general behavior of the dynamic shift registers is similar to that of the ring oscillators.

COMPARISON OF HEMT WITH FET DYNAMIC SHIFT REGISTER RELIABILITY DATA

_ 10·­~ :::J o

..c:

~ 1()4 -

3 ~ ~ 10'-w :i!: 1= Z 102 -

« w :i!:

10 f-

300

,./ /

/IJJ. /IJJ. ~

/

6 FET DIE MODE DYNAMIC SHIFT REGISTER

IJJ. HEMT DIE MODE DYNAMIC SHIFT REGISTER

250 200 150 100 50 CHANNEL TEMPERATURE, °C

Figure 1. Accelerated life test data for HEMT and FET dynamic shift registero.

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548

COMPARISON OF FET I.C.s WITH H EMT I.C.s

~1Q4 ::J ...J

~ o 103

I-W

~ 1= Z 102

c::( W

~

10

300

/

250

0/ /

~

200

/

/ /

0/

0/

/ /

/

f:,. NRL HEMT INVERTERS DIE MODE

o NRL FET INVERTERS DIE MODE

150 100 CHANNEL TEMPERATURE DC

Figure 2. Accelerated life test data of HEMT and FET ring oscillator integrated circuits.

The data of Figures 1 and 2 shows a general difference between HEMT I.c.s and FET I.C.s which is probably due to the stability and confinement of the 2DEG channel. The problems related to 2DEG confinement are introduced by variations in AEc introduced during the accelarated stress testing. An additional factor which may explain the difference may be the actual thickness of the AlGaAs donor layer in the enhancement mode configuration. Figure 3 shows the difference in MTF between enhancement mode circuits and depletion mode circuits indicating a marked difference between the two types. The extrapolated MTF for enhancement mode HEMTs at lOOOC is approximately l()4 hours while for depletion mode HEMTs, it is lOS hours. Therefore, we may conclude that for a HEMT enhancement mode depletion mode I.c., the reliability to a large extent is determined by the enhancement mode segment of the circuit.

Page 545: Semiconductor Device Reliability

DISCRETE FET RELIABILITY LIFE TESTS

106.-~--~----,------.--------,-------,

105

(J)

:; o :S 10' LU CC

:3 ~W !2 LU

2: i=1O" 2 « LU

2: 10

... NRL SAG-MODFETS ENHANCEMENT MODE

[', CNET TESTS

o THOMSON CSF ENHANCEMENT MODE

• GOULD-DEPLETION MODE

o NRL SAG-MODFETS DEPLETION MODE

1L--L __ -L ____ ~--~~----~~----~_ 350 300 50

DEVICE CHANNEL TEMPERATURE 1°C)

549

Figure 3. Accelerated life test results for enhancement mode and depletion mode HEMTs.

The results of Figure 1-3 indicate that thickness considerations (donor layers) may be critical in the reliability of enhancement mode -depletion mode HEMT integrated circuits. In the following accelerated life test results an additional thickness parameter has been added : that of the spacer region between two channels in HEMT transistors. Such transistors with multi - 2DEG are designed for power output with microwave gain at frequencies above 60 GHz. Three different types of HEMTs were fabricated with the spacer region between the two 2DEG channels being varied from 150A to 650A. Figure 4 summarizes the reliability of dual channel HEMTs.

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550

~ " o

10'

:. 10' w rr 3 « u.; 10' ~ w :i: i= z 10' ~ w :i:

10

300

RELIABILITY OF DUAL CHANNEL HEMTS

I I n+ AIGaAs b!018cm-3

~ UN DOPED AlGaAs 75A

X u'GaAs 500A T UNDOPED AIGaAs 75A <>

u -GaAs 4.000A

EFFECT OF WAVE FUNCTION OVERLAP ON MTF OF MULTI-2DEG HEMTS

100 CHANNEL TEMPERATURE

o

Figure 4. Accelerated life test results of multi-channel HEMTs for a channel spacer thickness of 1S0A, SOOA and 6S0A.

It is shown that the MTF of the mUlti-channel HEMTs icnreases with spacer thickness x. The dependence on the thickness x can not be explained from a thermal diffusion arguement. As the thickness x increases, two discrete channels are established which distribute the temperature increase over a larger region of the device. In the case of a spacer thickness x of lSOA, a higher channel current density is expected thus leading to a smaller median lifetime.

IV. Discussion of HEMT I.C. Degradation

A. Multi - 2 DEG HEMTs.

In order to understand multi - 2DEG HEMT degradation, a series of test structures were subjected to bias - stress testing at 2()()oC for 100 hours. The bound states in the quantum wells were determined by photoluminescence measurements as well as donor levels in the spacer layer. Using both photoreflectance and photolumminescence measurements, the movement of the conduction band edges as a result of accelerated life testing was determined. Figure S shows a decrease in the conduction band edge discontinuity between GaAs and AlGaAs as a result of aging. This effect would result in a deconfinement of carriers and a decrease in the transistor transconductance The second effect determined by the optical measurements is a movement of the bound state in the intra-channel

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551

well toward higher energies resulting in a spill-over of free electrons out of the quantum well channel. Both effects result in a transconductance degradation and a decrease in reliability.

MULTI- 2 DEG - HEMTS

I AIGaAs r

I GaAs

I I I

AIGaA.

NEUTRAL IDEPLETIONjSPACER1 LAYER I LAYER ! LAYEA I :S~~~I DEPLETION I NEUTRAL

_'4 _'4 ... , : :: I ': 1 I I I I I 1 I I I 1 1

I" -/-I I 1 1 I I I

EO' BOUND STATE AFTER 2OO'C/100HR AI. Si DIFFUSION

ED· OONOR LEVEL IN SPACER LAYERS

LAYER I LAYER -II

Ec' GaA. CONDUCTION BAND AFTER 2OO'C/100HR AI. Si DIFFUSION

Figure 5. Schematic representation of changes in the multi - channel HEMT conduction band structure.

B. Degradation of HEMT I.C.s

In order to explain the changes observed in HEMT integrated circuits, relaxed geometry structures were aged at 2000C for 200 hours. The extrapolation to the submicron geometry samples is then made assuming that the submicron geometry does not introduce new failure modes. In all cases the vertical heterostructure has been kept the same. Two types of lateral diffusion were observed after 200 hours and 2000C of relaxed geometry HEMT structures. The first is gold from the ohmic contacts into the gate channel, and the second is aluminum migration, first into the ohmic contact and then across the channel. The lateral migration of gold is shown in Figure 6 as a result of stressing at 2000C, 200 hours under biass. A depletion of gold from the contacts is shown, with an equivalent build-up of gold between the source and drain. The gold between the contacts represents the effects of interdiffusion of gold through the TiW diffusion barrier to the recessed channel. Also shown is of oxygen in the channel region which is probably the effect of the accelerated stress testing under bias. The bias conditions were at pinch-off at 0.8-1.0 volts.

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LATERAL MIGRATION EFFECTS IN HEMTS

105 SOURCE GATE

~ 104

Z ::J o o en ~ iii 103

Au IN AuGeNi /BEFORE REL TESTS

L___ Au IN HEMT --- ------ STRUCTURE,

~ 'I 2OO'C, 200 HRS '<l BIAS

DISTANCE, J..Im

DRAIN

25

Figure 6. SIMS lateral profile of gold in accelerated stress tested HEMTs.

A second important phenomenon related to lateral migration is the movement of aluminum from AlGaAs as a result of ohmic contact formation and accelerated stress testing. It was previously reported that Al migrates to the surface of the source - drain contacts as shown in Figure 7. There is a further migration of Al as a result of the 100 hour, 2000c bias test. The migration of Al into the gate recess region would further change the conduction band discontinuity on the confinement of the channel electrons. Figure 7 shows the comparison of aluminum composition in the initially deposited HEMT structure, after ohmic contact formation and after the bias accelerated stress tests. At each point the Aluminum concentration is observed to change from the as deposited HEMT structure.

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LATERAL MIGRATION OF ALUMINUM DETERMINED BY SIMS

Tmmm ! 0' Al'~7 ,am], I I

-+j GATE CHANNEL k-~ 104 AI, AFTER OHMIC CONTACT

~ . "~." ~.F~.~~.A~~I.~~ AI, 2000C, 100 HRS ............•... o ~t::. '" BIAS . t::.t::.l:;t::.t::.Mt::c.

U

\~~T ............................... AS DEPOSITED HEMT STRUCTURE

103~----~----~----~----L-----L-~ o 5 10 15 20 25

DISTANCE,11m

553

Figure 7. Lateral diffusion of aluminum after various accelerated stress tests.

The effects of diffusion in the heterojuction structures were also investigated by SIMS. Of specific interest are the degradation modes related to Al diffusion from the AlGaAs donor layer into the 2DEG channel. The resultant effect will be an increase in alloy scattering in the undoped GaAs. The SIMS profile shows a depletions of Al from the spacer region which has now been relaxed in verictal dimension so that it is 0.5 !AJll thick. The abruptness of the interface has not changed significantly as shown in Figure 8. The degree of build up of aluminum in the un doped GaAs will effectively negate the high electron mobility found in the 2DEG channel since the 2DEG region is present on the GaAs side of the hetero-interface.

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QP&O '00

5x10' i-

<Jl I-:2 :J a u « ...J

~ a I-

10' -

0

UNDOPED A1ovGa013As SPACER

'"

2OO0 C.2':RS BIAS

0 0 0 0 0

2 DEG

UN DOPED GaAs

""'=" L-ALLOY :r::::G

~ 0000:0

100 200 SPUTTER TIME. Min

300

Figure 8. Sputter profile of a HEMT heterojunction showing Al diffusion as a result of a 2000C, 100 hr bias test.

An additional affect observed in relaxed geometry HEMTs is the movement of the silicon dopant from the n+ AlGaAs layer into the undoped GaAs region which contains the 2DEG channel. The effect of dopant diffusion has been studied by SIMS and some impurity scattering has been observed in the 2DEG channel. The exact reason for the silicon movement is not well understood but may be due to a strain relief mechanism between Gao.73AlO.27As and GaAs.

e. Gate Leakage CUrrent

The time dependant leakage current which accompanies HEMT I.e. degradation may be explained by hot electrons which enter the depleted AlGaAs areas causing device and circuit performance to degrade over time. Such a problem may be modeled by solving the Bolzman and energy transport equations simultaneously for an electron temperature Te, and hot electron distribution function :

w yw2 -a(--+--)

KTe KTe fo (w) = Aexp

where:

A = normalization factor y = ratio of acoustic to intervally phonon coupling factors a = function of electron temperature which ensures a consistent

solution

The leakage current is then : lex) = qA(x)N(x) w3/l fo(w)dw. In the above formalism the distribution must be derived and solved from which the number of electrons available for gate leakage current and

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substrate current can be detennined. By solving for the electron temperature as a function of lateral FET geometry, the results indicate that the peak surface electron temperature of 3()()()oK may be reached during accelerated stress testing. Therefore hot electron effects may be responsible for for catastrophic failures.

V. Conclusions

The conclusions reached as a result of the present investigation have shown that : A. Enhancement mode HEMT I.C.s are ten times less reliable than

depletion mode HEMT cirucits. B. Rapid degradation of both D-mode and E-mode HEMTs occurs at

temperatures greater than 2000C. C. HEMT I.c.s generally follow the E-mode HEMT MTBF

projections. D. A basic difference in MTBF of FET and HEMT circuits is

observable and is related to the stability of the 2DEG channel.

Finally, the reliability analysis of HEMT circuits must address generic degradation modes.

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REFERENCES

1. A. Christou, Solid st. Electr. 22, 141 (1979).

2. T.1. Drummond, W. Kop, H. Morkoc and M. Keever, App. Phys. Lett. 41, 277 (1982).

3. M.I. Nathan and M. Heiblum, Solid State Electr. 25, 1063 (1982).

4. 1.F. Rockett and P. Delescluse, Inst. Phys. Conf. Ser., No. 65, pp. 385-392 (1982).

5. P.C. Chao, T. Yu, P.M. Smith, S. Wanuga and C.M. Huang, Electron. Lett. 19, 894 (1983).

6. C.P. Lee, D.L. Miller, D. Hou and R.1. Anderson 41 st. D.R.C., p. II A-7 (1983).

7. R. Fisher, T.J. Drummond, W. Kopp, H. Morkoc, K. Lee and M.S. Shur, Electron. Lett. 19, 189 (1983).

8. H. Dampkas, W. Brokerhoff and K. Iterme, Electron, Lett. 20, 615 (1984).

9. A. Christou and N. Papanicolaou, SolidState Electr. 29, No 2, 189-192 (1986).

10. W.T. Anderson, D.V. Morgan, F.A. Buot, and A. Christou, Quality and Reliability Engineering International, Vol. 4, pp. 255-2689 (1988).

Page 553: Semiconductor Device Reliability

AIGaAs AS A DIELECTRIC ON GaAs FOR DIGITAL I.C.'S: PROBLEMS AND SOLUTIONS

W. Ted Masse1ink IBM T . .J. Watson Research Center P.O. Box 218 Yorktown Heights, New York 10598 U.S.A.

ABSTRACT. GaAs field effect transistors (FETs) offer significant speed advantage over FETs based on Si because the electrons afC inherently faster in GaAs. Field effect transistors based on the AlGaAs/GaAs heterostructure have demonstrated unity current gain cut-off frequencies (fT) in excess of 110 GHz. Switching times of 5.8 ps have been measured in ring oscillator circuits cooled to 77 K. The presence of an intrinsic AIGaAs defect, OX, however, results in behavior which is undesirable for FET operation, particularly in digital applications. This defect is observed in all n-type AlGaAs and appears to be as dense as the doping concentration, itself. There are several solutions to the problems caused by the OX centers in doped AlGaAs. By using self-aligned technologies, it is possible to use undoped AIGaAs which does not contain the OX center. Mod­ifications such as the use of a thin InGaAs layer at the heterointerface with lower Al molc fraction AIGaAs allow us to use more standard GaAs FET technology and still avoid most of the problems associated with the DX center. These solutions to the problems of traps in AIGaAs may allow us not to rule out AlGaAs as a reliable dielectric for GaAs transistor applications.

I. Introduction

Electronic devices fabricated from direct bandgap III -V semiconductor materials such as GaAs are inherently faster than corresponding devices fabricated from silicon. This speed advantage is due to the higher electron velocity and mobility in materials such as GaAs when compared to Si. The higher mobility follows directly from the much smaller effective masses of electrons in direct bandgap semiconductors. The very fastest elec­tronic devices, moreover, are based on he/eros/ruc/ures of 1 I 1 -V semiconductors. These structures take advantage of the properties of not only one, but at least two different materials. This allows one greater flexihility in tailoring transport and charge control properties in the structure. For example, using microwave performance as a benchmark, the fastest transistors are FETs constructed in the material system A1.48 1 n.52As/ Ga.38In.62As which is, except for the strained Ga.38In.62As quantum well, lattice matched to InP. These FETs with 0.1 lIm gate length showed a frequency of unity current gain (fT) of 205 GHz.[l]

In spite of the promise of heterostructures based on AI.4RTn.52As/Ga.47In.S3As, AIGaAsjGaAs remains the mo~t important heterojunction system for testing novel electronic device ideas and also for application where more advanced processing and

557

A. Christou and B. A. Unger (eds.), Semiconduclor Device Reliability. 557-568. © 1990 Kluwer Academic Publishers.

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control is needed. A variety of devices make use of AlGaAs in AlGaAs/GaAs heterostructures. Heterostructure lasers use AlGaAs for optical waveguiding and con­finement. By including an AIGaAs/GaAs quantum well or superIattice in the active re­gion of the laser, the wavelength can also be decreased. A number of optical detectors also make use of AIGaAs/GaAs superlattices. For example, multiple heterojunction AlGaAs/GaAs avalanche photodiodes can be designed to preferentially provide multi­plication to only electrons in order to improve the noise performance of these devices. Heterojunction bipolar transistors (lIBTs) show significantly superior performance over homojunction bipolar transistors both in terms of gain as well as current density. Through the use of an AIGaAs emitter, which provides a barrier to hole transport from the base to the emitter, the emitter efficiency can be kept higher. This is especially im­portant as the base doping is increased as the base thickness is decreased for improved base transit times. Similar to J IBTs in many ways are a variety of structures which rely on resonant quantum tunneling through AIGaAs barriers. These structures are poten­tially very fast because the tunneling times are so short. Along the HBTs, the most important devices technologically today, are FETs based on heterostructures. The most popular example is the modulation-doped FET, or MODFET [2]. This device is also known as the HEMT which stands for "High Electron Mobility Transistor".

The AIGaAs/GaAs MODFET shares qualities of the MOSFET and of the GaAs MESFET. Like the MOSFET, the higher bandgap AlGaAs insulates the conducting channel from the gate metal. This allows higher gate potentials with lower gate leakage current. While the MESFET has a depletion depth which depends on gate bias, the MODFET's AlGaAs is a constant thickness so that the capacitance is not as gate volt­age dependent. On the other hand, by doping the AlGaAs, the threshold voltage can be controlled to produce either depletion or enhancement mode FETs. More important, in the modulation-doped heterostructure, the donors are spatially separated from the electrons in the channel. In this way high sheet electron densities can be achieved, but with electron mobilities as high or higher than those normally found only in very lightly doped GaAs. At low electric fields and low lattice temperatures, the electrons in these modulation doped heterostructures can have extremely high mobilities-values as high as 107 cm2/Vs have been reported.[3J Although such high mobilities are not realized at higher temperatures in structures suitable for FET fabrication, even at 77 K in tran­sistor structures, the low-field mobility is typically about 5x104 cm2/Vs. This mobility, however, degrades relatively quickly as the field is increased, so that useful electric fields, the mobility is closer to 2xl04 cm2/Vs [4]. This mobility is still much higher than one will find in either Si or GaAs doped heavily enough to provide adequate carrier con­centration for FET application. More important, these higher mobilities translate into higher velocities than in doped GaAs at least up to 104 V/cm [5]. These superior transport properties are reflected in the superior FET performance of MODFETs.

Through higher mobilities and peak velocities, the average velocity of electrons under the gate of MODFET can be higher than that of electrons in a MESFET. This means that the transconductance to gate capacitance ratio is higher in MODFETs. For ana­logue applications, this will translate into higher frequencies of operation. Recently, a 0.1 ,um AIGaAsjGaAs MODFET had a frequency of unity current gain (fT) of over 110 GHz [6]. Because of better electron confinement in the channel, the output resistance is also higher in the MODrET which aids in achieving high maximum frequency of operation (f.uwJ. The high frequency noise behavior of MODFETs is also better than that of ME~t< .toTs [7J. For a gate length of 0.5 pm, the difference is about 0.5 dB at

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10 GHz and 0.9 dB at 18 GIIz. For shorter gate lengths, speed and noise advantages of MODFETs over MESFETs become less noticeable. The digital performance of heterojunction FETs is also superior. At 77 K, switching times of 5.8 ps have been measured in a ring oscillator circuit [8] constructed of AIGaAs/GaAs MODFETs with gate lengths of 0.35 1Lm. The corresponding power dissipation per gate was only 1.76 mW. Encouraging results in MODFET circuits with higher fan-out have also been demonstrated. Recently, non-optimized room temperature 4 kbit SRAM access times of under 500 ps with 2W power dissipation have been reported [9]. The examples given above are representative of the performance advantages possible with AIGaAs/GaAs heterostructure FETs when compared to non-heterostructure GaAs FETs.

2. Problems with AIGaAs: the DX Center

Although the performance of FETs constructed using as AIGaAs as a doped dielectric on GaAs is excellent, there are serious problems which hinder the application of these devices in digital circuits. These problems are most apparent at 77 K where significant performance improvement makes operation desirable. Even at 300 K, things are not as straightforward as they seem. The most obvious instability observed in MODFETs at 77 K is the so-called "collapse" of the source-drain I-V characteristics. This behavior is characterized by a diode-like family of curves for small drain-source voltage and then very high output conductance for larger drain-source voltage. This behavior is illus­trated in Fig. I. Under illumination this behavior is not evident and the I-V curves look like normal FET characteristics. A second problem readily observed in MODFETs at 77 K is a shift of the threshold voltage which depends on temperature, illumination, and the history of operation [10]. When the device is cooled in the dark from room tem­perature to 77 K, the threshold gate voltage shifts to a more positive value. Upon illu­mination, the threshold returns to a value similar to that measured at 300 K.

10 77K Dark

';;( AI.3Ga.7As1GaAs MODFET .s8 o

H

1.0 1.5 20 2.5 Drain \l:)lIoge, Vos (V)

Fig. I. Drain-source I-V characteristics of an AlO•3Gao.7As/GaAs MODFET operated at 77 K in the dark.

30 " 17K Dark """;,, 4 AI.3Ga.7AslGaAs MOOFET

" " .s " " " " .5'2Il " " // " c // !!

/ "f !; Threshold Shift u " ,/ h ,," ,,"

/"/" " 0

" " ,," .--~5

.,~ ...... ~ 0 0.5 1.0 Gat. Voltage vGS (V)

Fig. 2. Drain current versus gate voltage for an Al0.3Gao.7As/GaAs MODFET operated at 77 K in the dark. The shift in threshold voltage is due to the fUling of DX centers in the AlGaAs.

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More serious are the threshold shifts which depend on the history of operation. This effect may be characterized as follows: the drain current is measured (in the dark) as a function of gate voltage for the FET in saturation beginning with subthreshold gate values, up to a fully on gate voltage, and then back down to subthreshold. Generally, the curve lo(V G ) with decreasing V G is different from ID(V s) measured with in­creasing V GS' an~ the threshold voltage becomes more positive aRer a forward gate bias has been applied. This effect is shown in Fig. 2. It is clear that operating a digital circuit at 77 K in the dark with these problems will be extremely difficult. Even at 300 K, there is peculiar trapping behavior in MODFETs fabricated from A1.3SGa.6SAs/GaAs heterostructures [11]. This trapping reveals itself in transient measurements of drain current when the gate voltage is pulsed in A1.3SGa.65As/GaAs depletion mode MODFETs. These transients have characteristic times in the 10 J.LS range and through comparison with deep-level transient capacitance spectroscopy (DL TS) measurements, it appears that they are due to trapping and emission of electrons from traps in the A1.3SGa.65As. Another manifestation of the same trapping center at 300 K has been ob­served in AI.Gal_.As/GaAs MODFET inverter chains [12]. The inverter chains were subjected to gated bursts of pulses of ns width. Especially the non-self-aligned struc­tures showed extreme pulse narrowing and attenuation. Such behavior is clearly unac­ceptable in circuit applications. Further investigation indicated that this pulse attenuation is due to a turn-on transient response of the individual FETs. This can be avoided by using self-aligned processing and lower mole fraction AIGaAs.

The instabilities mentioned above occurring in FETs are directly related to the trap in doped AIGaAs known as the DX center. The DX center is observed in all n-type AI.Gal_.As with x~0.22 at reduced temperatures [13]. The trap density is equal to the donor density. The value of the trap depth depends on how it is measured. Hall measurements of AI.Gal _.As indicate that the depth for small x is simply the shallow donor level [14]. The Hall depth reaches a maximum of 160 meV for x",,0.48. Fur­thermore, there is a larger barrier to emission as well as a barrier to capture. This results in persistent photoconductivity (PPC) behavior: if AIGaAs is cooled in the dark, the DX center traps are filled. If they are emptied by exposing the sample to white light, then they remain empty until the sample is warmed and recooled in the dark. This PPC effect suggests that strong lattice relaxation is involved in this trap [13]. The capture and emission barriers for electrons in DX centers have been studied using DLTS [\5]. Measuring the emission barrier height is difficult, but within experimental uncertainty does not depend on AI mole fraction. Capture barrier heights do depend on AI mole fraction and capture times vary several orders of magnitude with changes in Al mole fraction.

The first model to explain the DX center was proposed by Lang, Logan, and Jaros [13]. They suggested that the trap was a complex involving the donor and a defect such as an arsenic vacancy. Such a configuration would explain the data; it also suggests that the DX center can be eliminated through improved growth techniques and better stoichiometry control. In spite of considerable effort, however, altering the DX center density was never demonstrated. This model does not explain the results of pressure experiments. In these experiments, it was demonstrated that the application of hydrostatic pressure to the AI.Gal _ .As sample had the same effect as increasing x [13,16]. It was even shown that with sufficient pressure, the DX center could even be induced in GaAs [17] as a special case of AlxGal_ .As with x = 0.0. Clearly, then, this is not entirely a materials problem (e.g., an alloy problem) per se, but, rather, a band

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561

structure effect. More recently it has been proposed that through a very general mech­anism donors in semiconductors may become deep levels with barriers to electron emission [IS]. In this model, it is energetically favorable for the donor to become dis­placed from its lattice site and to capture two electrons. In order to maintain charge neutrality, then, half the donors are ionized and the other half are negatively charged OX centers. This model does not require the presence of AI, nor does it require other defects such as vacancies. The calculated displacement of the donor atom is more than I A [IS] which should be sufficient to explain the PPC effect. The energy of such a level depends only on the conduction band structure, with this level being a fixed energy lower than the Brillouin zone average of the lowest conduction band. These attributes are consistent with most of the experimental data and also explain the pressure data.

The model as described in Ref. IS does not predict any alloy effect in AIGaAs - that is, the effect totally depends on band structure. Careful OLTS measurements [19] reveal thllt there are actually at least three distinct OX center levels and that the popUlation of these levels depends on the Al mole fraction, x, of the AlxGa,_xAs. The reason for these levels may be that if the donor is displaced from its lattice site in a bond direction, then there are 4 equivalent anion neighbors which may be either Al or Ga [20]. Thus, there should be four different OX center configurations. Furthermore, the energies for these relative to the r band edge have been calculated [20J and are consistent with the data [19]. This alloy dependence of the OX center and its explanation is not contrary to the model of Ref. IS, but may serve to enhance or expand it.

3. Solutions

This section is not intended to provide a comprehensive list of possible solutions to the various problems that must inherently exist in doped AIGaAs due to the OX center. The following discussion, however, points out some general approaches and the specific means of realizing these ideas in field effect transistors. Four distinct approaches to eliminate the OX center problem in heterojunction field effect transistors are investi­gated: bandgap engineering to change OX level, designing a structure to keep the AIGaAs depleted, using undoped AIGaAs, and using low Al mole fraction AIGaAs. One obvious solution, the use of alternate materials systems, is not discussed.

1.1 SUPERLATTICE 'AIGa!\s'

Because the OX center level associated with a donor near Al atoms in AIGaAs is lower than that associated with a donor near all Ga atoms relative to the r band edge [20], the AIGaAs could be improved by spatially separating the Si donors from the AI atoms while maintaining the same AIGaAs bandgap. One way of doing this to replace the AIGaAs with an AlAs/GaAs superlattice and dope only the GaAs [21]. Ref. 21 com­pares this superlattice replacement for AIGaAs with conventional AIGaAs. The superlattice consisted of a series of alternating layers of of AlAs and GaAs with each period adding up to about 40 A. A typical example would be 15 A of AlAs and 25 A of GaAs. Only the GaAs was doped with Si and the two monolayers of GaAs adjacent to the AlAs of each period were left undoped. When this pseudo-alloy is compared with AIGaAs with the same bandgap (as measured by photoluminescence), a dramatic re­duction in PPC is observed as well as a lower activation energy for the donors and a higher donor activation coefficient. The remaining PPC observed may be due both to

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some incorporation of Si atoms at the AlAs/GaAs interfaces and to the higher energy DX center associated with Si near Ga atoms. When this pseudo-alloy is used to replace the AIGaAs in a modulation-doped heterostructure, the PPC effect and light sensitivity is also reduced [22]. Fig. 3 depicts the conduction band profile of such a structure. Because of spatial confinement, there are no density of states at the bottom of the con­duction band of the GaAs quantum wells. The lowest subband still lies above the Fermi level which allows such a structure to replace AIGaAs without substantially increase the amount of parallel conduction of electrons in the AIGaAs. Using this structure to eliminate deleterious effects in MODFETs at 77 K, however, were inconclusive [23].

metal GaAs

Fig. 3. Conduction band profile for a MODFET in which the AIGaAs is replaced by an AlAs/GaAs superlattice. Only the GaAs wells are doped with Si.

3.2 QUANTUM WELL HETEROSTRUCTURE MISFETs

A second concept which has been explored in the context of complimentary logic is a quantum well MISFET in which the doping for the quantum well channel is below the quantum well and, therefore, away from the gate [24]. Because the doped AIGaAs layer may be screened by the carriers in the quantum well channel, this structure can be de­signed so that the doped AIGaAs remains depleted even when the gate is forward biased. These heterostructures are composed of 650 A Alo.4Gao.6As which has a thin doped re­gion in it followed by a 300 A GaAs quantum well, 200 A Alo.4Gao.6As, and 50 A GaAs at the surface. The conduction band profile for such a structure is depicted in Fig. 4. Except for the thin doped region in the Alo.4Gao.,As below the quantum well, the entire structure is un doped. Computer modelling of this structure under various gate bias levels indicates that with proper spacing of the doped layer relative to the quantum well, the structure can be designed so that the AIGaAs remains depleted. This has the result of raising the DX center level relative to the Fermi level. Measurements to investigate bias-induced threshold shifts show that the shifts are much smaller than in similarly

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563

fabricated conventional MODFETs [24]. This structure may also be stacked with an n-channel and a p-channel for complementary logic circuits. Simulations of switching times and power dissipation indicate significant improvement over Si CMOS [25].

> Q)

1.6 ,.-......,-..,.--r-"'T""--r--r---,r----,.--r--,

1.2

>. 0.8 0'1 L Q) C w 0.4

GATE

Ef -----.

-200 200 400 600

Distance. 'A

Fig. 4. Conduction band proftle for the Quantum Well MISFET of Ref. 24. When used with a similar p-type quantum well channel. this structure is designed for compli­mentary logic applications.

GaAs

GaAs

800

Fig. 5. Conduction band profile for the GaAs gate heterojunction PET discussed in Ref. 26. The gate is fonned on the n + GaAs on the left.

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564

3.3 GaAs GATE HETEROSTRUCTURE PET WITH UNDOPED AIGaAs

Another solution to the problem of doped AIGaAs is to used undoped AlGaAs to achieve a structure similar to the Si MOSFET. In order to get reasonable threshold voltages, it is advantageous to design the structure symmetrically with GaAs both above and below the insulating AlGaAs [26]. Then the threshold voltage will be close to zero and, unlike in a conventional MODFET, will not depend on the doping of the AIGaAs. Additionally, because the AIGaAs is undoped, there are no OX centers associated with this device. This structure typically consists of (from the substrate, up) 8000 A undoped GaAs (lightly p-type), 350 A undoped Alo.sGao.sAs, and 3500 A n+ -GaAs. This structure must be fabricated into FETs using a self-aligned process in order to prevent the source resistance from being prohibitively high [27J because with no gate potential the channel is depleted. The conduction band edge and Fermi level is shown for this structure in Fig. 5. Results using this approach are extremely encouraging. No "collapse" of the drain I-V characteristics are observed at 77 K in the dark. Furthermore, no threshold shifts such as are observed in conventional MODFETs are reported.

GaAs

metal

Fig. 6. Conduction band proftle for the AI.1sGa. 8SAs/ InlsGa.8sAs pseudomorphic MODrET first described in Ref. 28.

3.4 A1.lsGa.ssAs/In. lsGa.ssAs PSElJDOMORPIIIC MODPET

Another way to avoid the problems described in section 2 is to use AI.Gal _ .As with x;:50.2, where the OX occupation probability is significantly reduced. Using a reduced Al mole fraction, however, reduces the conduction band discontinuity at the heterointerface, which results in less efficient electron transfer and therefore a smaller two-dimensional electron gas (20EG) concentration. Use of low AI mole fraction AIGaAs also compounds problems of the parallel conduction of electrons in the AIGaAs. These problems with using low mole fraction AlxGal.xAs can be avoided by replacing the GaAs with a thin InyGal . yAs channel. As long as y is not too large, this layer can be grown pseudomorphically on the GaAs, maintaining the same transverse lattice constant as GaAs. The bandgap ofInGaAs is smaller than that ofGaAs, so the

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565

total conduction band discontinuity between, for example, AI.lsGa.8SAs/In.lsGa.8SAs is even larger than that between Alo.3Gao.7As/GaAs. A typical pseudomorphic MODFET consists of an undoped GaAs buffer layer grown by molecular beam epitaxy on a semi­insulating GaAs substrate. This is followed by 200 A of undoped In.1sGa.gsAs, then a 30 A undoped AI.1sGa.8sAs spacer, 350 A of Si-doped AI.1sGa.ssAs, and a 50 A GaAs cap. The conduction band edge for such a structure is depicted in Fig. 6. The low temper­ature operation of these A1.1sGaRSAs/lnlsGa.8SAs pseudomorphic MODFETs appears to be ideal [28]. The low Al mole fraction allows on to avoid the undesirable persistent trap effects associated with higher mole fraction AlGaAs, and, because In.lsGa.gsAs is used instead of GaAs, one achieves a high 2DEG concentration with high average electron velocities. This results in superior FET characteristics. Unlike conventional MOD FETs, there is no "collapse" of the drain-source I-V characteristics at 77 K in the dark. When the device is illuminated, the I-V curves remain virtually unchanged and completely return to their original values when the source of illumination is removed. Additionally, there is no threshold shift (i.e., gate voltage hysteresis) as is observed in the Alo.3Gao.7As/GaAs MODFETs.

Henderson et at. have reported excellent millimeter wave performance in 0.25 .um gate­length A1.1sGa.8SAs/In.lsGa.8SAs pseudomorphic MODFETs [29]. Even at 60 GHz, these transistors shown maximum gain of 11.7 dB and a noise figure as low as 2.4 dB with associated gain of 4,4 dB. At 18 GHz, the noise figure was 0.9 dB with an associated gain of 10,4 dB. These results show significant improvement over AIGaAs/GaAs MODFETs. Superior digital performance of AI.1sGa.gsAs/In.lsGagsAs pseudomorphic MODFETs has been demonstrated through ring oscillator simulations [30]. The input parameters were chosen to agree with actual measured I .urn FETs. The higher current density and higher transconductance of the FETs with the In.lsGa.8sAs channel accounts for the anticipated improvement of roughly 2 ps at both 77 and 300 K. This better performance with the discussed problems which occur when higher Al mole fraction AIGaAs is used make this device a very good candidate for digital applications both at 300 and at 77 K.

4. Conclusions

Very high performance FETs are being constructed using AIGaAs as a dielectric on GaAs in a manner analogous to SiO~ on Si in the MOS system. Although the digital performance of these FETs is supenor to both MOSFETs and to GaAs MESFETs, traps in the AIGaAs render the usual configuration of this transistor unreliable at room temperature and especially at 77 K. This trap state, the DX center, appears to be una­voidable whenever donor doped AIGaAs is used. The DX center causes persistent photoconductivity in bulk n-type AIGaAs. The same trap manifests itself in FETs through extremely non-ideal "collapsed" drain-source I-V characteristics, through shifts in the threshold voltage which depend on temperature, illumination, and the history of operation, as well as through distortions of pulse trains even at 300 K. These problems may be avoided by finding some way to avoid DX centers which may be occupied. This may be accomplished by avoiding DX centers altogether by not doping the AIGaAs, by keeping the DX center above the Fermi level by keeping the conduction band high, or by using low Al mole fraction AIGaAs with a strained quantum well of InGaAs.

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ACKNOWLEDGEMENTS: The author would like to thank the following people for helpful conversations: H. Morkoy, T.N. Theis, P.M. Mooney, R.A. Kiehl, P.M. Solomon, and C. Van de Walle.

REFERENCES

I. Mishra, U.K., Brown, A.S., and Rosenbaum, S.E. (1988) "DC and RF Performance of 0.1 1!m Gate Length AI.4,In.52As-Ga.38In.62As Pseudomorphic HEMTs", 1988 IEDM Technical Digest, 180-183.

2. Solomon, P.M. and Morko9, II. (1984) "Modulation Doped GaAs/AIGaAs Heterojunction Ficld-Effect Transistors (MODFET's), Ultra High-Speed Device for Supercomputers", IEEE Trans. Electron Devices, ED-31, 1015-1027.

3. Pfeiffer, L., West, K.W., Stamer, tI.L., and Baldwin, K.W. (1989), "Electron Mo­bility of 107 cm2/V sec in Modulation Doped GaAs", Bulletin of the American Physical Society: Program of the 1989 March Meeting, 20-24 March 1989, St. Louis, MO, U.S.A., 34, 549.

4. Masselink, W.T., Henderson, T.S., Klem, J., Kopp, W.F., and Morko9, H. (1986) "The Dependence of 77 K Electron Velocity-Field Characteristics on Low-Field Mobility in AlGaAs-GaAs Modulation-Doped Structures", IEEE Trans. Electron Devices, ED-33, 639-645.

5. Masselink, W.T., Braslau, N., Wang, W.I., and Wright, S.L. (1987) "Electron Ve­locity and Negative Differential Mobility in AlGaAs/GaAs Modulation-Doped Heterostructures", App!. Phys. Lett., 51,1533-1535.

6. Lepore, A., Levy, M., Lee, B., Kohn, E., Radulescu, D., Tiberio, R., Tasker, P., and Eastman, L. (1988) "Fabrication and Performance of 0.1 {tm Gate-Length AlGaAs/GaAs HEMT's with Unity Current Gain Cut-Off Frequency in Excess of 110 GHz", presented at 1988 Device Research Conference, 20-22 June 1988, Boul­der, CO, U.S.A.

7. Goronkin, H. and Nair, V. (1985) "Comparison ofGaAs MESFET Noise Figures", IEEE Electron Device Letters, EDL-6, 47-49.

8. Shah, N.J., Pei, S.S., Tu, C.W., and Tiberio, R.C. (1986) "Gate-Length Dependence of the Speed of SSI Circuits Using Submicrometer Selectively Doped Heterostructure Transistor Technology", IEEE Transactions on Electron Devices, ED-33, 543-547.

9. Kuroda, S., Harada, N., Katakami, T., Mimura, T., and Abe, M. (1988) "HEMT VLSI Technology Using Nonalloyed Ohmic Contacts", 1988 IEDM Technical Di­gest, 680-683.

10. Kastalsky, A. and Kiehl, R.A. (1986) "On the Low-Temperature Degradation of (AlGa)As/GaAs Modulation-Doped Field-Effect Transistors", IEEE Trans. Electron Devices, ED-33, 414-423.

II. Nathan, M.I., Mooney, P.M., Solomon, P.M., and Wright, S.L. (1985) "Room­Temperature Electron Trapping in AI.35Ga.65As/GaAs Modulation-Doped Field­Effect Transistors", App!. Phys. Lett., 47, 628-630.

12. Kaneshiro, R.T., Kocot, C.R., Jaeger, R.P., Kofol, J.S., Lin, S.J.F., Littau, E., Luechinger, B., and Rohdin, II.G. (1988) "Anomalous Nanosecond Transient

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Component in a GaAs MODFET Technology", IEEE Electron Device Lett., 9, 250-252.

13. Lang, D.V. and Logan, R.A. (1979) "Trapping Characteristics and a Donor­Complex (OX) Model for the Persistent-Photoconductivity Trapping Center in Te­Doped AlxGat_xAs", Phys. Rev. D, 19, 1015-1030.

14 Chand, N., Henderson, T., Klem, J., Masselink, W.T., Fischer, R., Chang, Y.-c., and Morko~, II. (1984) "Comprehensive Analysis ofSi-Doped AlxGat_.As (x=O to 1): Theory and Experiments", Phys. Rev. B, 30, 4481-4492.

15. Mooney, P.M., Caswell, N.S., and Wright, S.L. (1987) "The Capture Barrier of the DX Center in Si-Doped AlxGat_xAs", J. App!. Phys., 62, 4786-4797.

16. Mizuta, M., Tachikawa, M., Kukimoto, 11., and Minomura, S. (1985) "Direct Evidense for the DX Center Being a Substitutional Donor in AIGaAs Alloy System", Jpn . .l. App\. Phys. Lett., 24, Ll43-Ll46.

17. Tachikawa, M., Fujisawa, T., Kukimoto, B., Shibata, A., Oomi, G., and Minomura, S. (1985) "Observation of the Persistent Photoconductivity Due to the DX Center in GaAs under IIydrostatic Pressure", .lpn. J. App!. Phys. Lett., 24, L893-L894.

IX. Chadi, D . .l. and Chang, K.J. (1988) "Theory of the Atomic and Electronic Structure of OX Centers in GaAs and AlxGat_As Alloys", Phys. Rev. Lett., 61, 873-876; (1989) "Energetics of OX-Center Formation in GaAs and AlxGat _.As Alloys", Phys. Rev. B, 39, 10063-10074.

19. Mooney, P.M., Theis, T.N., and Wright, S.L. (1988) "Effect of Local Alloy Disorder on Emission Kinetics of Deep Donors (DX Centers) in AlxGat_.As of Low AI Content", App!. Phys. Lett., 53, 2546-2548.

20. Morgan, T.N. (1989) "The Vacancy-Interstitial Model of OX Centers", Materials Science Forum, 38-41, 1079-1084; presented at the 15th Int. Conf. on Defects in Semiconductors, 22-26 August 1988, Budapest, Hungary.

21. Daba, T., Mizutani, T., and Ogawa, M. (1983) "Elimination of Persistent Photoconductivity and Improvement in Si Activation Coefficient by Al Spatial Separation From Ga and Si in AI- Cia - As:Si Solid System - A Novel Short Pe­riod AlAs/n-GaAs SuperJattice -", .lpn . .T. App!. Phys. Lett., 22, L627-L629.

22. Pearah, P., Henderson, T., Klem, .T., Masselink, W.T., Chand, N., and Mork09, H. (1985) "Reduced Light Sensitivity and Persistent Photoconductivity in Novel Mod­ulation Doped IIeterostructures Incorporating an n-GaAs/AIGaAs Superlattice as the High Bandgap Material",.T. Electronic Materials, 14, 1-7.

23. Masselink, W.T. and Mark09, II. (1985) (unpublished results).

24. Kiehl, R.A., Frank, D . .T., Wright, S.L., and Magericin, .J.H. (1987) "Device Physics of Quantum-Well Heterostructure MI3SFET's", 1987 IEDM Technical Digest, 70-73.

25. Kiehl, R.A., Scontras, M.A., Widiger, D . .T., and Kwapien, W.M. (1987) "The Po­tential of Complementary Heterostructure FET Ie's", IEEE Trans. Electron De­vices, ED-34, 2412-2421.

26. Solomon, P.M., Knoedler, C.M., and Wright, S.L. (1984) "A GaAs Gate Heterojunction FET &cdq, IEEE Electron Device Letters, EDL-5, 379-381.

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27. Baratte, B., LaTulipe, D.C., Knoedler, C.M., Jackson, T.N., Frank, D.J., Solomon, P.M., and Wright, S.L. (1986) "Self-Aligned Processes for the GaAs Gate FET", 1986 IEDM Technical Digest, 444-447.

28. Masselink, W.T., Ketterson, A, Klem, .T., Kopp, W., and Morko~, B. (1985) "Cryogenic Operation of Pseudomorphic A1GaAsjInGaAs Single-Quantum-Well MODFETs", Electronics Lett., 21, 937-939.

29. Henderson, T., Aksun, M.L, Peng, C.K., Morko~, H., Chao, P.c., Smith, P.M., Duh, K.-H.G., and Lester, L.F. (1986) "Microwave Performance of a Quarter­Micrometer Gate Low-Noise Pseudomorphic InGaAsjA1GaAs Modulation-Doped Field Effect Transistor", IEEE Electron Device Lett., EDL-7, 649-651.

30. Ketterson, AA (\986) "Ring Oscillator Circuit Simulation with Modulation Doped Field Effect Transistors", M.S. Thesis, University of Illinois at Urbana-Champaign.

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APPENDIX A. RELIABILITY STRESS SCREENING

F. Jensen (Leader), W.E. Camp, R. Murphy and R. Goarin

F. Jensen introduced the subject by defining reliability stress screening (also called burn-in or environmental stress screening) as a process that applies accelerated stresses designed to elimi­nate flaws or defects that have a high probability of surfacing as early failures in the field (use) environment. He then introduced the ten topics listed bdow for discussion. The panelists each gave their viewpoints on a number of the topics, especially concentrating on items 1 through 4, although some of the other topics also were touched upon ..

The participants especially voiced their feelings regarding the first two items. The subject of the MIL-HDBK-217 type predictions - in connection with the first item - generated some heated discussions (as always). Many researchers and practitioners are now suggesting that the failure rate of "good" components is zero, 1..=0, after possible freaks have been eliminated and before wearout sets in (as also debated in the second discussion point on the list). F. Jensen showed the figures illustrated overleaf and used these as a basis for discussing the two points. No firm con­sensus was reached, but nearly all participants in the discussion expressed serious doubts about the validity of the MIL-HDBK type predictions. As W. Camp said: "It's a game people play."

R. Goarin suggested that if you use stress screening to reject batches of components that show a poor reliability, then in principle, you will be getting lower failure rates overall. However, this is not the stated intention of stress screening. He also pointed out that problems, i.e. flaws, may actually be introduced in the components by stress screening (for example, by ESD or EOS). This potential danger was also illustrated by J. M¢ltoft, who related a number of case studies to this effect.

Subjects addressed by the panel:

1. Can component hazard rate (constant A in FITs) be reduced by RS S?

2. Statement: When freak failures are eliminated, the remaining devices are failure-free until wearout sets in.

3. Activation energies for freak failure mechanisms are frequently quoted in the EA =0.3-0.5 eV range (silicon ICs). Can we assume that EA values are constant down to say 25-125°C?

4. Is stress screening harmful, i.e. does it take away lifetime from the "good" compo­nents?

5. How do you choose a suitable screening environment? How about 12SOC/168h?

6. How much can you safely accelerate the stress condition? Temperature? Voltage?

7. Can stress screening be elirninated?

8. How about (non-stressful) reliability indicators?

9. Is stress screening applicable to all component technologies? all manufacturers?

10. Which defect types will the analyst screen and investigate?

569

A. Christou and B. A. Unger (eds.), Semiconductor Device Reliability, 569. © 1990 Kluwer Academic Publishers.

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APPENDIX B. LIFETIME EXTRAPOLATION AND STANDARDIZATION OF TESTS

A. Christou (Leader), J. M!1Iitoft, P.D.T. O'Connor, W.T. Anderson andP. Mauri

The discussion centered around the predictions which may be established from MIL­HDBK-217 which do not correspond to actual observations. The summary of the criticisms are:

a. IIQ - factors are incorrect

b. The physical models in the handbook are wrong.

c. The figures in the handbook have been arrived at from high temperature accelerated tests using the Arrhenius equation.

d. A constant failure rate is assumed while non-constant failure rates are observed.

Additional discussions centered around the accel<erated testing which is performed to iden­tify wearout failure mechanisms that mayor may not occur within the useful life of a device. In most cases it has been demonstrated that the wearout mechanism does not constitute a problem.

Professor M!1Iltoft gave the example of results reported as MTTF, median life or MTBF and being misinterpreted. The example is as follows:

From an accelerated test report the MlL-217 analyst gets:

r, T, EA and the test temperature 92

EA ( 1 1 ) This gives by using A = f and AI = Aze k a,:-~

Al = 225 FIT

at the actual operating temperature 91.

Prediction for 20 years of operation will yield

F(20 ) -1 -Alt_1 -225.10-9 .175200 years - - e - - e

=3.9%

However, the test was about a wearout phenomena characterized at the operating tempera­ture by the Weibull parameters

'1lt=5.106hoursand~=3 ('1h=T)Ze-~A(~-~)) 571

A_ Christou and B. A. Unger (eds.), Semiconductor Device Reliability. 571-572. © 1990 Kluwer Academic Publishers_ Printed in the Netherlands.

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Correct prediction would be

( t )p ( 175200):

F(20 years) = 1 - e ~ = 1 - e -~

=0.0043% !!

The discussion centered on rewriting of MIL-HDBK-217 using a more meaningful approach. The techniques for doing this were discussed and may be proposed in the near future.

Standardization was also discussed with the observation that standardization is carried out after a technology is mature and frozen. At that point, standardization is probably not necessary. Furthermore, standardization and excessive qualification in optoelectronics may impede progress.

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accelerated life tests 455 accelerated testing 147 acceleration factor 1 aging test 413 AlGa As 557 AlGa As/GaAs MODFETs 557 annealing 269, 291 Arrhenius relationship 75 avalanche photodiode 301

backgating-reliability 439 burn-in 43, 97, 413

carrier lifetime 343 charge pumping 507 CMOS ASICs 137 communications systems 147 component position 107 components 43, 147 compound semiconductor

device reliability 423 computer system 127 confinement 545 coupling 43 coupling loss 329 cumulative distribution function 107 cumulative hazard function 107

data and knowledge base 127 degradation 211, 269,301,343,507,517 degradation mechanisms 353 degradation models lO7 device characterization 211 device degradation 269, 507 device fabrication 177 device reliability 29,107,177,507 devices lO7 DFB laser 301, 343 digital ICs 423 diodes 517 distributed feedback 343 distributed feedback laser 301, 321 dose rate effects 517 DX center 557 ·1ynamic transconductance 507

electron wind 197

INDEX

573

electrostatic discharge 379 EMOS system 43

failure analysis 1, 127, 161,211,353 failure intensity 107 failure mechanisms 211, 413 failure mode 413 failure rate 75 failure rate function 107 failure simulation 137 FET439 fiber break 363 fiber movement 363 fiber to the home 75 fibre optic 147 freaks 97 front-to-rear tracking 75 FITH75

GaAs471 GaAs devices 197,423, 517 GaAs FETs 423, 479 GaAsICs269 GaAs MESFET transistors 177 GaAs MESFETs 29, 211,455 gate metallization systems 177 grating 343

hazard rate function 107 HBTs423 HEMTs 211,423,439 heterojunction FETs 491 heterostructures FETs 557 high-speed 545 hot carriers 507 hot electrons 507 hot holes 507 hydrogen 471

IC reliability 491 InGaAs avalanche photodiode 413 injected carrier 343 InP optical switch array 329 integrated circuits 471, 491,517 interdiffusion 545 ion implantation 291 ion implanted devices 29

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IR thermography 479

jacket shrink 363

ladder networks 147 lambda/f phase-shift 343 lasers 43,301 laser annealing 369 laser diodes 43 laser module 363 laser module design 75 laser reliability 75 laser-fiber coupling 75 LED 1,301 life testing 75, 161,455 light emitting diode 301 low cost module 75

matrix method 147 MBE439 mean life 353 mean or average value 107 mean time to failure 107 MESFETs 269, 479 MESFET reliability 29 MESFET transistors 177 metal transport 197 microwave 471 MMICs 269, 423, 471 Modeling 479 models 147 MOVPE301 MTBF 107 MTTF 107

nuclear methods 291

operating environment 75 optical connector 363 optical switch 43 optical switch module 329 optoelectronic devices 43 optoelectronic devices reliability 353 optoelectronic receiver 43 optoelectronics 1, 161

packaging 329 parametric degradation 147 parasitic effects 439 pdf 107

perturbed angular correlation 291 phase-shift 343 photodetectors 43 photodiodes 43 PIN photodiode 301 pistoning 363 precise alignment 329 probability density function 107 pseudomorphic MEDFET 557

qualification 75, 363

radiation stress testing 517 random failure 43,321 rate equations 379 redundancy 147 refractory metal systems 177 reliability 1,29,43,107,161,177,211,301,321, 329,363,413,455,471,479,491,507,517,545 reliability assessment 127 reliability methodology 137 reliability predictions 75, 147, 161 renewal theory 107 ring oscillators 545

screening 75 secure attachment 329 security 147 semiconductor components 97 semiconductor devices 321 semiconductor doping 291 semiconductor lasers 301, 379 SIMOX 507 simulation 479 single-mode fiber 329 socket 107 socket reliability 107 SOl 507 spectral stability 343 SPICE 137 stability 343 standard deviation 107 standby line redundancy 147 statistical analysis 127 statistical models 107 stress testing 29, 517 superimposed renewal processes 107 surges 321 systems 147

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TEC75 temperature cycling 75, 363 temperature measurement techniques 479 thermal expansion mismatch 363 thermal resistance 479 thermoelectric cooler 75, 363 tracking error 75 transistors 545 transmitter package 43

two-dimensional electron gas 545

uncontrolled environment 75 undersea 147 uniform grating 343

wear-out failure 321

yield and failure analysis 137

575