Semiconductor Device Modelling

Department of Electrical and Electronic Engineering Imperial College London

EE 2.3: Semiconductor Modelling in SPICE Course homepage: http://www.imperial.ac.uk/people/paul.mitcheson/teaching

Paul D. Mitcheson [email protected] Room 1111, EEE

EE2.3 Semiconductor Modelling in SPICE / PDM v1.4 1

1. Aims and Objectives 1.1. Course Aims To show how SPICE solves circuit problems To explain the three main SPICE semiconductor models 1.2. Learning Objectives

By the end of these lectures you should be able to: Understand the internal operation of 3 types of simulation in SPICE Know what the SPICE model parameters mean and how they relate to physical quantities Appreciate the issue of simulation convergence and how the semiconductor models used try

to improve convergence Be able to use your own custom semiconductor models in SPICE (see study group sheet)

2. Syllabus SPICE internals and algorithms SPICE semiconductor models

o Diode o BJT o MOSFET

3. Problem Sheet An exercise done in SPICE in the labs which gets you used to the SPICE model parameters, and shows you some of the dynamic effects of devices that you have seen the theory for in the first part of the course.

4. Recommended Reading This part of the devices course is relatively self contained. If, however, you want to know more about SPICE, the following are good books:

Semiconductor Device Modelling with SPICE, Giuseppe Massobrio and Paolo Antognetti, McGraw-Hill Inc.

Inside SPICE, overcoming the obstacles of circuit simulation, Ron Kielkowski, McGraw-Hill Inc.

SPICE for circuits and electronics using PSpice, Muhammad H. Rashid, Prentice Hall


5. Introduction You received an introduction to SPICE in the first year design project. Briefly, to remind you of the history and development of the software: SPICE (Simulation Program with Integrated Circuit Emphasis) is a well-known circuit simulator computer program which began with a mainframe program written at UC Berkeley by Lawrence Nagel (and others) during his PhD. The SPICE solver or engine (the core part of the program i.e. the part that solves the circuit equations) is free software but it is command line driven and is thus regarded as difficult to use. Consequently, several commercial versions (mostly based on the 2G7 release of the Berkeley program [PSpice is based on 2G7]) are available which provide a graphical interface and up to date component libraries (models of commercially available semiconductor components provided by the semiconductor manufacturers). In this part of the course we will look briefly at the internal workings of SPICE, the semiconductor models that are used and how they relate to the device theory you have already studied.

6. How SPICE solves circuit bias points a first stage of the simulation process

Why do we care how SPICE works internally? Because when things go wrong with a simulation, having some insight into the operation of the program helps you figure out how to make your simulation run and also allows you to use the program in a more efficient way. We will look in detail at how SPICE solves DC bias point simulations and then look briefly at some other types of simulation. We do it this way because the DC type calculations are fundamental to the operation of the other types of simulation and (with the exception of transient simulations) it is easy to extend the DC analysis that SPICE does to the other types of analysis.

6.1. Overview for a simple resistive circuit SPICE firstly forms a set of nodal equations for a circuit is it trying to solve. These are formed from the netlist. Lets see with an example. Consider the following basic circuit:

I1 n0 n1 3 R1 n1 n2 5 R2 n0 n2 10 R3 n2 n3 5 R4 n0 n3 10

Figure 1 Simple circuit with current source excitaiton

Firstly, SPICE forms a set of nodal equations based on KCL:

05

3 21 =+ VV


05105

32212 =++ VVVVV

0105

323 =+ VVV Which are rearranged and written in matrix form:

=

003

3.02.002.05.02.0

02.02.0

3

2

1

VVV

Then, Gaussian elimination is used to form an upper triangular matrix which is solved using back substitution (first solve for V3, then V2, then V1).

=

333

25.0002.03.00

02.02.0

3

2

1

VVV

You can see that this matrix is very easy to solve on computer, no matter how big it is. In essence, SPICE always tries to solve for nodal voltages which satisfy KCL by forming an equation of the form: [ ] [ ] [ ]IVG = Note that the current matrix is known. For many equations, the entry in the current matrix will be zero as KCL requires currents into a node sum to zero), but it will be non-zero if an active device, such as a current source, is present. In other words, the I matrix lists the current being actively injected into each node. Changing the current source for a voltage source makes it harder to solve(!) because it does not fit into our nice simple framework quite so easily. You might initially think that we could reformulate the expressions in the form of: [ ] [ ] [ ]VIR = And then do Gaussian elimination to solve for the current matrix Consider the circuit below and the equivalent nodal equations

Figure 2 Simple circuit with voltage excitation

05

211 =+ VVI

05105

32212 =++ VVVVV

0105

323 =+ VVV


Unfortunately we cannot form the matrix equations the voltages at the nodes (other than n1) are not known we do not know the [V] matrix in its entirety and thus cannot perform Gaussian elimination. Therefore, we would like to analyse circuits with current sources instead of voltage sources because the [I] matrix is always known, and we can therefore solve the circuit using Gaussian elimination. This is a special property about current excited circuits. Remarkable but true! So how do we cope with a voltage source in the circuit? After all, power supplies and batteries are voltage sources, not current sources!

Use a Norton Equivalent circuit. Although it is not always clear how to do this as we will now see. It is clear that in the case of Figure 2, the voltage source and current source could easily be converted into a Norton equivalent source. But how can you do it with the circuit branches as shown below?

Figure 3 Tricky to convert to a Norton source?

Figure 4 Not really!

6.2. Automatic Construction of the Matrix Equations The above is all very well, but how do we construct the matrices from the netlist? We did it in the example above by:

Taking the netlist Drawing the circuit Using KCL to write the nodal equations Writing those equations in a matrix form [ ] [ ] [ ]IVG =

That algorithm is quite hard to program into a computer! There must be a better way. and indeed there is!


Its called matrix construction by inspection and lets us go directly from the netlist to the matrix equation. This construction is done by using predefined element matrix templates which can be added together automatically as we step through the netlist if the templates are designed properly. Each template consists of a conductance matrix of N by N, where N is the number of terminals on the device and an Nx1 voltage array and an Nx1 current array, in the usual form of [ ] [ ] [ ]IVG = . This means that the template conductance matrix for a resistor is 2x2, a BJT is 3x3 and a MOSFET (with separate body contact) is represented by a 4x4 conductance matrix. Lets take the example of a resistor:

=

RR

RR

GGGG

Node 0 col

And the example for a current source:

=

II

Lets see how SPICE constructs the equations for our earlier circuit of Figure 1:

I1 n0 n1 3 R1 n1 n2 5 R2 n0 n2 10 R3 n2 n3 5 R4 n0 n3 10

Conductance Array

Voltage Array

Current Array

Node 1 col

Node 0 row Node 1 row

Node 0 col

Node 1 col

Voltage Array

Current Array

Conductance Array

Node 0 row Node 1 row


From the first line of the netlist, we have the current source definition:

=

33

1

0

VV

On reading the second line of the netlist we add the definition of R1:

=

033

2.02.02.02.0

2

1

0

VVV

Then on the third line we add R2:

=

033

3.02.01.02.02.01.01.0

2

1

0

VVV

On the fourth line add the R3 template:

=

0033

2.02.02.05.02.01.0

2.02.01.01.0

3

2

1

0

VVVV

And finally add the last line and the R4 template:

=

0033

3.02.01.02.05.02.01.0

2.02.01.01.02.0

3

2

1

0

VVVV

n0 n0 n1

n1

n2 n1 n0 n0 n1 n2

n2 n1 n0 n0 n1 n2

n1 n2 n3 n0 n0 n1 n2 n3

n1 n2 n3 n0 n0 n1 n2 n3


As we define V0 as ground, our final matrix equation to solve is:

=

00330

3.02.001.02.05.02.01.0

02.02.001.01.002.0

3

2

1

VVV

Note that we can add the matrices because as we add components into the circuit, any additional branch conductances appear in parallel with the existing elements and conductances in parallel add up. Another nice reason to use the [ ] [ ] [ ]IVG = instead of the [ ] [ ] [ ]VIR = form! But this equation by inspection is different from the one we derived using nodal analysis. Is it valid?

Use a Of course! Remove the first row and column (which you can do as the voltage was zero) and you have the same matrix as we started with. Now we know how SPICE solves any resistive circuit bias point with both voltage and current sources. What about simulations with capacitors and inductors? How are inductors and capacitors solved in a DC bias point simulation?

Simple - Capacitors are set open circuit and inductors to short circuit. So, what about solving for non-linear elements, like a diode, or BJT?

6.3. Solving circuits with non-linear elements Lets look at a simple circuit with a diode present. What happens to the matrix equation that SPICE has to work with? Non-linear elements, such as diodes, cannot be solved using the simple Gaussian elimination technique alone because we run into a problem. Consider the following circuit with just 1 unknown nodal voltage:

0exp2

5 11 =++tv

VIsV


This single nodal KCL equation is a transcendental (meaning it is an equation involving terms other than simple polynomials which generally cannot be rearranged so that the variable becomes the subject of the equation) and thus the equation can only be solved numerically. If we tried to form this into our G*V=I form and solve the normal way we would get:

[ ][ ]

=

ts V

VIV 11 exp55.0

We do not need to make any Gaussian elimination operations to solve this because there is only 1 node But it is still not clear how to solve it because it is transcendental. We can solve it using the Newton-Raphson algorithm, with which you should be familiar. Lets remind ourselves how this works. The Newton-Raphson algorithm is as follows:

)(')(

1n

nnn VF

VFVV =+ Where Vn+1 is the voltage at the next iteration and Vn is the voltage at the current iteration. This does not mean the voltage at node n or node n+1.

For the simple circuit above, 111 5.0exp5)( VVVIVF

ts

=

Therefore we have:

5.0exp

5.0exp5

11

11

11 1

=+t

s

ts

VV

VI

VVV

IVV

n

n

n

n

nn

Which is easy to solve on computer using a simple loop.

6.4. Bringing it all together So, in slightly a larger circuit, lets see what happens: Firstly, all voltage sources are replaced with current sources to give a circuit that looks something like the example below:

Figure 5 Solve using Gaussian Elimination and Newton-Raphson


The equations are: At node 1:

05

3 12 =+ VV At node 2:

0exp105

2212 =

++

ts V

VIVVV

Which can be formed into the following matrix equations (of course done in SPICE by inspection):

=

ts V

VIVV

2exp

3

21

3.02.02.02.0

To solve these matrix equations, SPICE first uses Gaussian elimination to form the following matrices:

=

3exp

3

21

1.002.02.0

2

ts V

VIVV

Then, Newton-Raphson will be used to solve the transcendental equation for V2, before back substitution is used to find V1. Now we have some idea of how SPICE can solve circuits of any combination of linear and non-linear elements with both voltage and current source excitation. You now know the basics of how SPICE solves operating point (static DC analysis) problems with R, L, C and non-linear elements. The topic of Newton-Raphson brings us nicely onto the next topic

7. Simulation Convergence and Convergence Aids Anyone who has used SPICE in simulating anything other than very basic circuits will probably be familiar with those times during which the simulator does not converge. If you have not seen a non-convergence of a simulation yet, dont worry, you will at some point! You may well have already encountered convergence problems in the first year design project. When SPICE fails to converge, the program stops with an error message about the voltages and currents that failed to converge.


Given the high frequency at which you can encounter convergence issues when simulating circuits in SPICE, it may surprise you to know that SPICE was designed with the convergence issue in mind as it is a known problem with iterative solution methods (i.e. Newton-Raphson) used in the internals of the program.

7.1. Basic Convergence Parameters The iterative Newton-Raphson algorithm, if converging, produces more and more accurate estimates of a solution with each iteration. There is a trade-off here with the time taken to find a result and the accuracy of the result. In order to control this accuracy/time trade off, there are limits that must be set by the SPICE user for the accuracy of the simulations (or, as you have done up to now, you can simply accept the default values). The important parameters are: RELTOL Fractional tolerance of voltages and currents VNTOL Node voltage tolerance ABSTOL Current branch tolerance ITL1 The number of iterations allowed for a bias point calculation So far, VNTOL and RELTOL will make sense to you. We have seen SPICE always solves equations for the nodal voltages. RELTOL is the relative voltage (and current) tolerance for the node voltages, i.e. if the voltage at each node in the simulation changes by less than RELTOL percent of the absolute value from one iteration to the next, then the node voltages are said to have converged to the answer. This is fine unless the node voltages are very small. As the node voltages reduce, then RELTOL requires SPICE to converge to smaller and smaller absolute numbers. This is where VNTOL comes in. VNTOL is the absolute nodal voltage tolerance. If the node voltages change by less than VNTOL from iteration to iteration, the simulation is also said to have converged. Thus, once the node voltages converge to within the limits of one of these parameters (whichever has the larger tolerance), the simulation might be in a position to stop. SPICE 1 used only these two parameters to control the algorithm accuracy. However, non-linear devices (semiconductor devices!) can have very large changes in currents with only small changes in voltage. This means that even if the nodal voltages are converged to within tolerance, Kirchhoffs current law may not have converged (i.e. the sum of currents into a junction may not be close to zero). Thus, SPICE 2 (on which all modern SPICE based simulators are based) introduced some basic parameters for tolerances on currents. RELTOL was expanded to cover maximum fractional changes in branch currents between iterations (as well as nodal voltages) and ABSTOL was introduces. ABSTOL, which is absolute branch current tolerance, is the maximum allowed absolute change in branch currents from one iteration to the next. There is also a limit on the total number of allowed iterations. This is controlled by the ITL1 parameter. Thus, the flow of the program is thus:

1. If number of iterations > ITL1, break 2. Do Newton-Raphson iteration to solve for nodal voltages 3. Check the solutions against VNTOL and RELTOL 4. If solution not converged within parameters, goto 2, else goto 5. 5. Check branch currents (known from the nodal voltages) against ABSTOL and RELTOL 6. If not converged, goto 1 else finish


7.2. Convergence Problems An example Again, we are going to concentrate on the convergence problems for simple DC bias point simulations (although this type of convergence problem could very well also appear in a transient simulation). Lets consider SPICE trying to solve the following simple circuit with a Newton-Raphson algorithm and see where we might run into trouble. Well do Newton-Raphson graphically to see how the problems might arise.

Newton-Raphson tries to find the intersection of the diode characteristic with the load line. Make sure you understand how the load line is drawn you are probably used to drawing them for voltage excited series circuits but this is a current excited parallel circuit. We first pick a starting point for the iterations. Lets choose somewhere around 1 V to start with. Graphically, the Newton-Raphson algorithm does the following:

Take a tangent to the diode curve at the starting point (this tangent is of course a small signal linearised model of the diode!) and see where that crosses the load line

This voltage is the starting point for the next iteration Repeat

You can see how this iterates towards the solution in the diagrams below.

Figure 6 Initial guess

Figure 7 First iteration

Figure 8 Second iteration


Imagine that the first guess had been at a lower voltage. Then the tangent at the second guess would be almost vertical and the algorithm can get stuck.

V11 V12,V13

We can see that we are always going to have a problem with the Newton-Raphson algorithm whenever we have a very high value of conductance on an element (in this case the diode) because the time taken for convergence of the algorithm may be large, or if the gradient is steep enough, the algorithm may not converge at all, with the next iteration voltage being the same as the last, and potentially no where near the actual solution There will also be a problem if the algorithm ends up in the part of the curve where the conductance of the diode is too small i.e. the slope of the graph is too shallow. We can see this because in the Newton-Raphson algorithm we will approach a divide by zero error as the derivative of the curve approaches zero. Graphically it means that the next guess at a node voltage will be very far from the actual answer- and back on a step part of the curve where we have long convergence times.

7.3. The GMIN Convergence Parameter This brings us to another more advanced convergence parameter you might find useful when using SPICE. This is a parameter called GMIN and is designed to stop divide by zero errors when simulating the exponentials of pn junctions, and to reduce the problem that an iteration may take the next voltage iteration far from the final solution. GMIN is a pure conductance and one is placed in parallel with every pn junction implemented in SPICE.

Figure 9 pn junction with GMIN convergence parameter

This means that the slope of the exponential of the diode in reverse bias is at least equal to GMIN.


In addition, GMIN is the minimum conductance allowed between any two neighbouring nodes in SPICE. If you set a resistance between two nodes with a conductance of less than GMIN, the simulator will not run. Note that there may be certain circumstances where you have to reduce GMIN the default value in SPICE is 1e-12. If the impedance of some components in your circuit are of this order of magnitude, although GMIN will aid convergence, it will potentially ruin the accuracy of your simulations. Think before you simulate! Essentially, if you have both a parallel GMIN with a pn junction, and a series resistance, simulating the resistance of the wires, the overall slope conductance is always kept within manageable levels so that the next iteration will neither be too far away from the previous guess (and possibly wildly inaccurate), or too close (long iteration times).

7.4. Setting the convergence parameters Novice SPICE users would not necessarily think to change the default settings of the convergence parameters. However, it is often worth thinking whether the defaults make sense for the simulation you are doing. For low voltage low power work, they are almost always a good starting point (this is what SPICE was designed for). The default value of VNTOL is 1 V. Do we really care about resolving voltages to 1 V when simulating a 100 V power supply? Probably not. So how do we set these convergence parameters? In PSpice Capture, go to Pspice|Edit Simulation Profile|Options tab

Figure 10 PSpice simulation options dialogue

We have looked in some detail at the operation of the DC bias point analysis. We will look briefly now at the other types of simulation that SPICE can do.

7.1. DC sweep simulations The DC sweep simulation is an extension to the bias point simulation. In a DC sweep, the steady state solutions to a circuit are simulated for a range of DC voltages of a chosen voltage source in the circuit (which could be a power supply or an input to an amplifier etc). For the first voltage value to be simulated, SPICE solves the matrix equations in the normal way, doing iteration if non-linear elements are present. The outcome of this simulation is then used as the starting points for the nodal voltages for the first value in the DC sweep (if iterations were requires and thus a starting guess is required for the next DC step). The outcome of that simulation is then used for the starting point for the nodal voltages in the next value of the DC sweep etc. Problems can arise in convergence when a voltage changes particularly quickly.


The DC sweep has a further convergence parameter associated with it ITL2. This is the number of iterations that can be done at each step in the DC sweep, i.e. it provides the same function as ITL1 in the DC bias analysis.

7.1. AC Simulations So far, we have seen SPICE effectively solve linear and non-linear elements in DC simulations. Performing an AC simulation is not so different from a DC simulation. However, the AC SPICE simulation does not solve for non-linear elements it does not have to perform Newton-Raphson. When you do an AC simulation in SPICE to get a bode plot of a circuits frequency response, the simulator makes linearised small-signal models of any non-linear devices. These are essentially the same models as you have seen in your analogue electronics courses and consist of (controlled) current and voltage sources and R, L and C. The component values are all constant during the simulation (which is necessary for the model to be linear of course) SPICE solves the nodal equations in almost exactly the same way as it would for a DC simulation only now the program cannot set inductances to short circuits and capacitors to open circuit. They simply become complex impedances. Consequently, at each given frequency, SPICE solves the matrix equations of the form [G][I]=[V], where the matrices now become complex. One anomaly with the AC simulation therefore, is that if you simulate something like a closed loop opamp circuit with a gain of 100 and an AC input voltage of 10 V, the output will be shown as 1000 V (if we are below the G*BW product) even through the power supplies to the opamp might only be 15 V. This is the problem with a linear model. If you want to really see the exact behaviour of a circuit, accurate at all voltages, then the best way to do it is with.

7.2. Large signal Transient Simulations These are the most complex type of simulation because they show the complete semiconductor models realistically at all operating points the full non-linear models are used (as in a DC bias point simulation and therefore Newton-Raphson is heavily used), but in contrast to the DC bias point simulations, capacitors and inductors cannot be set to open and short circuit respectively. SPICE therefore makes heavy use of numerical integration in these simulations. The exact detail of these simulations is however beyond the scope of this course for the time we have. So, what models does SPICE use internally for its semiconductor devices and how do they relate to the understanding you already have of semiconductor devices? We will look at the three most common devices, the p-n diode, the BJT and the MOSFET. You have been shown small signal models of devices in other devices lectures and in your analogue courses. SPICE uses similar small signal device models when performing an AC analysis. In this part of the course, however, we will be looking at the large signal models used by SPICE in a transient (time domain) analysis and how they relate to the device physics you have already learnt.


8. Types of Model used in SPICE There are three types of semiconductor model used in SPICE. One is the DC static model, one is the small signal AC model and one is the large signal transient model. We will look here at the DC models and transient models. The small signal models are essentially the same as you have seen in your analogue courses. The DC models are effectively the transient models with capacitors open circuited and inductances shorted. We will thus look at the models by starting with the DC model and then build them into the transient models with the addition of capacitances to take into account the dynamic effects.

9. The SPICE Diode Model

9.1. DC Model You have already been shown the equations which describe the diode model, in both static and AC conditions. The simple DC equation you know is the well known Shockley equation, that is:

= 1exp

tsD V

VII

Where IS is the diodes reverse saturation current, V is the applied voltage bias, Vt is the thermal voltage (equal to kT/q which is about 25mV at room temperature) and ID is the current through the device. The simple DC model used in SPICE is very similar to the Shockley equation, with the addition of a parameter n, and a convergence aid of a the GMIN parallel conductance (see Figure 11). The basic static diode model equation is thus:

GMINVnVVII D

tsD +

= 1exp

= 1exp

tsD nV

VII

Figure 11 The SPICE diode model has a parallel conductance to aid convergence

The parameter n is an ideality factor for the diode, known as the emission coefficient. It has a SPICE parameter called N (all SPICE parameters are given in capitals). So far we have assumed n


to be 1, and indeed, in a good diode it will almost be 1. This parameter will rise above 1 if there is significant recombination of carriers in the depletion layer. Therefore, n tends to be closer to 1 under high forward bias and more than 1 under small bias voltages because the depletion layer gets thinner as the forward bias is increased. The other SPICE parameter from this basic equation is IS. In order to allow faster simulations than this equation would provide, a simple approximation is made in moderate reverse bias. When VD

Figure 12 SPICE model DC diode characteristic split into 3 regions

Finally, a series resistance is added to the diode model to simulate the resistances of the connecting wires and the ohmic contact resistances, giving us the following simple static model:

Figure 13 Static DC diode model

And so, RSIVV DDD +=' In summary, the important SPICE parameters (given in capitals and corresponding to the physical parameters in italics) for setting the DC characteristic are:

IS (Is) RS (Rs) N (n) BV IBV

The reverse saturation current The Ohmic resistance of the contacts and bond wires The emission (or ideality) coefficient The breakdown voltage (inputted to SPICE as a positive number) The current at reverse breakdown (inputted to SPICE as a positive number)

With these parameters you can specify the complete static diode characteristic.


9.1.1. Limitation of the Diode Model The SPICE diode model does not include the effects of high level injection. When deriving the Shockley equation you previously made the assumption (although you probably did not realise it) that the number of minority carriers was much less than the number of majority carriers (this is low level injection). In power semiconductors, this is not necessarily the case because they operate in what is known as high level injection. The SPICE model does not include this effect (because it was originally designed to be used with low power signal devices). I do not expect you to understand how the physics changes in the device with low and high level injection I just want you to be aware of this limitation. If you take the power electronics course in 3rd year you will look briefly at these effects.

9.2. Large Signal Transient Model We now need to add dynamic effects to the diode model. This is fundamentally done by adding in capacitances to the model, as shown in Figure 14.

GMIN

RS

VD

VD C

Figure 14 SPICE Large signal transient model

We know the equations used for the current source (the Shockley equation with the addition of the non-ideality factor) and we understand the physical meaning of the series resistance RS and the reason for the GMIN resistor (that of Newton-Raphson algorithm convergence) . The question we now face is What equation does SPICE use to calculate the parallel capacitance and how does it relate to the physics? You know that there are two contributions to capacitance between the terminals of a diode. These are the diffusion capacitance and the depletion (or junction) capacitance. The depletion (junction) capacitance, dominant in reverse bias, is given by the following equation, which you have seen the derivation of earlier in the course:

))((2 0 VVNNNeNACDA

DAj +=

SPICE implements essentially the same equation, written slightly differently:


00

1

1)(2

VVNN

VNeNACDA

DAj

+=

Which can be written as:

0

1

)0(

VV

CC jj

=

This is the equation SPICE uses to calculate the depletion capacitance, where Cj(o) is the junction capacitance at zero applied bias. The diffusion capacitance, Cd, is dominant in forward bias. This is the capacitance associated with the stored minority carriers injected into the neutral regions. You have seen an equation for the diffusion capacitance written as:

IkTeCd =

SPICE uses the same equation, but adds in the diode ideality coefficient:

InkT

eCd = Consequently you can see the additional parameters (over and above the DC parameters) needed to specify the dynamic behaviour of a diode in SPICE:

CJ0 (Cj(0)) TT () VJ (V0)

Zero bias junction capacitance The transit time Built in junction voltage

You now know the most important parameters to allow you to specify a custom diode model in SPICE. There are a few more parameters which exist that we are not going to look at as we have covered the important ones.

9.3. A Note on the SPICE Area Parameter A and Device Scaling

SPICE has an area parameter called A, which can be used to scale any pn junction. The parameters IS, CJ0, RS and IBV are all proportional to device area. You therefore have two choices when entering these parameters:

Enter them as parameters per unit cross sectional area and set the A parameter to the correct cross sectional area of the device

Enter them as the values for a specific device and set the Area value to 1. Then if you want to have multiple devices in parallel, setting A=3 means your device will behave as if there were three devices in parallel.


10. The SPICE BJT model 10.1. DC model

This section of the notes is based on an npn transistor. I have chosen to use this as I believe most of you are more at home with it at the circuit level than the pnp transistor and here we are on the boundary of device physics and circuits so being able to relate the device physics with circuits is important.

10.1.1. Ebers-Moll injection model The model of the BJT used in SPICE is based around a set of equations known as the Ebers-Moll equations. One of the reasons that SPICE uses these equations is because, as you will see, the Ebers-Moll model is based on current sources and diodes, which are models we now already have in SPICE. We simply use them to build a sub-circuit of a bipolar transistor without needing to introduce any new components or equations into SPICE.

There are actually 2 versions of the Ebers-Moll model, the injection model and the transport model. SPICE uses the transport model, however, we will start by looking at the injection model because it is easier to relate to the device physics. We will then modify it into the transport model so that we can relate the device physics to the SPICE parameters.

You are aware that a BJT is physically built as two back to back diodes, as shown below:

B

CE

B

E C

Figure 15 The npn transistor as two diodes IMPORTANT: it does not really behave like this but this description is important to understanding the SPICE model!

You also know it DOES NOT BEHAVE like two discrete back to back diodes connected together two back to back diodes would not allow conduction between emitter and collector because one of them would always be in the blocking state. Transistor action (the effect of being able to control the current through one p-n junction by altering the bias across another nearby junction) only occurs because the two p-n junctions are physically very close together and have shared energy levels, so that carriers emitted from the emitter can be collected by the collector without flowing out of the base contact. In short, these two p-n junctions are not discrete they interact.


The BJT in Active Mode Before we look specifically at the Ebers-Moll model we should refresh our memory of the carrier flows in an npn BJT. You have previously seen a diagram something like that shown in Figure 16.

n+ p n

Electron current

Hole current

e b c

Recombination in base

Normal injection at b-e

junction

Collection of electrons by

collector

Reverse leakage of

holes

Figure 16 Electron and hole current in an npn BJT in the forward active region

In the forward active region, the base emitter junction is forward biased. The heavily doped emitter injects many electrons into the base region. Some of these escape out of the base contact (which is normal p-n diode behaviour if we consider the base-emitter junction to be a diode), some recombine with holes in the p-type base and the rest make it to the collector. Electrons are collected by the collector because they are attracted by the electric field in the depletion region of the base-collector junction. (The part of the depletion layer in the collector has ionised donor atoms which are positively charged and thus attract the negatively charged electrons). The electron concentrations along the length of the device are look as below:

n+ p n

npe

npc

e b c Figure 17 Electron carrier concentration in forward active region of operation


The collector current is proportional to the minority carrier concentration gradient in the base. In active mode, npc is approximately zero because the collector-base junction is reverse biased. Hence, the emitter current is controlled completely by the base emitter voltage (when the device is operating in the active mode) as this alters the concentration gradient by altering npe. We can think of the BJT operating in this way as the following large signal equivalent circuit.

Figure 18 Equivalent circuit of npn BJT operating in active mode: derived from device physics Where:

INbe electron current through the base emitter junction IPbe hole current through the base emitter junction IF the total current through the base-emitter junction (INbe + IPbe) BF fraction of electrons injected by the emitter which are collected by the collector

You should be able to see that this is an equivalent circuit of the device physics. There is:

Current through the base-emitter junction, which is made of electron and hole current (mainly electron current in this npn device)

A proportion (BF) of the electrons emitted from the emitter are collected by the collector We neglect any contribution that flow of holes from the reverse biased collector-base

junction have to collector current You can thus see that the base current makes up (1-BF) part of the collector current, plus the

contribution of holes to the base emitter current (IPbe). Using the normal definition of the forward current transfer ratio, F,

e

cF I

I=

We know we can simplify the diagram:

Figure 19 Transistor equivalent circuit - forward active region


And thus:

NbeFFF IBI = Which we need to remember for construction of the final model, in a few moments.

The BJT in saturation Now lets look at what happens to the device saturation. In saturation, both junctions are forward biased. If we look at the concentration of electrons in the device, we have:

Figure 20 BJT electron concentration in saturation

If we now look at a diagram of the carrier flows again, we have:

Figure 21 BJT carrier flows in saturation both junctions are forward biased

The main points to note here are:

The injected electron current from the emitter is significantly less than in the active mode because the concentration gradient of electrons in the base is reduced because npc has increased.

Both junctions are forward biased, meaning there is significantly increased base current due to forward hole injection across the base-collector junction.


Lets look at the electron current for a moment. We can think of this as being made of a forward and a reverse flow of electrons, due to the principle of linear superposition:

Figure 22 Carrier concentration in saturation region in base split into two components

The line marked 1 on the diagram shows the net concentration gradient of electrons in the

base and hence electron current is proportional to this gradient Line 2 shows the electron concentration gradient that would be achieved if the emitter-base

junction was isolated from the collector with the given base-emitter voltage Line 3 shows the electron concentration gradient that would be achieved if the collector-

base junction was isolated from the emitter with the given collector-base voltage The total current, It, is proportional to the net gradient, i.e.:

b

pcpet L

nnKI

''= Where K is just a constant of proportionality and Lb is the length of the base The forward current is:

b

pef L

nKI

'= The reverse current is:

b

pcr L

nKI

'=

Thus b

pcperft L

nnKIII

''== Which we can see is the net current from the concentration gradient. We can therefore think of the electron current as being the sum of the current injected from the emitter and that current injected from the collector, as shown in Figure 23, if the carrier concentration at the collector and emitter respectively, are zero.


n+ p n

Electron current

Hole current

e b c

Recombination in base

Normal injection at b-e

junction Collection of electrons by

collector

Collection of electrons by

emitter

Normal injection at b-c

junction

Figure 23 BJT operation in saturation mode - thinking of the electron current as two separate currents - one

injected from the emitter and one from the collector This shows us we can think of the transistor, in the saturation region, as two back to back diodes, where a proportion of the injected emitter (collector) current makes it to the collector (emitter). The part that doesnt make it all the way across the base region is either involved in recombination or flows out of the base. The base current supplies the recombination current and, in the case of the npn transistor, supplies two small hole currents to feed the two forward biased junctions. The Ebers Moll model makes use of the fact that the two separate p-n junctions exist, but adds an additional two current sources to allow for the interaction between them, so that the transistor action can be described. Figure 18 and Figure 19 showed only part of this story the device operating in saturation. The Ebers-Moll model effectively models a forward and a reverse BJT, each operating in active mode, to produce a complete BJT model that can also work in the saturation region. From Figure 23, we should now be able to see the physical mechanisms that lead us to the complete Ebers-Moll model equivalent circuit shown below, for an n-p-n transistor:

Figure 24 Ebers-Moll model of BJT (injection version)


IF forward transistor current (through the base emitter junction) IR reverse transistor current (through the base collector junction) INbc electron current through the base collector junction IPbc hole current through the base collector junction INbe electron current through the base emitter junction IPbe hole current through the base emitter junction BF fraction of electrons injected by the emitter which are collected by the collector BR fraction of electrons injected by the collector which are collected by the emitter In summary:

The diodes in Figure 24 represent the two p-n junctions of the BJT and the currents

through them represent the current that would flow through them if each junction was discrete (i.e. if it was a simple diode) with the voltages VBE and VBC across them. They refer therefore to the current marked normal injection in Figure 23. Note that IF is mainly electron current because of the heavy doping of the emitter.

The current sources in Figure 24 represent the interaction between the junctions i.e. some (most in a good BJT!) of the electron current which is injected into the base from the emitter passes through the base into the collector. The current sources correspond to the carrier flows marked collection of electrons by collector/emitter in Figure 23.

We had already showed that:

NbeFFF IBI = And therefore we can also write:

NbcRRR IBI = This gives us the final well known Ebers-Moll injection model:

B

CE

IF IR

FIF

IE

IB

IC

RIR

Figure 25 Ebers-Moll BJT model - injection version


The currents flowing in these diodes are given by:

= 1exp

t

BEESF nV

VII

= 1exp

t

BCCSR nV

VII

And thus the currents in the BJT terminals are given by the Ebers-Moll equations:

== 1exp1exp

t

BCCS

t

BEESFRFFC nV

VInVVIIII

== 1exp1exp

t

BEES

t

BCCSRFRRE nV

VInVV

IIII

)1()1( RRFFCEB IIIII +== You can see from the above equations that four parameters are needed to specify the Ebers-Moll model. These are: IES, ICS, R and F. However, it can be shown that F IES= R ICS (See the original paper by Ebers and Moll Large-Signal behaviour of junction transistors), and this is written as the parameter you know already know for a BJT Is.

SCSRESF III == This makes sense the equation you know for the behaviour of the BJT in the active mode is:

= 1exp

t

besc V

VII

In active mode, we assume the current contribution from the reverse biased base-collector junction is minimal and so:

=

== 1exp1exp

t

beS

t

beESFFFc V

VIVVIII


When you think about it, the emitter current is just the diode equation for the base-emitter junction. The collector current is just a proportion, F of this. Hence Is for the BJT is just the ISE (saturation current of the base-emitter junction) multiplied by the proportion of this current that is collected at the collector. Apart from the fact that SPICE can use the existing diode models and existing current source models to make a BJT with the Ebers-Moll model, what is so great about the Ebers-Moll model for computer simulation?

It works under all operating conditions active, saturation etc. SPICE does not need to implement different equations for different regions of operation.

10.1.2. Ebers-Moll Transport Model used in SPICE So far we have looked at the Ebers-Moll injection model and we said SPICE actually uses the transport model. To make things slightly more complex, SPICE does not use the standard Ebers-Moll transport model, but actually a modified transport model. We will look at the modified model (we need it to see how the SPICE parameters relate to the physics) but we will look at the standard transport model as a way through to understanding the modified model.

Figure 26 Ebers-Moll model - transport version

In this model, the equations for the currents in the current sources are given by:

= 1exp

t

BESCC nV

VII

= 1exp

t

BCSEC nV

VII

Where Is is the saturation current of each diode (IES and ICS) multiplied by the gain, F and R, as we defined before. All we have done here is introduced a change in notation the transport model is exactly the same as the injection model in terms of meaning and operation but is less easy to relate to the device physics. Unfortunately this is still not the final BJT model used by SPICE. There is one modification left to make before we can see the final model and how the parameters relate to the physics.


SPICE uses a model with only a single current source, as shown below:

Figure 27 Modified Ebers-Moll transport model used in SPICE

Note that the definitions of the diode currents are now different. This is in order to keep the terminal currents the same as the previous (two current source) model. In this model:

F

FF

= 1

R

RR

= 1

ECCCCT III = You can prove that the terminal currents in the double and single current source models are identical hence the models give the same result they are just a little different internally. You can now see how the BJT parameters in SPICE are essentially two sets of diode parameters which we have seen previously, plus the factors BF (F) and BR (R), which accounts for the interaction between the junctions. So what are physical meanings of F and R?

F is the current gain (IC/IB) of the device when it is operating with the emitter as the emitter and the collector as the collector in the active mode R is the current gain of the device when it is operating with the emitter as a collector and the collector as an emitter in the reverse active mode


Note that as the device is made to have higher forward current gain (the terminals for emitter and collector are not completely interchangeable due to different dopings of the collector and emitter) than reverse current gain. Finally, SPICE includes the effects of the contact resistances, and the convergence aid conductance, GMIN, is also present. So, the final large signal DC SPICE BJT model is given by:

B

CE

ICC/ F

IE

IB

IC

ICT

IEC/ R

rb

rcre

GMIN GMIN

Figure 28 Large signal DC BJT model

IS (Is) RE (re) RB (rb) RC (rc) NF (n) NR (n) BF (F) BR (R)

The transistor saturation current The Ohmic resistance of the contact and bond wire at the emitter The Ohmic resistance of the contact and bond wire at the base The Ohmic resistance of the contact and bond wire at the collector The emission (or ideality) coefficient for the base-emitter junction The emission (or ideality) coefficient for the base-collector junction The forward current gain The reverse current gain

Note that the BJT diode equations do not model breakdown, hence there are no BV and IBV parameters for the BJT model.

10.2. Large Signal Transient Model The transient model is built from the DC model in the same way that the diode model was built. We can therefore see very quickly what the parameters are for this model and how they relate to the physics. There are two junction capacitances, and essentially there are the same parameters used to specify these capacitances as there was in the diode. The only difference is we now have two times as many parameters one of each for each of the two capacitors. The parameters are:

CJE CJC VJE VJC TF TR

Zero bias base-emitter junction capacitance Zero bias base-collector junction capacitance Base-emitter junction built in voltage Base-collector junction built in voltage Forward transit time Reverse transit time


The forward transit time TF is the transit time associated with the base-emitter junction and the reverse transit time TR is the transit time associated with the base-collector junction.

Figure 29 SPICE Large Signal Transient BJT Model There is also an area scaling parameter A for the BJT, which works in exactly the same way as for the diode.


11. The SPICE MOSFET Models

11.1. DC Model Whilst there is essentially only 1 diode model used in SPICE and 1 BJT model, to complicate matters there are several MOSFET models in common use. The reason for this is that MOSFETS are very much the device of choice in modern circuit design, be it analogue or digital and consequently models have been developed which have got more accurate with time, and which model new occurrences in the device physics when as the device manufacturing allows devices to be made smaller. It is interesting to note that nowadays MOSFET is a rather outdated name for the device. The gate is no longer made of metal, normally being made of poly Silicon. Thus, you may occasionally see the MOSFET referred to as an IGFET Insulated gate FET. The original set of SPICE MOSFET models are known as the level 1, level 2 and level 3 models. These are the models used in the simulator PSpice, with which you are familiar. There are some other, much more complex (although of course more accurate) used by more specialist analogue design tools such as the Cadence design suite. One of the most important models used in Cadence is the BSIM (Berkeley Short Channel IGFET model) model. However, this model is way beyond the scope of this course because it has over 100 parameters in the DC model alone! (But it is good you are now aware of its existence.) The basic SPICE level 1 static model (as proposed by Shichman and Hodges) is as follows:

Figure 30 MOSFET characteristic

You have seen the proof of the MOSFET equation in your 1st year lectures:

( )

=2

2

0DS

DSTHGSeff

oxDSVVVV

LWCI

When the channel becomes pinched off, IDS saturates and barely rises further. At pinch-off VDS=VGS-VTH and so the current in saturation is given by setting VDS=VGS-VTH in the equation above, to give:


( )2021

THGSeff

oxDSsat VVLWCI =

You are already familiar with an empirical correction to these equations to account for the channel length modulation:

( ) [ ]DSDSDSTHGSeff

oxDS VVVVV

LWCI +

= 1

2

2

0

And:

( ) [ ]DSTHGSeff

oxDSsat VVVLWCI += 1

21 2

0

These are the essentially the equations implemented by SPICE in the static model (proving that your devices knowledge is already at a good level its good enough for the industry standard simulator!), but there are some points worthy of noting. The actual specific equations used by SPICE for the static level 1 model are: In the linear region:

( ) [ ]DSDSDSTHGSjl

DS VVVVV

XLWKPI +

= 122

2

In the saturation region:

( ) [ ]DSTHGSjl

DSsat VVVXLWKPI += 122

2

Xjl is the lateral diffusion parameter, which is the amount of lateral creep there is present when the source and drain are diffused. It is assumed to be equal at each side and is illustrated below. You can see that this effectively reduces the channel length.

Figure 31 Meaning of parameter Xjl

It is important to note that the threshold voltage changes with changes in body-source voltage, VBS. SPICE uses the following equation for the threshold voltage:


( )pBSpTTH VVV 220 += Where VT0 is the threshold voltage when the body-source voltage is zero, is the body effect parameter and p is the surface inversion potential. Note that if the bulk is connected to the source (i.e. the MOSFET is acting as a 3 terminal device, the threshold voltage is always equal to the value VT0). When would the bulk not be connected to the source?

When we have stacked transistors in integrated circuits. If you connected bulk to source on each transistor in an integrated circuit you would end up shorting many points in the circuit to ground

Figure 32 Large signal MOSFET model used in SPICE

Note that the diode equations present in this MOSFET model are not as detailed as the standard SPICE diode model - they do not include breakdown for instance. They are in fact modelled by the following equations: For forward bias on the body-source/body-drain diodes:

BSt

BSSSBS VGMINV

VII +

= 1exp

BDt

BDSDBD VGMINV

VII +

= 1exp


For negative reverse bias on those diodes:

BSt

BSSSBS VGMINV

VII +=

BDt

BDSDBD VGMINV

VII += These reverse bias terms are simply the first terms in a power series expansion of the exponential term. Note that the GMIN convergence resistance is also present. ISS and ISD are taken to be one constant in SPICE, known as SPICE parameter IS. When modelling MOSFETS in SPICE, it can sometimes be better to cancel out the diode that is present in the SPICE MOSFET model by setting the parameter IS to zero, and putting in an additional SPICE diode model, depending on how much detail is required. This is especially important in power electronics where high voltages are common place. The important parameters that you therefore need for the MOSFET model are:

L W KP (KP) VT0 (VT0) GAMMA () PHI (p) RS (RS) RD (RD) LAMBDA () XJ (Xjl) IS (ISS, ISD)

Channel length Channel width The transconductance parameter Threshold voltage under zero bias conditions Body effect parameter Surface inversion potential Source contact resistance Drain contact resistance Channel length modulation parameter Lateral diffusion parameter Reverse saturation current of body-drain/source diodes


11.2. Large Signal Transient Model Again, we need to add some capacitances to the DC model to create the transient model to form the final transient model, as shown below:

RSD

B

S

G

RD

IDSGMIN GMIN

CBS CBD

CGDCGS

CGB

Figure 33 Full transient model of MOSFET as implemented in SPICE

SPICE defines static overlap capacitances between gate and drain (CGB0), gate and source (CGS0), and gate and bulk (CGB0). These are fixed values, and are specified per unit width in SPICE.

11.2.1. In Saturation:

WCCC GSoxGS 032 +=

WCC GDGD 0=

These should not surprise you. In saturation, i.e. after pinch-off, the it is assumes that altering the drain voltage does not have any effect on stored charge in the channel and thus the only capacitance between gate and drain is the overlap capacitance. You have already seen the approximation that the gate-drain capacitance is simply 2/3 of the oxide capacitance when in saturation mode. SPICE also adds the overlap capacitance of the source and gate.

11.2.2. In the linear/triode region In this region, the following equations are used:

( ) WCVVVVVVCC GS

DSTHGS

THDSGSoxGS 0

2

21 +

=


( ) WCVVVVVCC GD

DSTHGS

THGSoxGD 0

2

21 +

= We will not show where these equations come from, but we will make one notable point: As the device is moved further into the linear region, i.e. VGS becomes large compared to (VDS-VTH) then the values of CGS and CGD become close to Cox/2 (plus the relevant overlap capacitance).

11.2.3. The body diodes The capacitances of the body diodes are given by slightly modified expressions for junction capacitances of the diode model: You are aware of the expression for a pn diode junction capacitance:

0

1

)0(

VV

CC jj

=

The MOSFET equation is based on the following slightly modified equation:

00

1

)0(

1

)0(

VV

C

VV

CC jswjj

+

=

The junction capacitance is made up of two components. The main component, due to Cj(0) is the normal junction capacitance that you are aware of from the diode equations. The second parameter is the perimeter junction capacitance of the diffused source. The diffusion of the source and drain is not constant throughout the source and drain across the whole area of the diffused region. The number of dopant atoms is greater in the centre of the source region than at the edges. Consequently, the junction capacitance is approximated as two separate junctions. The diffusion capacitance of the body diodes is not included in the model. Why is this?

The diffusion capacitance is zero in reverse bias and the MOSFET must be operated with the bulk-drain and bulk-source diodes in reverse bias to stop large bulk currents flowing



The additional parameters required for specifying the transient model in addition to those required by the DC model are thus:

CGD0 (CGD0) CGS0 (CGS0) CJ (Cj) CJSW (Cjsw) TOX (tox)

Gate drain overlap capacitance per unit width of device Gate source overlap capacitance per unit width of device Zero bias depletion capacitance for body diodes Zero bias depletion perimeter capacitance for body diodes Oxide thickness (used for calculating Cox)

1. Aims and Objectives1.1. Course Aims1.2. Learning Objectives

2. Syllabus3. Problem Sheet4. Recommended Reading5. Introduction6. How SPICE solves circuit bias points a first stage of the simulation process6.1. Overview for a simple resistive circuit6.2. Automatic Construction of the Matrix Equations6.3. Solving circuits with non-linear elements6.4. Bringing it all together

7. Simulation Convergence and Convergence Aids7.1. Basic Convergence Parameters7.2. Convergence Problems An example7.3. The GMIN Convergence Parameter7.4. Setting the convergence parameters7.1. DC sweep simulations7.1. AC Simulations7.2. Large signal Transient Simulations

8. Types of Model used in SPICE9. The SPICE Diode Model9.1. DC Model9.1.1. Limitation of the Diode Model

9.2. Large Signal Transient Model9.3. A Note on the SPICE Area Parameter A and Device Scaling

10. The SPICE BJT model10.1. DC model10.1.1. Ebers-Moll injection modelThe BJT in Active ModeThe BJT in saturation

10.1.2. Ebers-Moll Transport Model used in SPICE

10.2. Large Signal Transient Model

11. The SPICE MOSFET Models11.1. DC Model11.2. Large Signal Transient Model11.2.1. In Saturation:11.2.2. In the linear/triode region11.2.3. The body diodes

Semiconductor Device Modelling

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