Semester B.E. Degree Examinationo Jan.20l5 Analog ... · calculate the capacitor c and h1". Draw...

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USN Time: 3 hrs. 108532 Max. Marks:100 (08 Marks) ; 108 Marks) (04 Marks) (05 Marks) (05 Marks) Third Semester B.E. Degree Examinationo Dec.20l4l Jan.20l5 Analog Electronic Gircuits 4) o o c. E c_) C) t:a 6e 3 EOO .= o] d$ YO sO t* o() =7 -ao OE c-X {' .Y 6: !u >i (F -^o - olJ tr> O (-r < ; z Cd tr o c. b. Consider a half wave and full wave rectifier with capacitor input filter. Derive an expression Explain the following: i) Practical diode model. ii) Ideal diode model. iii) Piecewise linear model. for ripple factor. c. Explain the operation of negative clamper circuit. b. State and prove Miller's theorem. c. Obtain r-parameter model for CB mode. Note: Answer FIVE full questions, selecting at lesst TWO questions fro* each part. PART _ A 2 a. Consider a fixed bias circuit of a transistor. Obtain expressions for stability factor Srco, S\"gn and Sp. Draw the circuit diagram. (10 Marks) b. Design a voltage divider bias circuit for the given conditions: Ic : 1 rnA, S16e :20, P: 100, Vr : 1 V, Vcs : 6 V and Vcc : l2Y. Draw the circuit diagram. (10 Marks) a. For the common collector circuit shown in Fig. Q3 (a), the transistor h-parameters are hi. : -101, h.. : 1, ho. : 25 FA/V, hir: 1.2 K- Determine R1, Ai, A, Au, and Ro for the circuit. (10 Marks) a. Explain the low frequency response of single stage RC coupled amplifier. (10 Marks) b. An amplifier consists of 3 identical stages in cascade, the bandwidth of overall amplifier extends from 20 Hz to 20 kHz. Determine the bandwidth of individual stage. (05 Marks) c. For an amplifier, the midband gain is 100 and lower cut-off frequency is I kHz. Calculate the gain of the amplifier at frequency of 20 Hz. (05 Marks) lil{,ft 5t4{t Fig. Q3 (a) I of2 www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | VTU RESULTS | FORUM | VTU BOOKSPAR APP www.bookspar.com | VTU NOTES | QUESTION PAPERS | NEWS | VTU RESULTS | FORUM | VTU BOOKSPAR APP

Transcript of Semester B.E. Degree Examinationo Jan.20l5 Analog ... · calculate the capacitor c and h1". Draw...

Page 1: Semester B.E. Degree Examinationo Jan.20l5 Analog ... · calculate the capacitor c and h1". Draw the circuit diagram. (05}tarks) Consider a n-channel JFET uSing voltage divider bias.

USN

Time: 3 hrs.

108532

Max. Marks:100

(08 Marks) ;

108 Marks)(04 Marks)

(05 Marks)(05 Marks)

Third Semester B.E. Degree Examinationo Dec.20l4l Jan.20l5Analog Electronic Gircuits

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c.

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EOO.= o]d$

YO

sO

t*

o()=7

-aoOE

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>i (F-^o- olJ

tr>O

(-r <

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troc.

b. Consider a half wave and full wave rectifier with capacitor input filter. Derive an expression

Explain the following:i) Practical diode model.ii) Ideal diode model.iii) Piecewise linear model.

for ripple factor.c. Explain the operation of negative clamper circuit.

b. State and prove Miller's theorem.c. Obtain r-parameter model for CB mode.

Note: Answer FIVE full questions, selectingat lesst TWO questions fro* each part.

PART _ A

2 a. Consider a fixed bias circuit of a transistor. Obtain expressions for stability factor Srco, S\"gn

and Sp. Draw the circuit diagram. (10 Marks)b. Design a voltage divider bias circuit for the given conditions: Ic : 1 rnA, S16e :20, P: 100,

Vr : 1 V, Vcs : 6 V and Vcc : l2Y. Draw the circuit diagram. (10 Marks)

a. For the common collector circuit shown in Fig. Q3 (a), the transistor h-parameters arehi. : -101, h.. : 1, ho. : 25 FA/V, hir: 1.2 K- Determine R1, Ai, A, Au, and Ro for thecircuit. (10 Marks)

a. Explain the low frequency response of single stage RC coupled amplifier. (10 Marks)b. An amplifier consists of 3 identical stages in cascade, the bandwidth of overall amplifier

extends from 20 Hz to 20 kHz. Determine the bandwidth of individual stage. (05 Marks)c. For an amplifier, the midband gain is 100 and lower cut-off frequency is I kHz. Calculate

the gain of the amplifier at frequency of 20 Hz. (05 Marks)

lil{,ft5t4{t

Fig. Q3 (a)

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Page 2: Semester B.E. Degree Examinationo Jan.20l5 Analog ... · calculate the capacitor c and h1". Draw the circuit diagram. (05}tarks) Consider a n-channel JFET uSing voltage divider bias.

5a.

6a.

b.

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b.

10ES32

PART _ BConsider Darlington emitter follower circuit. Obtain expressions for R;2, R;1, A12, A;1.CompareRi andAiof eachandoverallstageif RE =3.3kf),h;.:1.1 kf),h..:2.5x10-a,hr.:50 and ho. :25 pNY. (lo Marks)For a voltage series feedback amplifier topology, obtain expression for Av and R;1. Alsoexplain the principle of voltage amplifier used in feedback amplifiers. (10 Marks)

Derive an expression for second harmonic distortion in power amplifiers, using 3-pointmethod.

A complementary symmetry push pull amplifier is operated with V.. = +t0V, [:TTij]Determine maximum output power, power rating of transistors and DC input power.

(10 Marks)

Explain the concept of positive feedback used in oscillators. (05 Marks)Obtain an expression for frequency of oscillation in Colpitt's oscillator. (10 Marks)In a RC phase shift oscillator using transistor. fo = l0 kHz. Rr : 25 kf), R2 : 57 kf),Rc:20 kf), R:7.1 ko and hi.: 1.8 ko. calculate the capacitor c and h1". Draw thecircuit diagram. (05}tarks)

Consider a n-channel JFET uSing voltage divider bias. Explain its DC analysis. Also derivean expression for transconductance gr. (10 Marks)Design a fixed bias circuit of Fig. Q8 (b) to have ac gain of - 15. Calculate the value of Ro toget this gain, if Vou : 40 V, Rc : 10 Mf), Ip5s : 10 mA, Vp : -4 V, Yos : 20 ps,C1 :0.1 pF. (10 Marks)

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6--+f,-" I

Rq

Fig. Q8 (b)

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