SEMATECH Workshop on 3D Interconnect Metrology Standardized Test Wafers for 3D-IC ...€¦ · ·...

SEMATECH Workshop on 3D Interconnect Metrology

Standardized Test Wafers for3D-IC Wafer Bonding Applications

James Hermanowski

SUSS MicroTec July 14, 2010

Overview

Key Performance Metrics for 3D-IC Wafer Level BondingSUSS Standardized Test WaferIntegration into 300mm Cluster Hardware and Software for Tool Self Diagnostics and Performance MetrologyMetrology for “Lights Out” ManufacturingTest Data and ResultsMetrology Challenges – Present and FutureSummary


Key Performance Metrics

GOAL to quickly measure and quantify interfaces created by 3D processing for process and equipment qualificationAlignment drive minimum via size, electrical resistance

Post bond alignmentIn-situ or in process metrologyMeasurement – wafer face to wafer face, wafer face to wafer back

Bond Quality – voiding and micro-voiding die yieldBond Strength die yield, die lifetime

Shear strength – to resist damage during wafer thinning after bondPull strength – to resist mechanical, thermal or packaging stresses

Hermiticity die lifetimePenetration of moisture or various undesired moleculesAbility to resist degradation or deterioration

Protective or seal rings around a die to prevent attack during later processing

Electrical Performance – yield and resistance


SUSS Standardized Test Wafer Design

Key Features of Test WafersProduced on various wafer types with various materials

Si with Cu, Si with oxide, Si with Ti, glass with metal300mm, 200mm, 150mm and smaller wafer sizes

Mirrored design across die and wafer – folds onto itself to accommodate wafer bonding25 different machine readable targets for automated alignment testing

Crosses, boxes, grids, dots, CognexPositive and negative toneFace to Face targets, IR targets, Back to Front targets

Human readable targets/verniersQuick check capabilityNot all companies have quick access to automation for metrology

Hermeticity testing featuresSeven different seal rings with widths 10 microns and higher

Via patterns for bond strength testing, capable of electrical testing


Cell Layout

0.5mm StreetsMirrored line

25 individual target designs

Large solid bonded area

SUSS logo

Area bonded by vias

Seal rings


Wafer Layout – Cu on SiMirrored line

IR Image of

Cu patterned test wafer


Combined Machine and Human Readable Targets

Combined Target and Vernier, 0.5um


Vernier Examples

Line length: 10, 50, 100, 200, 500, 800 (from left to right)

Line length: 10, 50, 100, 200, 500, 800 (from right to left)

Center Verniers: ±10micron with 1micron resolution; ±5micron

with 0.25micron resolution; ±1micron with 0.1micron resolution


Typical Registration Verniers, 0.1 μm

First Level Second Level


Reading Verniers

In the sample shown below the long bar in the center is the zeropoint.The point where the red lines overlap exactly with those of the first level, black, defines the measurement.In this case the registration is found at the long central bar which happens to be zero, ie., perfect.

If there was mis-registration of +0.4 μm then the forth set of bars to the right of the longer central bar would be perfectly aligned.


Verniers, 0.5 μm steps

First Level Second Level


Machine Readable MarksID

M

ask

Mod

el

Waf

er M

odel

4

5

6

7

8

9

10


Metrology by Linewidth Measurement

Typically a box within a box type image.

First Level Second Level After Alignment

Registration (X-axis) = (Ax – Bx) /2

Resolution of features are limited by diffraction, especially when using IR

Ax Bx


Metrology by Pattern Localization

Dimensions In-Plane image after bonding

Pattern recognition system locates origin of target #1 and target #2

Registration = Δ Origin (1, 2)


Example of Non-Overlapping Targets

33.2 μ

33.2 μ

10 µ

10 µ

117 μ

35 μ

9 μ

Wafer #1 Wafer #2


Cognex Recommended Mark


Backside polished wafers: Good contrast and easy alignment

Backside unpolished Difficult Metrology

Heavily doped wafer Very low IR TransmissionVery Difficult Metrology

IR Alignment Considerations


Integration into 300mm Production Cluster

Test wafers are integrated into SUSS 300mm tooling – Global Calibration Device

GCD use is integrated into software for tool self characterization, calibration, or test purposes.


Ceramic Tooling / Fixture (Patent Pending)

Transports aligned pair from BA300 to CB300

Delivers reproducible submicron alignment capabilities

Maintains wafer to wafer alignment throughout all process and transfer steps

No exclusion zone required for clamping

No cutouts in chuck for maximum yield

Maintains alignment accuracy through temperature ramp

Chuck CTE matches Si CTE

Increases throughput by reduction of thermal mass

Supports Industry Leading Submicron Post Bond Alignment Accuracy


Built-in Global Calibration

Global calibration runs a complete bond align cycleMeasures the entire process, not just sub-systemsUses the same optics/image processing to calibrate and align

Results are fed back to the system for compensationThree different alignment cycle calibration data are stored:

Fixture, Fusion, RPP™

Global Calibration Procedure uses fixture and GCS WafersLoad calibration device/wafersRun alignment cycle Join wafers (Fixture, Fusion, RPP)Re-measure wafer alignment of joined wafersFeedback data to control systemReference = global calibration standard for XYZθEncompasses correction for all tool movements in XYZ and theta


Path to ±350nm post bond alignment accuracy

Allows smaller via diameters and higher via densitiesAlignment accuracy exceeds TSV Roadmap

Global calibration system accounts for all errors and motions in the system

Closed loop, real time feedbackMicroscope tracking and correctionStage axis tracking and correction

Face to Face alignmentsReal time with live images, not historical imagesAllows tooling with zero cutouts for clamps or optical paths

RPP™ - Radial Pressure Propagation system allows engineering control over bond front during direct bonding

BA300UHP Bond Aligner ModuleHigh Density TSV Manufacturing


BA300 Components


Fusion Aligned Wafer Results BA300LEFT SIDE

Left Left -- XX

Left Left -- YY

RIGHT SIDE

Right Right -- XX

Right Right -- YY

Wfr Pr1 Wfr Pr2Lx (um) 0.350 0.250Ly (um) 0.100 0.150Rx (um) 0.100 0.150Ry (um) 0.100 0.100

Post Anneal Alignment Accuracy


BA300 Alignment Plot w/ Auto-Metrology


Cu-Cu Test SequenceSubmicron Post Bond AlignmentSUSS 300mm Cu Patterned Wafers100KN Bond Force425C Bond Temperature


Metrology for “Lights Out” Manufacturing

“Lights Out” operationA tool monitors its own results and takes corrective action to maximize yield

Pre-Bond metrology measures the alignment on wafer pairs BEFORE transfer to permanent bonding

Recipe defined alignment spec and actionsPASS move wafers to bonderFAIL separate and realignFAIL manual interventionFAIL reject wafers

Post Bond measures the final resultRecipe defined alignment spec and actionsPASS tool continues operationFAIL alarm triggers user intervention to prevent more wafers from bonding

IR images collected from pre-bond and post bond

metrologyAvailable optionally depending upon wafer and equipment configuration


Metrology Gage Study

Metrology Repeatability

-8-7-6-5-4-3-2-10123456

0 1 2 3 4 5 6 7 8 9

Run #

Mic

ron

Left XLeft YRight XRight Y

Worst case example of metrologyBonded wafer pairs measured repeatedly, one reading each dayMixed target style used

Wafer 1 – visible targetWafer 2 – IR targetStage motion required to focus on each targetIllumination type changed for each target

Ideal case is when both targets are:

In the same planeVisible using the same illuminationNo need to move stages or refocus


Hermiticity Evaluation

High resolution SAM image taken after wafer bondingBlue areas show good bond resultsGreen areas at wafer edge show water penetration into die


Hermiticity Evaluation

High resolution SAM image taken after additional 48 hours of water soakingBlue areas show good bond resultsGreen areas at wafer edge show water penetration into die

Water penetrates deeper into compromised die at wafer edge


Water Penetration of Edge Die

High resolution SAM with zoom into edge die regionSix die with seal ringsSmallest seal ring width penetrated by water


Water Penetration of Edge Die

48 hour exposure to water

High resolution SAM with zoom into edge die regionSix die with seal ringsTwo seal rings penetrated by waterNo other rings penetrated


Metrology Challenges Present and Future

Measurement standards for 3D alignmentsWafer face aligned to wafer back – via last approach and via after bondingWafer back aligned to wafer back –

Interface measurements through non-transparent wafersBond quality and alignmentsIR absorbing layers, metal layers and heavily doped Silicon

Targets are on two different planes – 3D spatially.

May require visible & IR illumination

How to measure when traditional forms of radiation

(visible or IR) will not penetrate the wafer stack?

Acoustic waves? Electrical?


Summary

An approach to quickly measure and quantify interfaces created by 3D processing has been established for process and equipment qualificationThe approach uses standardized test wafers which contain features to simply and easily quantify processes and equipment used in the manufacture of 3D-IC

Alignment drive minimum via size, electrical resistanceBond Quality – voiding and micro-voiding die yieldBond Strength die yield, die lifetimeHermiticity die lifetime

Technology has been integrated into SUSS’ XBC300 wafer bond production platform for automated tool calibration/controlChallenges remain for simplified metrology of non-transparent wafers and features which cannot be localized in two dimensions

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