Self-Triggered Recorder for Analog Waveforms v.3 (STRAW3...

Self-Triggered Recorder for Analog Waveforms v.3 (STRAW3) Data Sheet

Gary S. Varner

[email protected]

Department of Physics and Astronomy, University of Hawai’i at Manoa

3 December 2003

ABSTRACT This document is intended as a users’ manual for understanding and working with the third revision of a Self-Triggered Recorder for Analog Waveforms (STRAW3), a CMOS full-custom integrated circuit. As the name implies, this chip serves two functions: triggering on fast, bipolar pulses; as well as high-speed waveform sampling. Triggering is performed by an array of 4 discriminators looking at each of the 16 RF input channels. The thresholds of these 64 discriminators are set by 64 on-chip 20-bit DACs. Each discriminator channel is monitored with a dedicated 32-bit scaler. Analog waveform sampling is performed by a 256-deep Switched Capacitor Array (SCA) on each RF channel, capable of sampling between 0.7 – 3.4 GSa/s (74 - 366 ns sampling window) in either common-start or common-stop mode. Based upon experience with STRAW2, the attainable analog bandwidth should be approximately 1GHz. STRAW3 is fabricated in the TSMC 0.25µm process and packaged in a 100-pin TQFP package.

Keywords: GSa/s sampling, CMOS, SCA, GHz analog bandwidth.

1. Theory of Operation Low-power, high speed sampling of RF transients is needed to be able to exploit new initiatives in ultra-high energy neutrino detection [1,2,3]. Commercially available solutions are both very high power and expensive [4,5]. The functionality required is illustrated in Figure 1. Electromagnetic showering in a dense medium (such as ice or salt) of the secondary particles from the primary neutrino interaction is compact. As such, the charge excess produces a coherent radio pulse, emitted along a Cherenkov fan as illustrated. Detection of these transient pulses is done over a very wide bandwidth, to improve sensitivity as well as discriminate from anthropogenic and meteorological backgrounds.

stop

Trigger

High−speedSampling

1GHz BW

(0.2−1.2 GHz)

to Global Trigger

low−powerADC

~MSa/s

to Data Collection

RF antenna

Cherenkov

interaction

UHEυ

ElectroMagneticshower

υ

cone

~GSa/s

Figure 1: A simplified functional diagram of the STRAW3 chip.

1

A simplified way to think about the STRAW architecture is as a frequency down converter. Sampling a 1GHz signal above the Nyquist minimum requires multi-GSa/s operation. When events of interest are triggered, the samples are output to an ADC which samples in the multi-MSa/s range. The thousandfold reduction in required ADC operation reduces the digitized data produced by at least 3 orders of magnitude, and even more importantly, significantly reduces the power required. By coincidence, the power as measured for the STRAW2 chip is about 3 orders of magnitude less than that of the commercial Acqiris digitizer module[6] being flown in the ANITA-lite prototype balloon flight[7]. Figure 2 presents a more detailed rendering of the logical partitioning of the functionality of the STRAW3, with a description of the basic functionality provided in the figure caption. Complete schematics are available online [8]. A diagram of the actual chip layout, with these key function blocks indicated, is presented in Figure 3.

40k

20k

10k

2R

R

2R

R

2R

RR

2R

R

2R

inputs

8 RF

inputs

8 RF

Analog

buffer

Trigger Control

STRAW3 architecture

AMUX

8

8

Monitor

or Ext. ADC

to Data Acquisition

Global Trigger port

Threshold DACs (32x 20−bit)

Threshold DACs (32x 20−bit)

64x 32−bit

12

timing control

8

8

Trigger

Trigger

AMUX

scalers

Gain

ADC

SAR

2R

R R

2R

R

2R

R

2R

R

2R

DQ

Q’

D Q

Q’

+−

Q

Q’

D Q

Q’

D

−+

+−

−+

−+

+−

+−

−+

+−

−+

+−

+−

−+

SCA bank: 16 rows x 256 columns

SCA bank: 16 rows x 256 columns

Figure 2: A functional block diagram of the STRAW3 chip. Incoming RF signals are sampled in the SCA banks, with the sampling rate set in the timing control block. An array of 16*4 discriminators inside the Trigger block, with thresholds set by the DACs as shown, sense the RF inputs and output triggering levels. Upon acceptance of a trigger event, managed by the Trigger Control block, the stored analog samples are row-wise shifted out of the SCA array and serialized by the Analog Multiplexor (AMUX) block. This single selected channel is then put through a Gain adjust block and distributed to two blocks. The first is an on-chip Successive Approximation Register (SAR) Analog to Digital Converter (ADC). The second is an Analog buffer, which drives the analog sample value off-chip for either monitoring or digitization by an off-chip ADC. A data bus (not shown) carries the on-chip ADC conversion values as well as scaler and other diagnostic signals off chip.

2

12−bit SAR ADC

Discriminators

32x 32−bit scalers

32x 32−bit scalers

MLU/Trigger Control

32x 20−bit DACs

32x 20−bit DACs

Timing Control

SCA arrays

Figure 3: Floorplan diagram of the STRAW3 chip with primary functional blocks indicated.

As seen in Figure 3, the space required by the SCA array itself is actually quite modest. Even with 5 metal layers available, the routing was complicated in trying to keep the analog and digital sections well separated from each other. The RF signals are input as a differential pair to the bonding pads that appear reddish/pink along the left edge and wrapping slightly around to the top and bottom. The data bus output is at the right of the die. The top and bottom of the pad ring are primarily control signals and power. For orientation with Table 11, pin 1 is the uppermost on the left side, with numbering counter-clockwise.

1.1. Goals of STRAW3 The architecture of STRAW3 is fundamentally the same as that which has already been prototyped in the STRAW2 chip. Fabrication of a 3rd version was instigated to address the following issues:

• Fixed a logic flaw in the on-chip ADC which prevented proper operation • Adjusted the incoming RF on-chip micro-striplines to allow for proper 75 Ω termination, as well as

re-optimizing for higher analog bandwidth operation (1GHz f3dB target) • Added the ability to monitor 16 of the trigger outputs directly over the data bus • Removed large capacitance ESD structures on the 4 peripheral RF input channels, which had greatly

reduced their bandwidth compared with the other RF inputs

3

As a reminder, the requirements placed on the STRAW design are listed in Table 1. Of all of these constraints, the ability to obtain in excess of 1 GHz analog bandwidth is the most challenging. There is a direct trade-off between this bandwidth and the number of SCA samples because of capacitive loading.

> 1GHz ind. Adj.256 ind. Adj.16 OR of 1616 multiplicity

1-3 GHz high+low12 32 bits/ch.

<=16 ms cascade

TriggeringSTRAW Design Parameters

Input bandwidth

# of channels# of RF inputsSampling rate

Analog

ADC (SAR) bitsDigitize deadtime

High level thresholdLow level threshold

High level logicLow level logic

Comparator typeMonitor scalers

Trigger type

# SCA/channel

Table 1: STRAW architecture design specifications.

In order to avoid ambiguities caused by aliasing, the sampling rate must be at least twice the input bandwidth, which is often referred to as the Nyquist limit. Therefore, the sampling rate specification requires operation in the multi-GSa/s range. At these high sampling speeds, with the number of samples fixed at 256, the record window becomes rather short. Fortunately, the impulsive events of interest are only a few nanoseconds wide[11] and so a window of the order of 100ns is acceptable. The primary impact of this narrow window is that the latency of any global trigger, involving multiple STRAW chips, must be made as short as possible. With a single on-chip ADC (or even a fast off-chip ADC), it is difficult to digitize the samples and be ready to resume sampling in much less than a few milliseconds. This is understandable given the large number of samples to be digitized. At an ADC conversion rate of 1.25MHz, with 200ns for sample settling time + digital readout, it will take 4ms to read out the 16*256 (4k) samples. Therefore, in applications requiring zero deadtime or the possibility of burst events (e.g. “double-bang”), some type of “ping-pong” mode operation of multiple devices is mandated. For triggering purposes the high and low level discriminator outputs are treated quite differently. Operation at very low thresholds, well into the noise, can lead to trigger rates in the MHz rate per channel. Therefore at any given time a number of outputs may be on. Multiplicity logic is applied to help restrict the trigger to coincident events. The rationale behind the high level logic is that if any one channel exceeds this much higher level (well above noise), a signal level is present which should definitively be digitized and evaluated. The following sections go into detail describing how the functionality in the various logical blocks are implemented. These details include test results and/or expectations from simulation where appropriate. Most importantly, description is given where needed of how to interface the various control and bias pins for proper operation of the STRAW3. The following outline indicates the relevant sections for quick reference:

1. this introduction 2. Analog waveform sampling 3. Triggering 4. Analog sample digitization 5. Output Data selection 6. Pin-out and pin functional description 7. Packaging

4

2. Analog Waveform Sampling The high frequency inputs are sampled using a Switched Capacitor Array, which may be seen schematically in Figure 4. A write pointer goes round and round and when closed, samples the instantaneous voltage on the input. When the write pointer comes back around, the oldest samples are overwritten. The speed at which the write pointer propagates is controlled as described in the next subsection. input

Figure 4: Basic function of a Switched Capacitor Array (SCA), with a schematic of a single cell inset at right.

2.1. Sampling Rate Control In order to generate the on-chip write pointer, a standard inverter-chain ripple (“domino chain”) oscillator is used. As long as there are an odd number of stages, this chain will oscillate. Adjustment of the sampling frequency is done by adjusting the positive voltage rail of the inverter chain, designated Ripple Oscillator VDD or ROVDD. The larger the value of ROVDD, the faster the sampling rate. ROVDD can be adjusted from about the chip VDD/2 (2.5V/2 = 1.25V) up to about one diode drop above VDD. At the low side near 1.25V, the oscillator stops behaving properly, as the logical high voltage is near the voltage threshold of the other gates in the design, which are referenced to the regular 2.5V rail. In order to extend the dynamic range to longer times (for low-bandwidth operation), a better choice would be to adjust simultaneously both ROVDD and a dedicated ROGND, a separate VSS signal for the inverter chain. This strategy is adopted for a dedicated sampling-only chip named LABRADOR[9] (Large Analog Bandwidth Recorder Digitizer with Ordered Readout), which is a focused “sampling only” variant based on the original STRAW architecture. Since ROVDD is an analog input to the chip, it may be operated in excess of the VDD rail to the limit at which the input protection circuitry of the bonding pad starts to turn on. Operation above the rail allows the sampling rate to be run well in excess of 3GSa/s, assuring sampling definitively above the Nyquist frequency for signals up to 1.2GHz of analog bandwidth. Monitoring of the sampling frequency is done by measuring the Ripple Carry Out (RCO) from the chip. This square wave signal is a copy of the write pointer. Note that because of the way the logic is arranged inside the STRAW3 chip, both edges actually represent a sampling transition. Given that the number of cells is fixed, the relation of the RF sampling frequency to that of RCO may be expressed as:

RCORFsample ff 2256 ∗=

5

2.2. Expectations from STRAW2 The sampling frequency response of the STRAW2 chip was well determined, as shown in Figure 5. As this part of the circuitry was unchanged in STRAW3, very similar performance should be expected. Note that because of asymmetry in the rise and fall times of the inverters in the ripple oscillator (imbalance in the drive strengths of the NMOS and PMOS devices which make up the inverters), the positive and negative cycles have slightly different timebases. This effect will need to be calibrated, although the magnitude is not large. For example, for ROVDD = 2.5V, the difference of both the positive and negative pointer propagation with respect to the average value is about 2%. This corresponds to about a 7ps shift from the nominal 370ps window aperture.

STRAW2 Sampling Freq.

0

0.5

1

1.5

2

2.5

3

3.5

1 1.5 2 2.5 3

Freq. Adj. Voltage (ROVDD) [V]

Sam

plin

g Fr

eq.

[GSa

/s]

Avg.-cycle+cycleSPICE

Figure 5: SCA sampling frequency versus control voltage (applied to ROVDD). Measured values are compared

with SPICE simulations, indicating that these simulations were relatively conservative.

By monitoring RCO, ROVDD may be fed back to adjust the sampling frequency to a reference source. This has been implemented in the DALI Rev. B board[10]. Some amount of phase jitter remains in the PLL circuit used, though the frequency wander was measured to be less than 0.01% of baseline. At 3GSa/s (333ps/sample) this wander is sub-picosecond and should be negligible. However, the circuit employed did not lock the start phase of the write pointers. To do so in the current operating mode would over-constrain the feedback. This is an issue to be studied in operation of the STRAW3.

6

3. Impulsive Triggering An attempt was made to optimize the high-frequency performance of the comparators that form the discriminators used for triggering. A very real restriction was that although the TSMC 0.25µm CMOS process is respectably fast, the maximum gain bandwidth product was still insufficient for directly triggering on signals exclusively of greater than or equal to 1GHz of bandwidth. The arrangement of the 4 comparators and 1-shots that make up the discriminators for a single channel is shown in Figure 6.

1−shot

ICbias

1−shot

ICbias

to scalers

ICbias

VinV_LH

V_HL

V_HH

VTbias

VTbias VTbias

1−shot

ICbias

1−shotRF input

x10 boost

VBS

Vbias

Low level

to multiplicitysum

High level

to OR16

to scalers

to TMbusHLH

HHHHHL

HLL

(see Sect. 5)

R

highVth

lowVth

V_HL

V_HH

highVth

V_LH

lowVth

10R

VTbias

−

+

−

+

−

−

+

−

−

+

+

+

+

−+−

+

−

+

−

V_LL

V_LL

Figure 6: Trigger logic for a single RF channel. Scalers monitor the trigger frequency of each of the 4 discriminators. A current sum of the low-level discriminator outputs is performed to generate a global chip multiplicity. An OR of the high-level outputs is done to check if any one RF channel is above a high threshold level. In order to form pattern triggers, the HLH signal is also available for monitoring on the TMbus.

Each of the 4 threshold voltage levels shown is set with a dedicated 20-bit DAC, as will be explained in section 3.1.1 below. At the cost of increased power, it is possible to adjust the bias operating current for these comparators to improve performance by using a lower R value attached to the VTbias pin (increased current). The bias value Vbias may also be adjusted to optimize the performance of the booster amp. Proper operation of this times-10 booster amplifier requires that VBS be adjusted to approximately the value of the input offset voltage of the RF inputs. Some tweaking of this value may be required for optimal performance. Operation of the discriminators is discussed in the next subsection. In addition to adjusting the VTbias value, it is also possible to adjust the 1-shot output width by adjusting the bias current set by ICbias .

3.1. Discriminators A discriminator is consists of a high-speed comparator and a 1-shot. These elements may be seen in the layout drawing of Figure 7. The 1-shot is implemented as a delay on the reset pin of a D Flip-Flop, which is set high by the rising edge of the comparator. Because the noise threshold is a very steep function, it is essential that the fast comparator used have excellent overdrive performance. SPICE simulations indicated that for the few mV rms signals expected, it was necessary to include a buffer amplifier stage to maximize timing performance for small amplitude signals. SPICE simulation results of the response to one of the digitized RF pulses from a beam test at SLAC to confirm the Askaryan effect[11] is shown in Figure 8.

7

Fast Comparator Control Logic Width adj. Capacitor

Figure 7: Layout of a single discriminator channel, with key elements indicated.

e

Figure 8: SPICE simulation of the Discriminator response to an Askaryan RF pulse m

3.1.1. Reference Voltage Control (DACs) Each of the 64 discriminators used on the STRAW3 chip is required to be indiviallows for independence in the operation of the RF triggering channels, as well asoffsets of the comparators themselves. As mentioned above, because the noise trigfunction of reference voltage, fine adjustment of the reference voltage is required. Aas shown in Figure 9 was designed to meet these demands. Inset is a simulation rDAC. A perfect 20-bit DAC would be overkill. However, with extensive experiencin this and similar processes, some amount of mismatch is always present. To compadjust DAC on the output may also be though of in terms of a “trim DAC”, which canmain DAC codes.

8

Amplifier Output

d g

eee

Raw RF puls

Discriminator Output

easured in test beam[11].

ually adjustable. This compensation for input er rate is a very steep

two stage, 20-bit DAC sult for the fine-adjust in using R-2R ladders nsate for this, the fine-fill in gaps between the

Figure 9: Arrangement of the 20-bit DAC, with a 12-bit main stage and an 8-bit trim DAC. SPICE simulation of the 8-bit DAC is shown. A counter was incremented at a fine time step (30ns) and the uniformity of the DAC output versus input code is shown. The glitches seen are due to the use of a ripple counter and settling of the DAC during transition, as evidenced by the 0x01111111b to 0x10000000b transition clearly evident in the middle.

The main DAC has a Least Significant Bit (LSB) of about 0.6mV, which would already probably be good enough if ideal. Finer tuning and gap spanning is done with the fine-adjust DAC, which has an LSB of about 80µV. A detailed scan of the output voltage versus input code will be needed to determine the actual mapping. Fortunately, from experience, all DACs on the chip should show very similar response. Programming of these DAC values is described in Section 5.2.

3.1.2. 1-shot Control Reset of the 1-shot, once triggered, is performed by charging a 1pF capacitor with a programmable current source. Selection of the resistor value to be connected to the ICbias pin to obtain a desired discriminator output width is shown in Figure 10. These SPICE results are to be taken as indicative only and precise determination should be made experimentally. To first order the choice of resistor value should be:

][3.11][*2.1][ nskRnsW ICbiasoutput +Ω= adjustment to widths shorter than about 11-12 ns is not possible.

9

Discriminator 1-shot Width Adjust

y = 1.2288x + 11.262R2 = 0.9992

0

20

40

60

80

100

120

140

160

0 20 40 60 80 100

Resistance [kΩ]

1-sh

ot O

utpu

t Wid

th [n

s]

Width AdjustLinear (Width Adjust)

Figure 10: SPICE simulation determination of discriminator output width versus ICbias resistor.

3.2. Scalers In order to determine the proper threshold setting as a function of ambient noise seen by the RF chain, it is crucial to have some observable parameter as input to a feedback loop. A convenient observable is to measure the frequency at which a given discriminator channel is firing. In practice this is accomplished by using a counter, integrated over a selectable time, often designated as a “scaler”. These 32-bit counters employed are actually 31 bits of counting and 1 bit of overflow, to prevent the case of ambiguities that would happen if the counter were to wrap around without being noticed.

3.3. Trigger Logic The 4 discriminators on each channel consist of two so-called high-level and two low-level types. This designation refers to the nominal threshold voltage with respect to the zero signal input level. Each of these types has a positive and negative threshold type, as seen in Figure 5. The reasoning behind distinguishing between high and low level is that for the low level, at any given point in time, it is quite likely that a given channel will be above a low-level noise threshold. However, if we sum up the number on at any given instance and require that some number of them be on simultaneously, a much lower overall trigger rate may be obtained. In the usual convention, this number of channels that are above threshold is called the multiplicity. A current sum is done of the low-level outputs that are on and this is put into a comparator to be compared with a value that may be programmed in 5 of the GTM registers, as described in Section 5.2

10

4. Analog Sample Digitization

4.1. Sample Selection Inside the Gain block shown in Figure 2, there are a pair of analog multiplexors which select one of three possible analog signal sources: the SCA samples, one of the DAC outputs, or the calibration input (CAL). Selection of the signal source is done by loading the first two bits of the Gain and Trigger Multiplicity (GTM) register, which is described in more detail in Section 5.1. Table 2 shows the configuration to be used to select a given source to input to the ADC as well as drive off-chip through the analog superbuffer.

GTM bit Analog Source GTM0 GTM1 to ADC + Aout

0 X SCA channel selected by Address Counter 1 0 CAL direct connect to CAL pin 1 1 DAC channel selected by Address Counter

Table 2: Analog Source selection table.

In the case of the CAL input, the value selected is unambiguous. For the case of the SCA and DAC channels, the value selected depends upon decoding the address present in the Address Counter. An abridged table of the Address Counter addresses to SCA channel and DAC value is given in Table 3.

Address SCA selected DAC selected Scaler selected 0 Channel 1, Column 1 Channel 1, LHT Channel 1, HHL, low word 1 Channel 2, Column 1 Channel 2, LHT Channel 1, HHL, high word 2 Channel 3, Column 1 Channel 3, LHT Channel 1, HLL, low word 3 Channel 4, Column 1 Channel 4, LHT Channel 1, HLL, high word 4 Channel 5, Column 1 Channel 5, LHT Channel 2, HHL, low word 5 Channel 6, Column 1 Channel 6, LHT Channel 2, HHL, high word 6 Channel 7, Column 1 Channel 7, LHT Channel 2, HLL, low word 7 Channel 8, Column 1 Channel 8, LHT Channel 2, HLL, high word 8 Channel 9, Column 1 Channel 1, LLT Channel 3, HHL, low word 9 Channel 10, Column 1 Channel 2, LLT Channel 3, HHL, high word … … … … 15 Channel 16, Column 1 Channel 8, LLT Channel 4, HLL, high word 16 Channel 1, Column 2 Channel 1, HHT Channel 5, HHL, low word 17 Channel 2, Column 2 Channel 2, HHT Channel 5, HHL, high word 18 Channel 3, Column 2 Channel 3, HHT Channel 5, HLL, low word … … … … 23 Channel 8, Column 2 Channel 8, HHT Channel 6, HLL, high word 24 Channel 9, Column 2 Channel 1, HLT Channel 7, HHL, low word … … … … 31 Channel 16, Column 2 Channel 8, HLT Channel 8, HLL, high word 32 Channel 1, Column 3 Channel 9, LHT Channel 1, HHH, low word 33 Channel 2, Column 3 Channel 10, LHT Channel 1, HHH, high word … … … … 63 Channel 16, Column 4 Channel 16, HLT Channel 8, HLH, high word 64 Channel 1, Column 5 Channel 1, LHT Channel 9, HHL, low word DAC repeats after 64 65 Channel 2, Column 5 Channel 2, LHT Channel 9, HHL, high word Scaler repeats after 128… … … …

4095 Channel 16, Column 256 Channel 16, HLT Channel 16, HLH, high word

Table 3: Address Counter decoding for the SCA, DAC and Scaler channels.

11

4.2. Off-chip ADC A wide variety of off-chip ADCs may be used to digitize the output of the STRAW3 chip. Depending upon the bias current, set with choice of R value on ISbias, and the capacitive load of the ADC input, the output can be made to settle in less than 50ns. Settling performance to a given resolution should always be evaluated when choosing an ADC. In STRAW2, the settling time limitation was set by the settling of the analog value inside the gain block. A different and faster approach is being taken in the LABRADOR design; though STRAW3 should expect the settling time to probably be similar to STRAW2 as only minor changes were made to the gain block.

4.3. On-chip ADC STRAW3 implements a basic Successive Approximation Register type ADC. While R-2R mismatch in this type of can be vexing, with careful design and calibration, it may be made essentially seamless with an appropriate calibration.

4.3.1. On-chip ADC Sequencing Figure 11 shows a recommended timing diagram for operation of the on-chip ADC. Subsequent to a ACCLK strobe, which advances the sample to the next value of interest (except for a CAL input event), a settling time is required as shown. The frequency of the ADCCLK is adjustable, though at some upper value there is a degradation of the 12-bit fine bits due to insufficient settling time. Below some frequency there is no benefit to sampling any slower. These bounds should be determined experimentally and is one of the motivations behind providing a dedicated CALibration input. Simulation and experience indicate that for most applications, an ADCclk slower than about 40MHz should allow for sufficient settling time. After asserting ADCstart, the rising edge of the EOC signal (available on the ADCbus as bit DAT12 – see Table 5) may be used to latch the converted ADC data.

data ready

12

Successive Approximation ADC Timing

1376543

EOC

ADCclear

ADCstart

ADCclk

1 2

Figure 11: A timing diagram for the on-chip Successive Approximation Register ADC. After the rising edge of ADCstart, a new digitization is started. Note that it is not necessary to issue an ADCclear, another rising edge on ADCstart will commence another digitization cycle. Data is available for use on the rising edge of End Of Convert (EOC). At each ADCclk, the 12-bit DAC, which is the reference for the analog compare, has the next least significant bit toggled. Depending on if higher or lower than the reference value, a 0 or 1 is latched. This continues until the finest granularity bit is determined, with a one clock cycle delay for the 12-bits, as shown.

12

5. Programming and Output Data Selection In order to facilitate debugging and testing, provision has been made to monitor many of the internal logical signals inside the STRAW architecture. To rationalize this process, these signals have been bundled into buses, which may be selected as seen in Figure 12. While other signals come along for the ride, the primary items being monitored on these buses are the following:

• ADCbus = on-chip ADC conversion values • ADDRbus = Address Counter current address • TMbus = Trigger Monitor bus – direct observation of 16 of the discriminator outputs • SDbus = Scaler register values

In addition, two of the buses carry important monitoring signals for confirming programming and other status information. These crucial items are:

• ADCbus GTMout, Hitbus, PosNeg • ADDRbus Dout, PosNeg, HLout, Hitbus

As seen, two of these signals are so important as to be included in both modes. This is because it is desirable to access the write pointer stop position (via Hitbus) and write pointer transition polarity (via PosNeg) in either bus mode without switching. In terms of programming the two serial configuration ports, access to the serial outputs is essential for confirming proper operation. GTMout is the serial output for the GTM registers and Dout is the DAC register serial shift output bit.

16

16

16

SDbusTMbus

ADCbus

2:1 MUX

Out

Sel

B

A

TspySAd

ADDRbus DnA

busDAT out

16

2:1 MUX

Out

Sel

B

A16

1616

2:1 MUX

Out

Sel

B

A

Figure 12: Addressing structure of the internal data buses.

For quick reference, this same information of Figure 12 is provided in Table 4. A definition of the contents of these buses is found in Tables 5-8, as indicated below.

DnA SAd Tspy Bus selected Definition 1 X X ADCbus Table 5 0 0 X ADDRbus Table 6 0 1 0 SDbus Table 7 0 1 1 TMbus Table 8

Table 4: Internal Data Bus selection guide.

13

ADCbus Definition Output Name Description Comment DAT0 D0 ADC bit 0 LSB DAT1 D1 ADC bit 1 DAT2 D2 ADC bit 2 DAT3 D3 ADC bit 3 DAT4 D4 ADC bit 4 DAT5 D5 ADC bit 5 DAT6 D6 ADC bit 6 DAT7 D7 ADC bit 7 DAT8 D8 ADC bit 8 DAT9 D9 ADC bit 9

DAT10 D10 ADC bit 10 DAT11 D11 ADC bit 11 DAT12 EOC End Of Convert active high when done DAT13 GTMout GTM serial output GTMsin repeat after 12 DAT14 Hitbus Write pointer status active where stopped DAT15 PosNeg samples write pointer polarity during nRUN=H

Table 5: ADC bus member definition.

ADDRbus Definition Output Name Description Comment DAT0 S0 Address bit 0 LSB DAT1 S1 Address bit 1 DAT2 S2 Address bit 2 DAT3 S3 Address bit 3 DAT4 S4 Address bit 4 DAT5 S5 Address bit 5 DAT6 S6 Address bit 6 DAT7 S7 Address bit 7 DAT8 S8 Address bit 8 DAT9 S9 Address bit 9

DAT10 S10 Address bit 10 DAT11 S11 Address bit 11 DAT12 Dout DAC load serial output DIN echo after 1280 DAT13 PosNeg samples write pointer polarity during nRUN=H DAT14 HLout High Level trigger OR HL signal DAT15 Hitbus Write pointer status active where stopped

Table 6: ADDRbus member definition.

14

SDbus Definition Output Name Description Comment DAT0 SD0 Scaler bus bit 0/16 LSB of first/second word DAT1 SD1 Scaler bus bit 1/17 DAT2 SD2 Scaler bus bit 2/18 DAT3 SD3 Scaler bus bit 3/19 DAT4 SD4 Scaler bus bit 4/20 DAT5 SD5 Scaler bus bit 5/21 DAT6 SD6 Scaler bus bit 6/22 DAT7 SD7 Scaler bus bit 7/23 DAT8 SD8 Scaler bus bit 8/24 DAT9 SD9 Scaler bus bit 9/25

DAT10 SD10 Scaler bus bit 10/26 DAT11 SD11 Scaler bus bit 11/27 DAT12 SD12 Scaler bus bit 12/28 DAT13 SD13 Scaler bus bit 13/29 DAT14 SD14 Scaler bus bit 14/30 DAT15 SD15 Scaler bus bit 15/31 MSB of first/overflow

Table 7: SDbus member definition.

TMbus Definition Output Name Description Comment DAT0 HLH1 Trigger Monitor bit Chan. 1 Low High level fire DAT1 HLH2 Trigger Monitor bit Chan. 2 DAT2 HLH3 Trigger Monitor bit Chan. 3 DAT3 HLH4 Trigger Monitor bit Chan. 4 DAT4 HLH5 Trigger Monitor bit Chan. 5 DAT5 HLH6 Trigger Monitor bit Chan. 6 These can be used to DAT6 HLH7 Trigger Monitor bit Chan. 7 form a pattern DAT7 HLH8 Trigger Monitor bit Chan. 8 trigger DAT8 HLH9 Trigger Monitor bit Chan. 9 DAT9 HLH10 Trigger Monitor bit Chan. 10 DAT10 HLH11 Trigger Monitor bit Chan. 11 DAT11 HLH12 Trigger Monitor bit Chan. 12 DAT12 HLH13 Trigger Monitor bit Chan. 13 DAT13 HLH14 Trigger Monitor bit Chan. 14 DAT14 HLH15 Trigger Monitor bit Chan. 15 DAT15 HLH16 Trigger Monitor bit Chan. 16

Table 8: TMbus member definition.

15

5.1. GTM Registers In Table 9 are listed the 11 bits which form the Gain and Trigger Multiplicity (GTM) registers. GTM0 is the first bit shifted in and GTM10 the last. A sample timing diagram for this transfer is found in Figure 13. The first two bits select the analog value for sampling, as described in section 4.1. Table 2 provides a compact reference. The next 4 bits, GTM2 … GTM5 are used to set the gain. This also impacts the settling time of the SCA analog value and so should be evaluated for a given operating condition. The final 5 bits select the multiplicity, in a binary coded manner, with GTM6 as the Most Significant Bit and GTM10 as the Least Significant Bit. After 11 clocks, the data shifted in will appear on the GTMout line (DAT13 member of the ADCbus – see Table 5) for monitoring.

GTM Register Definition Bit # Alias if = 0 if = 1 Comments

GTM0 CD/Obus SCA (Obus) selected CAL/DAC selects GTM1 CAL/DAC CAL selected DAC selected GTM2 RSEL3 no connect VDD GTM3 RSEL2 no connect 46.4k Rpullup connected GTM4 RSEL1 no connect 11.6k Rpullup connected GTM5 RSEL0 no connect 23.2k Rpullup connected

GAIN pull-up resistors

GTM6 MLU4 OFF ON MSB GTM7 MLU3 OFF ON GTM8 MLU2 OFF ON 0 = hits > 0 GTM9 MLU1 OFF ON

GTM10 MLU0 OFF ON LSB

Table 9: Gain and Trigger Multiplicity register definition.

GTM10(very old) GTM10

GTM9 GTM10

GTM Register Load

GTM10(old)

GTM9GTMout (old)

GTMCLK

GTMSIN GTM1 GTM5GTM0

(old) (old) (old) (old) (old)

GTM6

GTM2

GTM2 GTM3 GTM4

(old)GTM0 GTM1 GTM3 GTM4 GTM5 GTM6

(old) (old)

Figure 13: Gain and Trigger Multiplicity (GTM) register load timing diagram. For monitoring, data is shifted out on the GTMout pin (see ADCbus definition in Table 5) after 12 clock cycles.

16

5.2. DAC Registers In Table 10 is listed the shift register definition for loading the 64x 20-bit DACs that are used to set the threshold value for the trigger elements described in Section 3.1. Register loading is diagrammed in Fig.14.

DAC Registers Definition Bit # DAC# DAC bit# Description Comments SIN0 1 1 Main DAC bit 0 LSB SIN1 1 2 Main DAC bit 1 SIN2 1 3 Main DAC bit 2

… … … … … SIN11 1 12 Main DAC bit 11 MSB SIN12 1 1 Fine-Adjust DAC bit 0 LSB SIN13 1 2 Fine-Adjust DAC bit 1

… … … … … SIN19 1 8 Fine-Adjust DAC bit 7 MSB SIN20 2 1 Main DAC bit 0 LSB SIN21 2 2 Main DAC bit 1

… … … … … SIN1279 64 8 Fine-Adjust DAC bit 7 MSB

Table 10: Digital to Analog Converter serial input programming register definition.

n−1273n−1274n−1275n−1276

SCLK

n−1277

DCLK

dat4 dat5

DAC Load Timing Diagram

n−1 dat1278dat0 dat1 dat2 dat3

n−1278

dat6SIN dat1279

Dout n−1280 n−1279

load DAC registers

n−2 n−1n−3 Figure 14: DAC Register load timing diagram. The serial shift data is output on the Dout monitor pin (ADDRbus DAT12 pin – see Table 6) and appears 64*20 clock cycles after entering the Serial INput (SIN) pin. The DAC registers are only updated from the serial input registers upon strobing of DCLK.

6. Pin-out and Pin Functional Description In Table 11 below is tabulated the pins for the STRAW3, with a brief description of pin functionality. For convenience, these pins are grouped by function. Where applicable, reference is made to the appropriate section of this data sheet where further detailed information is provided.

17

Section Pin # Pin name Description Comments 96 Vin1 RF input #1 97 Vrf1 ground reference for RF in #1

75 Ω between pair

98 Vin2 RF input #2 99 Vrf2 ground reference for RF in #2

75 Ω between pair


75 Ω between pair


75 Ω between pair


75 Ω between pair


75 Ω between pair


75 Ω between pair


75 Ω between pair


75 Ω between pair


75 Ω between pair


75 Ω between pair


75 Ω between pair


75 Ω between pair


75 Ω between pair


75 Ω between pair

29 Vin16 RF input #16

RF input

30 Vrf16 ground reference for RF in #1675 Ω between pair

RF GND 100,13,26 multi InGNDtop, InGNDmid, InGNDbot; respectively VDD multiple VDD +2.5V supply: pins 31,37,49,60,75,80,90,92 GND multiple GND 0V [VSS] supply: pins 34,41,45,51,63,66,84,95

32 VMbias DAC buffer amp bias pull-up R 33 ICbias Discriminator width adjust pull-up R -- see Fig. 10 35 Vbias x10 buffer amp bias pull-up R 36 VTbias Discriminator comparator bias pull-up R 48 ISbias Analog output Superbuff bias pull-up R 78 CMPbias on-chip ADC comparator bias pull-up R

Biases

83 TRGbias MLU comparator bias pull-up R

18

64 RCO Ripple Carry Out Sampling Freq. 65 ROVDD Ripple Oscillator VDD

see section 2.1

74 DAT0 Data bus bit 0 (LSB) 73 DAT1 Data bus bit 1 (count from 0) 72 DAT2 Data bus bit 2 71 DAT3 70 DAT4 69 DAT5 68 DAT6 67 DAT7 59 DAT8 58 DAT9 57 DAT10 56 DAT11 55 DAT12 54 DAT13 53 DAT14 Data bus bit 14

Data Bus

52 DAT15 Data bus bit 15 (MSB)

see section 5

91 DCLK DAC load -- serial reg transfer93 DIN DAC load input serial data DAC load 94 SCLK DAC serial shift register clock

see section 5.2

REG clear 89 REGCLR Reset DAC, MLU registers 85 GTMCLK GTM shift reg advance clock GTM load 86 GTMSIN GTM serial shift in data

see section 5.1/Table 9

87 nRUN not RUN -- assert high to freeze SCA values Trigger 88 LLtrig Low Level trigger -- MLU threshold exceeded 46 CAL Calibration input 50 Aout Analog output (superbuffered) Analog 82 VBS x10 gain stage reference voltage 76 ADCclk SAR step increment 77 ADCstart initiate conversion

on-chip ADC

79 ADCclear clear ADC registers see section 4.3

38 ACclk Address Counter increment 12-bit counter 39 ACrst Address Counter reset 40 SPAR Enable Address counter output 42 Cena scaler Count enable 43 RESET Reset scalers 47 TSPY Trigger Spy select 61 SAd Select Address/DAC 62 DnA select DAC not ADC

see Table 4

Misc. Control

81 ESSO Establish Stable Sample Output

Table 11: Pin definition table for the STRAW3 chip. If available, cross-references are provided.

19

7.Packaging STRAW3 is being fabricated in a quantity of 40 die as part of a multi-project wafer service provided by MOSIS[12]. While bare die are available for probing, most applications benefit from having a professional assembly house do the wire bonding; in particular where the performance matters. From MOSIS lot # T39S, there are to be 39 STRAW3 packaged die and one unpackaged die for probe testing. The bonding diagram as required by MOSIS is shown in Figure 15. Inasmuch as possible (without using a mechanical CAD package), this drawing is to scale. This wire bonding frame shown maps to a 100-pin Thin Quad Flat Pack (TQFP) package, available from two different vendors[13] and used by MOSIS. Note that the TQFP definition is a hard metric definition as per JEDEC standard, with pin pitch defined as 0.5mm.

7mm3.2mm

MOSIS ID

Figure 15: Bonding diagram for the STRAW3 die in a 100 lead TQFP package.

20

21

8.References 1. The ANtarctic Impulsive Transient Antenna [ANITA] Collaboration. For updated information, please see:

http://www.phys.hawaii.edu/~anita 2. A proposal for a SAlt Sampling Array (SALSA), the feasibility of which has been studied and published:

http://www.arxiv.org/abs/hep-ex/0108027 3. G. Varner et al., article 4858-31, SPIE Astronomical Instruments and Telescopes Conference 2003, August 2003 ,

available on-line as: http://www.phys.hawaii.edu/~idlab/publications/4858-31.pdf 4. Tektronix, Agilent and LeCroy all make digital signal oscilloscopes with required specs at >= few k$/channel for

comparable performance. 5. Acqiris Corporation: http://www.acqiris.com 6. Acqiris DC241, 1GHz bandwidth, 2-4 GSa/s, approx. 20W/channel 7. 2003 Antarctic balloon campaign: http://www.phys.hawaii.edu/~anita/antarctica03.html 8. STRAW3 schematics: http://www.phys.hawaii.edu/~idlab/project_files/salt/docs/STRAW3schematics.pdf 9. LABRADOR details: http://www.phys.hawaii.edu/~idlab/project_files/anita/docs/LABRADOR_Review.pdf 10. DALI Rev.B schematics: http://www.phys.hawaii.edu/~idlab/project_files/salt/docs/DALIREVB.pdf 11. Phys. Rev. Lett. 86 (2001) 2802-2805. Available on-line: http://www.arxiv.org/abs/hep-ex/0011001 12. MOSIS is a low-volume prototyping service provided through the University of Southern California and available at

discount price to academic institutions: http://www.mosis.org 13. A variety of packages are available: http://www.mosis.org/Technical/Packaging/Plastic/menu-pkg-plastic.html

http://www.arxiv.org/abs/hep-ex/0108027

http://www.acqiris.com/

http://www.phys.hawaii.edu/~anita/antarctica03.html

http://www.phys.hawaii.edu/~idlab/project_files/salt/docs/STRAW3schematics.pdf

http://www.phys.hawaii.edu/~idlab/project_files/anita/docs/LABRADOR_Review.pdf

http://www.phys.hawaii.edu/~idlab/project_files/salt/docs/DALIREVB.pdf

http://www.arxiv.org/abs/hep-ex/0011001

http://www.mosis.org/

Self-Triggered Recorder for Analog Waveforms v.3 (STRAW3...

Documents

Transcript of Self-Triggered Recorder for Analog Waveforms v.3 (STRAW3...