Self-timed and asynchronous design

Digital Integrated Circuits © Prentice Hall 1995Timing

Self-timed and asynchronous design

Functions of clock in synchronous design

1) Acts as completion signal2) Ensures the correct ordering of events

Truly asynchronous design

2) Ordering of events is implicit in logic1) Completion is ensured by careful timing analysis

Self-timed design

1) Completion ensured completion signal2) Ordering imposed by handshaking protocol


Self-timed pipelined datapath

R2 OutF2In

tpF2

Start Done

R1 F1

tpF1

Start Done

R3 F3

tpF3

Start Done

Req Req Req Req

Ack Ack Ack ACKHS HS HS


Completion Signal Generation

LOGIC

NETWORK

DELAY MODULE

In Out

Start Done

Using Delay Element (e.g. in memories)


Completion Signal Generation

Using Redundant Signal Encoding


Completion Signal in DCVSL

PDN

B0

PDNIn1In1In2In2

B1

Start

Start

VDD VDD

DoneB0

B1


Self-timed Adder

P0

C0

P1

G0

P2

G1

P3

G2 G3

VDD

Start

Start

P0

C0

P1

K0

P2

K1

P3

K2 K3

VDD

Start

Start

C0 C1 C2 C3 C4 C4

C4C0 C1 C2 C3 C4

VDD

Start

C4

C3

C2

C1

C4

C3

C2

C1

Start Done

(a) Differential carry generation

(b) Completion signal


Hand-shaking Protocol

Req

Ack

DataSENDER RECEIVER

Senders actionReceivers action

Req

Ack

Data

cycle 1 cycle 2

¿ ¿

¡

¬

(a) Sender-receiver configuration

(b) Timing diagram

Two-Phase Handshake


Event Logic — The Muller C-element

C

A

B

F

A B Fn+1

0011

0101

0FnFn

1

(a) Schematic (b) Truth table

VDD

FA

B

QS

R

A

B

F

Static

Dynamic


2-phase Handshake Protocol

C

Sender

logic

Receiver

logic

Data

Data Ready

Req

Ack

Data Accepted

Handshake logic


Example: Self-timed FIFO

C C

R1In Out

En

Acki

Reqi

R2 R3

CReq0

Acko

Done


4-phase Handshake Protocol (or RTZ)

Sender’s ActionReceiver’s ActionReq

Ack

Data

cycle 1 cycle 2

¿ ¿

¡

¬

Ð

ƒ


4-phase Handshake Protocol -Implementation

C

Sender

logic

Receiver

logic

Data

Data Ready

Req

Ack

Data Accepted

C

Handshake logic

S


Asynchronous-Synchronous Interface

Asynchronous

SystemSynchronous System

f

fin

Synchronization


A Simple Synchronizer

Vin

Vout

• Data sampled on Falling Edge of Clock

• Latch will eventually Resolve Signal Value,but ... this might take infinite time!


Synchronizer: Output Trajectories

Vin

VIH

VIL

Undefined VMS

t

1

0

Single Pole Model for Flip-Flop


Simulated Trajectory versus One Pole Model

SimulatedEstimated

0 0.2 0.4 0.6 0.8

time (nsec)

2.2

2.4

2.6

2.8

V (V

olt)


Mean Time to Failure


ExampleTf = 10 nsec = TTsignal = 50 nsectr = 1 nsect = 310 psecVIH - VIL = 1 V (VDD = 5 V)

N(T) = 3.9 10-9 errors/secMTF (T) = 2.6 108 sec = 8.3 yearsMTF (0) = 2.5 sec


Cascaded Synchronizers Reduce MTF

Sync Sync Sync

In OutO1 O2


Arbiters

Req1

Req2

Req1

Req2

Ack1

Ack2Arbiter

Ack1

Ack2

(a) Schematic symbol

(b) Implementation

A

B

Req1

Req2

A

BAck1 t

(c) Timing diagramVT gap

metastable


Synchronization at System Level

Reference clock

PC board

Chip 1 Chip 2

Logic Logic

I/O Data

1’

2’

1“

2“

Crystal-basedclock-generator

Clo

ckG

ener

ator

Clo

ckG

ener

ator


Skew of Local Clocks vs Reference

’

"

’

"

(a) Skew of local clock signalswith respect of reference clock.

(b) Local clock signals as produced

by PLL based clock generator.


Phase-Locked Loop Based Clock Generator

Phasedetector

Chargepump

Up

Down

Loopfilter

VCO

Clock decode &

buffer

Divide byN

Reference clock

Localclock

1 2 ...

Vcontr

Acts also as Clock Multiplier

Up

Down


Ring Oscillator0 1 2 N-1

In

VDD

M3

M1

M2

M4

M5

VDD

M6

Vcontr

(a) VCO

(b) Current starved inverter

Iref Iref


Example of PLL-generated clock

Self-timed and asynchronous design

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