Selected Seminar vlsi

554 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 8, NO. 3, AUGUST 2012

Simulink Modeling and Design of an EfficientHardware-Constrained FPGA-Based

PMSM Speed ControllerBogdan Alecsa, Marcian N. Cirstea, Senior Member, IEEE, and Alexandru Onea, Member, IEEE

Abstract—The aim of this paper is to present a holistic ap-proach to modeling and field programmable gate array (FPGA)implementation of a permanent magnet synchronous motor(PMSM) speed controller. The whole system is modeled in theMatlab Simulink environment. The controller is then translatedto discrete time and remodeled using System Generator blocks,directly synthesizable into FPGA hardware. The algorithm isfurther refined and factorized to take into account hardwareconstraints, so as to fit into a low-cost FPGA, without significantlyincreasing the execution time. The resulting controller is thenintegrated together with sensor interfaces and analysis tools andimplemented into an FPGA device. Experimental results validatethe controller and verify the design.

Index Terms—Field programmable gate array (FPGA), per-manent magnet synchronous motor (PMSM), simulink, systemgenerator.

I. INTRODUCTION

M ODERN FPGA devices offer a multitude of resources,thus moving forward from their original intended uti-

lization: implementing glue logic in complex digital systems.Nowadays, the whole complex digital system can reside into thefield programmable gate array (FPGA), leading to the concept ofsystem on a programmable chip (SoPC). However, the main ad-vantage FPGAs offer is the possibility to implement algorithmsdirectly into hardware, maintaining the parallelism of the algo-rithm in the implementation and thus minimizing the executiontime. Consequently, the FPGA utilization in industrial controlapplications became the subject of intensive research [1], [2].

There are many approaches regarding both the controller type(ranging from neural networks [3]–[5] and fuzzy logic [6], [7]to classical PID (proportional-integral-derivative) based controlalgorithms) and the implementation (ranging from pure hard-ware implementations [3] to combined hardware-software [6],[8] or pure software solutions using soft processor intellectualproperty (IP) cores [1], [9], [10]).

Manuscript received December 02, 2011; revised January 30, 2012; acceptedMarch 22, 2012. Date of publication April 06, 2012; date of current version July23, 2012. Paper no. TII-11-0970.

B. Alecsa and A. Onea are with the Automatic Control and Applied Infor-matics Department, “Gh. Asachi” Technical University of Iasi, 700050, Ro-mania (e-mail: [email protected]; [email protected]).

M. N. Cirstea is with the Department of Computing and Technologyt, AngliaRuskin University, Cambridge CB1 1PT, U.K. (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TII.2012.2193891

Another key factor, which contributed to the successful adop-tion of FPGA-based solutions, is the availability of a wide rangeof design tools [1], [11]. For example, the possibility to designthe whole system in Matlab Simulink, at a high level of abstrac-tion, and simulate it with bit and cycle accuracy, offers a highdegree of confidence in the “correct first time” operation of thecircuit [12].

A short overview of the literature regarding FPGA-based con-trollers for electric motors will be presented in the next para-graphs, aiming to highlight the space this paper tries to fill in.Although references [11]–[14] partly review this domain, newerliterature will be considered. In [3], a “holistic” approach is con-sidered for modeling and FPGA implementation of a sensorlesscontroller for the induction motor. Using a state-space observerand a controller based on neural networks, the authors presentthe modeling of the whole system (including the motor, thus theterm “holistic”) using VHDL. After validation through simula-tion, the controller was experimentally verified. In [15], the al-gorithm for direct hardware implementation of neural networksis presented in detail.

In [6], the authors propose a speed control system for a perma-nent magnet synchronous motor (PMSM) based on hardware/software partitioning: an adaptive speed controller, based onfuzzy logic, was implemented by software running on a NIOSII soft processor, while the current controllers, with faster dy-namics, were implemented in hardware. In [7], the same au-thors propose a hardware implementation of the adaptive fuzzycontroller, this time applied to a permanent magnet linear syn-chronous motor. Another example of hardware/software parti-tioning is given in [16], where a multi-axis motion controlleris implemented on a DSP (digital signal processor)/FPGA plat-form: the servo control loop (current and position/velocity con-trol) was implemented in hardware on FPGA, while the trajec-tory generation was done by software on the DSP.

In [17], a sensorless controller for the induction motor ispresented, using Direct Torque Control (DTC) and a state ob-server. The controller was designed in LabView FPGA and im-plemented on a National Instruments RIO PXI-7831R board,into a Virtex-II family FPGA.

In [18], a two axes motion control system is presented,partitioned between software and hardware: the PMSM currentcontrol loops are implemented in hardware, while the speedloops and the trajectory generation are based on software. Asimilar system is presented in [8], where PID speed controllersfor DC motors were implemented as hardware modules, whilethe multi-axes trajectory generation was performed by soft-ware on a MicroBlaze soft processor. It is worth noticing

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ALECSA et al.: SIMULINK MODELING AND DESIGN OF AN EFFICIENT HARDWARE-CONSTRAINED FPGA-BASED PMSM SPEED CONTROLLER 555

the speed controllers, designed in VHDL, were validated bySimulink-ModelSim co-simulation.

In [19], a simple yet effective control method for BLDC(brushless DC) motors is presented. The speed is controlledby using only two values for the PWM duty cycle, leading toa very economic implementation. In [20], the stability of theproposed method is further analyzed.

In [21] and [22], a control system for a PMSM associatedwith an analog position resolver is presented. Hysteresis cur-rent controllers are implemented into the FPGA for the threephases of the motor, together with a module for resolver sig-nals processing, based on the CORDIC (coordinate rotation dig-ital computer) algorithm. It is worth noticing the target FPGA(AFS600 Fusion produced by Actel) integrates analog to dig-ital conversion peripherals: analog to digital converter (ADC),analog prescalers, analog multiplexer. The emergence of suchchips highlights a move of the FPGA vendors toward the em-bedded market, dominated by microcontrollers.

In [23], the authors present the design in Simulink, usingthe DSP Builder software from Altera, of a PMSM controlsystem. The system employs hysteresis current controllers anda PI speed controller and uses 56 of the DSP blocks (9 9 bitswide) of an Altera Stratix II EP2S60F1024C4 FPGA.

In [24], a sensorless controller for a synchronous motor is pre-sented, using PI current controllers and sinusoidal PWM. Therotor speed and position are estimated by using the extendedKalman filter, a very demanding algorithm due to the severalmatrix multiplication and inversion operations it requires. Thealgorithm has been optimized and factorized for efficient FPGAimplementation, finally occupying 36 hardware multipliers (18

18 bits).In [25], the authors present a sensorless control system for

the PMSM, using high-frequency signal injection to estimatethe momentary stator inductance. A digital PLL (phase-lockedloop) is employed for signal processing. Both the PLL and thespace vector modulation (SVM) algorithm use CORDIC tocompute the needed trigonometric functions.

In [10], a comparison between a hardware implementationand a pure software implementation running on an ARMCortex-M1 soft processor is presented, for the case of a PMSMhysteresis current controller. Coordinate transforms and aresolver signal processing unit were also implemented.

In [26], a reusable IP cores library for electrical vehicle (EV)propulsion control is presented. The library is organized hierar-chically, having at the base an arithmetic unit for matrix-vectormultiplication. As a case study, the control of an EV equippedwith induction motors is presented.

In [27], a sensorless control system for a PMSM is presented,partitioned between hardware and software: the PI current con-trollers, the coordinate transforms, the SVM algorithm and theposition sliding mode observer were implemented in hardware,while speed estimation and control are performed by softwarerunning on a NIOS II processor.

In [28], a control system for an induction motor supplied byan inverter bridge through a resonant circuit is presented. Thesystem is described in AHDL (Altera HDL) and uses 76 hard-ware multipliers (9 9 bits).

From this short literature review, some conclusions can bedrawn: (i) From [6], [8], [18], and [27], where only parts of the

controllers are implemented in software, results that hardwareimplementation of algorithms is the obvious choice for high de-manding applications; software implementations are preferredfor tasks with less stringent computation time constraints, orwhen reuse of existing code is desirable [9]. Moreover, in [10], adirect comparison is made between hardware and software im-plementations, highlighting the hardware advantages. In [29],comparison is made between an FPGA based hardware imple-mentation and a DSP based software solution: the hardware so-lution is 11 times faster than the software, leading to a muchhigher controller bandwidth. In [1], the comparison is extendedto a MicroBlaze soft processor implementation, which is evenslower than the DSP implementation. (ii) The vast majority ofthe reviewed papers (except [3], [23]) lack a holistic modelingof the control system: there is a fracture between the design andsimulation of the controller and drive, on one hand, and the de-sign of the FPGA implementation, on the other hand. In [1], ahardware in the loop (HIL) validation step is proposed to fill inthis gap. (iii) Most of the reviewed controllers employ a largequantity of the FPGA resources and need a serious revision forimplementation in low cost devices, with a limited number ofhardware multipliers. Only in [21], [22], [24], and [26] are takensteps to apply the algorithm architecture adequation (AAA) op-timization strategy, so as to minimize the usage of critical re-sources. (iv) It can be considered that the state of the art inFPGA hardware design is based on hardware description lan-guages (HDL), as they are employed in most of the reviewedpapers. As this design methodology resembles to software de-velopment, it has been proven to lead to a similar degree of faultsin the implementation [30]. However, modern design tools, likeLabView FPGA [17], [31], DSP Builder [23] or System Gener-ator [32], [33] are gaining momentum. It has been proven [32]that System Generator can lead to comparable results in termsof obtained speed as HDL description for complex designs. In[33], both the VHDL and the System Generator designs of anadaptive filter show similar performance in terms of speed andarea.

This paper will thus try to fill in the gap found in the existingliterature: it proposes a holistic modeling of a PMSM speed con-trol system in the Matlab Simulink environment, which allowsvalidation by simulation of the controller model, as well as ofthe FPGA hardware; it also takes into account severe hardwareconstraints, leading to a very low cost FPGA implementation.The steps to be followed to get from a continuous time con-troller model to a discrete, FPGA synthesizable model, based onSystem Generator blocks, are outlined. The algorithm is refinedto fit into a low-cost FPGA, keeping its inherent parallelism.The short execution time is of paramount importance in orderto use a low-cost current measurement scheme. The system isexperimentally tested and is proved to work correctly.

II. FPGA CONTROLLER DESIGN

A. Motor and Controller Modeling

The PMSM is usually modeled in the rotor synchronous ro-tating frame ( frame), as this approach eliminates the time-varying inductances from the voltage equations in the statorframe. The motor model, as well as the controller derivation,


has been presented in [34]. Suffice it to say here that the speedcontrol system consists of two PI current controllers, a com-bined PI-P speed controller (double speed feedback loop) [35],an axes decoupling and back electromotive force (BEMF) com-pensation module, direct and inverse coordinate transforms.

A motor model from the SimPowerSystems Simulink li-brary was used for simulation. The controller was designedin Simulink and the control parameters were validated bysimulation. It is worth mentioning that the resulting currentclosed loop systems are described by first-order transfer func-tions, while the speed closed-loop system is described by asecond-order transfer function.

In reality the motor is fed by a three phase voltage sourceinverter (VSI). The VSI is controlled using space vector modu-lation (SVM) and the SVM algorithm is applied directly to the

voltage components. For the purpose of simulation, in afirst phase, the SVM algorithm was replaced with an to

coordinate transform and the resulting three phase volt-ages were fed to the motor model.

For the algorithm discretization, the SVM has a significantimpact: it sets the maximum sampling rate, which is fixed by theSVM pulse width modulation (PWM) carrier frequency. This,in turn, is limited by the switching characteristics of the VSIpower transistors. The carrier frequency was chosen in this caseas 20 kHz, meaning a sampling period µs.

B. Controller Discretization

After the simulation in “continuous time” has validated thecontroller, this must be discretized to enable digital implemen-tation. The discrete operations to be performed are shortly de-scribed in the following.

The to transform consists of two consecutive trans-forms, to and to

(1)

(2)

The axes decoupling block performs the followingoperations:

(3)

The to transformation is exactly the same as theto transformation, but is applied to voltages

(4)

The PI controllers were discretized using the Tustin approxi-mation. Two implementation choices were considered for the PIcontrollers. One is based on the PI transfer function seen as aninfinite impulse response (IIR) filter, described by the equation

(5)

where is the integral gain, is the proportional gain, isthe controller input and is the controller output.

The other implementation considers the P and I componentsof the controller in parallel. This is expressed as

(6)

where is the output of the integral part and the same nota-tions as in (5) are kept for the rest of the symbols. Equation (6)has the advantage that it offers the possibility to implement ananti-windup strategy for the integral part. The first term on theright-hand side of (6) corresponds to the P part, while the restcorresponds to the I part.

Considering the controller gain factors and sampling periodfixed, the coefficients for multiplications in (5) and (6) can beprecomputed. Comparing (5) and (6), it is clear that (5) is easierto implement, as it needs only two multiplications and two ad-ditions. Equation (6) needs two multiplications, but three addi-tions. If the result of each operation is registered, this also meansan additional step in computation. However, integral windup canbe very inconvenient.

There are two commonly used anti-windup strategies: con-ditional integration and tracking back calculation. In [36] and[37], specific strategies for PI (PID) speed controllers are pro-posed. However, for the double loop PI-P controller [35] usedhere, conditional integration with the condition for integrationobtained from the second (P) loop shows very good behavior.

The discrete equations were implemented using System Gen-erator blocks and fixed point arithmetic. The 18 bit precisionwas used for all multiplications (to make use of the 18 18embedded multipliers of the low cost FPGA), whereas addi-tions were limited to 24 bits. All limitations were applied usingadditional hardware for saturation on overflow, thus ensuringstable system behavior even when the representation limits arereached. The fixed point position is different in each block, de-pending on the magnitude of the signals the block works with.This is another great advantage of the FPGA implementationover a DSP (or any other processor) implementation: the com-puting architecture is not fixed, it can be tailored in any point toaccommodate the task at hand.

The design was verified by simulation at this point. Thesimulation was performed with a sample time of 50 µs for theSystem Generator blocks. The discrete controller was simulatedtogether with the continuous one. The differences between sig-nals of the continuous model and the ones of the discrete modelwere computed and analyzed in Simulink, thus validating thealgorithm. The errors introduced by the discretization process(quantization errors, errors due to integrators Tustin approxi-mation, errors due to zero-order hold outputs) were evaluatedand proved acceptable. For example, for a 200 rad/s stepincrease of the speed and a simulation length of 0.05 s, whichis enough to reach steady state, the speed root mean squaredeviation (RMSD) between the continuous and the discretemodel is around 0.25 rad/s and the axis current RMSD isaround 0.008 A. Simulations with different word lengths wereperformed. No significant improvement of the RMSD wasobserved for higher word lengths, so the 18 bits precision waskept. The decrease of the sampling period has a much higher


Fig. 1. Simulink implementation of the control algorithm.

impact on RMDS improvement, but it is not an option for thesystem discussed: the sampling frequency is limited by the VSIpower transistors switching characteristics.

Although the System Generator blocks are directly synthesiz-able in FPGA hardware, the algorithm can not be implementedin this form for two main reasons: (i) The algorithm would needa 20 kHz clock, derived from the 50 MHz system clock, and theresults are ensured to be valid synchronously to this clock. Ofcourse, the results are available much earlier, but the rest of thesystem should take care of valid results reading. Additionally,it is not good design practice to have multiple clock signals, es-pecially if derived by combinational means. (ii) The algorithmin this form would use independent hardware resources for alloperations. While this is not an issue for logic or add/subtractoperations, it is certainly a problem when limited hardware re-sources come into account, like multipliers or Random AccessMemory (RAM) blocks. Additionally, many operations dependon the result of other operations, so they could use the samehardware sequentially.

For these reasons, the algorithm was factorized and trans-formed into a sequential automaton driven by the system clock,keeping a high degree of parallelism to ensure a very short ex-ecution time.

C. Control Algorithm Implementation

Through the factorization process, the algorithm was reorga-nized to employ only four multipliers. The other operations willbe performed by dedicated hardware, but multipliers are a scarceresource on low-cost FPGAs. Analyzing the algorithm, it wasobserved that it only needs four multipliers, while keeping itsinherent parallelism [34].

The problem with sharing the multipliers between severalfunctional blocks resides in the increased complexity of thedatapath and the datapath controller. Each input of the fourmultipliers is fed by a six inputs multiplexer. The inputscorrespond to the utilizations of the multiplier. The datapathcontroller performs the multiplexer selection and saves theselected values into the multiplier input registers. The outputof each multiplier is distributed to all the functional blocksthat use it. The datapath controller ensures the multiplicationresult is saved into the correct functional block by enabling thecorresponding register.

The Simulink implementation of the control algorithm is pre-sented in Fig. 1. All the functional blocks were implementedusing System Generator components. Only the datapath signalsare explicitly shown on the figure, signals flowing from onefunctional block to the other. There are links between each func-tional block that needs multiplication operations and the multi-plication engine. Also, there are links from the datapath con-troller to each functional block. These links were implementedusing “Goto” and “From” Simulink signal routing blocks.

For the datapath signals, the number format can also be ob-served in Fig. 1. The signals between functional blocks are 18bits wide, represented in signed fixed point format. For example,“Fix_18_15” for signal x_ia means the current in the axis(flowing in the stator coil) is represented as a signed valueon 18 bits, using 15 bits for the fractional part and 3 bits for theinteger part (including the sign bit). Although, as it will be dis-cussed later on, the currents are measured using 12 bit ADCs,the ADC value must be processed to obtain the current value,and the processing is performed on 18 bits. The multiplier en-gine multiplexer selection signal, x_mux_sel, is unsigned in-teger, 3 bits wide: “Ufix_3_0”. The datapath controller triggersignal is a logic signal, 1 bit wide: “Bool”. As already stated, therepresentation format varies along the datapath according to thevalue range of the results of various operations. For example,the motor speed may vary from around 750 to 750 rad/s, re-quiring 11 bits for the integer part, while the motor currents arelimited to 2 A, needing only 3 bits for the integer part.

The datapath controller is a Moore type finite-state machine(FSM). The FSM remains in zero state until the algorithm istriggered. Afterwards, the FSM passes unconditionally fromone state to the next, in each state activating one state variable(“one hot” encoding). The FSM sequences in fact the opera-tions in the functional blocks shown in Fig. 1. The FSM has26 states, so the algorithm needs 26 clock cycles to complete.Fig. 2 presents the FSM state diagram. The functional blocks towhich the variables refer in each state are codified in the figureby circles with different fill patterns and listed below. Someoverlapping of operations in different functional blocks canbe observed, accounting for parallel execution by independenthardware (for example, in state 11, multiplier cells 1 and 2 havebeen used by the speed PI block and multiplier cells 3 and 4have been used by the decoupling block, and the multiplicationresults are saved in different registers in these blocks by the


Fig. 2. State diagram of the FSM.

state variable signal). Although “one hot” encoding was used,in each of the overlapping states the state variable was giventwo names, for clarity, each one corresponding to the usageof the variable (for example, the state variable of state 11 isnamed PI_P_w_step4 and axes_dec_step2). Besides the statevariables, the FSM has an additional 3 bit output, msel, used toselect the appropriate input to the multiplier cells. This is thex_mul_sel signal from Fig. 1. The msel value is changed in thenext state after it was used, specifically after the save_mul_selsignal was asserted. The save_mul_sel signal is employedto save the input values to the multiplier input registers. Allstate variable names (except save_mul_sel, which is recurring)reflect their connection to a functional block (trans1—theto transform, trans2—the to transform, PI_P_w—thePI-P speed controller, axes_dec—the axes decoupling block,

PI_qd—the and axes current controllers, trans3—the totransform). In the last state, a ready signal is asserted, to

signal the algorithm execution has finished.The datapath controller was implemented using a Moore

State Machine from the Xilinx Reference Blockset of SystemGenerator. The state machine is described by the transition andoutput matrixes, which are translated to read-only memories(ROM). For implementation, distributed RAM is employed.

The approach presented here is different from others by thefact that the whole datapath of the algorithm is controlled bythe same FSM. While a modular approach with each functionalblock controlled by its own FSM (as in [14], [22], and [24]) mayoffer more chances for reuse, it eliminates the possibility of ex-ecution overlapping. As it can be seen in Fig. 2, this overlappingcan be significant (more than 20% of the FSM states).


Fig. 3. The PI-P speed controller with anti-windup mechanism.

Fig. 3 presents the internal structure of the PI-P speed con-troller block, as an example. The links to multiplier cells 1 and2 can be observed, as well as the sequencing registers and thedatapath controller signals. The upper part of Fig. 3 presents thePI controller, implementing (6). The error input signal is calcu-lated from the reference speed and the measured speed. It is thenmultiplied by . At the same time, it is added to the previoussample time error and multiplied by . This result is thenconditionally added to the previous value of the integral part ofthe controller. At the end, the resulted integral part and the pro-portional part are added together, giving an intermediate speedvalue to be used by the second P controller. For multiplication,the multiplier cells 1 and 2 are used. Reinterpret blocks are usedto make the number representation transparent for the multipliercells, because different utilizations employ different formats. Atthe input in the multiplier cell, the fixed point is forced to 0, andat the output is replaced in the right position.

The lower data flow in Fig. 3 is the P controller. It computesthe intermediate speed error, using the measured speed and theoutput of the PI controller, then multiplies it by the gain factorand saves it to the Reg8 register. The registered value is lim-ited (with saturation) to 18 bits. In case saturation is reachedat this point (the unsaturated and the saturated values do notmatch), the integration in the PI controller is deactivated, toavoid windup. Because the feedback for the conditional inte-gration comes from the second loop, the behavior of the wholespeed controller is much improved (as will be shown in the ex-perimental results). The P controller uses also the multiplier cellnumber 1. All the operations are sequenced by the datapath con-troller signals, shown on the left side of Fig. 3. The same prin-ciple is used for all the functional blocks in Fig. 1.

The current PI controllers were implemented using (5), be-cause it is easier to implement. As the output values of thesecontrollers are saturated on overflow, the saturation acts also asan anti-windup mechanism: the command is limited to the max-

imum value allowed by the format. This strategy is not usable forthe speed controller, because the number format allows valuesmuch larger than the maximum obtainable speed.

D. Space Vector Modulation (SVM)

As already stated, the voltage is applied to the motor usingSVM. A geometric version of the SVM algorithm was used,which needs only simple comparisons and three sets of for-mulae to compute the PWM threshold values (it does not needtrigonometric functions). The algorithm, presented in [38], wasredesigned to use only two multipliers. It is a “5 step” versionof the SVM, making use of only one of the null vectors, the 000vector. Although this puts more stress on the low side transis-tors of the VSI, it has the great advantage it prolongs the pe-riod in which the stator currents can be measured. This is dueto the fact that a low cost current measurement scheme was em-ployed, measuring in fact the voltage drop over shunt resistorsconnected in series to the low side VSI transistors. In order toget correct current measurement, at the instant of measurement,the current flowing in the low side transistors must be the cur-rent flowing in the stator coils. That is, the current measurementmust be synchronized with the 000 null vector application bythe SVM.

The SVM algorithm was designed as an independent module,also by the datapath-controller paradigm. It needs ten clockcycles to complete. The modulator was tested standalone, fedwith sinusoidal voltages. The VSI outputs were filtered bypassive low pass filters and observed using an oscilloscope.Fig. 4 presents an oscilloscope capture with the VSI filteredsignals: the three phases and the neutral point. The obtainedcharacteristic signals are equivalent to sinusoidal signals withminimum magnitude signal injected to the neutral point [39].

The PWM circuit used by SVM was designed to provide 15bits resolution (1.3 ns time resolution) using the phase shiftpossibility of the digital clock managers (DCM) present on the


Fig. 4. VSI filtered signals obtained by SVM.

TABLE IPITTMAN 3441 PMSM PARAMETERS

FPGA [40]. This way, the controller is not in danger of limit cy-cling, as the resolution of the command signals is higher thanthe resolution of the feedback signals (the ADCs have 12 bitsresolution).

III. EXPERIMENTAL RESULTS

The presented design was synthesized and implemented ina low cost XC3S500E Spartan-3E FPGA, produced by Xilinx.Besides the control algorithm and sensors interfacing hardware,a ChipScope virtual logic analyzer core was inserted in theFPGA and used to capture internal signals. The ChipScopecore is driven by a 20 kHz clock signal. This way, the sensorinterface was debugged and the controllers were verified. Thecontroller was tested with a 19.1 V 3441 Pittman PMSM,fed by a PM50 Technosoft three phase inverter. The motorcharacteristics are given in Table I. It is a low-power motor, buthas the advantage of a very low inertia. Thus, it makes a goodcase study for a high bandwidth controller.

The control system is synchronous, with a system clock of50 MHz. As previously stated, the control algorithm executionneeds 26 clock cycles. The SVM algorithm takes ten clockcycles to complete, while the current acquisition using theADCS7476 device (ADC with serial interface) needs 74 clockcycles for data transfer. So the whole execution takes 110clock cycles, meaning 2.2 µs at 50 MHz clock rate. The highcomputation speed is essential for the system to be able toacquire the currents in the same sample period in which it

Fig. 5. Speed controller step response (without anti-windup mechanism).

Fig. 6. Speed controller step response (with anti-windup mechanism).

derives the command signal. For the current loop experimentalverification, refer to [34].

Figs. 5 and 6 present speed signal captures from the experi-ments using the Chipscope core. This way, a comparison can bemade between the controller without anti-windup mechanismand the one with anti-windup mechanism, for a step referencechange on speed from 0 rad/s to 400 rad/s. In both cases, the risetime is set by the motor dynamics (the torque to inertia ratio) toabout 10 ms. In Fig. 5, the overshoot due to integral windup issignificant. However, the response in Fig. 6 exhibits no over-shoot whatsoever.

The presented controller occupies only 10 of the 20 FPGAembedded multipliers, 36% of the logic resources, and 1 RAMblock. So a much cheaper FPGA device could be used, or ahigher resolution in computation can be achieved.

IV. CONCLUSION

A new holistic modeling of an FPGA speed controller forPMSM was presented, using Matlab Simulink and SystemGenerator. The approach presented allows the modeling of thecontroller and the controlled system in the same environment,leading to a real time FPGA implementation. A clear method-ology for controller design in System Generator was proposed,and the steps followed in order to obtain a synchronous factor-ized design from a first iteration are presented.

The key achievements are related to the effective use of theon-chip hardware multipliers, by the original design of the con-trol algorithm to match the hardware resources, keeping its in-herent parallelism. Thus, high speed of control signal processing


is possible. Further contributions are related to the integration ofthe sensor interfaces and logic analyzer tools together with thecontroller, those enabling the holistic hardware verification ofthe system.

The controller was implemented in a low-cost FPGA and wasable to execute in only a fraction of the sample period (the wholeexecution takes 110 clock cycles, meaning 2.2 µs at 50 MHzclock rate), thus enabling a cost effective current measurementscheme. An efficient anti-windup strategy was also defined, al-lowing effective motor control limited only by the mechanicalpart dynamics.

Experimental results have proven the correct operation of thecontroller, thus validating the viability of the design method.One drawback of the design method is given by the simula-tion requirements: after algorithm factorization and redesignusing the datapath/controller paradigm, it must be simulated inSimulink with a fixed step, given by the clock period. Specif-ically, the simulation must be performed with a step of 20 ns.This leads to a very costly simulation in terms of processingtime and required memory on the host computer. However, theadvantage of validation by simulation is significant. Other vali-dation techniques suffer from the same drawback: in HIL, eventhough the simulation is performed on the FPGA, the input andoutput data must be generated by and analyzed on a host com-puter, the time to transfer the huge amount of data being com-parable to the simulation time for the proposed method.

It is expected that this methodology can be adapted for fu-ture use to a range of drive systems. A Simulink library basedon System Generator will be created, containing ready to useconfigurable modules for drives control, as current/speed/posi-tion controllers, SVM modules (different zero vector allocationschemes), sinusoidal PWM modules (different zero sequencesignal injection schemes). Also, future work will target com-putationally more intensive control algorithms, like predictivecontrollers [41], [42], that will take full advantage of the execu-tion speedup by parallelization that FPGAs can offer.

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[10] I. Bahri, E. Monmasson, F. Verdier, and M. E.-A. Ben Khelifa, “SoPC-based current controller for permanent magnet synchronous machinesdrive,” in Proc. IEEE Int. Symp. Ind. Electron., ISIE’10, Bari, Italy, Jul.2010.

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[12] E. Monmasson and M. N. Cirstea, “FPGA design methodology for in-dustrial control systems—A review,” IEEE Trans. Ind. Electron., vol.54, no. 4, pp. 1824–1842, Aug. 2007.

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[14] M.-W. Naouar, E. Monmasson, A. A. Naassani, I. Slama-Belkhodja,and N. Patin, “FPGA-based current controllers for AC machinedrives—A review,” IEEE Trans. Ind. Electron., vol. 54, no. 4, pp.1907–1925, Aug. 2007.

[15] A. Dinu, M. N. Cirstea, and S. E. Cirstea, “Direct neural-network hard-ware-implementation algorithm,” IEEE Trans. Ind. Electron., vol. 57,no. 5, pp. 1845–1848, May 2010.

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[17] J. Lis, C. T. Kowalski, and T. Orlowska-Kovalska, “Sensorless DTCcontrol of the induction motor using FPGA,” in Proc. 2008 IEEE Int.Symp. Ind. Electron., ISIE’08, Cambridge, U.K., Jun.–Jul. 2008.

[18] Y.-S. Kung, R.-F. Fung, and T.-Y. Tai, “Realization of a motion controlIC for x-y table based on novel FPGA technology,” IEEE Trans. Ind.Electron., vol. 56, no. 1, pp. 43–53, Jan. 2009.

[19] A. Sathyan, N. Milivojevic, Y.-J. Lee, M. Krishnamurthy, and A.Emadi, “An FPGA-based novel digital PWM control scheme forBLDC motor drives,” IEEE Trans. Ind. Electron., vol. 56, no. 8, pp.3040–3049, Aug. 2009.

[20] N. Milivojevic, M. Krishnamurthy, Y. Gurkaynak, A. Sathyan, Y.-J.Lee, and A. Emadi, “Stability analysis of FPGA-based control of brush-less DC motors and generators using digital PWM technique,” IEEETrans. Ind. Electron., vol. 59, no. 1, pp. 343–351, Jan. 2012.

[21] L. Idkhajine, A. Prata, E. Monmasson, and M.-W. Naouar, “System onchip controller for electrical actuator,” in Proc. IEEE Int. Symp. Ind.Electron., ISIE’08, Cambridge, U.K., Jun.–Jul. 2008.

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[26] R. de Castro, R. E. Araujo, and D. Feitas, “Reusable IP cores libraryfor EV propulsion systems,” in Proc. IEEE Int. Symp. Ind. Electron.,ISIE’10, Bari, Italy, Jul. 2010.

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[40] B. Alecsa, A. Tisan, and M. Cirstea, “High resolution 6 channels pulsewidth modulator for FPGA-based AC motor control,” in Proc. Int.Conf. Appl. Electron., AE’11, Pilsen, Czech Republic, Sep. 2011.

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Bogdan Alecsa received the B.Sc. degree in com-puter engineering from the “Gh. Asachi” TechnicalUniversity, Iasi, Romania, the M.Sc. degree in auto-motive embedded software from the “Politehnica”University of Timisoara, Timisoara, Romania, andthe Ph.D. degree in systems engineering from the“Gh. Asachi” Technical University, in 2011, with athesis on FPGA-based controllers for fast processes.

He is currently a Teaching Assistant with theAutomatic Control and Applied Informatics Depart-ment, “Gh. Asachi” Technical University. He has

previously worked for five years as a hardware engineer in the automotiveindustry. He has authored one technical book and has coauthored more than15 peer reviewed papers. His interests include hardware design of efficientFPGA-based control algorithms, embedded systems, and electric drives.

Dr. Alecsa has served as a Reviewer for the IEEE TRANSACTIONS ON

INDUSTRIAL INFORMATICS and the IEEE TRANSACTIONS ON INDUSTRIAL

ELECTRONICS since 2011.

Marcian N. Cirstea (M’97–SM’04) received theDegree in electrical engineering from TransilvaniaUniversity of Brasov, Romania, and Ph.D. de-gree in 1996 from Nottingham Trent University,Nottingham, U.K.

He is currently Professor of Industrial Electronicsand Head of the Computing and Technology Depart-ment at Anglia Ruskin University, Cambridge, U.K.,after previously working for De Montfort University,U.K. He has co-authored several technical books andover 120 peer reviewed papers, three of which have

received awards. His research is focused on digital controllers for power elec-tronics.

Prof. Cirstea has delivered six international tutorials on VHDL Design forPower Electronic Systems Modeling and FPGA Controller Prototyping. He isFounder and Past Chairman of the Electronic Systems on Chip Technical Com-mittee of the IEEE Industrial Electronics Society, Fellow of IET and Char-tered Engineer (CEng). He is Associate Editor for the IEEE TRANSACTIONS

ON INDUSTRIAL ELECTRONICS and the IEEE TRANSACTIONS ON INDUSTRIAL

INFORMATICS and was General Chair of IEEE Conferences (ISIE’2008, Cam-bridge, U.K., and OPTIM’2012, Brasov, Romania). He has coordinated a Euro-pean renewable energy project consortium.

Alexandru Onea (M’07) received the M.Sc. de-gree in electrical engineering from the InstitutulPolitehnic, Iasi, Romania, in 1987, and the Ph.D.degree in automatic control from the “GheorgheAsachi” Technical University, Iasi, in 1996.

He has over three years of industry experience.Since September 1991, he was with the ControlSystems Group at the “Gheorghe Asachi” TechnicalUniversity. In 1997, he was appointed AssociateProfessor at the Automatic Control and AppliedInformatics Department, “Gheorghe Asachi” Tech-

nical University, and became Full Professor in 2007. His research interestsinclude control of advanced electrical drives, control of hybrid electric vehicles,adaptive control, and embedded systems.

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