Sect-13

Section 13: Appendices

Appendix A - Device specifications

Appendix B - CAN Bus

Appendix C - PCB Layout diagrams

Appendix D - PCB Link selection details

Appendix E - UPS Module General Specifiication

S-12.fm5 - Issue 2 Dated 21/08/97 i

SECTION 13 - Appendices 7200 Series UPS Service Manual

ii S-12.fm5 - Issue 2 Dated 21/08/97

A:

Appendix A : Device Specifications

A.1 74HCT245 – Octal 3-state, non-inverting bus transceiver

The HCT245 is a 3-state non-inverting transceiver that is used for 2-way asyn-chronous communication between data busses. The device has an active-lowOutput Enable pin, which is used to place the I/O ports into high-impedancestates. The Direction control determines whether data flows from A-to-B or fromB-to-A.

Figure A-1: 74HCT245

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

Direction

A0

A1

A2

A3

A4

A5

A6

A7

Gnd

Vcc (+5V)

OE

B0

B1

B2

B3

B4

B5

B6

B7

2

3

4

5

6

7

8

9

1

19

18

17

16

15

14

13

12

11

Direction

A0

A1

A2

A3

A4

A5

A6

A7

Output

B0

B1

B2

B3

B4

B5

B6

B7

Enable

CONTROL INPUTS

Output Enable

Direction Operation

L L Data transmitted from bus B to bus A

L H Data transmitted from bus A to bus B

H X Busses isolated – (Hi-impedance state)

App-a.fm5 - Issue 2 Dated 21/08/97 A-1

Appendix A 7200 Series UPS Service ManualDevice specification

A.2 74HCT273 Octal D-type Flip-Flop

The HCT273 consists of eight D-type flip-flops with common Clock and Resetinputs. Each flip-flop is loaded with a low-to-high transition of the Clock input.Reset is asynchronous (i.e. at any time) and active low.


1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

Reset

Q0

D0

D1

Q1

Q2

D2

D3

Q3

Gnd

Vcc

Q7

D7

D6

Q6

Q5

D5

D4

Q4

Clock

2

4

7

8

13

14

17

18

11

1

3

5

6

9

12

15

16

19

Clock

D0

D1

D2

D3

D4

D5

D6

D7

Reset

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

INPUTS OUTPUTS

Reset Clock D Q

L X X L

H H H

H L L

H L X No change

H X No change

A-2 App-a.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual Appendix ADevice specification

A.3 Type 4052 Dual 4-channel Multiplexer

The 4052 device contains two 4-way multiplexer switches controlled by two ad-dress (select) inputs. Each switch is identified as “X” or “Y”. An ‘inhibit’ inputturns off both switches when set high.

Figure A-3: 4052 Multiplexer

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1Y

3Y

Y

4Y

2Y

Inhibit

Vee

Vss

Vdd

3X

2X

X

1X

4X

Sel (A)

Sel (B)

6

10

9

12

14

15

11

13

3

Inhibit

Select (A)

Select (B)

1X

2X

3X

4X

X

Y

INPUTS OUTPUTS

Inhibit A B X Y

L L L 1X 1Y

L L H 2X 2Y

L H L 3X 3Y

L H H 4X 4Y

H X X None None

1

5

2

4

1Y

2Y

3Y

4Y



A.4 74HC573 Octal D-type Flip-Flop

The 74HCT573 consists of eight D-type flip-flops with common Latch Enableand Output Enable inputs. Each flip-flop is loaded with a low-to-high transitionof the Latch Enable input. Output Enable is asynchronous and active low.


1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

O/enable

D0

D1

D2

D3

D4

D5

D6

D7

Gnd

Vcc

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Latch Enable

2

3

4

5

6

7

8

9

11

1

19

18

17

16

15

14

13

12

Latch Enable

D0

D1

D2

D3

D4

D5

D6

D7

Output Enable

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

INPUTS OUTPUTS

Output Enable Latch Enable D Q

L H H H

L H L L

L L X No change

H X X Hi-Z



A.5 SN75176A Differential Bus Transceiver

The SN75176 differential bus transceiver is designed for bi-directional data com-munication on multi-point bus transmission lines. It is designed for balancedtransmission lines and meets EIA Standard RS-422A.

Figure A-5: SN75176A

The device combines a 3-state differential line driver and a differential-input linereceiver, both of which operate from a single +5V power supply. The driver andreceiver have active-high and active-low enables, (DE) and (RE) respectively,that can be externally connected together to function as direction control.

The driver differential outputs and the receiver differential inputs are connectedtogether internally to form a differential I/O bus port which is designed to offerminimum loading to the bus whenever the driver is disabled. The receiver oper-ates on a differential input greater then 0.2mV, as shown in the above table.

These ports feature good common-mode noise rejection when used on a balanceline making them ideal for use over party-line applications.

1

2

3

4

8

7

6

5

RD

RE

DE

DI

Vcc

DD/RI

DD/RI

GND

Function Table (Driver)

Function Table (Receiver)

INPUTS OUTPUTS

Data In (DI) Data Enable (DE) DD/RI DD/RI

H H H L

L H L H

X L Hi-Z Hi-Z

DIFFERENTIAL INPUTS OUTPUTS

A – B RE RD

VID > 0.2V L H

-0.2V < VID < 0.2V L ?

VID < -0.2V L L

X H Hi-Z

1

2

3

4

7

6

RD

RE

DE

DI

DD/RI

DD/RIBUS

Driver

Receiver



A.6 SN75155 Line Driver and Receiver

The SN75155 is a line driver and receiver that is designed to satisfy the require-ments of the standard interface between data terminal equipment (DTE) and datacommunication equipment (DCE) as defined by EIA standard RS232.

A Response Control input (RTC) is provided for the receiver. A resistor, or resis-tor and bias voltage, can be connected between the Response Control input andground to provide noise filtering.

Figure A-6: SN75155

1

2

3

4

8

7

6

5

Vcc-

DA

RY

GND

Vcc+

RTC

DY

RA

1

8

REFERENCEREGULATOR

5

2

4

6

Vcc-

Vcc+

RA

DA

GND

RTC

7

3

DY

RY



A.7 MAX232 Dual EIA-232 Driver/Receiver

The MAX232 is a dual driver/receiver that includes a capacitive voltage generatorto supply EIA-232 voltage levels from a single +5V supply.

Each receiver converts the EIA-232 inputs to 5V TTL/CMOS levels. These re-ceivers have a typical threshold of 1.3V and a typical hysteresis of 0.5V, and canaccept ±30V inputs.

Each driver converts TTL/CMOS input levels into EIA-232 levels.

Figure A-7: MAX232

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

C1+

VS+

C1-

C2+

C2-

VS-

T2OUT

R2IN

Vcc

GND

T1OUT

R1IN

R1OUT

T1IN

T2IN

R2OUT

23

4

56

7

8

16

15

14

1312

11

10

9

VS+C1-

C2+

C2-VS-

T2OUT

R2IN

Vcc

GND

T1OUT

R1INR1OUT

T1IN

T2IN

R2OUT

1C1+

2Vcc -1.5VC1-

C2+

C2-

C1+

-2Vcc +1.5V



A.8 8251A Programmable Communications interface

Figure A-8: 8251A

A.8.1 Introduction

The 8521A is a Universal Synchronous/Asynchronous Receiver/Transmitter(USART) designed for use with a wide range of microcomputers (CPUs).

In a communication environment, the device converts parallel data on the systemdata bus into a serial format for transmission and also converts the incoming serialcommunication line data into parallel form acceptable to the data bus. In carryingout these transformations the 8251A also deletes or inserts ‘framing’ bits or char-acters that are required by the communication mode in use. Data is passed be-tween the ‘transmit’ or ‘receive’ sections and the ‘data bus buffer’ by means of aninternal 8-bit data bus, with the transfer between these sections being controlledby the ‘read/write control logic’ block at a rate determined by its clock input.However the serialised information is clocked into the ‘transmit buffer’ (from theinternal bus) and ‘receive buffer’ (from communications line) by independent ex-ternal clock signal – TxC and RxC respectively.

Like other I/O devices in a microcomputer system, the 8251A functional config-uration is programmed by the system’s software for maximum flexibility. Thus inaddition to the system data the 8251A also receives Mode/command words fromthe CPU which determines its operating parameters such as baud-rate, characterlength, number of start/stop bits, parity and synchronous/asynchronous mode ofoperation. The device differentiate between system data and Mode/commandwords by observing the state of its (C/D) input, as described below.

The 8251A has facilities that allow the CPU to read the status of the device at anytime during its functional operation – activated when (RD)=0 and (C/D) =1 (seetable below). Some of the bits in the status register have identical meanings to ex-ternal output pins, so that the 8251A can be used in a completely polled or inter-rupt-driven environment. The following information is available from the statusregister (described in more detail later):

TxE

CTS

SYNDET/BD

TxRDY

CS

C/D

RD

RxRDY

1

2

3

4

5

6

7

8

9

10

28

27

26

25

24

23

22

21

20

19

D2

D3

RXD

GND(Vss)

D4

D5

D6

D7

TxC

WR

D1

D0

Vcc(+5V)

RxC

DTR

RTS

DSR

RST

CLK

TxD

11

12

13

14

18

17

16

15

TxE

CTS

SYNDET

TxRDY

CS

C/D

RD

RxRDY

RxD

TxCWR

RxC

DTR

RTS

DSR

RST

CLK

TxD

DataBus

Buffer

ReceiveControl

TransmitControl

TransmitBuffer

(P to S)

DB0....DB7

ModemControl

ReceiveBuffer

(S to P)

Read/WriteControlLogic

InternalData Bus



• Transmitter section ready (TxRDY) (not identical to external TxRDY pin)• Receiver section ready (RxRDY)• Transmit buffer empty (TxE)• Parity error• Overrun error (CPU fails to read a character before the arrival of the next)• Framing error (stop/start bit detection error)• Synchronisation (SYNDET)• Data Set Ready (DSR)

A.8.2 Functional description

Following is a description of the 8251A device based on the block diagram at thetop of the previous page:

Data Bus Buffer

This tri-state, bi-directional, 8-bit buffer interfaces the 8251A to the system databus. All transmitted and received data passes though the buffer together with‘control words’ and ‘command words’.

Read/Write Control Logic

This functional block accepts inputs from the system control bus and generatescontrol signals for the overall device operation. It contains the ‘control word’ and‘command word’ registers that store the various control formats for the device’sfunctional definition. The control inputs are described below:

Chip Select (CS). This input allows the device to be individually selected fromother devices within its address range, and is active low. When this input is highit is not possible to read from (or write to) to the device, and its data bus outputsare driven to a high impedance state.

Read (RD). This input is taken low when the associated processor wishes toread the data held in the 8251A’s Data Bus Buffer.

Write (WR). This input is taken low when the associated processor wishes totransfer data from the system data bus to the 8251A’s Data Bus Buffer.

Control/Data (C/D). This input, in conjunction with the (RD) and (WR) in-puts, informs the 8251A that the word on the system data bus is either a ‘data char-acter’ or a ‘control/status’ information. A logic high indicates ‘data’ and lowindicates ‘control//status’ word.

As the above four inputs all affect the Read/Write functions these are summarizedin the table below:

Table A-1:

C/D RD WR CS DATA FLOW

0 0 1 0 CPU Reads Data from 8251A Data Bus Buffer

0 1 0 0 CPU Writes Data to 8251A Data Bus Buffer

1 0 1 0 CPU Reads Status Byte from 8251A Data Bus Buffer

1 1 0 0 CPU Writes Control Byte to 8251A Data Bus Buffer

X 1 1 0 Data Bus Buffer = High Z

X X X 1 Data Bus Buffer = High Z



Reset (RST). The 8251A assumes an idle state when this input is taken high.And when it returns low it remains in this state until it receives a new ‘mode con-trol’ instruction from the associated processor.

Clock (CLK). This input is used for internal timing within the 8251 and doesnot control the transmit or receive rate. Generally, it should be at least 30 timesthe transmit or receive rate.

Transmit buffer

The ‘transmit buffer’ accepts parallel data from the ‘data bus buffer’, converts itto a serial bit-stream, inserts the appropriate characters or bits required by thecommunication protocol in use, and outputs a composite serial data-stream on theTxD output pin.

Transmit control

The ‘transmit control’ block manages all the activities associated with the trans-mission of serial data. It accepts and issues signals both externally (describedbelow) and internally to accomplish this function.

Transmit Clock (TxC). The serial data on TxD is clocked out on the fallingedge of the TxC signal.

Transmitter Ready (TxRDY). This output goes high when data in the ‘databus buffer’ has been shifted into the ‘transmit buffer’ and informs the CPU thatthe 8251A is ready to receive the next data character for transmission. TxRDY isautomatically reset by the leading edge of the WR input when a data character isloaded from the CPU.

Transmitter Empty (TxE). The TxE output goes high when the transmittersection has transmitted its data and the ‘transmit buffer’ is empty. It will remainhigh until a new data byte is shifted into the ‘transmit buffer’.This line can be used to indicate the end of a transmission mode, so that the CPU“knows” when to “turn the line around” in the half-duplex operational mode.

Receive buffer

The ‘receive buffer’ accepts serial data from the transmission line (RxD), con-verts it to a parallel format, checks for characters or bits required by the commu-nication protocol in use, and sends an “assembled” character to the CPU via the‘data bus buffer’.

Receive control

The ‘receive control’ block manages all receiver-related activities, including‘start’, ‘stop’ and ‘parity’ bit detection and the detection of several error states.The external signals associated with this block are:

Receiver Clock (RxC). The ‘receiver clock’ (RxD) controls the rate at whichthe character is to be received. In “synchronous” mode, the baud rate (1x) is equalto the actual frequency of (RxD). In “asynchronous” mode the baud rate is a frac-tion of the actual (RxD) frequency as selected by the “mode” instruction. This canbe set to 1/16th or 1/64th of (RxC).

Receiver Ready (RxRDY). This output indicates to the processor that datahas been shifted into the receiver buffer from the receiver section and may nowbe read. The signal is active high and is reset when the buffer is read by the proc-essor.



Sync Detect (SYN-DET). This signal is used only in the synchronous mode. Itcan be either an input or output depending on whether the program is set for in-ternal or external synchronisation. As an output, a high level indicates when thesync character has been detected in the received data stream after the InternalSynchronisation mode has been programmed. SYN-DET is reset when the statusbuffer is read or when a reset signal is activated.

SYN-DET performs as an input when the External Synchronisation mode is pro-grammed. External logic can supply a positive-going signal to indicate to the8251 that synchronisation has been attained. This will cause it to initialise the as-sembly of characters on the next falling edge of RxC. To successfully achievesynchronisation, the SYN-DET signal should be maintained in a high conditionfor at least one full cycle of RxC.

Modem control

The 8251A has a set of control inputs and outputs that can be used to simplify theinterface to almost any modem. The modem control signals are general purposein nature and can be used for functions other than modem control, if necessary.

Data Terminal Ready (DTR). This signal reflects the state of bit 1 in theCommand Instruction. It is commonly used to signal to an associated modem thatthe 8251 is ready.

Data Set Ready (DSR). This input signal forms part of the status byte that maybe read by the processor. DSR is generally used as a response to DTR, by themodem, to indicate that it too is ready. The signal acts only as a flag and does notcontrol any internal logic.

Request To Send (RTS). This signal reflects the state of bit 5 in the commandinstruction. It is normally used to initiate a data transmission by requesting themodem to prepare to send.

Clear To Send (CTS). This input is generally used as a response to RTS by amodem, to indicate that transmission may begin.



A.9 UC3845 Current-mode PWM Controller

Figure A-9: UC3845

A.9.1 Introduction

The UC3845 integrated circuit provides features necessary to implement off-lineor dc-to-dc fixed-frequency current-mode control schemes with a minimumnumber of external components.

Some of the internally implemented circuits are an ‘undervoltage lockout’(UVLO) featuring a start-up current of less than 1 mA and a precision ‘voltagereference’ trimmed for accuracy at the error amplifier input. Other internal cir-cuits include logic to ensure latched operation, a pulse-width modulation (PWM)comparator (which also provides current-limit control), and a totem-pole outputstage designed to source or sink high-peak current. The output stage, suitable fordriving N-channel MOSFETs, is low when it is in the off state.


Input supply

The device can be powered by a single supply rail of up to 30V (Vcc/Gnd); butwhen power is first applied the undervoltage lockout (UVLO) comparator holdsoff the circuit’s operation until Vcc rises above 8.4V. Conversely, on power-downUVLO turns off the device when Vcc falls below 7.6V.

If Vcc falls within the permissible operating voltage limits, the UVLO ‘sets’ anS-R flip-flop which ‘enables’ a 5V reference voltage generator whose output ispresented to the external circuitry via pin 8 (Vref). In practice this stable referencevoltage can be used to bias the oscillator’s external frequency determining com-ponents. Note that the 5V reference voltage is monitored by the ‘vref good logic’block which inhibits the output gate if this voltage is in error. Vref is also dividedby two, and the resulting 2.5V reference voltage is internally connected to the‘voltage error amp’ non-inverting input.

PWM Control

The output PWM signal at pin 6 is controlled by the PWM latch which is ‘set’ (pin6 driven high) by the internal oscillator output going high. As the oscillator is offixed frequency this means that the leading edge of the output PWM pulses appearat a regular interval irrespective of their adopted pulse-width.

1V

S

R

OSCILLATOR

S/R 5VREF

Vref GOODLOGIC

7

5

8

4

1

2

3

Vcc

GND

Vref

RT/CT

Vfb

Comp

Isense

7

6

5

Type UC3845Current Mode PWM controllerUVLO

V ErrorAmp

CurrentSenseComparator

2R

R

2.5V

PWMLatch

OU

TP

UT

Toggle



The oscillator frequency is determined by external R-C components connected topin 4 (RT/CT). Generally, the timing resistor is connected between pin 8 (Vref)and pin 4 (RT/CT); and the timing capacitor between pin 4 (RT/CT) and pin 5(Gnd). The oscillator frequency is then calculated as:

Note: In the UC3845 version of this device range the output PWM frequency isonly half the oscillator frequency due to the implementation of an extra T (toggle)flip flop connected ahead of the output gate, which is included to limit the outputmark-to-space to 2:1 (i.e. maximum 50% duty cycle).

The PWM latch is ‘reset’ (pin 6 driven low) by the ‘current sense comparator’when the current sense signal applied to pin 3 exceeds the level set by the ‘voltageerror amp’ output.

The ‘voltage error amp’ output is in turn determined by a voltage feedback signalapplied to pin 1 (Vfb) and its gain is set by the value of an external resistor con-nected between pins 1 & 2. The Vfb signal therefore sets the threshold for the‘current sense comparator’ which in then determines the PWM switching point.

Start Stop Control

The ‘demand’ output from the ‘volts error amp’ to the ‘current sense comparator’is connected via two diodes and a 2:1 resistive attenuator; and is limited by a zenerto 1V at the comparator’s input. It is possible therefore to ‘stop’ the i.c’s internaloperation by either making pin 1 less than two diode drops (<1.2V) with respectto ground, or by taking pin 3 greater than 1V.

In the former case, the ‘current sense comparator’ is effectively ‘seeing’ zerodemand from the ‘volts error amp’ and applies a permanent ‘reset’ to the ‘PWMlatch’. In the latter case the current sense signal is permanently greater than the‘demand’ signal from the ‘volts error amp’ and the ‘current sense comparator’again permanently resets the ‘PWM latch’.

F 1.72RT CT×-------------------=



A.10 PCA82C250 CAN Controller Interface

Figure A-10: PCA82C250

Table A-2: Truth table of CAN transceiver.

A.10.1 Introduction

The device combines a 3-state differential line driver and a differential-input linereceiver, both of which operate from a single +5V power supply.

The driver differential outputs and the receiver differential inputs are connectedtogether internally to form a differential I/O bus port which is designed to offerminimum loading to the bus whenever the driver is disabled. The receiver oper-ates on a differential input greater then 0.9V, as shown in the above table.

These ports feature good common-mode noise rejection when used on a balanceline making them ideal for use over party-line applications.

TxD CANH CANL RxD

0 CANH > (CANL+0.9V) 0

1 (or floating) Floating Floating 1

X Floating Floating X

>0.75VCC Floating Floating X

X floating if VRs > 0.75VCC

floating if VRs > 0.75VCC

X

1

2

3

4

8

7

6

5

TxD

GND

Vcc

RxD

Rs(SI)

CANL

CANH

Vref

Driver

ReferenceVoltage

Protection

Slope/Standby

1

2

3

4

8

7

6

5

TxD

GND

Vcc

RxD

Rs

CANL

CANH

Vref

CA

N B

US



A.10.2 Functional Description

The PCA82C250 is the interface between the CAN protocol controller and thephysical bus. The device provides differential transmit capability to the bus anddifferential receive capability to the CAN controller.

Pin 8 (Rs) allows three different modes of operation to be selected: high-speed,slope control or standby. For high-speed operation, the transmitter output transis-tors are simply switched on and off as fast as possible. In this mode, no measuresare taken to limit the rise and fall slope. Use of a shielded cable is recommendedto avoid RFI problems. The high-speed mode is selected by connecting pin 8 toground.

For lower speeds or shorter bus length, an unshielded twisted pair or a parallelpair of wires can be used for the bus. To reduce RFI, the rise and fall slope shouldbe limited. The rise and fall slope can be programmed with a resistor connectedfrom pin 8 to ground. The slope is proportional to the current output at pin 8.

If a HIGH level is applied to pin 8, the circuit enters a low current standby mode.In this mode, the transmitter is switched off and the receiver is switched to a lowcurrent. If dominant bits are detected (differential bus voltage >0.9 V), RxD willbe switched to a LOW level. The microcontroller should react to this condition byswitching the transceiver back to normal operation (via pin 8). Because the re-ceiver is slow in standby mode, the first message will be lost.

Table A-3: Rs Summary

CONDITION FORCED AT Rs(SI)

MODE RESULTING VOLTAGE OR

CURRENT AT Rs(SI)

VRs > 0.75VCC standby IRs < |10µA|

10 mA < IRs < 200 µA slope control

0.4VCC < VRs < 0.6VCC

VRs < 0.3VCC high-speed

IRs < -500µA



A.11 80C166 Microcontroller

A.11.1 Introduction

The SAB 80C166 is the first representative of the Siemens SAB 80C166 familyof full featured single-chip CMOS microcontrollers. It combines high CPU per-formance (up to 10 million instructions per second) with high peripheral function-ality and enhanced I/O-capabilities; and offers the following major features:

• High performance 16-bit CPU with 4-stage pipeline • Up to 256 KBytes linear address space for code and data • 1 KByte on-chip RAM • 32 KBytes on-chip ROM (SAB 83C166 only) • Programmable external bus characteristics for different address ranges • Multiplexed or demultiplexed, 8-Bit or 1 6-Bit external data bus • 512 Bytes on-chip special function register area • Idle and power down modes 8-channel interrupt-driven single-cycle data

transfer facilities via Peripheral Event Controller (PEC) • 16-Priority-level interrupt system • 10-Channel 10-bit A/D converter with 9.7µS conversion time • Two multi-functional general purpose timer units with 5 timers • Two serial channels (USARTs) • Programmable watchdog timer • Up to 76 general purpose I/O lines


Figure A-11: 80C166 Internal block diagram

CPU-CoreInternalROMArea

10-BitADC

Ext.Bus

Control

Port 2Port 3Port 5Port 1

Port4

Port0

WatchdoogOSC

InternalRAM

CAPCOM

[T0][T1]

GPT1

[T2][T3][T4]

USARTASC1

USARTASC0

��

GPT2

[T5][T6]

Interrupt Controller

16

2

16 16 1610

32

16

16

16

16

16

XTAL

PEC



A.11.3 Memory organization

The memory space of the 80C166 is configured in a Von Neumann architecturewhich means that code memory, data memory, registers and I/O ports are organ-ized within the same 256 KBytes linear address space. The entire memory spacecan be accessed byte wise or word wise. Particular portions of the on-chipmemory have additionally been made directly bit addressable.

1 KByte of on-chip RAM is provided as a storage for user-defined variables, forthe system stack, general purpose register banks and even for code. A registerbank can consist of up to 16 word wide (R0 to R15) and/or byte wide (RL0, RHO,..., RL7, RH7) so-called General Purpose Registers (GPRs).

512 bytes of the address space are reserved for the Special Function Registers,which are used for controlling and monitoring functions of the different on-chipunits. To meet the needs of designs where more memory is required than is pro-vided on chip, up to 256 KBytes of external RAM and/or ROM can be connectedto the microcontroller.

A.11.4 External Bus Controller

All of the external memory accesses are performed by a particular on-chip Exter-nal Bus Controller (EBC). It can be programmed either to Single Chip Modewhen no external memory is required, or to one of four different external memoryaccess modes, which are as follows:

- 16-/18-bit Addresses,16-bit Data, Demultiplexed

- 16-/18-bit Addresses, 16-bit Data, Multiplexed

- 16-/18-bit Addresses, 8-bit Data, Multiplexed

- 16-/18-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on Port 1 and data is input/output on Port 0. In the multiplexed bus modes both addresses and data use Port0 for input/output.

Important timing characteristics of the external bus interface (Memory CycleTime, Memory Tri- State Time, Read/Write Delay and Length of ALE, i.e. ad-dress setup/hold time with respect to ALE) have been made programmable toallow the user the adaption of a wide range of different types of memories. In ad-dition, different address ranges may be accessed with different bus characteris-tics. Access to very slow memories is supported via a particular ‘Ready’ function.A HOLD/HLDA protocol is available for bus arbitration.

For applications which require less than 64 KBytes of external memory space, anon-segmented memory model can be selected. In this case all memory locationscan be addressed by 16 bits and Port 4 is not required to output the additional seg-ment address lines. Semiconductor Group.

A.11.5 Central Processing Unit (CPU)

The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arith-metic and logic unit (ALU) and dedicated SFRs. Additional hardware has beenspent for a separate multiply and divide unit, a bit-mask generator and a barrelshifter.

Based on these hardware provisions, most of the 80C166’s instructions can be ex-ecuted in just one machine cycle which requires 100ns at 20-MHz CPU clock. Forexample, shift and rotate instructions are always processed during one machine



cycle independent of the number of bits to be shifted. All multiple-cycle instruc-tions have been optimized so that they can be executed very fast as well: branchesin 2 cycles, a 16 x 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reduc-ing the execution time of repeatedly performed jumps in a loop from 2 cycles to1 cycle.

A system stack of up to 512 bytes is provided as a storage for temporary data. Thisis allocated in the on-chip RAM area, and is accessed by the CPU via the stackpointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitlycompared against the stack pointer value upon each stack access for the detectionof a stack overflow or underflow.

A.11.6 Interrupt System

With an interrupt response time within a range from just 250ns to 600ns (in caseof internal program execution), the 80C166 is capable of reacting very fast to theoccurrence of non- deterministic events.

The 80C166 architecture supports several mechanisms for fast and flexible re-sponse to service requests that can be generated from various sources internal orexternal to the microcontroller. Any of these interrupt requests can be pro-grammed to being serviced by the Interrupt Controller or by the Peripheral EventController (PEC).

In contrast to a standard interrupt service where the current program execution issuspended and a branch to the interrupt vector table is performed, just one cycleis ‘stolen’ from the current CPU activity to perform a PEC service. A PEC serviceimplies a single byte or word data transfer between any two memory locationswith an additional increment of either the PEC source or the destination pointer.PEC services are very well suited, for example, for supporting the transmission orreception of blocks of data, or for transferring A/D converted results to a memorytable. The 80C166 has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities.

A separate control register which contains an interrupt request flag, an interruptenable flag and an interrupt priority bit field exists for each of the possible inter-rupt services. Via its related register, each source can be programmed to one ofsixteen interrupt priority levels. Once having been accepted by the CPU, an inter-rupt service can only be interrupted by a higher prioritized service request. For thestandard interrupt processing, each of the possible interrupt sources has a dedicat-ed vector location.

The 80C166 also provides an excellent mechanism to identify and process excep-tions or error conditions that arise during run-time; so-called ‘Hardware Traps’.Hardware traps cause immediate non-maskable system reaction which is similarto a standard interrupt service (branching to a dedicated vector table location).Except when another higher prioritized trap service is in progress, a hardware trapwill interrupt any actual program execution. In turn, hardware trap services cannormally not be interrupted by standard or PEC interrupts.

A.11.7 Capture/Compare (CAPCOM) Unit

The CAPCOM unit supports generation and control of timing sequences on up to16 channels with a maximum resolution of 400ns (@ 20 MHz CPU clock). TheCAPCOM unit is typically used to handle high speed I/O tasks such as pulse andwaveform generation, pulse width modulation (PMW), Digital to Analog (D/A)conversion, software timing, or time recording relative to external events.



Two 16-bit timers (T0/T1) with reload registers provide two independent timebases for the capture/ compare register array.

The input clock for the timers is programmable to several prescaled values of theCPU clock, or may be derived from an overflow/underflow of timer T6 in moduleGPT2. This provides a wide range of variation for the timer period and resolutionand allows precise adjustments to the application specific requirements. In addi-tion, an external count input for CAPCOM timer T0 allows event scheduling forthe capture/compare registers relative to external events.

The capture/compare register array contains 16 dual purpose capture/compareregisters, each of which may be individually allocated to either CAPCOM timerT0 or T1, and programmed for capture or compare function. Each register has oneport pin associated with it which serves as an input pin for triggering the capturefunction, or as an output pin to indicate the occurrence of a compare event.

When a capture/compare register has been selected for capture mode, the currentcontents of the allocated timer will be latched (captured) into the capture/compareregister in response to an external event at the port pin which is associated withthis resister. In addition, a specific interrupt request for this capture/compare reg-ister is generated. Either a positive, a negative, or both a positive and a negativeexternal signal transition at the pin can be selected as the triggering event. Thecontents of all registers which have been selected for one of the five comparemodes are continuously compared with the contents of the allocated timers. Whena match occurs between the timer value and the value in a capture/compare regis-ter, specific actions will be taken based on the selected compare mode.

A.11.8 General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multi-functional timer/counter structurewhich may be used for many different time related tasks such as event timing andcounting, pulse width and duty cycle measurements, pulse generation, or pulsemultiplication.

The GPT unit incorporates five 16-bit timers which are organized in two separatemodules, GPT1 and GPT2. Each timer in each module may operate independentlyin a number of different modes, or may be concatenated with another timer of thesame module.

Each of the three timers T2, T3, T4 of module GPT1 can be configured individu-ally for one of three basic modes of operation, which are Timer, Gated Timer, andCounter Mode. In Timer Mode, the input clock for a timer is derived from theCPU clock, divided by a programmable prescaler, while Counter Mode allows atimer to be clocked in reference to external events.

Pulse width or duty cycle measurement is supported in Gated Timer Mode, wherethe operation of a timer is controlled by the ‘gate’ level on an external input pin.For these purposes, each timer has one associated port pin (TxIN) which servesas gate or clock input. The maximum resolution of the timers in module GPT1 is400ns (@ 20 MHz CPU clock).

The count direction (up/down) for each timer is programmable by software. Fortimer T3 the count direction may additionally be altered dynamically by an exter-nal signal on a port pin (T3EUD).

With its maximum resolution of 200ns (@ 20MHz), the GPT2 module providesprecise event control and time measurement. It includes two timers T5, T6, bothof which can be clocked with an input clock which is derived from the CPU clock



via a programmable prescaler. The count direction (up/down) for each timer isprogrammable by software. Concatenation of the timers is supported.

A.11.9 A/D Converter

For analog signal measurement, a 10-bit A/D converter with 10 multiplexed inputchannels and a sample and hold circuit has been integrated on-chip. It uses themethod of successive approximation. The sample time (for loading the capaci-tors) and the conversion time adds up to 9.7 us @ 20MHz CPU clock.

For applications which require less than 10 analog input channels, the remainingchannel inputs can be used as digital input port pins.

The A/D converter section supports four different conversion modes. In the stand-ard Single Channel conversion mode, the analog level on a specified channel issampled once and converted to a digital result. In the Single Channel Continuousmode, the analog level on a specified channel is repeatedly sampled and convert-ed without software intervention. In the Auto Scan mode, the analog levels on apre-specified number of channels are sequentially sampled and converted. In theAuto Scan Continuous mode, the number of pre-specified channels is repeatedlysampled and converted.

The Peripheral Event Controller (PEC) may be used to automatically store theconversion results into a table in memory for later evaluation, without requiringthe overhead of entering and exiting interrupt routines for each data transfer.

A.11.10 Parallel Ports

The 80C166 provides up to 76 I/O lines which are organized into five input/outputports and one input port. All port lines are bit-addressable, and all input/outputlines are individually (bit-wise) programmable as inputs or outputs via directionregisters. The I/O ports are true bidirectional ports which are switched to high im-pedance state when configured as inputs. During the internal reset, all port pinsare configured as inputs.

All port lines have programmable alternate input or output functions associatedwith them. Port 0 and Port 1 may be used as address and data lines when accessingexternal memory, while Port 4 outputs the additional segment address bits A17/A16 in systems where segmentation is enabled to access more than 64 KBytes ofmemory. Port 2 is associated with the capture inputs or compare outputs of theCAPCOM unit and/or with optional bus arbitration signals (BREQ, HLDA,HOLD). Port 3 includes alternate functions of timers, serial interfaces, optionalbus control signals (WR, BHE, READY) and the system clock output (CLK-OUT). Port 5 is used for the analog input channels to the A/D converter. All portlines that are not used for these alternate functions may be used as general purposeI/O lines.

A.11.11 Serial Channels

Serial communication with other microcontrollers, processors, terminals or exter-nal peripheral components is provided by two serial interfaces with identicalfunctionality, Asynchronous/ Synchronous Serial Channels ASC0 and ASC1.

They support full-duplex asynchronous communication up to 625 Kbaud andhalf-duplex synchronous communication up to 2.5 Mbaud @ 20 MHz CPU clock.

Two dedicated baud rate generators allow set up of all standard baud rates withoutoscillator tuning. For transmission, reception, and erroneous reception, 3 separateinterrupt vectors are provided for each serial channel.



In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preced-ed by a start bit and terminated by one or two stop bits. For multiprocessor com-munication, a mechanism to distinguish address from data bytes has beenincluded (8-bit data + wake up bit mode). In synchronous mode one data byte istransmitted or received synchronously to a shift clock which is generated by the80C166.

A number of optional hardware error detection capabilities has been included toincrease the reliability of data transfers. A parity bit can automatically be gener-ated on transmission or be checked on reception. Framing error detection allowsrecognition of data frames with missing stop bits.

A.11.12 Watchdog Timer

The Watchdog Timer represents one of the fail-safe mechanisms which have beenimplemented to prevent the controller from malfunctioning for longer periods oftime.

The Watchdog Timer is always enabled after a reset of the chip, and can only bedisabled in the time interval until the end of initialization; thus, the chip’s start-upprocedure is always monitored. The software has to be designed to service theWatchdog Timer before it overflows. If, due to hardware or software related fail-ures, the software fails to do so, the Watchdog Timer overflows and generates aninternal hardware reset and pulls the RSTOUT pin low in order to allow externalhardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the CPU clock divided eitherby 2 or by 128. Each time it is serviced by the application software, the high byteof the Watchdog Timer is reloaded. Thus, time intervals between 25µs and 420mscan be monitored (@ 20MHz CPU clock). The default Watchdog Timer intervalafter reset is 6.55 ms (@ 20MHz CPU clock).

A.11.13 Bootstrap Loader

The 80C166 provides a built-in bootstrap loader (BSL) which allows the execu-tion of the start program outside its internal RAM. The program to be started isloaded via the serial interface ASC0 and does not require external memory or aninternal ROM.

The 80C166 enters BSL mode when ALE is sampled high at the end of a hardwarereset and if NMI becomes active directly after the end of the internal reset se-quence. BSL mode is entered independent of the selected bus mode.

After entering BSL mode the 80C166 scans the RXDO line to receive a zero byte,i.e. one start bit, eight ‘0’ data bits and one stop bit. From the duration of this zerobyte it calculates the corresponding baud rate factor with respect to the currentCPU clock and initializes ASC0 accordingly. Using this baud rate, an acknowl-edge byte is returned to the host that provides the loaded data.

The 80Cl66 exits BSL mode upon a software reset (ignores the ALE level) or ahardware reset (remove conditions for entering BSL mode before).


B:

Appendix B : Controller Area Networking (CAN)

B.1 Introduction

The CAN (Controller Area Network) is an ISO defined serial communicationsbus that was originally developed during the late 1980’s for the automotive indus-try. Its basic design specification called for a high bit rate, high immunity to elec-trical interference and an ability to detect any errors produced. Not surprisingly,due to these features the CAN serial communications bus has become widely usedthroughout the automotive, manufacturing and aerospace industries.

B.2 CAN Architecture

The CAN communications protocol describes the method by which informationis passed between devices. It conforms to the Open Systems Interconnectionmodel which is defined in terms of layers (See Figure B-1). Each layer in a deviceapparently communicates with the same layer in another device, but actual com-munication is between adjacent layers in each device and the devices are onlyconnected by the physical medium via the physical layer of the model. In practice,the physical medium consists of a twisted-pair or optical coupling with appropri-ate termination.

The CAN architecture defines the lowest two layers of the model – i.e. the datalink and physical layers. The application levels are linked to the physical mediumby the layers of various emerging protocols, dedicated to particular industry areasplus any number of propriety schemes defined by individual CAN users.

Figure B-1: Open Systems Interconnection model

The 7200 Series UPS system uses a type 80C200 standalone CAN controllerwhich directly interfaces to the microcontrollers, and the connection to the phys-ical medium is implemented with the 82C250 integrated circuit.

app-b.fm5 - Issue 2 Dated 21/08/97 B-1

Appendix B 7200 Series UPS Service ManualController Area networking (CAN)

B.3 Varieties Of CAN

CAN exists in two forms; ‘Basic CAN’ and ‘Full CAN’. The difference betweenthe two types of controller are mainly cost. Basic CAN is cheaper because it re-quired less buffer space and CPU workload: Full CAN is less demanding on thework required by the CPU.

‘Basic CAN’

Basic CAN has a tight coupling between the CPU and the CAN controller, whereall messages broadcast on the network have to be individually checked by the mi-crocontroller. With Basic CAN, the messages are held in the CPU’s memory, andthe CPU must do all the work in keeping track of messages. The CPU must alsohandshake with the 82C200 controller (using ‘message sent’ and ‘message ar-rived’ interrupt handlers) to send and receive messages. This results in the CPUbeing ‘tied up’ checking messages rather than processing them; all of which tendsto limit the practicable baud rate to 250kBaud.

‘Full CAN’

With Full CAN, all the messages are held in the CAN controller (82C200) and ac-cessed by the CPU as dual-ported RAM. Acceptance filters mask out the irrele-vant messages, using identifiers (ID), and presents the CPU with only thosemessages that are of interest. The CPU therefore has little work to do in handlingthe messages.

For example, the CAN protocol has a special type of message that means “whoever

holds this message, please send it now”. With Full CAN, the controller automaticallylistens for these messages and sends them only if it happens to contain the request-ed message: if the message Id is masked out then no action is taken.

In the basic CAN specification, it has a transmission rate of up to 250 kbaud whilstfull CAN runs at 1MBaud

B.4 CAN Bus protocol

B.4.1 CAN Addressing

There are no source and destination addresses in a CAN message. Message iden-tifiers are used to tag a message type, and each node decides, using bit-masks,which messages it retrieves from the bus – this process is called acceptance filter-ing, and different controller chips provide different levels of filtering sophistica-tion.

The Full CAN protocol allows for two lengths of message identifiers: Part A(standard CAN) allows for 11 message identification bits, which yield 2,032 dif-ferent identifiers, whilst extended CAN (Part B) has 29 identification bits, produc-ing 536,870,912 separate identifiers.

Part A devices such as the 82C200 can only transmit and receive standard CANprotocol. If used on an extended CAN system in which 29 bit IDs are present, thedevice will cause errors and crash the entire network.

The data-link layer defines the format and timing protocol with which the mes-sages are transmitted. There are two descriptor bytes and up to eight data bytes.The descriptor bytes are particularly important as they define the priority and typeof message being transmitted.

B-2 app-b.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual Appendix BController Area networking (CAN)

Figure B-2:

B.5 Priorities handling

The identifier field contains 11 bits and is used to identify the message as well asdetermining its bus access priority. Bits 7-10 of the identifier field define the mes-sage priority, with the highest priority having for the smallest identifier binaryvalue. This means that messages can have a priority number between 0 (high pri-ority) and 15 (low priority). Allocation of message priorities is a feature of theCAN bus that makes it particularly attractive for use within a strongly real timecontrol environment.

B.5.1 Coping with message collisions

As has been said, a fundamental CAN characteristic is that the lower the messagenumber, the higher its priority - an identifier consisting entirely of zeros is there-fore deemed to be the highest possible priority message.

A node can start transmitting at any time when the bus is silent (idle), with thefirst part of a message transmitted being the message identifier field – most sig-nificant bit first. The node constantly monitors the CAN bus and if it is the onlynode currently transmitting it will receive back the message bit-by-bit as it sendsit.

The bus has the property that if any node transmits a ‘0’ (called a dominant bit)then all nodes read back a zero. Thus if two nodes begin to transmit simultaneous-ly, the first source to send a zero, when the other source attempts one, gets controlof the CAN bus and goes on to complete its message.

Thus if a transmitter ‘A’ is overruled by a source ‘B’ sending a higher prioritymessage, the fact that the message read back by ‘A’ does not match the messageit attempted to send means that it will temporarily halt. Another attempt will sub-sequently be made to send it once the bus is released and returns to an ‘idle’ state.Any collisions will always be resolved because the CAN protocol requires thatmessage identifiers are unique (which is why there are so many priorities).

This functionality is part of layer 1 and is contained entirely within the 82C200CAN controller device and is therefore transparent to the CAN user.

B.5.2 Interactive Communication

It is possible to send a request for data to a specified address, and the remote trans-mission request (RTR) bit defines whether the message sent is a request for dataor the actual data itself. The data-length code tells the receptor how many data

Parity Bits

app-b.fm5 - Issue 2 Dated 21/08/97 B-3

Appendix B 7200 Series UPS Service ManualController Area networking (CAN)

bytes the message contains. In the case of data requests, no data bytes follow andtherefore the data-length code has no direct relation to the number of data bytes.

The maximum number of nodes on a CAN bus is 32. The limit of messages persecond ranges from about 2000 to about 5000 on a bus with 250kbaud transmis-sion rate, depending on the number of bytes per message.

B.6 The Physical Layer

CAN can use a number of physical media such as twisted wire-pairs, fibre-opticsetc. The commonest method is the former. Signalling is carried out using differ-ential voltages and it is from this that CAN derives much of its noise immunityand fault tolerance. The two signal lines are termed ‘CAN_H’ and ‘CAN_L’ and, inthe quiescent state, sit at 2.5V. A logic high (1) is denoted by CAN_H being aboveCAN_L and as such is termed a ‘dominant’ bit; whilst a logic low (0) has CAN_L

above CAN_H, yielding a ‘recessive’ bit.

The use of voltage differentials allows CAN networks to function when one of thesignalling lines is open, or in extremely noisy environments. With a simple twist-ed pair, the differential CAN inputs effectively cancel out noise, provided it iswithin the common mode range.

B-4 app-b.fm5 - Issue 2 Dated 21/08/97

C:

Appendix C : PCB Layout diagrams

C.1 Overview

This appendix contains layout diagrams for the major circuit boards fitted acrossthe entire 7200 product range. The diagrams are highlighted to show the locationof the configuration jumpers, indicator LEDs and variable resistors; the input/output connectors are also identified.

Figure C-1 - Rectifier logic board Part Nº4520074A assembly

Figure C-2 - Inverter logic board Part Nº 4530025T assembly (Post March 1997)

Figure C-3 - Inverter logic board Part Nº 4530024S assembly (Post March 1997)

Figure C-4 - UPS logic board Part Nº4550007H assembly (Post March 1997)

Figure C-5 - UPS logic board Part Nº4550004E assembly (Pre March 1997)

Figure C-6 - Static switch trigger PCB Part Nº 4542043Z (Post March 1997)

Figure C-7 - Static switch trigger PCB Part Nº 4542041X (Pre March 1997)

Figure C-8 - Operator Interface PCB Part Nº 4550005F assembly

Figure C-9 - High voltage interface PCB Part Nº 4590054O assembly

Figure C-5 - UPS logic board Part Nº4550004E assembly (Pre March 1997)

app-c.fm5 - Issue 3 Dated 09/11/98 C-1

Appendix C 7200 Series UPS Service ManualPCB Layout Diagrams

R22Man(10-

R21Batte(200

R20Batte(200

R19Batte(0 - 5

al

H9 (Inpu(-20

H1Ext(UP

H8 (Incoon r

H7 PCBfailu

it

it

mit

it

j. re

in1

ts

X1

X1

Figure C-1: Rectifier logic board Part N º4520074A assembly

ual DC voltage Adj 500V)

ry float voltage Adj - 500V)

ry boost voltage Adj - 500V)

ry test voltage Adj 50V)

H4 (A)Rectifier in manumode

H3 (G)Rectifier in float mode

H2 (G)Rectifier in boost mode

H1 (A)Rectifier under battery test mode

X7 = 2 - 3

X6 = 1 - 2

R)t undervoltage %)

0 (R)ernal rectifier off S logic)

R)rrect phase rotation ectifier input

(R) power supply re

R17Rectifier current limAdjust

R18Battery current limAdjust

H6 (R)Rectifier current liactive

H5 (G)Battery current limactive

R121Battery voltage compensation Adw.r.t. to temperatu2.98 volts at X5 p= 25° C

X5 = 1 - 2

X8 = Test poinX9 = 0 - 5

3 = 0v = gnd

0 = 2 - 3

X12 = 0v = gnd

C-2 app-c.fm5 - Issue 3 Dated 09/11/98

7200 Series UPS Service Manual Appendix CPCB Layout Diagrams

Test Point

Test Poin

X160-10-2

=

X15 0 - 12400 Hz s

RA

ts Adj. min.)

ation

ation

tion

ation

CB ply fail

nv off µP

+ sat

+ sat

– sat

+ sat

– sat

T – sat

ble block

50%

lele enable

R245Volts C-N

R248150% Inv(0.6V @ X

X3ve PCBs

Figure C-2: Inverter logic board Part Nº 4530025T assembly (Post March 1997)

X8

t X10

6 pulse Inv I feedback

witching

241mplitude of Tri-wave

R247φ displacement Adj Inv to Mains

R242Inv 3ph volts adj.

R243Man inv vol(clockwise =

H2(G)400v oper

H3(G)415v oper

H4(A)Man opera

H1(G)380v oper

H11(R) = Ppower sup

H12(R) = I

H9(R) = T

H5(R) = R

H6(R) = R

H7(R) = S

H8(R) = S

H10(R) =

H13(R) = Ribbon ca

H14(R) = Overload 1

X18OV = gnd

X12 1-2 0-1(closed)=temp enab0-2(open) =Ribbon cabTest Point X9R244

Volts B-N AdjR246Volts A - N adjustment

Adj

I Limit10 pin 4)

X17OV = gnd

X6Aux Inv Logic PCB

X1 X2To Base Dri

X4To UPS Logic PCBs

R27Tri-wave Amplitude measurement



Test Poin

Test Poin

Test Poin

R244Volts B-N

X160-10-2

R245Volts C-N

=

f. set

lts Adj. = min.)

tion

tion

tion

tion

– sat

sat

n cable

enable

B ly fail

off µP

block

%

+ sat

sat

sat

– sat

X15 0 - 12400 Hz

R241Amplitu

Mains

Figure C-3: Inverter logic board Part Nº 4530024S assembly (Post March 1997)

t X8

t X9

t X10

Adj

Adj

6 pulse Inv I feedbackX18OV = gnd

X14Not Used

X17OV = gnd

R242Inv volts re

R243Man inv vo(clockwise

H2(G)400v opera

H3(G)415v opera

H4(A)Man opera

H1(G)380v opera

H10(R) = T

H9(R) = T +

X12 1-2 Ribboenable

X13 2-3 Temp

H11(R) = PCpower supp

H12(R) = Inv

H13(R) = Ribbon cable

H14(R) = Overload 150

H5(R) = R

H6(R) = R –

H7(R) = S+

H8(R) = S

Test Point X11

switching

de of Tri-wave

R246150% Inv I limit (0.6v @ X10 pin4)

R247φ displacement Adj Inv to



S1

RE

SE

T B

UT

TO

NQ

1

Q2

Q3

3 -

4 =

Clo

sed

= S

tan

da

rd7

- 8

= P

ass

wo

rd o

ver-

rid

e o

pe

n =

sta

nd

ard

H11

& H

12

X3

3 =

1-2

X1

2

Figure C-4: UPS logic board Part Nº4550007H assembly (Post March 1997)

H8

(A

mb

er)

Inte

rna

l ba

tte

ry c

ha

rge

r (A

ctiv

e)

Fo

r O

vert

em

p:

Ove

rcu

rre

nt:

E

PO

; D

C O

verv

olta

ge

Byp

ass

ON

/OF

F

R2

09

@ 2

0 p

in 1

5 V

olt

ad

just

X2

8 o

pe

n =

Sta

nd

ard

clo

sed

=H

ard

wa

re R

ese

t

Inv

ON

/OF

FR

ect

ON

/OF

F

R2

12

@ A

no

de

V4

52

.5 V

olt

ad

just

X2

0 1

-2 =

Po

we

r su

pp

ly r

ail

µPs

refe

ren

ce

X2

9 o

pe

n =

Po

we

r su

pp

lym

on

itor

en

ab

led

X1

6 1

-2 =

Dis

pla

ye

na

ble

d

X2

6 =

1-2

= O

pe

n =

Sta

nd

ard

X2

5 =

2 -

3X

17

= 2

- 3

= P

ow

er

sup

ply

fa

il sa

ve d

ata

X1

5 =

2 -

3X

18

pin

8 =

0V

X3

2

Lin

ked

= R

S4

85

en

ab

led

X2

4

1-2

: 3

-4 =

RA

M e

na

ble

d

X2

3

2-3

= E

PR

OM

en

ab

led

X2

2

1-2

= E

PR

OM

en

ab

led

X2

1

2-3

= R

AM

en

ab

led

X1

3

2-3

= R

AM

en

ab

led

X1

4

op

en

X1

9

op

en

= n

ot

use

d

X3

1

Lin

ked

= e

na

ble

inte

rna

lb

att

ery

ch

arg

er

Err

or

Co

de

dis

pla

y0

1 =

no

rma

l op

era

tion

V4

5

Ca

len

da

r P

.S

X3

4 =

1

-2 1

+1

& P

ara

llel

2-3

Sin

gle

mo

du

le

X3

5

1-2

= S

ep

era

te B

at

2-3

= C

om

mo

n B

at

X3

6

1-2

= S

ep

era

te B

at

2-3

= C

om

mo

n B

at

NO

Lin

ks F

itte

d



Figure C-5: UPS logic board Part Nº4550004E assembly (Pre March 1997)

X11

= o

pe

nR

S2

32

en

ab

led

H8

(R

)In

tern

al b

att

ery

ch

arg

er

(Act

ive

)

S1

RE

SE

T B

UT

TO

N(o

/te

mp

; O

verl

oa

d;

EP

O;

DC

ove

rvo

lts

Q1

B

ypa

ss O

N/O

FF

R2

09

@ X

20

pin

15

Vo

lt a

dju

st

X2

8 o

pe

n =

Sta

nd

ard

clo

sed

=H

ard

wa

re R

ese

t

Q2

Inv

ON

/OF

F

Q3

R

ect

ON

/OF

F

R2

12

@ A

no

de

V4

52

.5 V

olt

ad

just

X2

0 1

-2 =

Po

we

r su

pp

ly r

ail

µPs

refe

ren

ce

X2

9 o

pe

n =

Po

we

r su

pp

lym

on

itor

en

ab

led

X1

61

-2 =

Dis

pla

ye

na

ble

d

X2

6 =

3 -

4X

25

= 2

- 3

X1

7 =

2 -

3 =

Po

we

r su

pp

ly f

ail

save

da

taX

15

= 2

- 3

X1

8 p

in 8

= 0

VX

32

L

inke

d =

RS

48

5 e

na

ble

d

X2

4

1-2

: 3

-4 =

RA

M e

na

ble

d

X2

3

2-3

= E

PR

OM

en

ab

led

X2

2

1-2

= E

PR

OM

en

ab

led

X2

1

2-3

= R

AM

en

ab

led

X1

3

2-3

= R

AM

en

ab

led

X1

4

op

en

X1

9

op

en

= n

ot

use

d

X3

1

Lin

ked

= e

na

ble

inte

rna

lb

att

ery

ch

arg

er

H11

& H

12

Err

or

Co

de

dis

pla

y0

1 =

no

rma

l op

era

tion

V4

5

7-8

= P

ass

wo

rd p

rote

ctio

n



X1

X1= 0= 0

N

C:

Figure C-6: Static switch trigger PCB Part Nº 4542043Z (Post March 1997)

SCR Trigger Leads

4 = 0v = gnd

1 - 3 closed - 5 closed

Contactor Aux Feedback

/ATo UPS Logic X5

DC feed for contactor K1

DC To contactor K1

APP-C1.FM5 - Issue 2 Dated 21/08/97 C-7


X1

X1

X1

N

Figure C-7: Static switch trigger PCB Part Nº 4542041X (Pre March 1997)

SCR Trigger Leads

4 = 0v = gnd

2 = 0 - 3

1 = 1 - 2

Contactor Aux Feedback

/A

To UPS Logic X5

DC feed for contactor

To contactor

C-8 APP-C1.FM5 - Issue 2 Dated 21/08/97


Figure C-8: Operator Interface PCB Part Nº 4550005F assembly

X2

4 =

1 -

2

H1

(G

)In

tern

al D

C/A

C

po

we

r su

pp

ly O

K

X5

= R

S2

32

A

ux

9 p

in s

ock

et

X3

N/A

CA

N b

us

au

x

To U

PS

log

ic

X6

CA

N b

us

Po

we

r su

pp

ly in

pu

t to

UP

S lo

gic

X4

X8

= R

S2

32

M

ain

25

pin

so

cke

tX

4

RS

23

2 9

pin

or

RS

48

5 s

ock

et

X2

1 =

2 -

3

X2

2 =

2 -

3

X2

0 =

1 -

2

X2

5 =

1 -

2

X1

3 =

2 -

3

X1

8 =

2 -

3

X1

5 =

1 -

2

X1

6 =

2 -

3

X1

7 =

1 -

2 :

3 -

4

N/A

N/A

X2

3 =

2 -

3

X11

= o

pe

n

X1

4 =

op

en

X1

9 =

op

en

X2

6 =

op

en

X1

2 =

2 -

3

X1

= T

o d

isp

lay

R2

1 =

Co

ntr

ast

A

dju

st



Figure C-9: High voltage interface PCB Part Nº 4590054O assemblyX13 : Inverter heat-sink

X12 : Transformer ambient temperature

x10 : Input temperature

X31 to X40 : CT burden settin

x11 Output temperature

x9 : Battery temperature

X7 : Manual isolation Q1 - Q4

X5 : Inverter volts

X6 : Bypass volts

: Critical Bus volts

Rectifier input volts

2 : Battery volts

x1 to UPS logic PCB

x27 : IDC 2

x26 : IDC 1

x24 : Inv B

x23 : Inv A

x22 : I Batt

x21 : I out A

x20 : I out B

x19 : I out C

x18 : Rectifier

x17 : N/A

x16 : N/A

x15 : Batt Fuse

x14: N/A

X8 : Battery breaker & EPO

x25 : Inv C



X1

2 =

Te

st p

oin

t

0-3

clo

sed

40

0V

= 6

.20

V

X8

= T

est

po

int

Figure C-10: Parallel logic PCB Part Nº 4520075B1

= V

CO

in lo

op

(lo

w)

2 =

Cu

rre

nt

sha

re e

na

ble

d (

low

)3

= R

ect

ifie

r p

ara

llele

d (

low

)

X6

0

-1o

pe

n =

re

du

nd

an

cycl

ose

d =

ca

pa

city

0-2

op

en

= c

om

mo

n b

att

ery

clo

sed

= s

ep

era

te b

att

ery

0-3

op

en

= s

tan

da

rd0

-4o

pe

n =

No

MS

SC

(1

+1

)cl

ose

d =

MS

SC

(m

ulti

)0

-5o

pe

n =

sta

nd

ard

0-6

op

en

= s

tan

da

rd0

-7o

pe

n =

No

co

nta

cto

r in

MS

SC

clo

sed

= c

on

tact

or

in M

SS

C0

-8o

pe

n =

no

rma

l op

era

tion

clo

sed

= T

est

mo

de

act

ive

H3

(g

ree

n)

= S

lave

mo

de

act

ive

(O

ff)

H2

(re

d)

= P

ara

llel c

ab

le e

rro

r (O

ff)

H1

(re

d)

= P

ara

llel e

rro

r (s

ele

ct)

(Off

)

X1

32

-3 =

Pa

ralle

l scr

ee

n c

om

mo

n

To X

3 o

n o

the

r m

od

uleTo

X2

on

oth

er

mo

du

leX

40

-1 c

lose

d

X5

0-1

clo

sed

0-2

clo

sed

R1

9P

ara

llel e

rro

r (a

dju

st

for

R6

8 lo

we

r)3

80

V =

5.9

0V

R6

8 (

low

er)

To U

PS

log

ic

X9

Dig

ital g

rou

nd

1 =

In

tern

al S

ync

OK

(h

igh

)2

= F

req

ue

ncy

GV

CO

3 =

4.0

0V

4 =

N/A

5 =

Gro

un

d

R2

0 =

4.0

0 v

olt

ad

just

@ X

8-3

X7

1-2

= 6

0H

z o

pe

ratio

n2

-3 =

50

Hz

op

era

tion

X1

0 =

An

alo

gu

e g

rou

nd

X11

op

en

= s

low

sle

w

rate

(0

.1H

z/S

ec)

clo

sed

= F

ast

sle

w

rate

(0

.2H

z/S

ec)

R1

8 =

Fre

qu

en

cy a

dju

st @

X 8

-2


D:

Appendix D : PCB link selection

D.1 Introduction

The tables in this appendix provide details of the configuration jumpers fitted tothe various control printed circuit boards, and indicates their “default” settings.Layout diagrams are provided in Appendix C which give details of the links’exact location.

D.2 Rectifier Logic PCB Part Nº 4520074A. 30 to 60kVA

Table D-1: Rectifier logic board jumper link position

Jumper Link

Position Function

X5 1 - 2 Disable battery temperature/voltage compensation (Standard)

2 - 3 Enable battery temperature/voltage compensation

X6 1 - 2 Increased DC regulation speed for units below 60kVA

2 - 3 Decreased DC regulation speed for units above 80kVA

X7 1 - 2 Fast walk-in: 1 Second

2 - 3 Slow walk-in: 5 Seconds

X9 0 - 1 openRectifier in Auto mode (Standard)

0 - 2 open

0 - 1 closedRectifier in Float mode

0 - 2 open

0 - 1 openRectifier in Boost mode

0 - 2 closed

0 - 1 closedRectifier in ‘Test’ mode

0 - 2 closed

0 - 3 closed Reduced input current limit forced on

open (Standard)

0 - 4 closed Rectifier forced on - Ignore UPS Logic

open UPS Logic control enabled (Standard)

0 - 5 open Disable driver IC - D6

closed Enable driver IC - D6 (Standard)

X10 1 - 2 Enable rectifier temperature monitor

2 - 3 Disable rectifier temperature monitor (Standard)

App-d.fm5 - Issue 2 Dated 21/08/97 D-1

Appendix D 7200 Series UPS Service ManualPCB Link Selection

D.3 UPS Logic PCB Part Nº4550007H. 30 - 60kVA

Table D-2: UPS logic board jumper link positions

Jumper Position Function

X12

Open (Standard)

1 - 2 Not Required

3 - 4 Not Required

X13 1 - 2 EPROM Enable

2 - 3 RAM Enable (Standard)

X14

1 - 2 Not Required

Test

ing

onl

yno

rma

lly o

pen

3 - 4 Not Required

5 - 6 Not Required

7 - 8 Not Required

X151 - 2 PLL option with

2 - 3 PLL option with (Standard)

X16Open CAN Bus to display disabled

1 - 2 CAN Bus to display enabled (Standard)

X171 - 2 ALE enable data save

2 - 3 Power supply fail enable data save (Standard)

X191 - 2 EPROM II enable (not required)

2 - 3 RAM II enable (not required)

X201 - 2

+5V PCB enables microprocessor ref. For VA calculations (Standard)

2 - 3 V ref. enables microprocessor ref. For VA calculations

X211 - 2 Not Required

2 - 3 RAM enable (Standard)

X221 - 2 EPROM enable (Standard)

2 - 3 Not Required

X23

1 - 2 Not Required

2 - 3 EPROM enable (Standard)

3 - 4 Not Required

4 - 5 Not Required

CAP IN

FIN AUX

D-2 App-d.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual Appendix DPCB Link Selection

X24


2 - 3 EPROM enable (not required)


4 - 5 EPROM enable (not required)

X251 - 2 Manual reset of output buffers

2 - 3 Microprocessor reset of output buffers (Standard)

X26

1 - 2OPEN = Inverter operation in ‘Auto’ mode (Standard)CLOSED = Inverter operation in ‘Manual’ mode

3 - 4CLOSED = Inverter voltage error lockout (10s) enabled (Standard)OPEN = Inverter voltage error lockout (10s) disabled

5 - 6CLOSED = Reset event history buffer to zeroOPEN = Event history buffer enabled (Standard)

7 - 8OPEN = Password security enabledCLOSED = Password security disabled (Standard)

X28Open Power up reset enabled (Standard)

Closed Power up reset disabled

X29Open 2.5V power supply monitor enabled (Standard)

1 - 2 2.5V power supply monitor disabled

X31Open Internal battery disabled

1 - 2 Internal battery installed and charger enabled (Standard)

X32Open RS485 port disabled

1 - 2 RS485 port enabled (Standard)

X331 - 2 Calender IC supply from VRAM (Standard)

2 - 3 Calender IC supply from internal battery

X341 - 2 G.V.C.O. to inverter logic = parallel module

2 - 3 Micro V.C.O. to inverter logic = single module

X351 - 2 Seperate battery per module (parallel system)

2 - 3 Common battery (parallel system)

X361 - 2 Seperate battery per module (parallel system)

2 - 3 Common battery (parallel system)




D.4 Inverter Logic PCB Part Nº4530025T. 30 - 60kVA

Table D-3: Inverter logic board jumper link positions

D.5 Operator Logic Board Part Nº 4550005F 30-60 kVA

Table D-4: Operator Logic Board jumper link position


X12

0 - 1 Open= Test inverter over-temperature sensors

0 - 1Closed = Enable Inverter over-temperature sensors (Stand-ard)

0 - 2 Open= Enable ribbon cable detector (Standard)

0 - 2 Closed = Disable ribbon cable detector

0 - 3 Closed = Voltage select override. Enables manual inverter volts Adj by R243

Test

ing

On

lyO

pen

= S

tan

dar

d

0 - 4

0 - 5 Frequency select override

0 - 6 Force the Inverter ON => ignore all blocks

0 - 7 Ignore Inverter ‘On Load’ signal

X15

0 - 1 2400 Hz switching frequency (Standard)

0 - 2 4800 Hz switching frequency

0 - 10 - 2

9600 Hz switching frequency

0 - 5 1200 Hz switching frequency

X16

0 - 10 - 2

6 pulse Inverter current feedback (Standard)

0 - 3 12 pulse Inverter current feedback


X11Open +5v enable main CPU (Standard)

Closed ALE enable main CPU

X12 1 - 2 Main CPU enable EPROM

2 - 3 +5v enable EPROM (Standard)

X13 1 - 2 Main CPU enable RAM

2 - 3 +5v enable RAM (Standard)



X14 1 - 2 Not Required Testing Only

Open = Standard2 - 3 Not Required

X151 - 2 Main CPU enable EPROM (Standard)

2 - 3 Not Required

X16

1 - 2 Not Required

2 - 3 Main CPU enable EPROM (Standard)

3 - 4 Not Required

4 - 5 Not Required

X17

1 - 2 Write to RAM enable (Standard)

2 - 3 Not Required

3 - 4 Main CPU enable RAM (Standard)

4 - 5 Not Required

X181 - 2 Not Required

2 - 3 Main CPU enable RAM (Standard)

X191 - 2 Not Required RAM extension

(Normally open)2 - 3 Not Required

X201 - 2 Read/Write RS232 enable (Standard)

2 - 3 Read/Write RS485 enable

X211 - 2 Enable port x4 for RS485

2 - 3 Enable port x4 for RS232 (Standard)

X221 - 2 Enable port x4 for RS485

2 - 3 Enable port x4 for RS232 (Standard)

X231 - 2 Inhibit buzzer

2 - 3 Enable buzzer (Standard)

X241 - 2 Enable CAN bus to UPS logic (Standard)

2 - 3 Disable CAN bus to UPS logic

X251 - 2 Enable RS485 bus to port x4 (Standard)

2 - 3 Disable RS485 bus to port x4

X26Open +5v power supply reset enabled (Standard)

Closed +5v power supply reset disabled




D.6 Static Switch Driver PCB Part Nº 4542043Z 30-60 kVA

Table D-5: Static Switch Driver board jumper link position

D.7 High Voltage Interface PCB Part Nº 4590054O 30-60kVA

Table D-6: High Voltage Interface Board jumper link position.

D.8 Parallel Logic PCB Part Nº 4520075B


x11

0 - 1 open Enable load on inverter command (Standard)

0 - 1 closed Disable load on inverter command

0 - 2 open Enable load on bypass command(Standard)

0 - 2 closed Disable load on bypass command

0 - 3 open Disables bypass fire command

0 - 3 closed Enable bypass fire command (Standard)

0 - 4 N/A Not used

0 - 5 open Test static switch temperature monitor

0 - 5 closedInhibit static switch temperature monitor (stand-ard)


— 0 - 1

30 kVA CT burden selection

X31 0 - 2

X31: X32: X33: X34: X35: X37: X38: X39: X40 0 - 3

— 0 - 1


X31: X32: X33: X34 0 - 2

X35: X36: X37: X38: X39: X40 0 - 3

— 0 - 1


— 0 - 2

X31: X32: X33: X34: X35: X36: X37: X38: X39: X40 0 - 3




X4

0 - 1open Priority selector disabled

closed Priority selector enabled for ≥ 1 module (standard 1+1)

0 - 2to

0 - 8open

Priority selector for ≥ 2 modules (multi module only) Link combination sets logic for number of units requiredopen = standard for 1+1

X5

0 - 1 (1st Unit)open

Link combination sets logic for number of units operatingFor 1+1 operation links 0 - 1, 0 - 2, 0 - 3 are closed.

closed (standard)

0 - 2 (2nd Unit)open

closed (standard)

0 - 3 (3rd Unit)open

closed (standard)

0 - 4 (4th Unit)open (standard)

closed

0 - 5 (5th Unit)open (standard)

closed

X6

0 - 1 open 1 + 1 redundancy (standard)

closed 1 + 1 capacity

0 - 2open Common battery for all UPS modules

closed Separate battery for each UPS module (standard)

0 - 3open Priority selector enables parallel shutdown (standard)

closed Priority selector disables parallel shutdown

0 - 4open No MSSC installed (1 + 1) (standard)

closed MSSC installed (enables control for multi modules)

0 - 5 N/A

0 - 6 N/A

0 - 7open No contactor in MSSC (standard)

closed Contactor in MSSC

0 - 8open Normal operation

closed Test mode active

X71 - 2 60 Hz operation

2 - 3 50 Hz operation (standard)

X11open G.V.C.O. Slow slew rate = 0.1 Hz/Second (standard)

closed G.V.C.O. Fast slew rate = 0.2 Hz/Second

X131 - 2 Parallel cable screen earthed

2 - 3 Parallel cable screen not earthed (standard)



D.9 DC – DC power supply PCB Part Nº 4503028K

Table D-7: DC-DC power Supply Board link position

Soldered Link Position Function

CV1 Closed Enables the input voltage 260V – 600V

CV2 Closed Enables input under voltage protection


E:

Appendix E : Specification

MECHANICAL CHARACTERISTICS UNITS Model kVA Rating

30 40 60

Height mm 1400

Width mm 710

Depth mm 800

Weight kg 480 540 620

Colour (2 tone) – RAL 7001

Protection grade – With enclosure open or shut = IP20

Ventilation – assisted by internal intake fans

Airflow m3/h 480 9600 960

Cable entry – Βοττοµ

Environmental UNITS Model kVA Rating

30 40 60

Operating temperature °C 0 to +40

Maximum temperature for an 8 hour day – 40°C derate by 1.5% per °C between +40° and +50°

Mean temperature for a 24 hour day – 35°C max

Relative humidity – <90% at 20°C

Altitude – <1000m a.s.l. (derate by 1% per 100m between 1000m and 2000m)

Storage temperature °C -25 to +70

Acoustic noise at rated load (taken 1m from the apparatus according to ISO3746)

dBA 56.0

EMC Standard – Designed to meet EN 50091 part 2

Safety standard – Designed to meet EN 50091 part 1

App-e.fm5 - Issue 2 Dated 21/08/97 E-1

Appendix E 7200 Series UPS Service ManualSpecification

INPUT RATINGS UNITS Model kVA Rating

30 40 60

Power consumption at rated load while float charging the battery (400V)

kVA32,8 43,5 64,9

Power consumption at rated load while boost charging the battery (400)

kVA41,0 54,3 81,1

Input current level normal running (400V) A47,0 63,0 94,0

Input current level full battery recharge (400V) A59,0 78,0 117,0

Line voltage V a.c. 380 - 400 - 415 3Ph + N

Current rating of neutral cable A 1,4 times rated current

Permissible input voltage variation % +10 –15

Frequency Hz 50 or 60

Permissible input frequency variation % ± 5

Power walk-in — Progressive over 10 seconds

Power factor at 380/400/415 V cos Φ 0,8

with optional input filter fitted >0,9

SYSTEM DATA UNITS Model kVA Rating

30 40 60

Efficiency at 50% load % 92,0 92,6 93,1

Efficiency at 100% load % 91,5 92,0 92,5

Losses at rated load kW 2,2 2,8 3,9

Losses with battery on boost charge kW 2,8 3,4 4,5

Losses with no load kW 0,9 1,1 1,3

E-2 App-e.fm5 - Issue 2 Dated 21/08/97

7200 Series UPS Service Manual Appendix ESpecification

OUTPUT RATINGS UNITS Model kVA Rating

30 40 60

Voltage V a.c. 380/400/415 (preset on commissioning) 3 Ph N

Frequency Hz 50 or 60 (presettable)

Power at 0,8pf kVA 30 40 60

Power at 1,0pf kW 24 32 48

Normal current at 0.8pf A 43 57 87

Overload ability at 0,8pf3 φ

1 φ

— 110% for 60 minutes125% for 10 minutes150% for 1 minute

200% for 30 seconds

Current limiting short circuit (inverter)150% rated current (3 phase) for

220% rated current (1 phase) for

—5 Seconds

5 Seconds

Maximum permissible non linear load % 100 with 3 : 1 crest factor

Voltage stability — steady state % ± 1

Voltage stability — transient state % ± 5

Reset time to within ± 1% ms 20

Frequency stability — synchronised — The output will synchronise with the input supply within ±0.5 Hz of nominal frequency (adjustable to ±2 Hz)

Frequency stability — unsynchronised — ± 0,1% when the input supply frequency is outside the synchronising range

Phase voltage asymmetry — balanced load — ± 1%

Phase voltage dissymmetry — 100% unbalanced load — ± 2 %

Voltage phase shift — with balanced load Angle o 120 ± 1

Voltage phase shift — with unbalanced load Angle o 120 ± 1

Output voltage distortion — linear load — 1% typical 2% max

Output voltage distortion — non–linear load (3:1 crest factor)

— ≤ 5% max

Maximum frequency slew rate Hz/sec 0,1 to 1,0

Synchronised transfer to bypass ms 0 approximately

Unsynchronised transfer to bypass ms 20 approximately

Overload on bypass(without fuses)

— 10 x rated current for 100 ms



INTERMEDIATE DC RATINGS UNITS Model kVA Rating

30 40 60

Voltage limits of inverter operation for380V minimum

maximum

Vdc320

460


maximum

Vdc330

475


maximum

Vdc 340

490

Number of lead-acid cells UPS 380 V Nº 192

UPS 400 V Nº 198

UPS 415 V Nº 204

Float charge voltage UPS 380 V V d.c. 432

UPS 400 V V d.c. 446

UPS 415 V V d.c. 459

Boost charge voltage UPS 380 V V d.c. 460

UPS 400 V V d.c. 475

UPS 415 V V d.c. 490

End of discharge voltage UPS 380 V V d.c. 320

UPS 400 V V d.c. 330

UPS 415 V V d.c. 340

Absolute maximum voltage (manual charge) UPS 380 V

V d.c. 480

UPS 400 V V d.c. 495

UPS 415 V V d.c. 510

Rectifier output current rating A 75

Voltage stability with rectifier — ± 1%

Residual alternating voltage — ≤ 1%

Battery charging cycle — Characteristics to DIN 41772 I-U, boost-to-floating charge switching, with current

measuring criterion plus control of charging time


7200 Series UPS Service Manual Appendix ESpecification

Maximum boost charge duration hours 1 - 15 hours ( selectable )

Charging current A 3 - 15 5 - 20 6 - 30

Inverter power at rated load kW 25,7 34,1 50,8

Input current to inverter at minimum voltage A 78 103 154

Efficiency of inverter @50% load % 93,8 94,4 94,8

Efficiency of inverter @100% load % 93,3 93,8 94,4

INTERMEDIATE DC RATINGS UNITS Model kVA Rating

30 40 60

STATIC SWITCH CIRCUIT UNITS Model kVA Rating

30 40 60

Overload from stand-by supply A 10 times the rated current for 100ms

current rating of neutral cable A 1,4 time the rated current.



BATTERY CABINETS

MECHANICAL CHARACTERISTICS

UNITS Type B38 Ah

Type C50 Ah

Type D85 Ah

Dimensions (W X H X D) mm690 x 1400 x 800 1050 x 1400 x 800

2 x855 x 1400 x 800

Weight (without batteries) kg 130 150 250

For use with units 30 - 40 kVA 30 - 40 kVA 30 - 40 - 60 kVA

Battery circuit breaker size Amps 100 100 160

Ventilation — Natural + +

Lifting — trans-pallet entry + +

+

+ + +

BATTERY CIRCUIT BREAKER BOX

No of Poles

Suitable for UPS size

(kVA)Part Nº

Magnetic overload setting

(adjustable)

100 A 4 30 - 40 250 – 400

160 A 4 60 500 - 800

+

Undervoltage trip coil rating all units – 110Vdc (6,7 — 9,2 kOhms)

Auxiliary contacts (for signalling) all units

– 1 set changeover


Sect-13

Documents

Transcript of Sect-13