SeaLion FinalReport RevC

8/11/2019 SeaLion FinalReport RevC

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FPGA-Driven Video/Camera System

Final Report

Mark Taylor,LeadDion Moses

Kyler DotsonMatt Plummer

August 24, 2009 December 11, 2009

Digilent, Incororate!, Sponsor"lint "ole,Mentor

21# $% Main &t% &uite DPullman, 'A 991()

An!re* +-allon,Faculty Resource$lectrical.Mec/anical $ngineering uil!ing

m 12#'as/ington &tate ni3ersity

Pullman, 'A

$$41( $lectrical $ngineering DesignP% D% Pe!ro*,Insructor

&c/ool o $$"&Pullman, 'A 991(4

Team Sea Lion Progress Report Page 1 of 11


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e3ision 5istory

e3ision Aut/or Date 6otesA DM 12.7.09 "reate!

MP 12.7.09 A!!e! reerences to imact e3aluation

" MT 12.14.09 A!!e! "o!e to Aen!i8 an! $!ite!

Team Sea Lion Progress Report Page ! of 11


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Table of Contents

1 Intro!uction%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% (1%1 Purose%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% (1%2 &coe%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% (1%) ist o Acronyms%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% (

2 Pro:ect Abstract%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 7) $8ecuti3e &ummary %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% ;

)%1 Printe! "ircuit oar! Design%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% ;)%2 -P2 T-TD %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 1(4%)%2 Pmo!"AM1 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 204%)%) Pmo!--"%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 22

# Pro:ect Management an! -uture 'ork %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%2)( Imact $3aluation%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 2)

(%1 Pro:ect &coe%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 2)(%2 Pro:ect &olution &ummary%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 2)(%) Pro:ect Design "onsi!erations%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 24

7 "onclusion%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 2(; Ackno*le!gement%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 2(9 Aen!i8%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 2(

9%1 =5D &ource%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 2(9%1%1 Team &ource%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 2(

9%1%1%1 Pi8elProc%3/!%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 2(9%1%1%2 o8Painter%3/!%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 299%1%1%) "/aracterPainter%3/!%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% )2

9%1%1%4 "/aracterom%3/!%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 449%1%1%# "oori!inate?Inserter%3/!%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% (#9%1%1%( &PI%3/!%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 709%1%1%7 tb?"oor!inate?Inserter%3/!%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 7)9%1%1%; tb?=ector?To?A&"II%3/!%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 7#9%1%1%9 =ector?To?A&"II%3/!%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 7(

9%1%2 omanian


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9%1%2%1 I2"tils%3/!%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 799%1%2%2 I"2"ore%3/!%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 799%1%2%) I2""tl%3/!%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% ;#

9%1%) "D "ontroller%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 9)9%2 oar! ayout%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 9(

9%2%1 ->2 T-TD ill o Materials %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%9(9%2%2 Pmo!"AM1 ill o Materials%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 979%2%) Pmo!--" ill o Materials%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 9;

9%)


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1 Introduction

1.1 Purpose

T/e -P


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Fig$re 1 % &em'ers of Team Sea Lion( Dion &oses) &att Pl$mmer) *yler Dotson) &ar+ Taylor

3 !"ecuti#e Summary

3.1 Printed Circuit $oard %esign

T/e team got a large /ea! start *it/ /ar!*are !esign consi!erations !uring t/e &ring semester o 2009an! selecte! an! researc/e! all o t/e /ar!*are nee!e! to comlete t/e ro:ect% Mark Taylorcomlete! all o t/e reBuire! mo!iications to t/e ->2 T-TD boar! an! ma!e sure t/at t/ePmo!"AM1 *oul! be able to interace *it/ t/e 6e8ys2%

Digilent recei3e! a small batc/ o t/e rototye ->2 T-TD boar!s !esigne! by Taylor rom t/eirabrication acility an! an engineer at Digilent successully /an! loa!e! t/e arts on t/e boar! allo*ingt/e team to start !e3eloment *it/ t/em% &ince t/e team /a! only t/ree o t/ese boar!s a3ailablecareul /an!ling *as a necessity%

T/e team acBuire! t*o Pmo!"AM1 boar!s a3ailable to rototye *it/% T/e team electe! to kee oneo t/e ->2 T-TD boar!s as *ell as t/e Pmo!"AM1 in t/e assigne! *orkstation on camus% T/e


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ot/er P"s are eit/er on t/e !esks o Dion Moses or Mark Taylor at Digilent% T/is allo*e! e3eryonein t/e team to /a3e in!een!ent access to t/e boar! assemblies at any time% T/e a3ailability ocomlete! test assemblies *as a real a!3antage to t/e team%

3.2 FP&A Firm'are %esign

T/e team oun! a large amount o reerence material to /el go or*ar! *it/ t/e =5D !esign in t/ero:ect% &imilar ro:ects taking lace at t/e Digilents omanian oice in3ol3e! cameras an! !islaysin t/e ast an! t/e team *as gi3en !irection by t/e mentor to reer to t/ese sources to see i t/ey coul!be use! to get any insig/t into tec/niBues o camera control an! lacing image !ata on a !islay% T/isro3e! to be a great resource since a great le3el o comatibility *as be 3eriie! bet*een t/ereerence! *orks an! to */at *as in3ol3e! in t/e ro:ects o3erall !esign%

Dion Moses rimarily ocuse! on t/e imlementation o t/e irm*are or t/is !esign% T/e teamnominate! /im to be t/e c/ie arc/itect or t/e ro:ect% As t/e c/ie arc/itect, /e !i! a roug/ global!ra*ing co3ering all asects o t/e !esign% T/e !ra*ing *as broken u into comonents% $ac/comonent /a! a !eine! interace t/at interconnecte! one comonent to anot/er% T/e arc/itect !eine!

t/ese interconnects an! assigne! in!i3i!ual comonents to members o t/e team% $ac/ team membert/en took t/eir comonent an! !esign t/e internals o eac/, ensuring t/at t/e interconnect signals matc/t/e original seciication !e3eloe! by t/e arc/itect% T/is ensure! t/at */en all o t/e comonents*ere broug/t back toget/er ater t/eir !e3eloment, t/ey *oul! be able to communicate *it/ eac/ot/er an! *ork as originally seciie! by t/e arc/itect% T/is aroac/ enable! t/e !esign to be brokenu an! !e3eloment to rocee! among comonents in arallel, allo*ing or greatest eiciency an!see!%

T/e c/osen !esign rocess also allo*e! or ease o testing */en t/e nee! or !ebugging arose% Testingconsiste! o *riting an! running test benc/ simulations o in!i3i!ual comonents */en necessary%'riting test benc/es an! 3eriying outut *as time consuming an! unnecessary i team members *ere

careul to ollo* t/e !esign o t/e arc/itect% &imulating test benc/es *ere useul to ro3e t/at a gi3encomonent !i! ollo* t/e interace seciication create! by t/e arc/itect% I a comonents be/a3ior!i! not ollo* t/at set by t/e arc/itect, it intro!uce! errors into t/e rest o t/e system%

3.3 (is)

T/e greatest risk in t/e ro:ect *as t/e uncertainty o camera selection% It *as !isco3ere! later in are3ious semester t/at &T Microelectronics /a! !iscontinue! ro!uction o t/e =&(#02=01# cameramo!ule% Digilents main sulier, Digikey, /a! aroun! t/reet/ousan! in stock, but t/ey !i! not lan tourc/ase any more */en sulies got lo*% T/e team sent a great !eal o time in t/e re3ious semester

trying to select a camera mo!ule t/at coul! be rea!ily accessible in smaller Buantities but oun! t/atsuliers *ere not intereste! in selling mo!ules or releasing !ata s/eets to buyers o small Buantities%&uliers target /ig/3olume clients suc/ as cellular tele/one comanies */o urc/ase mo!ules ont/e or!er o /un!re!s o t/ousan!s o units%

T/e team oun! a target mo!ule or consi!eration !esigne! by +mni3ision% T/is mo!ule reBuire! ne*rinte!circuit boar!s to be !esigne! an! abricate! beore signiicant =5D !esign can be *ritten orteste!% T/is mo!ule *as accessible in smaller Buantities an! suorte! by t/e manuacturer at t/e time%


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*.1.1 Pi"el Processor

T/e main =5D !esign asect or t/e team t/ereore re3ol3e! aroun! t/e !e3eloment o an imagerocessor mo!ule% Moses !e3eloe! a !esign or t/e mo!ule t/at took 24bit


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&*itc/ing bet*een t/ese t*o states occurs continuously as i8el !ata is analyEe! rom t/e rest o t/erame until t/e en! o t/e rame% '/en t/e $+- occurs, signiie! by t/e 3ertical count o 3i!eo !atalines rom t/e camera becoming greater t/an 4;0, stInit"omarison is latc/e! as t/e ne8t resent state%T/is signiies t/e beginning o t/e ne8t rame */ere initial i8el !ata analysis begins again%

In or!er to !etermine an aroriate range o


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ensures t/at t/e 3ie*er *ill be able to !istinctly rea! c/aracters, instea! o blurring toget/er *it/rai!ly c/anging coor!inate 3ectors% T/e c/aracter ainter block o t/e !esign is ma!e u o oursmaller blocks% T/ese blocks are ma!e u as ollo*s@

*.1.2.1 $loc) (A+

T/e block AM *as instantiate! using nati3e >ilin8 rimiti3es% T/e -P


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gi3ing it a reres/ rate o )05E%

*.2 Implementation and %emonstration

sing t/e inal =5D iles rom our !esign t/e team *as able to establis/ an -P


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Figure 6 / F42 TFT%$ (e#. A. Top Sil)screen


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Figure 7 / F42 TFT%$ (e# $ Scematic


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Figure 8 / F42 TFT%$ (e# $ Top Sil)screen


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*.3.2 PmodCA+1

Figure 19 / PmodCA+1 Scematic


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Figure 11 / PmodCA+1 Top Sil)screen


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*.3.3 PmodFFC

Figure 12 / PmodFFC Scematic


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Figure 13 / PmodFFC Top Sil)screen

Proect +anagement and Future :or)

T/e tasks erorme! in t/e ro:ect /a3e been mostly !esignoriente!% T/e o3erall ormat an!seciications o t/e ro!uct *ere !eci!e! uon an! a general arc/itecture or t/e sot*are *as

en3isione!% Members *ere continually *riting sot*are mo!ules an! a *orking /ar!*are rototye*as built%

-uture *ork on t/e /ar!*are si!e inclu!es a ne* camera P" t/at *ill be reBuire! !ue to artobsolescence issues% Digilent also seeks to comletely re3am t/e !esign o t/e ->2T-TD to anot/erboar! t/at *ill /a3e a better screen an! !ierent connector as *ell% A!!itionally, ro!uct!ocumentation *ill be *ritten an! a ackage !esigne! or eac/ o t/ese ne* ro!ucts%

5 Impact !#aluation

To t/oroug/ly e3aluate t/e imact o t/e teamFs ro:ect, t/is section *ill a!!ress t/e current solution

*it/ resect to et/ical, societal, economic, an! global consi!erations% T/e urose o t/is e3aluation isto ensure t/at t/e ro:ect solution is most eecti3e *it/ resect to t/e re3iously liste! consi!erations%

5.1 Proect Scope

T/e scoe o t/is ro:ect *as to !esign a 3i!eo.camera system */ic/ interaces *it/ a Digilent 6e8ys2-P


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t/ese mo!ules *as essential or t/e irm*are */ic/ controlle! t/e 3i!eo !islay an! image recognitionalgorit/m%

To !e3elo t/e irm*are t/e team !eci!e! to rogram t/e Digilent 6e8ys2 -Pilin8 I&$ 'ebPack*/ic/ is ree sot*are H1#% + course t/e cost o t/e teams labor *as ree o c/arge%

'/en t/is ro!uct is intro!uce! it *ill be t/e lo*est cost 3i!eo !islay !e3eloment solution a3ailableon t/e market% elo* in -igure 12 is a table summariEing t/e teams market researc/%


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6 Conclusion

'it/ t/e comletion o t/e rototye !emonstrate! at t/e inal oster session, t/e team realiEe! t/eirgoal o creating t*o ne* ro!ucts to integrate into DigilentFs ro!uct line%

A "M+& camera *as c/osen or t/e Pmo! "AM1 */ic/ it t/e alication% Images rom t/e camera

are o t/e reBuire! Buality or e!ucational an! /obbyist use% A boar! *as lai! out or t/e Pmo!"AM1,*/ic/ successully interaces *it/ t/e 6e8ys2 boar!% Mo!iications to t/e ->2 T-TD boar! *illallo* it to be use! as a /ysical interace or t/e camera%

T/e reerence !esign ut toget/er by t/e team is comlete% "amera images are 3ie*able on t/e !islayat a rame rate /ig/ enoug/ to simulate 3i!eo% T/e sot*are successully in!s a re! $D in t/ecameraFs rame, /ig/lig/ts it *it/ a bo8 on t/e screen, an! !ra*s t/e bo8Fs coor!inates%

Part a3ailability issues *ill orce a re!esign o t/e Pmo! "AM1, but t/is s/oul! be tri3ial an! t/ereerence !esign *ill /a3e to be mo!iie! only slig/tly to accet a !ierent camera mo!ule%

7 Ac)no'ledgement

T/e team *oul! like to t/ank Digilent an! "lint "ole or sonsoring our team an! t/is ro:ect% Ina!!ition, t/e team *oul! like to t/ank o/n ates, oy ean, Mike 5iggens, an! $lo!


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------ utputs:------------------------------------------------------------------------------ !evision "istory:--

-- 09#0$#2009%DionM&: cre'ted--------------------------------------------------------------------------libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;

entityPixelProcis

Port(PRED_I:in STD_LOGIC_VECTOR(5downto0); RESET :in STD_LOGIC;

PGREEN_I:in STD_LOGIC_VECTOR(5downto0); PBLUE_I:in STD_LOGIC_VECTOR(5downto0); PRED_O:out STD_LOGIC_VECTOR(5downto0); PGREEN_O:out STD_LOGIC_VECTOR(5downto0); PBLUE_O:out STD_LOGIC_VECTOR(5downto0); PDE:in STD_LOGIC; HCNT:in STD_LOGIC_VECTOR(9downto0); VCNT:in STD_LOGIC_VECTOR(9downto0); DCLK_I:in STD_LOGIC);endPixelProc;

architectureBeh!iorlofPixelProcis

------------------------------------------------------- Constant Declarations -------------------------------------------------------

--constant threshold values that the most minimum red pixel value will be--compared toconstantr_li"h#Thre$hol%:std_logic_vector(5downto0):&(others&''1');constant"_li"h#Thre$hol%:std_logic_vector(5downto0):&"100100";constant_li"h#Thre$hol%:std_logic_vector(5downto0):&"100100";

constantr_%rThre$hol%:std_logic_vector(5downto0):&"110000";constant"_%rThre$hol%:std_logic_vector(5downto0):&(others&''0');constant_%rThre$hol%:std_logic_vector(5downto0):&(others&''0');

type$re"_#*+eis($#I,i#Co-+ri$o,$#U+%#e$#Co,#Co-+ri$o,);signal$#Pre$$#Nex#:$re"_#*+e:&$#I,i#Co-+ri$o,;

--Dynamically changing red pixel valuessignalr_#hre$h:std_logic_vector(5downto0):&(others&''0');signal"_#hre$h:std_logic_vector(5downto0):&(others&''0');signal_#hre$h:std_logic_vector(5downto0):&(others&''0');


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signalhloc:std_logic_vector(9downto0):&(others&''0');signal!loc:std_logic_vector(9downto0):&(others&''0');

signalDhloc:std_logic_vector(9downto0):&(others&''0');signalD!loc:std_logic_vector(9downto0):&(others&''0');

signal/o0,%:std_logic:&'0';signalD/o0,%:std_logic:&'0';

signal+lce-e,#:std_logic:&'0';

begin

--may have to latch on 50 MHz clockREG:process(DCLK_I)begin

ifRESET&'1' then$#Pre$1&$#I,i#Co-+ri$o,;

elsifrising_edge(DCLK_I)then$#Pre$1&$#Nex#;

endif;endprocess;

ColorCo-+ri$o,:process($#Pre$PRED_IPGREEN_IPBLUE_I)begincase$#Pre$is

when$#I,i#Co-+ri$o,&'--finds initial reddest pixelifPRED_I'&r_%rThre$hol%andPRED_I1&r_li"h#Thre$hol%and

PGREEN_I1&"_li"h#Thre$hol%andPGREEN_I'&"_%rThre$hol%and

PBLUE_I1&_li"h#Thre$hol%andPBLUE_I'&_%rThre$hol%then

$#Nex#1&$#U+%#e;else

$#Nex#1&$#I,i#Co-+ri$o,;endif;

when$#U+%#e&'$#Nex#1&$#Co,#Co-+ri$o,;

when$#Co,#Co-+ri$o,&'--finds next reddest pixel by comparison

ifPRED_I'r_#hre$handPGREEN_I1"_#hre$handPBLUE_I1_#hre$hthen$#Nex#1&$#U+%#e;

elsifVCNT'&507then$#Nex#1&$#I,i#Co-+ri$o,;

else$#Nex#1&$#Co,#Co-+ri$o,;

endif;

whenothers&'$#Nex#1&$#I,i#Co-+ri$o,;

endcase;endprocess;

--latch data appropriatelyColorC+#0re:process($#Pre$PRED_IPGREEN_IPBLUE_IHCNTVCNT)begin

if$#Pre$&$#U+%#ethen


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-- TARGETHCNT : STD_LOGIC_VECTOR(9 downto 0), LED coordinates-- TARGETVCNT : STD_LOGIC_VECTOR(8 downto 0), LED coordinates-- TARGETVALID : STD_LOGIC, paint enablesignal---- Outputs:-- BOXPAINT : STD_LOGIC, indicator to thelcd controller to--

overwrite image data at the current--pixel coordinates with box color for painting the

--box.

---------------------------------------------------------------------------- Revision History:---- 10/25/2009 (MarkT): created------------------------------------------------------------------------libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;

entityBoxPi,#erisPort(

CLK:inSTD_LOGIC;DISPL56HCNT:inSTD_LOGIC_VECTOR(9downto0);DISPL56VCNT:inSTD_LOGIC_VECTOR(8downto0);T5RGETHCNT:inSTD_LOGIC_VECTOR(9downto0);T5RGETVCNT:inSTD_LOGIC_VECTOR(8downto0);T5RGETV5LID:inSTD_LOGIC;BO7P5INT:outSTD_LOGIC);

endBoxPi,#er;

architectureBeh!iorlofBoxPi,#eris-------------------------------------------------------------------------- Component Declarations------------------------------------------------------------------------

-- Xilinx Library Components

-- Project Components

-------------------------------------------------------------------------- General control and timing signals------------------------------------------------------------------------signali,#_hor_#r"e#_coor%i,#e$:integerrange0to102481;signali,#_!er#_#r"e#_coor%i,#e$:integerrange0to51281;signali,#_%i$+l*_!c,#:integerrange0to51281;signali,#_%i$+l*_hc,#:integerrange0to102481;signal+i,#:std_logic;

constant!er#icl_+%%i,":NATURAL:&20;constanthori9o,#l_+%%i,":NATURAL:&20;

------------------------------------------------------------------------


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-- Data path signals------------------------------------------------------------------------

-------------------------------------------------------------------------- Implementation------------------------------------------------------------------------

begin

--tie internal signals to port signalsi,#_%i$+l*_!c,#1&co,!_i,#e"er(DISPL56VCNT);i,#_%i$+l*_hc,#1&co,!_i,#e"er(DISPL56HCNT);

i,#_!er#_#r"e#_coor%i,#e$ 1&co,!_i,#e"er(T5RGETVCNT);i,#_hor_#r"e#_coor%i,#e$1&co,!_i,#e"er(T5RGETHCNT);

---------------------Clocked logic-------------------------------cloce%_lo"ic:process(CLK)isbegin

if(rising_edge(CLK))then

if(T5RGETV5LID

&

'1')

then--if box painter is enabled

--Draw Top/Bottom of the boxif((i,#_%i$+l*_!c,#&(i,#_!er#_#r"e#_coor%i,#e$ 8

!er#icl_+%%i,"))OR(i,#_%i$+l*_!c,#&(i,#_!er#_#r"e#_coor%i,#e$

!er#icl_+%%i,")))then

if((i,#_%i$+l*_hc,#'&(i,#_hor_#r"e#_coor%i,#e$8hori9o,#l_+%%i,"))

AND(i,#_%i$+l*_hc,#1&(i,#_hor_#r"e#_coor%i,#e$ hori9o,#l_+%%i,")))then

BO7P5INT1&'1';

else--not on the horizontal area of top/bottomBO7P5INT1&'0';

endif;

--Draw sides of the boxelsif((i,#_%i$+l*_!c,#'(i,#_!er#_#r"e#_coor%i,#e$8

!er#icl_+%%i,"))AND(i,#_%i$+l*_!c,#1(i,#_!er#_#r"e#_coor%i,#e$

!er#icl_+%%i,")))then

if((i,#_%i$+l*_hc,#&(i,#_hor_#r"e#_coor%i,#e$8hori9o,#l_+%%i,"))

OR(i,#_%i$+l*_hc,#&(i,#_hor_#r"e#_coor%i,#e$

hori9o,#l_+%%i,")))

then

BO7P5INT1&'1';

--Place a 'dot' in the center of the targetelsif((i,#_%i$+l*_hc,#&i,#_hor_#r"e#_coor%i,#e$)

AND(i,#_%i$+l*_!c,#&(i,#_!er#_#r"e#_coor%i,#e$)) )then

BO7P5INT1&'1';


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else-- not on the sides or centerBO7P5INT1&'0';

endif;

else--not in the target perimeterBO7P5INT1&'0';

endif;

else--box painter is disabledBO7P5INT1&'0';

endif;

endif;---------------------end Clocked logic------------------

endprocess;--------------------------------------------------------------------

endBeh!iorl;

8.1.1.3 CaracterPainter.#d-------------------------------------------------------------------------- CharacterPainter.vhd ; Character drawing mechanism for the Team Sea Beast project-------------------------------------------------------------------------- Author: Mark Taylor-- Copyright 2009 Digilent, Inc.-------------------------------------------------------------------------- Module description---- Inputs:-- DISPLAYHCNT : STD_LOGIC_VECTOR(9 downto 0), current PIXEL writing coordinates-- DISPLAYVCNT : STD_LOGIC_VECTOR(8 downto 0), current PIXEL writing coordinates-- CHARACTERVALID : STD_LOGIC, paint enable signal---- Outputs:-- CHARACTERPAINT : STD_LOGIC, indicator to the lcdcontroller to

--overwrite image data at the current

--pixel coordinates with character color

---------------------------------------------------------------------------- Revision History:---- 11/10/2009 (MarkT): created------------------------------------------------------------------------libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;


entityChrc#erPi,#erisPort(

CLK:inSTD_LOGIC; 4OSI :in std_logic;


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attributeINIT_=5 :string; attributeINIT_=B :string; attributeINIT_=C :string; attributeINIT_=D :string; attributeINIT_=E :string; attributeINIT_=3 :string; attributeINIT_> :string; attributeINIT_>= :string; attributeINIT_>> :string; attributeINIT_>? :string; attributeINIT_>@ :string; attributeINIT_>A :string; attributeINIT_> :string; attributeINIT_> :string; attributeINIT_> :string; attributeINIT_>5 :string; attributeINIT_>B :string; attributeINIT_>C :string; attributeINIT_>D :string; attributeINIT_>E :string; attribute

INIT_>3

:string

; attributeINITP_ :string; attributeINITP_ :string; attributeINITP_? :string; attributeINITP_@ :string; attributeINITP_A :string; attributeINITP_ :string; attributeSRV5L_5 :string; attributeSRV5L_B :string; attributeRITE_4ODE_5 :string; attributeRITE_4ODE_B :string; attributeINIT_5 :string;

attributeINIT_B :string; attributeSI4_COLLISION_CHECK:string; attributeBO7_T6PE :string;------------------------------------------------ signalchrc#erRO4_hor+ix+o$ :std_logic_vector(2downto0); signalchrc#erRO4_!er#+ix+o$ :std_logic_vector(3downto0); signalchrc#erRO4_+ixel$#roe :std_logic; signallocR54_#ie_#o_",% :std_logic; signallocR54_%i+ :std_logic_vector(0downto0); signalchrc#erRO4_$cii_i, :std_logic_vector(7downto0); signallocR54_%%r :std_logic_vector(10downto0); signallocR54_e, :std_logic; signallocR54_e, :std_logic; signal

locR54_%%r

:std_logic_vector

(10downto0

); signallocR54_%i :std_logic_vector(7downto0); signallocR54_%i :std_logic_vector(7downto0); signallocR54_%i+:std_logic_vector(0downto0);

signal$+i_locR54_e,:std_logic;signal$+i_locR54_%%r:std_logic_vector(10downto0);signal$+i_locR54_%#:std_logic_vector(7downto0);

signalci_locR54_e,:std_logic;


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signalci_locR54_%%r:std_logic_vector(10downto0);signalci_locR54_%#:std_logic_vector(7downto0);

signali,#Hc,#:integerrange0to80081;--PLD-1 - horizontal countersignali,#Vc,#:integerrange0to52581;-- LFD-1 - verical counter

-- constants for display timingconstantTHD:integer:&639; --Pixels/Active Line (pixels)

constantTVD:integer:&479; --Lines/Active Frame (lines)constantTVBP:integer:&27; --Verical synchro Back Porch (lines)constantTHBP:integer:&2; --Horizontal synchro Back Porch (pixels)

--Pixel counter / Character counterssignali,#HorPixPo$:integerrange0to1681;--character width * 2signali,#Ver#PixPo$:integerrange0to2081;--character height * 2signal!ec#HorPixPo$:std_logic_vector(3downto0);--helper signalsignal!ec#Ver#PixPo$:std_logic_vector(4downto0);--helper signalsignali,#HorChrPo$:integerrange0to4081;--number of chars / rowsignali,#Ver#ChrPo$:integerrange0to2481;--number of chars / column

------------------------------------------------

----------------------------------------------------------------------------------------Component Declarations

--------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------- componentChrc#erRO4 port(HorPixPo$ :in std_logic_vector(2downto0);

Ver#PixPo$ :in std_logic_vector(3downto0);5SCII_IN :in std_logic_vector(7downto0);PixelS#roe:out std_logic);

endcomponent;----------------------------------------------------------------------------------------

componentR54B


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INIT_B:bit_vector:&x"0000000000000000000000000000000000000000000000000000000000000000";

INIT_C:bit_vector:&x"0000000000000000000000000000000000000000000000000000000000000000";

INIT_D:bit_vector:&x"0000000000000000000000000000000000000000000000000000000000000000";

INIT_E:bit_vector:&x"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3:bit_vector:&x"0000000000000000000000000000000000000000000000000000000000000000";

INIT_


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x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_=:bit_vector:&

x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_=:bit_vector:&

x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_=5:bit_vector:&

x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_=B:bit_vector:&

x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_=C:bit_vector:&

x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_=D:bit_vector:&

x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_=E:bit_vector:&

x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_=3:bit_vector:&

x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_>:bit_vector:&

x"0000000000000000000000000000000000000000000000000000000000000000"; INIT_>=:

bit_vector:&

x"0000000000000000000000000000000000000000000000000000000000000000";

INIT_>>:bit_vector:&x"0000000000000000000000000000000000000000000000000000000000000000";

INIT_>?:bit_vector:&x"0000000000000000000000000000000000000000000000000000000000000000";

INIT_>@:bit_vector:&x"0000000000000000000000000000000000000000000000000000000000000000";

INIT_>A:bit_vector:&x"0000000000000000000000000000000000000000000000000000000000000000";

INIT_>:bit_vector:&x"0000000000000000000000000000000000000000000000000000000000000000";

INIT_>:bit_vector:&x"0000000000000000000000000000000000000000000000000000000000000000";

INIT_>:bit_vector:&x"0000000000000000000000000000000000000000000000000000000000000000";

INIT_>5:bit_vector:&x"0000000000000000000000000000000000000000000000000000000000000000";

INIT_>B:bit_vector:&x"0000000000000000000000000000000000000000000000000000000000000000";

INIT_>C:bit_vector:&x"0000000000000000000000000000000000000000000000000000000000000000";

INIT_>D:bit_vector:&x"0000000000000000000000000000000000000000000000000000000000000000";

INIT_>E:bit_vector:&x"0000000000000000000000000000000000000000000000000000000000000000";

INIT_>3:bit_vector:&

x"0000000000000000000000000000000000000000000000000000000000000000"; INITP_:bit_vector:&x"0000000000000000000000000000000000000000000000000000000000000000";

INITP_:bit_vector:&x"0000000000000000000000000000000000000000000000000000000000000000";


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attributeINIT_BofR54B


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"0000000000000000000000000000000000000000000000000000000000000000"; attributeINIT_=ofR54B


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attributeINITP_?ofR54B


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---------------------------------------------------------------------------------------- 7L7I_?:Chrc#erRO4 portmap(5SCII_IN(7downto0)&'chrc#erRO4_$cii_i,(7downto0) HorPixPo$(2downto0)&'chrc#erRO4_hor+ix+o$(2downto0) Ver#PixPo$(3downto0)&'chrc#erRO4_!er#+ix+o$(3downto0) PixelS#roe&'chrc#erRO4_+ixel$#roe);----------------------------------------------------------------------------------------

7L7I_


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);

----------------------------------------------------------------------------------------

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

-- mapping the std_logic_vector ports to internal integersi,#Hc,#1&co,!_i,#e"er(DISPL56HCNT);i,#Vc,#1&co,!_i,#e"er(DISPL56VCNT);

--Map Pixel/Character addresses with outside signals!ec#HorPixPo$1&co,!_$#%_lo"ic_!ec#or(i,#HorPixPo$ 4);!ec#Ver#PixPo$1&co,!_$#%_lo"ic_!ec#or(i,#Ver#PixPo$ 5);

chrc#erRO4_hor+ix+o$1&!ec#HorPixPo$(3downto1);--divide number by two and sharechrc#erRO4_!er#+ix+o$1&!ec#Ver#PixPo$(4downto1);--divide number by two and share

--Create Character Address bus to share with block RAMlocR54_%%r1&((co,!_$#%_lo"ic_!ec#or(i,#HorChrPo$ 6))F

(co,!_$#%_lo"ic_!ec#or(i,#Ver#ChrPo$ 5)));

--use our CHARACTERVALID "enable" signal in connection with the PixelStrobe

CH5R5CTERP5INT1&chrc#erRO4_+ixel$#roe;

--blockRAM input muxes between SPI component and the CI component based on SS pinlocR54_e,1&ci_locR54_e,when SS&'1' else

$+i_locR54_e,;locR54_%i1&ci_locR54_%#whenSS&'1' else

$+i_locR54_%#;locR54_%%r1&ci_locR54_%%rwhenSS&'1' else

$+i_locR54_%%r;

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

-ixer:process(CLKi,#Hc,#i,#Vc,#)begin


if(i,#Vc,#1TVBP)then--before vertically displayable region, reset vertical countersi,#Ver#PixPo$1&0;--reseti,#Ver#ChrPo$1&0;--reset

elsif((i,#Vc,#'&TVBP)AND(i,#Vc,#1&(TVBPTVD)))then--in verticallydisplayable region

if(i,#Hc,#1&THBP)then--before horizontally displayable region or at hor = 0i,#HorPixPo$1&0;--reseti,#HorChrPo$1&0;--reset--new line, increment vertical countersif(

(i,#Hc,#

&

THBP

8

1)

AND(i,#Vc,#

'

TVBP)

)

then--pixel beforedisplayable, increment

if(i,#Ver#PixPo$119)theni,#Ver#PixPo$1&i,#Ver#PixPo$1;--increment

elsei,#Ver#PixPo$1&0;--reset, begin new char linei,#Ver#ChrPo$1&i,#Ver#ChrPo$1;--increment w/o

checkendif;

endif;


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--increment intHorPixPos, maintain intHorCharPoselsif((i,#Hc,#'THBP)AND(i,#HorPixPo$115))then

i,#HorPixPo$1&i,#HorPixPo$1;--incrementelsif((i,#Hc,#'THBP)AND(i,#HorPixPo$&15))then

i,#HorPixPo$1&0;--reseti,#HorChrPo$1&i,#HorChrPo$1;--increment

endif;endif;

endif;-- end clocked logicendprocess;

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

endBeh!iorl;

-------------------------------- EOF ---------------------------------------------------

9.1.1.4 CharacterRom.vhd-------------------------------------------------------------------------- CharacterROM.vhd -- Contains maps for ASCII characters-------------------------------------------------------------------------- Author: Mark Taylor-- Copyright 2008 Digilent, Inc.-------------------------------------------------------------------------- Module description------ Inputs:------ Outputs:------------------------------------------------------------------------------ Revision History:

---- 10/30/2008(MarkT): created--------------------------------------------------------------------------

libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;

entityChrc#erRO4isPort(

HorPixPo$:inSTD_LOGIC_VECTOR(2downto0);Ver#PixPo$:inSTD_LOGIC_VECTOR(3downto0);

5SCII_IN:inSTD_LOGIC_VECTOR(7downto0);PixelS#roe:outSTD_LOGIC

);endChrc#erRO4;

architectureBeh!iorlofChrc#erRO4is

signalChrSelec#:integerrange0to95;--used to convert ascii value to lookup value


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-------------------------------------------------------------------------- Our ROM type------------------------------------------------------------------------

typeTO_DI4_5isarray(integerrange0to9integerrange0to7)ofstd_logic;typeTHREE_DI4_5isarray(integerrange0to95)ofTO_DI4_5;

-------------------------------------------------------------------------- General control and timing signals

------------------------------------------------------------------------constant5$ciiRO4:THREE_DI4_5:&((('0''0''0''0''0''0''0''0') -- SPACE('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''1''0''0''0''0''0') -- !('0''0''1''0''0''0''0''0')('0''0''1''0''0''0''0''0')('0''0''1''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''1''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(

('0''0''1''0''1''0''0''0') -- "('0''0''1''0''1''0''0''0')('0''0''1''0''1''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''1''0''1''0''0''0') -- #('0''0''1''0''1''0''0''0')('0''1''1''1''1''1''0''0')('0''0''1''0''1''0''0''0')('0''1''1''1''1''1''0''0')('0''0''1''0''1''0''0''0')('0''0''1''0''1''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))


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(('0''0''0''1''0''0''0''0') -- $('0''0''1''1''1''1''0''0')('0''1''0''1''0''0''0''0')('0''0''1''1''1''0''0''0')('0''0''0''1''0''1''0''0')('0''1''1''1''1''0''0''0')('0''0''0''1''0''0''0''0')

('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''1''1''0''0''0''0''0') -- %('0''1''1''0''0''1''0''0')('0''0''0''0''1''0''0''0')('0''0''0''1''0''0''0''0')('0''0''1''0''0''0''0''0')('0''1''0''0''1''1''0''0')('0''0''0''0''1''1''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''1''1''0''0''0''0') -- &('0''1''0''0''1''0''0''0')('0''1''0''1''0''0''0''0')('0''0''1''0''0''0''0''0')('0''1''0''1''0''1''0''0')('0''1''0''0''1''0''0''0')('0''0''1''1''0''1''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''1''1''0''0''0''0') -- '('0''0''0''1''0''0''0''0')('0''0''1''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(

('0''0''0''0''1''0''0''0') -- (('0''0''0''1''0''0''0''0')('0''0''1''0''0''0''0''0')('0''0''1''0''0''0''0''0')('0''0''1''0''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''0''1''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')


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('0''0''0''0''0''0''0''0'))

(('0''0''1''0''0''0''0''0') -- )('0''0''0''1''0''0''0''0')('0''0''0''0''1''0''0''0')('0''0''0''0''1''0''0''0')('0''0''0''0''1''0''0''0')

('0''0''0''1''0''0''0''0')('0''0''1''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''0''0''0''0''0') -- *('0''0''0''1''0''0''0''0')('0''1''0''1''0''1''0''0')('0''0''1''1''1''0''0''0')('0''1''0''1''0''1''0''0')('0''0''0''1''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''0''0''0''0''0') -- +('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''1''1''1''1''1''0''0')('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')

('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''0''0''0''0''0') -- ,('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''1''1''0''0''0')('0''0''0''0''1''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''0''0''0''0''0') -- -(minus)('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''1''1''1''1''1''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')


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('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''0''0''0''0''0') -- .(period)('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')

('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''1''1''0''0''0''0')('0''0''1''1''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''0''0''0''0''0') -- /('0''0''0''0''0''1''0''0')('0''0''0''0''1''0''0''0')('0''0''0''1''0''0''0''0')('0''0''1''0''0''0''0''0')('0''1''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''1''1''1''0''0''0') -- 0('0''1''0''0''0''1''0''0')('0''1''0''0''1''1''0''0')('0''1''0''1''0''1''0''0')('0''1''1''0''0''1''0''0')('0''1''0''0''0''1''0''0')

('0''0''1''1''1''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''1''0''0''0''0') -- 1('0''0''1''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''1''1''1''0''0''0')('0''0''0''0''0''0''0''0')

('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''1''1''1''0''0''0') -- 2('0''1''0''0''0''1''0''0')('0''0''0''0''0''1''0''0')('0''0''0''0''1''0''0''0')('0''0''0''1''0''0''0''0')


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('0''0''1''0''0''0''0''0')('0''1''1''1''1''1''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''1''1''1''1''1''0''0') -- 3

('0''0''0''0''1''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''0''1''0''0''0')('0''0''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''0''1''1''1''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''0''1''0''0''0') -- 4('0''0''0''1''1''0''0''0')('0''0''1''0''1''0''0''0')('0''1''0''0''1''0''0''0')('0''1''1''1''1''1''0''0')('0''0''0''0''1''0''0''0')('0''0''0''0''1''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''1''1''1''1''1''0''0') -- 5('0''1''0''0''0''0''0''0')('0''1''1''1''1''0''0''0')('0''0''0''0''0''1''0''0')

('0''0''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''0''1''1''1''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''1''1''0''0''0') -- 6('0''0''1''0''0''0''0''0')('0''1''0''0''0''0''0''0')('0''1''1''1''1''0''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')

('0''0''1''1''1''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''1''1''1''1''1''0''0') -- 7('0''1''0''0''0''1''0''0')('0''0''0''0''0''1''0''0')


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('0''0''0''0''1''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''1''1''1''0''0''0') -- 8('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''0''1''1''1''0''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''0''1''1''1''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''1''1''1''0''0''0') -- 9('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''0''1''1''1''1''0''0')('0''0''0''0''0''1''0''0')('0''0''0''0''1''0''0''0')('0''0''1''1''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''0''0''0''0''0') -- :('0''0''1''1''0''0''0''0')

('0''0''1''1''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''1''1''0''0''0''0')('0''0''1''1''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''0''0''0''0''0') -- ;('0''0''1''1''0''0''0''0')('0''0''1''1''0''0''0''0')('0''0''0''0''0''0''0''0')

('0''0''1''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''1''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''0''1''0''0''0') --


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('0''0''0''1''0''0''0''0')('0''0''1''0''0''0''0''0')('0''1''0''0''0''0''0''0')('0''0''1''0''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''0''1''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')

('0''0''0''0''0''0''0''0'))

(('0''0''0''0''0''0''0''0') -- =('0''0''0''0''0''0''0''0')('0''1''1''1''1''1''0''0')('0''0''0''0''0''0''0''0')('0''1''1''1''1''1''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''1''0''0''0''0''0') -- >('0''0''0''1''0''0''0''0')('0''0''0''0''1''0''0''0')('0''0''0''0''0''1''0''0')('0''0''0''0''1''0''0''0')('0''0''0''1''0''0''0''0')('0''0''1''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(

('0''0''1''1''1''0''0''0') -- ?('0''1''0''0''0''1''0''0')('0''0''0''0''0''1''0''0')('0''0''0''0''1''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''1''1''1''0''0''0') -- @('0''1''0''0''0''1''0''0')

('0''0''0''0''0''1''0''0')('0''0''1''1''0''1''0''0')('0''1''0''1''0''1''0''0')('0''1''0''1''0''1''0''0')('0''0''1''1''1''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))


52/101

(('0''0''1''1''1''0''0''0') -- A('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''1''1''1''1''1''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')

('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''1''1''1''1''0''0''0') -- B('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''1''1''1''1''0''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''1''1''1''1''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''1''1''1''0''0''0') -- C('0''1''0''0''0''1''0''0')('0''1''0''0''0''0''0''0')('0''1''0''0''0''0''0''0')('0''1''0''0''0''0''0''0')('0''1''0''0''0''1''0''0')('0''0''1''1''1''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''1''1''1''0''0''0''0') -- D('0''1''0''0''1''0''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''1''0''0''0')('0''1''1''1''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(

('0''1''1''1''1''1''0''0') -- E('0''1''0''0''0''0''0''0')('0''1''0''0''0''0''0''0')('0''1''1''1''1''0''0''0')('0''1''0''0''0''0''0''0')('0''1''0''0''0''0''0''0')('0''1''1''1''1''1''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')


53/101

('0''0''0''0''0''0''0''0'))

(('0''1''1''1''1''1''0''0') -- F('0''1''0''0''0''0''0''0')('0''1''0''0''0''0''0''0')('0''1''1''1''1''0''0''0')('0''1''0''0''0''0''0''0')

('0''1''0''0''0''0''0''0')('0''1''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''1''1''1''0''0''0') -- G('0''1''0''0''0''1''0''0')('0''1''0''0''0''0''0''0')('0''1''0''1''1''1''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''0''1''1''1''1''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''1''0''0''0''1''0''0') -- H('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''1''1''1''1''1''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''0''0''0''0''0''0''0')

('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''1''1''1''0''0''0') -- I('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''1''1''1''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''1''1''1''0''0') -- J('0''0''0''0''1''0''0''0')('0''0''0''0''1''0''0''0')('0''0''0''0''1''0''0''0')('0''0''0''0''1''0''0''0')('0''1''0''0''1''0''0''0')('0''0''1''1''0''0''0''0')


54/101

('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''1''0''0''0''1''0''0') -- K('0''1''0''0''1''0''0''0')('0''1''0''1''0''0''0''0')

('0''1''1''0''0''0''0''0')('0''1''0''1''0''0''0''0')('0''1''0''0''1''0''0''0')('0''1''0''0''0''1''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''1''0''0''0''0''0''0') -- L('0''1''0''0''0''0''0''0')('0''1''0''0''0''0''0''0')('0''1''0''0''0''0''0''0')('0''1''0''0''0''0''0''0')('0''1''0''0''0''0''0''0')('0''1''1''1''1''1''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''1''0''0''0''1''0''0') -- M('0''1''1''0''1''1''0''0')('0''1''0''1''0''1''0''0')('0''1''0''1''0''1''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')

('0''1''0''0''0''1''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''1''0''0''0''1''0''0') -- N('0''1''0''0''0''1''0''0')('0''1''1''0''0''1''0''0')('0''1''0''1''0''1''0''0')('0''1''0''0''1''1''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''0''0''0''0''0''0''0')

('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''1''1''1''0''0''0') -- O('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')


55/101

('0''1''0''0''0''1''0''0')('0''0''1''1''1''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''1''1''1''1''0''0''0') -- P

('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''1''1''1''1''0''0''0')('0''1''0''0''0''0''0''0')('0''1''0''0''0''0''0''0')('0''1''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''1''1''1''0''0''0') -- Q('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''1''0''1''0''1''0''0')('0''1''0''0''1''0''0''0')('0''0''1''1''0''1''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''1''1''1''1''0''0''0') -- R('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''1''1''1''1''0''0''0')

('0''1''0''1''0''0''0''0')('0''1''0''0''1''0''0''0')('0''1''0''0''0''1''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''1''1''1''1''0''0') -- S('0''1''0''0''0''0''0''0')('0''1''0''0''0''0''0''0')('0''0''1''1''1''0''0''0')('0''0''0''0''0''1''0''0')('0''0''0''0''0''1''0''0')

('0''1''1''1''1''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''1''1''1''1''1''0''0') -- T('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')


56/101


57/101

('0''1''0''0''0''1''0''0')('0''0''1''0''1''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')

('0''0''0''0''0''0''0''0'))

(('0''1''1''1''1''1''0''0') -- Z('0''0''0''0''0''1''0''0')('0''0''0''0''1''0''0''0')('0''0''0''1''0''0''0''0')('0''0''1''0''0''0''0''0')('0''1''0''0''0''0''0''0')('0''1''1''1''1''1''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''1''1''1''0''0''0''0') -- [('0''1''0''0''0''0''0''0')('0''1''0''0''0''0''0''0')('0''1''0''0''0''0''0''0')('0''1''0''0''0''0''0''0')('0''1''0''0''0''0''0''0')('0''1''1''1''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(

('0''0''0''0''0''0''0''0') -- \('0''1''0''0''0''0''0''0')('0''0''1''0''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''0''1''0''0''0')('0''0''0''0''0''1''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''1''1''0''0''0''0') -- ]('0''0''0''0''1''0''0''0')

('0''0''0''0''1''0''0''0')('0''0''0''0''1''0''0''0')('0''0''0''0''1''0''0''0')('0''0''0''0''1''0''0''0')('0''0''1''1''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))


58/101


59/101

('0''0''0''0''0''0''0''0'))

(('0''0''0''0''0''0''0''0') -- c('0''0''0''0''0''0''0''0')('0''0''1''1''1''0''0''0')('0''1''0''0''0''0''0''0')('0''1''0''0''0''0''0''0')

('0''1''0''0''0''1''0''0')('0''0''1''1''1''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''0''0''1''0''0') -- d('0''0''0''0''0''1''0''0')('0''0''1''1''0''1''0''0')('0''1''0''0''1''1''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''0''1''1''1''1''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''0''0''0''0''0') -- e('0''0''0''0''0''0''0''0')('0''0''1''1''1''0''0''0')('0''1''0''0''0''1''0''0')('0''1''1''1''1''1''0''0')('0''1''0''0''0''0''0''0')('0''0''1''1''1''0''0''0')('0''0''0''0''0''0''0''0')

('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''1''1''0''0''0') -- f('0''0''1''0''0''1''0''0')('0''0''1''0''0''0''0''0')('0''1''1''1''0''0''0''0')('0''0''1''0''0''0''0''0')('0''0''1''0''0''0''0''0')('0''0''1''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''0''0''0''0''0')\i0 -- g0('0''0''0''0''0''0''0''0')('0''0''1''1''1''1''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''0''1''1''1''1''0''0')('0''0''0''0''0''1''0''0')


60/101

('0''0''1''1''1''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''1''0''0''0''0''0''0')\i0 -- h0('0''1''0''0''0''0''0''0')('0''1''0''1''1''0''0''0')

('0''1''1''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''1''0''0''0''0')\i0 -- i0('0''0''0''0''0''0''0''0')('0''0''1''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''1''1''1''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''0''1''0''0''0')\i0 -- j0('0''0''0''0''0''0''0''0')('0''0''0''1''1''0''0''0')('0''0''0''0''1''0''0''0')('0''0''0''0''1''0''0''0')('0''1''0''0''1''0''0''0')

('0''0''1''1''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''1''0''0''0''0''0''0')\i0 -- k0('0''1''0''0''0''0''0''0')('0''1''0''0''1''0''0''0')('0''1''0''1''0''0''0''0')('0''1''1''0''0''0''0''0')('0''1''0''1''0''0''0''0')('0''1''0''0''1''0''0''0')('0''0''0''0''0''0''0''0')

('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''1''1''0''0''0''0')\i0 -- l0('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')


61/101


62/101


63/101

('0''0''0''0''0''0''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''0''1''0''1''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')

('0''0''0''0''0''0''0''0'))

(('0''0''0''0''0''0''0''0')\i0 -- w0('0''0''0''0''0''0''0''0')('0''1''0''0''0''1''0''0')('0''1''0''1''0''1''0''0')('0''1''0''1''0''1''0''0')('0''1''0''1''0''1''0''0')('0''0''1''0''1''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''0''0''0''0''0')\i0 -- x0('0''0''0''0''0''0''0''0')('0''1''0''0''0''1''0''0')('0''0''1''0''1''0''0''0')('0''0''0''1''0''0''0''0')('0''0''1''0''1''0''0''0')('0''1''0''0''0''1''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(

('0''0''0''0''0''0''0''0')\i0 -- y0('0''0''0''0''0''0''0''0')('0''1''0''0''0''1''0''0')('0''1''0''0''0''1''0''0')('0''0''1''1''1''1''0''0')('0''0''0''0''0''1''0''0')('0''0''1''1''1''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''0''0''0''0''0')\i0 -- z0('0''0''0''0''0''0''0''0')

('0''1''1''1''1''1''0''0')('0''0''0''0''1''0''0''0')('0''0''0''1''0''0''0''0')('0''0''1''0''0''0''0''0')('0''1''1''1''1''1''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))


64/101

(('0''0''0''0''1''0''0''0')\i0 -- {0('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''1''0''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''0''1''0''0''0')

('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''1''0''0''0''0')\i0 -- |(vertical bar)0('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''1''0''0''0''0''0')\i0 -- }0('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''0''1''0''0''0')('0''0''0''1''0''0''0''0')('0''0''0''1''0''0''0''0')('0''0''1''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(('0''0''0''0''0''0''0''0')\i0 -- ~0('0''0''0''0''0''0''0''0')('0''0''1''0''0''1''0''0')('0''1''0''1''1''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0'))

(

('0''0''0''0''0''0''0''0')\i0 -- DEL -> SPACE0('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')('0''0''0''0''0''0''0''0')


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('0''0''0''0''0''0''0''0')));\i0 --end character ROM0

begin

ChrSelec#1&(co,!_i,#e"er(5SCII_IN)832)when(co,!_i,#e"er(5SCII_IN)'&32)else0;

PixelS#roe1&

5$ciiRO4(ChrSelec#)(co,!_i,#e"er(Ver#PixPo$)co,!_i,#e"er(HorPixPo$));

endBeh!iorl;

8.1.1. Cooridinate;Inserter.#d-------------------------------------------------------------------------- Coordinate_Inserter.vhd ; Takes coordinates passed from LED locator-- and converts them to ASCII to write into the-- block ram for display via the CharacterPainter-------------------------------------------------------------------------- Author: Mark Taylor-- Copyright 2009 Digilent, Inc.

-------------------------------------------------------------------------- Module description---- Inputs:-- TARGETHCNT : STD_LOGIC_VECTOR(9 downto 0), Horizontal coordinate-- TARGETVCNT : STD_LOGIC_VECTOR(8 downto 0), Vertical coordinate-- TARGETVALID : STD_LOGIC, CoordinateValid---- Outputs:-- WE: out STD_LOGIC; -- activates write sequence on block RAM-- ADDRESS : out STD_LOGIC_VECTOR(10 downto 0);-- DATA : out STD_LOGIC_VECTOR(7 downto 0)--------------------------------------------------------------------------

-- Revision History:---- 11/12/2009 (MarkT): created------------------------------------------------------------------------libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;

LibraryUNISI4;useUNISI4.!co-+o,e,#$.all;

entityCoor%i,#e_I,$er#erisPort(

CLK : inSTD_LOGIC;T5RGETHCNT : inSTD_LOGIC_VECTOR(9downto0);T5RGETVCNT : inSTD_LOGIC_VECTOR(8downto0);T5RGETV5LID : inSTD_LOGIC;E : outSTD_LOGIC;5DDRESS : outSTD_LOGIC_VECTOR(10downto0);D5T5 : outSTD_LOGIC_VECTOR(7downto0));

endCoor%i,#e_I,$er#er;


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5SCII_OUT : outstd_logic_vector(7downto0) );endcomponent;

------------------------------------------------------------------------

begin

---------------------------------------------------------------------------

46_:Vec#or_To_5SCII portmap(CLK&'CLKVECTOR_IN&'co,!er#er_i,+0#(9downto0)DECPL5CE&'%ec_+lce(1downto0)CONVERTER_RE4(9downto0)&'co,!er#er_re-i,%er(9downto0)5SCII_OUT(7downto0)&'co,!er#er_$cii_o0#(7downto0));

---------------------------------------------------------------------------

-- Convert input vectors to integersi,#_#r"e#hc,#1&co,!_i,#e"er(T5RGETHCNT);i,#_#r"e#!c,#1&co,!_i,#e"er(T5RGETVCNT);

-- Create ADDRESS bus based on hor/vert character coordinates

i,#_r-_!er#_%%re$$1&r-_!er#_$#r#_%%re$$;

5DDRESS1&co,!_$#%_lo"ic_!ec#or(i,#_r-_hor_%%re$$ 6)Fco,!_$#%_lo"ic_!ec#or(i,#_r-_!er#_%%re$$ 5);

-- Create DATA from either converter output or char_outD5T51&co,!_$#%_lo"ic_!ec#or(i,#_%# 8);

i,#_co,!er#er_$cii_o0#1&co,!_i,#e"er(co,!er#er_$cii_o0#);

co,!er#er_i,+0#1&co,!er#er_i,i#whenco,!er#er_i,+0#_$el&'1' elseco,!er#er_re-i,%er;

i,#_%#1&i,#_co,!er#er_$cii_o0#when%#_o0#+0#_$el&"00"else

ch_,o_#r"e#when%#_o0#+0#_$el&"01"else$cii_co--when %#_o0#+0#_$el&"10"else$cii_$+ce;

-----------------------------------------------------

-----------------------------------------------------

------------------------------------------------------- FSM-----------------------------------------------------

/$-:process(CLK)

begin if(rising_edge(CLK))thencase$##eis

--Timer statewhen$


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--ns logicif(#i-er_+re$cler1+re$cle_!l0e)then

#i-er_+re$cler1i-er_+re$cler1;$##e1&$;

whenothers&'null;

endcase;

--Write Vertical Coords to RAMwhen$>&'

--output logicE1&'1';--writing to RAM enabled%#_o0#+0#_$el1&"00";i,#_r-_hor_%%re$$1&(r-_hor_$#r#_%%re$$4i);

--ns logiccaseiis

when0&'i1&i1;co,!er#er_i,+0#_$el1&'0';%ec_+lce1&"01";--tens place


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$##e1&$>;when1&'

i1&i1;co,!er#er_i,+0#_$el1&'0';%ec_+lce1&"00";--ones place$##e1&$>;

when2&'i1&0;

$##e1&$?;whenothers&'

null;endcase;

--Write semicolon and spaces to RAMwhen$?&'

--output logicE1&'1';--writing to RAM enabled--ns logiccaseiis

when0&'i1&i1;%#_o0#+0#_$el1&"11";

i,#_r-_hor_%%re$$1&(r-_hor_$#r#_%%re$$82);$##e1&$?;

when1&'i1&i1;%#_o0#+0#_$el1&"11";i,#_r-_hor_%%re$$1&(r-_hor_$#r#_%%re$$81);$##e1&$?;

when2&'i1&0;--reset%#_o0#+0#_$el1&"10";i,#_r-_hor_%%re$$1&(r-_hor_$#r#_%%re$$3);$##e1&$


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endBeh!iorl;

---------------------------- EOF --------------------------------------------

8.1.1.5 SPI.#d-------------------------------------------------------------------------- SPI.vhd --Serial Peripheral Interface Implementation-------------------------------------------------------------------------- Author: Mark Taylor-- Copyright 2008 Digilent, Inc.-------------------------------------------------------------------------- Module description-- This VHDL configuration implements SPI. Specifically, it will use-- what Atmel describes as SPI, Mode 0. This will be used to read in-- a specific number of bytes from a connected Digilent CerebotII board-- and place the values read in registers that can be accessed by other-- modules.---- Inputs:-- Slave Select pin (SS)-- Master out, Slave in pin (MOSI)-- Slave clock pin (SCK)---- Outputs:------------------------------------------------------------------------------ Revision History:

---- 05/20/2008(MarkT): created-- 11/13/2008(MarkT): modified from Wireless Demo Robot source to suit-- VGA/Character Display project.--------------------------------------------------------------------------

libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;

entitySPIis

Port(CLK:inSTD_LOGIC;--system clockSS:inSTD_LOGIC;SCK:inSTD_LOGIC;4OSI:inSTD_LOGIC;/D#Re%*:outSTD_LOGIC;-- activates write sequence on block RAM5DDRESS:outSTD_LOGIC_VECTOR(10downto0);D5T5:outSTD_LOGIC_VECTOR(7downto0)


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);endSPI;

architectureBeh!iorlofSPIis

-------------------------------------------------------------------------- General control and timing signals------------------------------------------------------------------------signalc,#Bi#Po$i#io,:integerrange0to7:&7;signalc,#B*#eN0-er:integerrange0to6:&0;--only 0 -> 5 is validsignal0//erChr:std_logic_vector(7downto0):&"00000000";--Character registersignal0//erHor5%%r:std_logic_vector(7downto0):&"00000000";--Horizontal Address registersignal0//erVer#5%%r:std_logic_vector(7downto0):&"00000000";--Vertical Address registersignalc,#SCK%eo0,ce:integerrange0to7:&0;--SCK must be positive for 4 system clocks to

registersignal/SCK_ri$i,"_e%"e:std_logic:&'0';signal/Tri""er:std_logic:&'0';--used to trigger sending datasignalc,#Tri""er:integerrange0to3:&0;--extend data write over multiple clock periods

begin

---------------------Clocked logic-------------------------------

cloce%_lo"ic:process(SCKSSCLK)isbegin

if(rising_edge(CLK))then--all processes occur on system clock edge

if(SS&'0')then--make sure the device is being selected

if((SCK&'1')AND(c,#SCK%eo0,ce15))thenif(c,#SCK%eo0,ce&4)then--we've detected an edge

/SCK_ri$i,"_e%"e1&'1';--indicate that we've detected anedge

endif;c,#SCK%eo0,ce1&c,#SCK%eo0,ce1;--increment

elsif(SCK&'0')thenc,#SCK%eo0,ce1&0;--reset

endif;

if(/SCK_ri$i,"_e%"e&'1' )then--Mode 0 calls for samping on the risingedge

/SCK_ri$i,"_e%"e1&'0';--reset

------------------------Horizontal Position --------------------------if(c,#B*#eN0-er&0)then

0//erHor5%%r1&0//erHor5%%r(6downto0)F4OSI;

if(c,#Bi#Po$i#io,'0)thenc,#Bi#Po$i#io,1&(c,#Bi#Po$i#io,81);

--decrement counterelse

c,#B*#eN0-er1&(c,#B*#eN0-er1);--increment byte number

c,#Bi#Po$i#io,1&7;--resetendif;

------------------------Vertical Position -----------------------------


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elsif(c,#B*#eN0-er&1)then

0//erVer#5%%r1&0//erVer#5%%r(6downto0)F4OSI;


--decrement counter

else c,#B*#eN0-er1&(c,#B*#eN0-er1);--increment byte number

c,#Bi#Po$i#io,1&7;endif;

------------------------Characters-------------------------------------

elsif(c,#B*#eN0-er&2)then-- Character expected

0//erChr1&0//erChr(6downto0)F4OSI;


--decrement counter/Tri""er1&'0';--make sure it is off

elsec,#Bi#Po$i#io,1&7;--reset/Tri""er1&'1';--trigger transmission of data

endif;------------------------------------------------------------------------

endif;--end cntByteNumber dependent

endif;--end fSCK_rising_edge logic

-----------Reset Routines----------------------------------------else-- SS = '1'

/Tri""er1&'0';--reset

-- fDataReady


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0//erHor5%%r1&0//erHor5%%r1;--incrementhorizontal position for burst writes

endif;else-- cntTrigger = 3

null;endif;

elsec,#Tri""er1&0;--reset

D5T51&(others&''0');--reset5DDRESS1&(others&''0');--reset/D#Re%*1&'0';

endif;--end fTrigger = '1'

endif;--end rising_edge(CLK) logic

endprocess;

endBeh!iorl;

8.1.1.6 tb;Coordinate;Inserter.#d---------------------------------------------------------------------------------- Company:-- Engineer: Mark Taylor---- Create Date: 19:26:54 11/15/2009-- Design Name:-- Module Name: C:/Documents and Settings/mtaylor/MyDocuments/EE416/Source/WorkingSource/tb_Coordinate_Inserter.vhd-- Project Name: cameraNexys1-- Target Device:-- Tool versions:-- Description:---- VHDL Test Bench Created by ISE for module: Coordinate_Inserter

---- Dependencies:---- Revision:-- Revision 0.01 - File Created-- Additional Comments:---- Notes:-- This testbench has been automatically generated using types std_logic and-- std_logic_vector for the ports of the unit under test. Xilinx recommends-- that these types always be used for the top-level I/O of a design in order-- to guarantee that the testbench will bind correctly to the post-implementation-- simulation model.--------------------------------------------------------------------------------LIBRARYieee;USEieee

.std_logic_1164

.ALL

;USEieee.std_logic_unsigned.all;USEieee.numeric_std.ALL;ENTITY#_Coor%i,#e_I,$er#erISEND#_Coor%i,#e_I,$er#er;ARCHITECTUREeh!iorOF#_Coor%i,#e_I,$er#erIS

-- Component Declaration for the Unit Under Test (UUT)


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COMPONENTCoor%i,#e_I,$er#er

PORT( CLK:IN std_logic; T5RGETHCNT:IN std_logic_vector(9downto0); T5RGETVCNT:IN std_logic_vector(8downto0); T5RGETV5LID:IN std_logic; E:OUT std_logic;

5DDRESS:OUT std_logic_vector(10downto0); D5T5:OUT std_logic_vector(7downto0) ); ENDCOMPONENT;

--Inputs signalCLK:std_logic:&'0'; signalT5RGETHCNT:std_logic_vector(9downto0):&(others&''0'); signalT5RGETVCNT:std_logic_vector(8downto0):&(others&''0'); signalT5RGETV5LID:std_logic:&'0';

--Outputs signalE:std_logic;

signal5DDRESS:std_logic_vector(10downto0); signalD5T5:std_logic_vector(7downto0);

-- Clock period definitions constantCLK_+erio%:time:&1us;BEGIN

-- Instantiate the Unit Under Test (UUT) 00#:Coor%i,#e_I,$er#erPORTMAP( CLK&'CLK T5RGETHCNT&'T5RGETHCNT T5RGETVCNT&'T5RGETVCNT T5RGETV5LID&'T5RGETV5LID

E&'E 5DDRESS&'5DDRESS D5T5&'D5T5 );

-- Clock process definitions CLK_+roce$$:process begin

CLK1&'0';waitforCLK_+erio%2;CLK1&'1';waitforCLK_+erio%2;

endprocess;

-- Stimulus process $#i-_+roc:process begin

waitforCLK_+erio%2;

-- Place stimulus hereT5RGETHCNT1&"0001111011";--123T5RGETVCNT1&"111001000";--456T5RGETV5LID1&'0';


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waitforCLK_+erio%20;

wait; endprocess;

END;

8.1.1.7 tb;-ector;To;ASCII.#d---------------------------------------------------------------------------------- Company:-- Engineer: Mark Taylor---- Create Date: 18:39:23 11/15/2009-- Design Name:-- Module Name: C:/Documents and Settings/mtaylor/MyDocuments/EE416/Source/WorkingSource/tb_Vector_To_ASCII.vhd-- Project Name: cameraNexys1-- Target Device:-- Tool versions:-- Description:--

-- VHDL Test Bench Created by ISE for module: Vector_To_ASCII---- Dependencies:---- Revision:-- Revision 0.01 - File Created-- Additional Comments:---- Notes:-- This testbench has been automatically generated using types std_logic and-- std_logic_vector for the ports of the unit under test. Xilinx recommends-- that these types always be used for the top-level I/O of a design in order-- to guarantee that the testbench will bind correctly to the post-implementation-- simulation model.--------------------------------------------------------------------------------

LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.all;USEieee.numeric_std.ALL;ENTITY#_Vec#or_To_5SCIIISEND#_Vec#or_To_5SCII;ARCHITECTUREeh!iorOF#_Vec#or_To_5SCIIIS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENTVec#or_To_5SCII PORT(

CLK:

IN std_logic; VECTOR_IN:IN std_logic_vector(9downto0);

DECPL5CE:IN std_logic_vector(1downto0); CONVERTER_RE4:OUT std_logic_vector(9downto0); 5SCII_OUT:OUT std_logic_vector(7downto0) ); ENDCOMPONENT;

--Inputs


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signalCLK:std_logic:&'0'; signalVECTOR_IN:std_logic_vector(9downto0):&(others&''0'); signalDECPL5CE:std_logic_vector(1downto0):&(others&''0');

--Outputs signalCONVERTER_RE4:std_logic_vector(9downto0); signal5SCII_OUT:std_logic_vector(7downto0);

-- Clock period definitions constantCLK_+erio%:time:&1us;BEGIN

-- Instantiate the Unit Under Test (UUT) 00#:Vec#or_To_5SCIIPORTMAP( CLK&'CLK VECTOR_IN&'VECTOR_IN DECPL5CE&'DECPL5CE CONVERTER_RE4&'CONVERTER_RE4 5SCII_OUT&'5SCII_OUT );

-- Clock process definitions CLK_+roce$$:process begin

CLK1&'0';waitforCLK_+erio%2;CLK1&'1';waitforCLK_+erio%2;

endprocess;

-- Stimulus process $#i-_+roc:process begin


-- Place stimulus hereVECTOR_IN1&"0001111011";--123DECPL5CE1&"10";waitforCLK_+erio%;VECTOR_IN1&CONVERTER_RE4;DECPL5CE1&"01";waitforCLK_+erio%;VECTOR_IN1&CONVERTER_RE4;DECPL5CE1&"00";


wait;

endprocess;

END;

8.1.1.8 -ector;To;ASCII.#d-------------------------------------------------------------------------- Vector_To_ASCII.vhd ; Vector to ASCII converter for the Team Sea Beast project


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-------------------------------------------------------------------------- Author: Mark Taylor-- Copyright 2009 Digilent, Inc.-------------------------------------------------------------------------- Module description---- Inputs:-- VECTOR_IN : STD_LOGIC_VECTOR(9 downto 0), vector to be converted;max=>999

-- DECPLACE : STD_LOGIC_VECTOR(2 downto 0), control signal---- Outputs:-- CONVERTER_REM : STD_LOGIC_VECTOR(9 downto 0), remainder to berecursively fed into converter-- ASCII_OUT : STD_LOGIC_VECTOR(7 downto 0), ascii value output---------------------------------------------------------------------------- Revision History:---- 11/15/2009 (MarkT): created------------------------------------------------------------------------libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;

useIEEE.STD_LOGIC_UNSIGNED.ALL;


entityVec#or_To_5SCIIisPort(

CLK : inSTD_LOGIC;VECTOR_IN : inSTD_LOGIC_VECTOR(9downto0);DECPL5CE : inSTD_LOGIC_VECTOR(1downto0);CONVERTER_RE4 : outSTD_LOGIC_VECTOR(9downto0);5SCII_OUT : outSTD_LOGIC_VECTOR(7downto0)

);endVec#or_To_5SCII;

architectureBeh!iorlofVec#or_To_5SCIIis

----------------------------------------------------------------------------------------Signal Declarations

--------------------------------------------------------------------------------------signali,#_i,+0#:integerrange0to102481;signali,#_co,!_re-i,%er:integerrange0to102481;signal-0l_


78/101

,e$#e%_loc:process(CLK)isbegin


if(i,#_i,+0#1(1-0l_


79/101

8.1.2 (omanian &eneric I2C Controller

8.1.2.1 I2C0tils.#d------------------------------------------------------------------------------------ Co(p'ny: Digilent !o('ni'-- )ngineer: )lod *yorgy---- Cre'te D'te: +:2:+ 0#22#2009-- Design '(e: I2C M'ster !e/erence Design-- Module '(e: I2Ctils - P'c1'ge-- Proect '(e: I2CM'sterCtl-- 3'rget Devices:-- 3ool versions:-- Description: 3his p'c1'ge de/ines I2C 4us st'te const'nts 'nd I2C 4it-level-- co(('nd const'nts. I2CCore 'nd I2CCtl ('1e use o/ these const'nts---- Dependencies:---- !evision:

-- !evision 0.0+ - 5ile Cre'ted-- Addition'l Co((ents:------------------------------------------------------------------------------------

lirr*IEEE

0$eIEEE%STD_LOGIC_


80/101

---- Dependencies: I2Ctils p'c1'ge - I2Ctils.vhd---- !evision:-- !evision 0.0+ - 5ile Cre'ted-- Addition'l Co((ents:------------------------------------------------------------------------------------

lirr*IEEE0$eIEEE%STD_LOGIC_


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e,%+roce$$

+roce$$C&DA e"i, i/Ri$i,"_E%"eC&DA#he, &toRQ&"--i/


82/101


83/101

--


84/101

he,st&toAQS

nstateRQst&to he,st&toQS

i/Csla3e'aitQJJ#he,nstateRQst&to"

e,%i/

he,st&to"QS

nstateRQstI!le he,st!AQS nstateRQst! he,st!QS i/Csla3e'aitQJJ#he, nstateRQst!" e,%i/ he,st!"QS

nstateRQst!D he,st!DQS c$eC"MDi$ he,cm!&tartQS--repe'ted st'rt '/ter 'c1 re'd nstateRQst&tartA he,cm!ea!QS

nstateRQst!A he,cm!'riteQS nstateRQst'rA he,cm!&toQS nstateRQst&toA he,o#her$QS

e,%c$e

he,st'rAQS nstateRQst'r he,st'rQS i/Csla3e'aitQJJ#he, i/CarbostQJ


85/101

nstateRQstI!le e,%c$e

e,%+roce$$------------------------------------------------------------------------------------ pen-dr'in outputs /or 4i-direction'l


86/101

0$eIEEE%STD_LOGIC_UNSIGNED%5LL

lirr*!igilent0$e!igilent%I2"tils%ll

e,#i#*I2""tli$------------------------------------------------------------------------------------ 3itle : Mode o/ oper'tion

-- Description: 3he controller c'n 4e instructed to initi'te#continue#stop '-- d't' tr'ns/er using the stro4e %A


87/101

------------------------------------------------------------------------------------ I2C Core h'ndling 4it-level co(('nds----------------------------------------------------------------------------------

CO4PONENTI2""ore

PORTC"K@IN$#%_lo"ic&&T@IN$#%_lo"ic"MD@INcm!?tye

D?I@IN$#%_lo"ic&DA@INOUT$#%_lo"ic&"@INOUT$#%_lo"ic&@OUT$#%_lo"ic$@OUT$#%_lo"icD?+@OUT$#%_lo"ic

ENDCO4PONENT#*+estate?tyei$CstI!le,st&tart,st&tart'ait,st'rite,st'rite'ait,st&to,

stea!,stea!'ait,st&Ack,st&Ack'ait,stDataea!,stMAck'ait,stM6Ack'ait&ta, stM6Ack'ait&to,st$rror,st$rror'ait--5


88/101

el$i/C!ecit"ountQJ


89/101

----------------------------------------------------------------------------------0

&6"?P+"@+roce$$C"K e"i, i/Ri$i,"_E%"eC"K#he, stateRQnstate r"ore"m!RQi"ore"m!

e,%i/

e,%+roce$$i8888888888888888888888888888888888888888888888888888888888888888888888888888888888-- 5


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i/Cbit"ountQ#he, el$e !ecit"ountRQJT?&TAT$?D$"+D$@+roce$$Cstate,A&T,D&T,r*it,core$rr,

coresy,coresy,coreDout,bit"ount,r&st e"i,


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nstateRQstate i 88%e/0l# i$ #o $#* i, c0rre,# $##e

c$eCstatei$

he,stI!leQSi 88,o co--,% i, +ro"re$$ i/Cr&stQJ


92/101


93/101

e,%i/

he,st$rrorQSi 88$i",lli," error i/CCA&TQJJ ,%D&TQJJorr&stQJ


94/101

PORTCck2#M5E@i,STD_LOGIC

--5or(i1e control sign'lsD@o0#STD_LOGIC@o0#STD_LOGICD"K@o0#STD_LOGIC$D@o0#STD_LOGIC_VECTORC@%o,#o

%o,#o"/arA!!ress@o0#STD_LOGIC_VECTORC


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D"KRQck2#M5EM+D$RQJJ--MD)>=> 'nd D) /lo'tingD$RQJJ--trist'te

-- ('pping the stdlogicvector ports to intern'l integersint5cntRQcon3?integerC5cntint=cntRQcon3?integerC=cnt

--M'p Pixel#Ch'r'cter 'ddresses 7ith outside sign'ls3ect5orPi8PosRQcon3?st!?logic?3ectorCint5orPi8Pos,?3ect=ertPi8PosRQcon3?st!?logic?3ectorCint=ertPi8Pos,@5orPi8PosRQ3ect5orPi8PosC>%o,#o


96/101


97/101


98/101

+


99/101

8.3 &antt Cart

Figure 1 / &antt Cart


100/101

19 (eferences

H1 M% 5o!son, JPrototying Image Processing AlicationsG, >cell +nline, H+nline !ocument2007, Hcite! 2009 &etember 21, A3ailable 5TTP@

/tt@..***%8ilin8%com.ublications.8cellonline.8cell?(2.8c?!.)1))?(2it%!

H2 % 5ammes, A%P%'% Wo/m, "% oss, M% "/a*at/e, % Draer, '% 6a::ar, J5ig/ PerormanceImage Processing on -P


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H12 einoc/is D=P, H+nline Document, Hcite! 2009, December 0(, A3ailable5TTP@..***%einoc/is%com.!o*nloa!.!3b%!

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SeaLion FinalReport RevC

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