Schematics Document DT TRANSPORT or Prescott … · VIN +VCC_CORE Core voltage for CPU AC or...
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A A B B C C D D E E 1 1 2 2 3 3 4 4 Size Document Number Rev Date: Sheet of LA-1811 1.0 Cover Sheet 1 66 Wednesday, September 24, 2003 Compal Electronics, Inc. Schematics Document Compal confidential MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL 2003-09-01 DT TRANSPORT or Prescott uFCPGA with ATI-RC300M+SB200 core logic LA-1811 REV:1.0 assistenza compaq
Transcript of Schematics Document DT TRANSPORT or Prescott … · VIN +VCC_CORE Core voltage for CPU AC or...
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LA-1811 1.0
Cover Sheet
1 66Wednesday, September 24, 2003
Compal Electronics, Inc.
Schematics DocumentCompal confidential
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2003-09-01
DT TRANSPORT or Prescott uFCPGAwith ATI-RC300M+SB200 core logic
LA-1811
REV:1.0
assistenza compaq
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LA-1811 1.0
Block Diagram
2 66Wednesday, September 24, 2003
Compal Electronics, Inc.
page 7
MDC & BT Conn
EC I/O Buffer
page 25
VGA DDR x2 CHB
page 39
page 41
HDDConnector
page 31
Thermal SensorADM1032AR
page 44
AC-LINK
page 45
LCD Conn ATI-RC300M
VIA VT1211
DC/DC Interface CKT.
page 25
page 47
CABLE CONN.
page 40
page 14,15,16
page 49
page 4,5,6
Audio Codec
ATI-M9+X/M10C
page 44,45
page 26,27,28,29
CDROM Connector
IDSEL:AD20(PIRQA,B#,GNT#2,REQ#2)
page 37
BGA 457 pin
page 46
CardBus Controller
868 pin u-BGA
Secondary IDE
NS 87591
IDSEL:AD19(PIRQD#,GNT#1,REQ#1)
page 43
Super I/O
page 35
VGA DDR x2 CHA
FDD
IDSEL:AD18(PIRQC#,GNT#3,REQ#3)
ADI 1981B
Primary IDE
Touch Pad
Mini PCIsocket
IEEE 1394TI-TSB43AB22
Compal confidential
AGP BUS
page 30
USB2.0
page 34
page 50,51,52,53,54,55,56,57
page 34
page 45
ATI-SB200
H_A#(3..31)
PCI BUS
RTC CKT.
page 23
RJ45 CONN
LAN
Int.KBD
Power Circuit DC/DC
uFCBGA-479/uFCPGA-478 CPU
H_D#(0..63)
page 22
page 26
page 40
ATA-100
page 47
RJ11 CONN
IDSEL:AD16(PIRQA#,GNT#0,REQ#0)
2.5V DDR- 200/266
BIOS
USB conn x3
A-Linkpage 38
Power OK CKT.
ATA-100
page 7
PSB
Intel Northwood/Prescott Processor
page 43
page 48
Fan Control
page 44
Mini-PCI solt
LPC BUS
AMP & Audio Jack
RTL 8101BL
page 32
File Name :LA1811
W/EXT VGA CHIP
page 45
800MHz
DDR-SO-DIMM X2
Slot 0,1
page 17,18,19,20,21
3.3V 33 MHz
page 44
W/EXT VGA CHIP
Power On/Off CKT.
BANK 0, 1, 2, 3
Memory BUS(DDR)
FIR
W/O EXT VGA CHIP
page 8,9,10,11,12,13
CRT & TV-OUT Conn.
TI PCI1520/1620
VGA M9 Embeded
PARALLEL
W/O EXT VGA CHIP
*RJ45 CONN*LINE IN JACK*DC JACK*COM PORT*USB CONN x1*SPDIF*5V INPUT*VOLUME ADJUSTMENT KEY+TV-OUT PORT
page 30
Card slot
BT/USB KEYUSB1.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CLOCK GENERATORICS951402AGT
page 24
page 33
page 44
page 36
USB2.0 Ctrl.NEC uPD720101
IDSEL:AD23(PIRQA/C/D#,GNT#4,REQ#4)
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Date: Sheet o f
LA-1811 1.0
Notes List
3 66Wednesday, September 24, 2003
Compal Electronics, Inc.
External PCI Devices
Voltage Rails
IDSEL # PIRQ
DDR SO-DIMM 0
REQ/GNT #DEVICE
NB Internal VGA
1 0 1 0 0 0 0 XA0
AGP BUS
SOUTHBRIDGE
USB
AC97
ATA 100
ETHERNET
1394
LAN
CARD BUS
Wireless LAN(MINI PCI)
N/A
AGP_DEVSEL
AD31 (INT.)
AD30 (INT.)
AD31 (INT.)
AD31 (INT.)
AD24(INT.)
AD16
AD19
AD20
AD18
2
N/A
3
0
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
A
A
D
B
C
A
A
A.B
C
D
I2C / SMBUS ADDRESSING
DEVICE HEX ADDRESS
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)
A2
D2
1 0 1 0 0 0 1 X
1 1 0 1 0 0 1 X
Power Plane
B+
+1.25VS
Description
VIN
+VCC_CORE Core voltage for CPU
AC or battery power rail for power circuit.
1.25V switched power rail for DDR Vtt
The voltage for Processor VID select
Adapter power supply (19V)
+VCCVID
ON
N/A
N/A
S3
OFF
ON
S5
OFF
N/A
OFF
N/A
N/A
ON
N/A
OFF
OFF OFF
S0-S1 Symbol Note :
: means Digital Ground
: means Analog Ground
@ : means just reserve , no build
NAGP@ : means just build when no external AGP VGA chip build in (UMA).
OFF
OFF
ON
2.5V switched power rail
+3VS OFF
ON*
+2.5VS
3.3V switched power rail
ONON
2.5V system power rail for DDR
ON*
ON
OFF
+2.5VALW
+2.5V
ON
1.5V I/O power rail for ATI-RS300M/RC300M NB AGP.
OFF
2.5V always on power rail
+3VALW
ON
ON
OFF
ON
OFF
+1.5VS
3.3V always on power rail
+1.8VS
ON
1.8V switched power rail for ATI-RS300M/RC300M NB.
OFF
OFF
OFF
ON
ON
+1.2VS_VGA 1.2V I/O power rail for ATI-VGA M9+X/M10P. ON OFFOFF
12V always on power rail
+5VS
ON
ONON
OFF
ON
ON
ON
+12VALW
5V switched power rail OFF
RTC power
ON*
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
ON
RTCVCC ON
ON*+5VALW 5V always on power rail
+3V 3.3V system power rail for SB,LAN,CardReader and HUB.
ON
ON
OFF
+5V 5V system power rail .
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
ON ON OFF
M10@ : means build VGA M10M9@ : means build VGA M9+XM9-M10@ : means build VGA M9 or M10 1520@ : means build Cardbus PCI15201620@ : means build Cardbus PCI1620
EXT USB AD23(EXT.) 4 A,C,D
ATI@ : means build ATI SB USB2.0 related to turn on the function .NEC@ : means build NEC USB2.0 related to turn on the function .
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5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CK_BCLK#
H_A#4H_A#5H_A#6
H_A#9H_A#10H_A#11
H_A#14H_A#15H_A#16
H_A#19H_A#20H_A#21
H_A#24H_A#25H_A#26
H_A#31
H_A#29H_A#30
H_D#1H_D#2H_D#3
H_D#6H_D#7H_D#8
H_D#11H_D#12H_D#13
H_D#16H_D#17H_D#18
H_D#21H_D#22H_D#23
H_D#26H_D#27H_D#28
H_D#31H_D#32H_D#33
H_D#36H_D#37H_D#38
H_D#41H_D#42H_D#43
H_D#46H_D#47H_D#48
H_D#51H_D#52H_D#53
H_D#56H_D#57H_D#58
H_D#61H_D#62H_D#63
H _ I E R R #
H_REQ#1H_REQ#2H_REQ#3
H _ A D S #<8>
H_LOCK#<8>
CK_BCLK<24>CK_BCLK#<24>
H_HIT#<8>H_HITM#<8>
H_DEFER#<8>
H_BOOTSELECT <56>
H _ B N R #<8>H _ B P R I #<8>
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+5VS+5VS
LA-1811
Prescott Processor in uFCPGA478
4 66Wednesday, September 24, 2003
Compal Electronics, Inc.
Pull-up56ohmto +VCC_COREPull-up 56ohmto +VCC_CORE
Pull-up 62ohmto +VCC_CORE
Prescott
B6 FERR# FERR#/PBE# Pull-up 62ohmto +VCC_CORE
Pull-up 62ohmto +VCC_CORE
Reference Intel documentDesktop P4 Spec.: 10988 P4 0.13u 512KB L2 EMTS Rev.2.0
Desktop Prescott Spec.: 11910 Prescott EMTS Rev.0.5
Pin number NorthwoodPin name
PrescottPin name
Commend Commend
AA20 ITPCLKOUT0 Pull-up56ohmto +VCC_CORE
TESTHI6 Pull-up 62ohmto +VCC_CORE
Pop
Pop
Pop
Pop
Pop
PopDepop
Pop
Pop
Depop
DepopPop
Pop
Northwood
Pop
Depop
Depop
AB22 ITPCLKOUT1 Pull-up 56ohmto +VCC_CORE
TESTHI7 Pull-up 62ohmto +VCC_CORE
AD2 NC VIDPWRGD Pull-up 2.43K ohmto +VCCVID
float
AD3 NC float VID5 Pull-up1Kohm to+3VRUN & connectto PWRIC
AF3 NC float VCCVIDLB Connect to +VCCVID
Northwood MT
Northwood MTPin name
AD20
VCCA VCCIOPLLConnect to CPUFilter
FERR#
ITPCLKOUT0
ITPCLKOUT1
Connect to CPUFilterAE23
Connect to CPUFilter
Connect to CPUFilter
NC
NC
NC
VCCA
VSS
VCCIOPLL VCCA
AD1 VSS BOOTSELECT
VCCIOPLL
VSS
Connect to GND CPU determine
AE26 VSS Connect to GND OPTIMIZED/COMPAT#
Commend
float
Pop
Pop
Pop
TESTHI12 TESTHI12AD25 DPSLP
Connect to CPUFilterConnect to CPUFilter
Connect to GND
Connect to GND
Pop
Pop
float
float
float
Depop
Depop
Depop
Pull-up 62ohmto +VCC_CORE Pop
Pull-up 200ohmto +VCC_CORE
Connect to PLDthrough 0ohm Pop Pop
A6 TESTHI11 GHIPull-up 200ohmto +VCC_CORE
Pull-up 62ohmto +VCC_CORE
Connect to PLD CPUPREF through0ohm PopPop Pop
TESTHI11
R230@62_0402_5%
R900
100K_0402_5%
R1099
47K_0402_5%
R1100
47K_0402_5%
R899 22K_0402_5%
Prescott
JP8A
AMP_3-1565030-1_Prescott
R231 51_0402_5%
Q1062SC2411K_SC59
Q107
MMBT3904_SOT23
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ITP_TDI
ITP_TCK
ITP_TDO
H_VID_PWRGD
H_THERMTRIP#
H_PROCHOT#
H_PWRGOOD
CK_ITP#
V I D 3V I D 4V I D 5
ITP_TRST#
H_RS#0
H_RESET#
ITP_BPM#0
H_PROCHOT#
ITP_BPM#2
V I D 0
H_THERMTRIP#
ITP_DBRESET#
H_TESTHI0_1
C O M P 0
ITP_TDO
H_VCCA
ITP_BPM#1
H_FERR#
H_TESTHI11
ITP_TRST#
ITP_BPM#5
H_TESTHI10
H_THERMDC
ITP_TMS
H_DPSLP#
V I D 1V I D 2
V I D 5
V I D 3
H _ V S S A
CPU_STP#
H_RS#[0..2]<8>
H_TRDY#<8>
H_A20M#<26>H_FERR#<26>
H _ I G N N E #<26>
H_PWRGOOD<26>H_STPCLK#<26>
H_INTR<26>
H_INIT#<26>H_RESET#<8,26>
H _ D R D Y #<8>
H_THERMDA<7>H_THERMDC<7>
H_THERMTRIP#<7>
V C C S E N S E<56>
H_DSTBN#0 <8>H_DSTBN#1 <8>
H_DSTBN#3 <8>
H_DSTBP#0 <8>
H_DSTBP#2 <8>H_DSTBP#3 <8>
H_ADSTB#1 <8>
H_DINV#0 <8>
H_DINV#2 <8>
H_PROCHOT# <26,51>
H_DINV#3 <8>
H_CPUSLP# <26>
V I D 2<56>V I D 1<56>
V I D 5<56>
V I D 3<56>
VID_PWRGD<55,56>
CK_ITP<24>CK_ITP#<24>
CPUCLK_STP#<11,26,56>
BSEL0<13,24>BSEL1<13,24>
+CPU_GTLREF
+CPU_GTLREF
+VCCVID
+VCC_CORE
+3VS
+VCC_CORE
+VCC_CORE
+VCC_CORE
+3VS
+VCCVID
+VCCVID
+VCC_CORE
LA-1811
Prescott Processor in uFCPGA478
5 66Thursday, September 25, 2003
Compal Electronics, Inc.
Place near SB200 (U6)
Close to the CPU
3. Place decoupl ing cap 220PF near CPU.
GTL Reference Voltage
2 . P l a c e R _ A a n d R _ B n e a r C P U .
Layout note :
R_A
R_B
1 . +CPU_GTLREF Trace wide12mils(min),Space 15mils
1.Place cap within 600 mils ofthe VCCA and VSSA p ins .
Note: Please change to 10uH, DC currentof 100mA parts and close to cap
PLL Layout note :
2 .H_VCCIOPLL,HVCCA,HVSSA t race wide12 mils(min)
Close to the ITP
Between the CPU and ITP
H_TESTHI12
If CPU is P4 , Change theresistor R539,R540 value to51.1_0603_1%,or prescott61.9_0603_1%
If CPU is P4 , Change the resistorR546 value to 75_0603_1%
If CPU is P4 , Change the resistorR550 value to 39_0402_5%
If CPU is P4 , Change the resistorR556 value to 27.4_0402_5%
PIR BOM 92.09.01
R522 56_0402_5%
4.7K_0402_5%
R1125
12K_0402_5%
R559680_0603_5%
R55047_0402_5%
C854
33U_D2_8M_R35
G
D
SQ45
2N7002 1N_SOT23
C546
RP137 56_0804_8P4R_5%
L37 LQG21F4R7N00_0805
Prescott
JP8B
AMP_3-1565030-1_Prescott
R54754.9_0603_1%
R541 2.43K_0603_1%
L36 LQG21F4R7N00_0805
R529 56_0402_5%
R514
@0_0402_5%
C547
R527 56_0402_5%
R518 300_0402_5%
R552 150_0402_5%
RP94 1K_1206_8P4R_5%
R519 56_0402_5%
R543 1K_0402_5%
C544
33U_D2_8M_R35
R53951.1_0402_1%
R558
R10170_0402_5%
R546
R556 47_0402_5%
R515 56_0402_5%
C932
Q95MMBT3904_SOT23
49.9_0402_1%
R513 56_0402_5%
4.7K_0402_5%
Q96
R54051.1_0402_1%
U32A
SN74LVC14APWLE_TSSOP14
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
LA-1811
CPU Decoupling
6 66Wednesday, September 24, 2003
Compal Electronics, Inc.
Place 11 North of Socket(Stuff 6)
Place 12 Inside Socket(Stuff all)
Place 9 South of Socket(Unstuff all)
Place Inside Socket around the edge
C178
470U_D2_2.5VM
22U_1206_16V4Z
C14322U_1206_16V4Z
C180
470U_D2_2.5VM
22U_1206_16V4Z
0.22U_0603_10V7K
C132
0.22U_0603_10V7K
C139
0.22U_0603_10V7K
C183
@470U_D2_2.5VM
22U_1206_16V4Z
C134
C153
C15122U_1206_16V4Z
C14522U_1206_16V4Z
C135
C14622U_1206_16V4Z
0.22U_0603_10V7K
C163
470U_D2_2.5VM
C179
470U_D2_2.5VM
22U_1206_16V4Z
C141
C14722U_1206_16V4Z
C167
470U_D2_2.5VM
C152
22U_1206_16V4Z 22U_1206_16V4Z
C138
C165
470U_D2_2.5VM
0.22U_0603_10V7K
C131
C176
@330U_D2E_2.5VM
C14222U_1206_16V4Z
C136
22U_1206_16V4Z
C182
470U_D2_2.5VM
C15022U_1206_16V4Z
22U_1206_16V4Z
C140
C166
@330U_D2E_2.5VM
C14922U_1206_16V4Z
22U_1206_16V4Z
C164
470U_D2_2.5VM
C133
C14822U_1206_16V4Z
C174
470U_D2_2.5VM
C177
470U_D2_2.5VM
C14422U_1206_16V4Z
C175
470U_D2_2.5VM
C137
C181
470U_D2_2.5VM
0.22U_0603_10V7K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_THERMDC
H_THERMDA
EN_DFAN2 EN_FAN2
FAN1 FAN2
H_THERMTRIP#
EC_SMC_2 <46>
EC_SMD_2 <46>
H_THERMDA <5>
H_THERMDC <5>
EN_FAN1<46> EN_FAN2<46>
F A N S P E E D 2<46>F A N S P E E D 1<46>
H_THERMTRIP#<5>
MAINPWON <50,51,53>
+3VALW
+VCC_CORE
+3VS +3VS
+12VALW
LA-1811
CPU Thermal Sensor&FAN CTRL
7 66Wednesday, September 24, 2003
Compal Electronics, Inc.
Thermal Sensor ADM1032AR
Address:1001_100X
FAN CONN.1 FAN CONN. 2
PIR BOM 92.09.01 PIR BOM 92.09.01
C265
10U_0805_10V4Z
10K_0402_5%
R917 8.2K_0402_5%
C840
0.1U_0402_10V6K
R920 10K_0402_5%
R918 8.2K_0402_5%JP11
ACES_85205-0300
C253
C
BE
Q90
FMMT619_SOT23
JP10
ACES_85205-0300
U10A
LM358A_SO8
R283
@10K_0402_5%
C856
1000P_0402_16V7K
C855
1000P_0402_16V7K
C
BE
Q91
FMMT619_SOT23
D25
1N4148_SOD80
0.1U_0402_10V6K
1000P_0402_16V7K
Q172SC2411K_SC59
D68R913 100_0402_5%
D67
1SS355_SOD323
C83810U_0805_16V4Z
C266
10U_0805_10V4Z
R286 300_0402_5% C256 @1U_0603_10V6K
R919 10K_0402_5%
10U_0805_16V4Z
10K_0402_5%
D26
1N4148_SOD80
R914 100_0402_5%
C841
0.1U_0402_10V6K
C908
LM358A_SO8
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_D#[0 . . 63 ]
H_REQ#[0..4]
H_A#[3..31]
H_D#62
H_DSTBP#3
H_D#37
H_D#59
H_DINV#2
H_D#39
H_D#54
H_D#11
H_DSTBN#2
H_D#12
H_D#46
H_D#63
H_D#8
H_DSTBP#2
H_D#48
H_D#50
H_DSTBN#0
H_D#19
H_D#47
H_D#0
H_D#6
H_D#13
H_D#5
H_D#9
H_D#18
H_D#4
H_D#28
H_D#57
H_D#40
H_D#36
H_DSTBP#1
H_D#43
H_D#33
H_D#24H_D#25
H_D#34
H_D#29
H_D#55
H_DSTBN#3
H_DINV#0
H_D#16
H_D#51
H_D#2
H_D#45
H_D#31
H_D#23
H_D#52
H_D#3
H_D#20
H_D#17
H_D#7
H_DINV#3
H_D#22
H_D#15
H_D#30
H_DSTBP#0
H_D#32
H_D#58
H_D#10
H_D#1
H_D#35
H_D#21
H_D#41
H_D#44
H_D#42
H_D#53
H_D#60
H_D#27
H_D#38
H_DSTBN#1
H_D#56
H_D#49
H_D#26
H_D#61
H_DINV#1
H_D#14
H_A#28
H_ADSTB#1
H_A#7
H_A#30
H_A#3
H_A#20
H_A#29
H_A#6
H_A#22
H_A#18
H_A#24
H_REQ#3
H_A#23
H_BNR#
H_A#9H_A#8
H_A#25
H_A#11
H_DEFER#
H_A#10
H_ADSTB#0
H_A#4
H_DRDY#
H_LOCK#
H_A#17
H_TRDY#
H_A#27
H_A#16
H_A#13
H_HIT#
H_ADS#
H_RS#1
H_RESET#
H_DBSY#
H_A#5
COMP_P
H_A#15H_A#14
H_A#26
H_A#31
H_HITM#
H_RS#2
H_BPRI#
H_REQ#1
NB_GTLREF
H_A#19
H_REQ#2
H_A#21
H_REQ#4
H_REQ#0
H_RS#0
H_A#12
H_BR0#
COMP_N
CPVSS
CPVDD
H_D#[0..63] <4>
H_A#[3..31] <4>
H_REQ#[0..4] <4>
H_DSTBP#0 <5>
H_DSTBN#3 <5>
H_DSTBN#0 <5>
H_DSTBP#3 <5>
H_DSTBP#2 <5>H_DSTBN#2 <5>
H_DSTBP#1 <5>H_DSTBN#1 <5>
H_TRDY#<5>
H_RS#1<5>
H_DEFER#<4>
H_HITM#<4>H_HIT#<4>
NB_PWRGD<48>
H_ADSTB#1<5>
H_DRDY#<5>
H_ADSTB#0<5>
H_RS#2<5>
H_LOCK#<4>
H_DBSY#<5>
H_BPRI#<4>H_BNR#<4>
H_RS#0<5>
H_RESET#<5,26>
NB_RST#<17,26,39>
H_ADS#<4>
H_BR0#<4>
H_DINV#3 <5>
H_DINV#0 <5>
H_DINV#2 <5>
H_DINV#1 <5>
SUS_STAT#<27>
+VCC_CORE
+VCC_CORE
+1.8VS
+VCC_CORE
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
ATI RC300M-AGTL+
8 66Wednesday, September 24, 2003
Compal Electronics, Inc.
C363 CLOSE TO Ball W28
PLACE CLOSE TO U27 BallW28, USE 20/20WIDTH/SPACE
Note: PLACE CLOSE TO RC300M,USE 10/10 WIDTH/SPACEL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
--> 412_0402_1%
R383
49.9_0402_1%
C372
0.1U_0402_10V6K
R381 24.9_0402_1%
C366
0.1U_0402_10V6K
R384
100_0402_1%
C368
0.1U_0402_10V6K
C369
0.1U_0402_10V6K
L34
HB-1M2012-121JT03_0805
C362
1U_0603_10V6K
C36422U_1206_16V4Z_V1
R382 49.9_0402_1%
C371
0.1U_0402_10V6K
C365
0.1U_0402_10V6K
R385
4.7K_0402_5%
C361
1U_0603_10V6K
C363
220P_0402_25V8K
R380 412_0402_1%
C370
0.1U_0402_10V6K
C9740.1U_0402_10V6K
C367
0.1U_0402_10V6K
PART 1 OF 6
PE
NTI
UM
IV
ADD
R. G
RO
UP
1AD
DR
. GR
OU
P 0
CO
NTR
OL
MIS
C.
DAT
A G
RO
UP
0D
ATA
GR
OU
P 1
DAT
A G
RO
UP
2D
ATA
GR
OU
P 3
AG
TL+
I/F
U 2 7 A
216RC300M_BGA_718
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MPVSS
DDRA_DQ44
DDRA_DQ48DDRA_DQ49
DDRA_DQ54
DDRA_DQ59
DDRA_DM0
DDRA_DM3
DDRA_ADD15
DDRA_CLK3
MEN_COMP
DDRA_DQ3
DDRA_DQ33
DDRA_DQ52
DDRA_ADD4
DDRA_ADD8
DDRA_DM5
DDRA_CLK1
DDRA_DQ18
DDRA_DQ21
DDRA_DQ23
DDRA_ADD10
DDRA_DM6
DDRA_CLK4
DDRA_DQ6
DDRA_DQ13
DDRA_DQ38
DDRA_DQ42DDRA_DQ43
DDRA_DQ47
DDRA_DQS1
DDRA_DQ57
DDRA_ADD12
DDRA_CLK0
DDRA_CLK1#
DDRA_DQ7
DDRA_DQ15
DDRA_DQ17
DDRA_DQ24DDRA_DQ25
DDRA_DQ35
DDRA_DQ40DDRA_DQ41
DDRA_DQ60
DDRA_DQ63
DDRA_ADD6
DDRA_ADD9
DDRA_RAS#DDRA_CAS#
DDRA_DQS4
MPVDD
DDRA_CLK3#
DDRA_CLK4#
DDRA_DQ9
DDRA_DQ62
DDRA_ADD5
DDRA_DM4
DDRA_DQ4
DDRA_DQ32
DDRA_DQ34
DDRA_DQ53
DDRA_DQ56
DDRA_CKE_R0DDRA_CKE_R1
DDRA_DQ11
DDRA_DQ14
DDRA_DQ16
DDRA_DQ37
DDRA_DQ55
DDRA_DQS5
DDRA_CLK0#
DDRA_DQ20
DDRA_DQ26DDRA_DQ27
DDRA_DQ45
DDRA_ADD2
DDRA_ADD7
DDRA_DQ2
DDRA_DQ5
DDRA_DQ51
DDRA_DQ61
DDRA_ADD3
DDRA_ADD13
DDRA_DQS0
DDRA_DQ0DDRA_DQ1
DDRA_DQ8
DDRA_DQ19
DDRA_DQ12
DDRA_DQ28
DDRA_DQ39
DDRA_DQ46
DDRA_ADD14
DDRA_DM2
DDRA_WE#
DDRA_DQS2
DDRA_DQ30
DDRA_DQ50
DDRA_DQ58
DDRA_ADD1
DDRA_ADD11
DDRA_DM7
DDRA_DQS6
DDRA_DQ10
DDRA_DQ22
DDRA_DQ29
DDRA_DQ36
DDRA_DM1
DDRA_DQS3
DDRA_DQ31
DDRA_ADD0
DDRA_DQS7
DDRA_CKE_R2DDRA_CKE_R3
DDRA_CS#0DDRA_CS#1
DDRA_CS#3DDRA_CS#2
DDR_VREF
DDRA_DQ23
DDRA_SDQ22
DDRA_SDQ23DDRA_DQ19
DDRA_DQ22DDRA_SDQ18
DDRA_SDQ19
DDRA_DQ18
DDRA_ADD[0..15]
DDRA_SDQS[0..7]
DDRA_SDQ[0..63]
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ4
DDRA_SDQ5DDRA_DQ5DDRA_DQ1
DDRA_DQ4DDRA_DQ0
DDRA_DQ30
DDRA_DQ29DDRA_DQ25
DDRA_DQS3 DDRA_SDQS3
DDRA_DQ28
DDRA_DQ31
DDRA_SDQ30
DDRA_DQ27
DDRA_SDQ28
DDRA_SDQ31
DDRA_DQ24
DDRA_SDQ29
DDRA_DQ26
DDRA_SDQ24
DDRA_SDQ27
DDRA_SDQ26
DDRA_DM3 DDRA_SDM3
DDRA_SDQ25
DDRA_DM0
DDRA_DQS0 DDRA_SDQS0
DDRA_SDM0
DDRA_DQ9
DDRA_DQ10
DDRA_DQ15DDRA_DQ11
DDRA_DQ8DDRA_DQ12
DDRA_DQ14
DDRA_DQ13
DDRA_DM1
DDRA_DQS1
DDRA_SDM1
DDRA_SDQS1
DDRA_SDQ9
DDRA_SDQ8
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ15
DDRA_SDQ14
DDRA_SDM[0..7]
DDRA_SDM5
DDRA_SDQS6DDRA_DQS6
DDRA_DM7
DDRA_DQ51
DDRA_DQ54
DDRA_SDQS7
DDRA_DQ50
DDRA_SDM7
DDRA_DQS5
DDRA_SDM4
DDRA_DQS7
DDRA_SDQS4
DDRA_SDQ50
DDRA_SDQS5
DDRA_SDQ54
DDRA_DM4
DDRA_SDQ51DDRA_DQ55
DDRA_DM5
DDRA_SDQ55
DDRA_DQS4
DDRA_SDM6DDRA_DM6
DDRA_DQ49 DDRA_SDQ49DDRA_SDQ53DDRA_DQ53
DDRA_SDQ48DDRA_DQ48DDRA_DQ52 DDRA_SDQ52
DDRA_SDQ63DDRA_DQ63DDRA_DQ59 DDRA_SDQ59
DDRA_SDQ62DDRA_DQ62DDRA_DQ58 DDRA_SDQ58
DDRA_SDQ61DDRA_DQ61DDRA_DQ57 DDRA_SDQ57
DDRA_SDQ56DDRA_DQ56DDRA_DQ60 DDRA_SDQ60
DDRA_SDQ43DDRA_SDQ47DDRA_DQ47
DDRA_DQ43
DDRA_SDQ46DDRA_SDQ42
DDRA_DQ46DDRA_DQ42
DDRA_DQ45DDRA_DQ41
DDRA_SDQ45DDRA_SDQ41
DDRA_SDQ40DDRA_SDQ44DDRA_DQ44
DDRA_DQ40
DDRA_DQ39DDRA_DQ35 DDRA_SDQ35
DDRA_SDQ39
DDRA_SDQ38DDRA_SDQ34
DDRA_DQ38DDRA_DQ34
DDRA_DQ33DDRA_DQ37
DDRA_SDQ33DDRA_SDQ37
DDRA_SDQ32DDRA_SDQ36
DDRA_DQ32DDRA_DQ36
DDRA_SDQ21DDRA_SDQ17
DDRA_DQ21DDRA_DQ17
DDRA_SDQ16DDRA_SDQ20
DDRA_DQ16DDRA_DQ20
DDRA_DM2 DDRA_SDM2
DDRA_SDQS2
DDRA_DQ2
DDRA_DQ3
DDRA_DQ6
DDRA_DQ7DDRA_SDQ3DDRA_SDQ7
DDRA_SDQ2DDRA_SDQ6
DDRA_DQS2
DDRA_CLK0<14>
DDRA_CLK3<15>
DDRA_CLK1#<14>
DDRA_CLK4<15>
DDRA_CLK3#<15>
DDRA_CLK1<14>
DDRA_CLK4#<15>
DDRA_CLK0#<14>
DDRA_SDQ[0..63] <14,15,16>
DDRA_SDQS[0..7] <14,15,16>
DDRA_SDM[0..7] <14,15,16>
DDRA_ADD[0..15] <14,15,16>
DDRA_CKE_R0<14,16>DDRA_CKE_R1<14,16>DDRA_CKE_R2<15,16>DDRA_CKE_R3<15,16>
DDRA_CS#0<14,16>DDRA_CS#1<14,16>DDRA_CS#2<15,16>DDRA_CS#3<15,16>
DDRA_RAS#<14,15,16>DDRA_CAS#<14,15,16>
DDRA_WE#<14,15,16>
+2.5V
+1.8VS
+2.5V+2.5V
DDR_VREF
+2.5V
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
ATI RC300M-DDR I/F
9 66Wednesday, September 24, 2003
Compal Electronics, Inc.
DDR_VREF trace width of20mils and space20mils(min)
L
Group 6 sweep Group 7
Place these resistorclosely DIMM0,all trace lengthMax=0.75"
Layout note
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RP64
0_0404_4P2R_5%
C381
0.1U_0402_10V6K
RP46
0_0404_4P2R_5%
R405 49.9_0402_1%
RP31
0_0404_4P2R_5%
RP52
0_0404_4P2R_5%
RP61
0_0404_4P2R_5%
C376
0.1U_0402_10V6K
C385
0.1U_0402_10V6K
C384
0.1U_0402_10V6K
C374 0.47U_0603_16V7K
RP63
0_0404_4P2R_5%
C860
@0.1U_0402_10V6K
RP47
0_0404_4P2R_5%
RP30
0_0404_4P2R_5%
RP36
0_0404_4P2R_5%
C380
0.1U_0402_10V6K
RP33
0_0404_4P2R_5%
C388
0.1U_0402_10V6K
RP55
0_0404_4P2R_5%
R412 0_0402_5%
RP34
0_0404_4P2R_5%
C386
0.1U_0402_10V6K
R403 0_0402_5%
RP48
0_0404_4P2R_5%
RP51
0_0404_4P2R_5%
C859
@0.1U_0402_10V6K
C382
0.1U_0402_10V6K
RP45
0_0404_4P2R_5%
R413 0_0402_5%
R395 0_0402_5%
R415 0_0402_5%
RP37
0_0404_4P2R_5%
R387 0_0402_5%
+C378
100U_D2_10VM
R406 0_0402_5%
R404 0_0402_5%
R409
1K_0603_1%
R408
1K_0603_1%
RP44
0_0404_4P2R_5%
R394 0_0402_5%
R416 0_0402_5%
C858
@0.1U_0402_10V6K
R398 0_0402_5%
C383
0.1U_0402_10V6K
RP62
0_0404_4P2R_5%
RP58
0_0404_4P2R_5%
RP40
0_0404_4P2R_5%
RP59
0_0404_4P2R_5%
RP54
0_0404_4P2R_5%
RP43
0_0404_4P2R_5%
R389 0_0402_5%
ME
M I/
F
PART 2 OF 6
U 2 7 B
216RC300M_BGA_718
R386 0_0402_5%
RP41
0_0404_4P2R_5%
RP57
0_0404_4P2R_5%
RP49
0_0404_4P2R_5%
L35HB-1M2012-121JT03_0805
C391
0.1U_0402_10V6K
RP28
0_0404_4P2R_5%
RP50
0_0404_4P2R_5%
R388 0_0402_5%
C375
1U_0603_10V6K
RP56
0_0404_4P2R_5%
C387
0.1U_0402_10V6K
C373 0.47U_0603_16V7K
C857
0.1U_0402_10V6KC379
0.1U_0402_10V6K
RP27
0_0404_4P2R_5%
R407 0_0402_5%
R397 0_0402_5%
RP60
0_0404_4P2R_5%
C390
0.1U_0402_10V6K
C861
@0.1U_0402_10V6KC389
0.1U_0402_10V6K
C377
0.1U_0402_10V6K
RP53
0_0404_4P2R_5%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
A_AD[0..31]
A_CBE#[0..3]
AGP_AD2
AGP_SBA2
AGP_WBF#
AGP_AD27
AGP_AD18
AGP_AD4
AGP_SBSTB#
AGP_AD13
AGP_PAR
AGP_SBA6
AGP_SBA1
AGP_AD25
AGP_AD20
AGP_AD7AGP_AD6
AGP_ST2
AGP_AD28
AGP_CBE#3
AGP_AD31
AGP_AD14
AGP_AD3
AGP_DBI_LOAGP_RBF#
AGP_SBA4
AGP_AD12
AGP_AD1
AGP_DEVSEL#
AGP_ADSTB1
AGP_SBSTB
AGP_AD26
AGP_AD10
AGP_ST0
AGP_ADSTB1#
AGP_AD29
AGP_AD22
AGP_DBI_HI/PIPE#
AGP_STOP#
AGP_ADSTB0
AGP_AD19
AGP_AD9
AGP_ST1
AGP_SBA7
AGP_CBE#0
AGP_AD23
AGP_AD8
AGP_AD16
AGP_AD11
AGP_SBA5
AGP_SBA3
AGP_FRAME#
AGP_CBE#2
AGP_ADSTB0#
AGP_AD5
AGP_AD0
AGP_IRDY#
AGP_CBE#1
AGP_AD21
AGP_AD17
AGP_SBA0
AGP_TRDY#
AGP_AD30
AGP_AD24
AGP_AD15
A_AD11
A_AD17
A_AD20
A_END#
A_AD27
A_AD6
A_DEVSEL#
A_AD26
A_AD24A_AD25
A_AD18
A_AD9
A_AD0
A_AD3
A_AD7
A_AD5
A_ACAT#
A_AD12
A_AD15
A_SBGNT#
A_AD1
A_AD13
A_AD16
A_AD30
A_AD22
A_AD29
AGP_GNT#
A_CBE#3
A_OFF#
A_AD31
A_AD8
A_SBREQ#
A_CBE#0A_CBE#1A_CBE#2
A_AD23
A_AD14
A_PAR
A_AD19
A_AD4
A_AD28
A_AD2
A_STROBE#
A_AD10
AGP_REQ#
A_AD21
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
LVDS_SSOUTAGP_SBA6
AGP_SBA7 LVDS_SSIN
AGPREF_8X
AGP_COMP
LVDS_SSOUT
LVDS_SSIN
AGP8X_DET#
DDC_DAT
D D C _ C L K
AGP8X_DET#
AGPREF_8X
AGP_ST[0..2]
AGP_AD[0..31]
AGP_SBA[0..7]
AGP_CBE#[0..3]
AGP_SBA1
AGP_SBA0
A_AD[0..31]<13,26>
A_CBE#[0..3]<13,26>
AGP_RBF# <17>AGP_WBF# <17>
AGP_TRDY# <17>AGP_IRDY# <17>
AGP_FRAME# <17>
AGP_ADSTB1# <17>
AGP_ADSTB0# <17>
AGP_STOP# <17>
AGP_SBSTB# <17>AGP_SBSTB <17>
AGP_PAR <17>
AGP_ADSTB1 <17>
AGP_ADSTB0 <17>
AGP_DBI_HI/PIPE# <17>AGP_DBI_LO <17>
AGP_DEVSEL# <17>
AGP_GNT#<17>AGP_REQ#<17>
VREF_8X_IN<17>
A_DEVSEL#<26>
A_SBGNT#<26>
A_OFF#<26>
A_END#<26>
A_SBREQ#<26>
A_ACAT#<26>
A_PAR<13,26>A_STROBE#<26>
ENABLT# <17,25>
ENAVDD <17,25,46>
AGP_BUSY# <17,27>
AGP_STP# <17,27>
SSOUT <17>
DDC_DAT <17,25>
D D C _ C L K <17,25>
PCI_PIRQA#<17,26,31,35,36>
AGP8X_DET#<17>
SSIN <17>
AGP_AD[0..31] <17>
AGP_SBA[0..7] <17>
AGP_ST[0..2] <17>
AGP_CBE#[0..3] <17>
+1.5VS +3VS
+3VS
+3VS
+3VS
+1.5VS
+1.5VS
+1.5VS+1.5VS
+1.5VS
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
ATI RC300M-AGP, ALINK BUS
10 66Wednesday, September 24, 2003
Compal Electronics, Inc.
AGPAND LVDS MUXED SIGNALS
?
PLACE CLOSE TOCONNECTOR
8X(M9+M10@)Ra 169_0402_1%
324_0402_1%100_0402_1%
S1
S0
LVDS SPREAD SPECTRUM
Note: PLACE CLOSE TO U27 (NB RC300M)L
4X(NAGP@)
RbRc
52.1_0402_1%
Ra
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI request
1K_0402_1%1K_0402_1%
Rb
Rc
Note: PLACE CLOSE TO U27 (NB RC300M)L
PIR BOM 92.06.23
C553
0.1U_0402_10V6K
C550
0.1U_0402_10V6K
R945
NAGP@47K_0402
C557
0.1U_0402_10V6K
C573
0.1U_0402_10V6K
C943
0.1U_0402_10V6K
R560 NAPG@0_0402_5%
R573@0_0402_5%
C556
0.1U_0402_10V6K
C935
@0.01U_0402_16V7Z
U33
@SM561BS_SO8
C570
0.1U_0402_10V6K
C567
0.1U_0402_10V6K
C864
@0.01U_0402_16V7Z
C572
0.1U_0402_10V6K
C560
0.1U_0402_10V6K
C951
@0.01U_0402_16V7Z
R567
@0_0402_5%
C938
0.1U_0402_10V6K
C950
@0.01U_0402_16V7Z
C942
0.1U_0402_10V6K
C948
@0.01U_0402_16V7Z
C574
0.1U_0402_10V6K
R576
324_0402_1%
R1086
@0_0402_5%
C554
0.1U_0402_10V6K
R1144 @0_0402_5%
R563 NAPG@0_0402_5%
C934
@0.01U_0402_16V7Z
C578
0.1U_0402_10V6K
C947
@0.01U_0402_16V7Z
C555
0.1U_0402_10V6K
R577
100_0402_1%
C939
0.1U_0402_10V6K
C945
0.1U_0402_10V6K
C568
0.1U_0402_10V6K
R564 @0_0402_5%
R565 @0_0402_5%
+C551
47U_B_6.3VM
C952
@10P_0402_25V8K
R1088@0_0402_5%
R572
@0_0402_5%
R574
@0_0402_5%
C936
@0.01U_0402_16V7Z
C562
0.1U_0402_10V6K
C940
0.1U_0402_10V6K
R569
@0_0402_5%
C946
0.1U_0402_10V6K
C577
0.1U_0402_10V6K
C569
0.1U_0402_10V6K
R5708.2K_0402_5%
C549
@0.1U_0402_10V6K
C563
0.1U_0402_10V6K
C561
0.1U_0402_10V6K
C564
0.1U_0402_10V6K
C566
0.1U_0402_10V6K
C576
0.1U_0402_10V6K
C571
0.1U_0402_10V6K
C559
0.1U_0402_10V6K
C632
10U_0805_10V4Z
C941
0.1U_0402_10V6K
C575
0.1U_0402_10V6K
R561 NAPG@0_0402_5%
L38@BLM21P300S_0805
C548
@10U_0805_6.3V6M
R562 NAPG@0_0402_5%
C933
@0.01U_0402_16V7Z
C949
@0.01U_0402_16V7Z
R568
@0_0402_5%
R994 NAPG@0_0402_5%
C558
0.1U_0402_10V6K
+C552
47U_B_6.3VM
C944
0.1U_0402_10V6K
R575
169_0402_1%
R1005 0_0402_5%
C565
0.1U_0402_10V6K
R1087
@0_0402_5%
C937
0.1U_0402_10V6K
PART 3 OF 6
PC
I Bus
0 /
A-L
ink
I/F
PC
I BU
S 1
/ A
GP
Bus
(GP
IO ,
TMD
S ,
ZVP
ort)
U27C
216RC300M_BGA_718
R995 NAPG@0_0402_5%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RC300M_X2
RC300M_X1
CLK_AGP_66M
CLK_MEM_66M
CLK_AGP_66M
LVSSR
+1.8VS_LPVDD
+1.8VS_LVDDR
CRMA_R
COMPS_R
LUMA_R
HSYNC_R
GREEN_RRED_R
BLUE_R
VSYNC_R
NB_RSET
27M_TV 27M_TV_R
CLK_NB_BCLK#CLK_NB_BCLK
RC300M_X2
3VDDCCLDDCDATA_RDDCCLK_R
CRMA_R
3VDDCDA
DDCDATA_R
DDCCLK_R
CLK_MEM_66M
GREEN_RCRT_G
VSYNC_R
CRT_B BLUE_R
CRT_HSYNC
CRT_R
HSYNC_R
RED_R
CRT_VSYNC
LPVSS
RC300M_X1
TV_CRMALUMA_R TV_LUMA
TV_COMPSCOMPS_R
PLLVSS_18
PLLVDD_18
CPUCLK_STP#
CLK_AGP_66M<24>
TXACLK-_NB <25>
TXA0+_NB <25>
TXB0+_NB <25>
TXB2+_NB <25>TXBCLK-_NB <25>
TXB2-_NB <25>
TXA1-_NB <25>
TXBCLK+_NB <25>
TXA0-_NB <25>
TXB1+_NB <25>TXB1-_NB <25>
TXA2-_NB <25>
TXACLK+_NB <25>
TXA2+_NB <25>
CLK_NB_BCLK#<24>CLK_NB_BCLK<24>
3VDDCCL <17,25>
TV_LUMA <17,41,48>TV_COMPS <17,41,48>
TV_CRMA <17,41,48>
3VDDCDA <17,25>
CLK_MEM_66M<24>
CRT_HSYNC<17,25>CRT_VSYNC<17,25>
CRT_B<17,25>
CRT_R<17,25>CRT_G<17,25>
REFCLK1_NB<24>
TXB0-_NB <25>
TXA1+_NB <25>
PCI_RST# <26,30,31,34,35,36,43,46>
CPUCLK_STP# <5,26,56>
+1.8VS
+1.8VS
+3VS
+3VS
+1.8VS
+1.8VS
+1.8VS
+3VS
+2.5VS
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
ATI RC300M-VIDEO I/F
11 66Wednesday, September 24, 2003
Compal Electronics, Inc.
Note: PLACE CLOSE TO U27 (NB CHIP)
L Note: PLACE CLOSE TO U6 (VGA CHIP)
L
wait 1% new part
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
L Note: PLACE CLOSE TO U27 (NB CHIP)
R595 NAPG@0_0402_5%
C600
10U_0805_16V4Z
R590 1K_0402_5%
R599 NAPG@0_0402_5%
C601
@15P_0402_50V8J
L58
FBM-11-160808-121-T_0603
L63
KC FBM-L11-201209-221LMAT_0805
C594
0.1U_0402_10V6K
R587
68_0402_5%
R596 NAPG@0_0402_5%
RP104
NAGP@0_4P2R_0402_5%
L61KC FBM-L11-201209-221LMAT_0805
L59
KC FBM-L11-201209-221LMAT_0805
L62KC FBM-L11-201209-221LMAT_0805
C5870.1U_0402_10V6K
R592 NAGP@22_0402_5%
R597 NAPG@0_0402_5%
C605
@18P_0402_50V8K
C588
0.1U_0402_10V6K
[email protected]_20P_6X1430004201
R593
@1M_0402_1%
L60KC FBM-L11-201209-221LMAT_0805
R589 @0_0402_5%
C598
0.1U_0402_10V6K
R591
@10_0402_5%
C592
0.1U_0402_10V6K
G
D S
Q97@2N7002 1N_SOT23
L64
KC FBM-L11-201209-221LMAT_0805
PART 4 OF 6
CR
TCLK. GEN.
SV
IDLV
DS
U27D
216RC300M_BGA_718
C596
10U_0805_16V4Z
R594 NAPG@0_0402_5%
R584 715 _0402_1%
R598 NAPG@0_0402_5%
C590
0.1U_0402_10V6K
C591
10U_0805_16V4Z
C589
0.1U_0402_10V6K
C586
0.1U_0402_10V6K
C603
@15P_0402_50V8J
X2
NAGP@27MHZ_20P_6N
R588
@10_0402_5%
C602
[email protected]_0402_16V7K
C599
0.1U_0402_10V6K
RP103
NAGP@0_4P2R_0402_5%
C593
0.1U_0402_10V6K
R585 0_0402_5%
C604
@18P_0402_50V8K
C595
0.1U_0402_10V6K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.5VS +2.5V
+VCC_CORE
+3VS
+3VS
+1.5VS
+1.8VS
+1.5VS
+1.8VS
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
ATI RC300M-POWER
12 66Wednesday, September 24, 2003
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
C583
0.1U_0402_10V6K
C582
0.1U_0402_10V6K
C579
10U_0805_10V4Z
C580
0.1U_0402_10V6K
C581
0.1U_0402_10V6K
R418M9-M10@0_0603_5%
GND
U27F
216RC300M_BGA_718
R419 NAGP@0_0603_5%
PART 5 OF 6
PO
WE
R
CO
RE
PW
R
AG
P P
WR
MEM
I/F
PWR
CPU
I/F
PWR
ALIN
K PW
R
U 2 7 E
216RC300M_BGA_718
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
A_AD[0..31]
A_CBE#[0..3]
A_AD22
A_AD24
A_AD30
A_AD17
A_AD18
A_PAR
A_AD31
A_CBE#0
A_CBE#3
A_AD26
A_AD28
A_AD21
A_AD29
A_AD20
A_AD27
A_AD25
A_AD23
A_AD[0..31]<10,26>
A_CBE#[0..3]<10,26>
A_PAR<10,26>
BSEL1 <5,24>
BSEL0 <5,24>
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
ATI RC300M-SYSTEM STRAP
13 66Wednesday, September 24, 2003
Compal Electronics, Inc.
0: IOQ=11: IOQ=12
DEFAULT:1
A_AD23 : CLOCK BYPASS DISABLE
A_AD24 : MOBILE CPU SELECT
A_CBE#3: NOT USED
0: DISABLE1: ENABLE
0: TEST MODE 1: NORMAL MODE
00: 100 MHZ01: 133 MHZ10: 200MHZ11:166 MHZ
A_AD28: SPREAD SPECTRUM ENABLE
0: DISABLE1: ENABLE
0: REDUCEDE SET
DEFAULT : 0
DEFAULT: 01
1: FULL SET
A_AD26 : ENABLE IOQ
DEFAULT: 1
A_AD29: STRAP CONFIGURATION
A_AD27: FrcShortReset#
A_AD[31..30] : FSB CLK SPEED
DEFAULT:0
DEFAULT: 1
0: TEST MODE1: NORMAL
DEFAULT: 10
A_AD22 : OSC PAD OUTPUT PCICLK
DEFAULT: 1
A_CBE#0 :NO USED
DEFAULT: 1
DEFAULT : 1
A_AD20 : INTERNAL CLK GEN ENABLE
0: DEBUG MODE1: NORMAL
0: BANIAS CPU1: OTHER CPU
00: 1.05V01: 1.35V11: 1.75V10: 1.45V
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
PAR: EXTENDED DEBUG MODE
0:PCICLK OUT 1: OSC CLK OUT
DEFAULT : 1
A_AD21 : AUTO_CAL ENABLE
DEFAULT : 10: DISABLE1: ENABLE
A_AD18 : ENABLE PHASE CALIBRATION
0: DISABLE 1:ENABLE
DEFAULT: 0
A_AD25/A_AD17 : CPU VOLTAGE[1..0]
DEFAULT: 0
00: 1.05V01: 1.35V11: 1.75V10: 1.45V
AD25=1 DESTOP CPUAD25=0 MOBILE CPUAD17--DON'T CARE
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
R431 4.7K_0402_5%
R428 4.7K_0402_5%
R422 4.7K_0402_5%
R429 @4.7K_0402_5%
R469 @4.7K_0402_5%
R430 @10K_0402_5%
R438 10K_0402_5%
R425 4.7K_0402_5%
R461 10K_0402_5%
R463 @4.7K_0402_5%
R427 10K_0402_5%
R434 10K_0402_5%
R443 10K_0402_5%
R435 @4.7K_0402_5%
R452 10K_0402_5%
R448 10K_0402_5%
D86RB751V_SOD323
R468 @4.7K_0402_5%
R423 4.7K_0402_5%D85RB751V_SOD323
R454 @4.7K_0402_5%
R460 4.7K_0402_5%
R465 4.7K_0402_5%
R464 @4.7K_0402_5%
R466 @4.7K_0402_5%
R420 10K_0402_5%
R444 @4.7K_0402_5%
R467 @4.7K_0402_5%
R421 @4.7K_0402_5%
R424 10K_0402_5%
R440 @4.7K_0402_5%
R457 @4.7K_0402_5%
R462 @4.7K_0402_5%
R426 @4.7K_0402_5%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDRA_SDQS[0..7]
DDRA_SDQ[0..63]
DDRA_ADD[0..15]
DDRA_SDQ32
D D R A _ S D Q S 3
DDRA_SDQ42
D D R A _ S D Q S 2
D D R A _ S D Q S 5
DDRA_WE#
DDRA_SDQ16
DDRA_SDQ35
DDRA_SDQ27
DDRA_SDQ18
DDRA_SDQ40
DDRA_SDQ25
DDRA_SDQ33
DDRA_SDQ44
D D R A _ R A S #D D R A _ C A S #
DDRA_SDQ39
DDRA_SDQ46
DDRA_SDQ36
DDRA_SDM5
DDRA_SDQ37
DDRA_SDQ31
DDRA_SDM3
DDRA_SDQ20
DDRA_SDQ29
DDRA_SDM2DDRA_SDQ22
D D R A _ S D Q S 7DDRA_SDQ58
DDRA_SDM7DDRA_SDQ62
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54DDRA_SDQ55
DDRA_SDQ7
DDRA_SDM1DDRA_SDQ14
DDRA_SDM0DDRA_SDQ5
DDRA_SDQ12
D D R A _ S D Q S 0DDRA_SDQ1
DDRA_SDQ8
DDRA_SDQ3
DDRA_SDQ10D D R A _ S D Q S 1
DDRA_CS#0 DDRA_CS#1
D D R A _ A D D 5
DDRA_ADD12D D R A _ A D D 9
D D R A _ A D D 3D D R A _ A D D 1
DDRA_ADD13
D D R A _ A D D 4D D R A _ A D D 2D D R A _ A D D 0
DDRA_ADD11D D R A _ A D D 8
SMB_CK_CLK2<15,24,27>
DDRA_SDQ[0..63]<9,15,16>
DDRA_ADD[0..15]<9,15,16>
DDRA_SDM[0..7]<9,15,16>
DDRA_SDQS[0..7]<9,15,16>
D D R A _ C K E _ R 1<9,16>
DDRA_CLK0<9>
DDRA_WE#<9,15,16>
DDRA_CLK1# <9>DDRA_CLK1 <9>
D D R A _ C A S # <9,15,16>D D R A _ R A S # <9,15,16>
D D R A _ C K E _ R 0 <9,16>
DDRA_CS#0<9,16> DDRA_CS#1 <9,16>
+2.5V
+2.5V
+2.5V
LA-1811
DDR-SODIMM SLOT1
14 66Wednesday, September 24, 2003
Compal Electronics, Inc.
System Memory Decoupling caps
DDRA_VREF trace width of20mils and space 20mils(min)
DIMM0
Group 6 sweep Group 7Group 6 sweep Group 7
Group 0 sweep Group 1
Group 0 sweep Group 1
L
REVERSE
C419
0.1U_0402_10V6K
C431
0.1U_0402_10V6K
C414
0.1U_0402_10V6K
C435
0.1U_0402_10V6K
C428
0.1U_0402_10V6K
C425
10U_0805_6.3V6M
C424
0.1U_0402_10V6K
C430
0.1U_0402_10V6K
C432
0.1U_0402_10V6K
0.1U_0402_10V6K
R472
1K_0603_1%
C412
C416
0.1U_0402_10V6K
C433
0.1U_0402_10V6K
C436
0.1U_0402_10V6K
C422
0.1U_0402_10V6K
C426
0.1U_0402_10V6K
C434
0.1U_0402_10V6K
C438
10U_0805_6.3V6M
C417
0.1U_0402_10V6K
C437
0.1U_0402_10V6K
C429
0.1U_0402_10V6K
C415
0.1U_0402_10V6K
R473
1K_0603_1%
C418
0.1U_0402_10V6K
C427
0.1U_0402_10V6K
C413
0.1U_0402_10V6K
JP24
AMP_1565918-1
C421
0.1U_0402_10V6K
C420
0.1U_0402_10V6K
C423
0.1U_0402_10V6K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDRA_SDQS[0..7]
DDRA_SDM[0..7]
DDRA_SDQ[0..63]
D D R B _ V R E F
DDRA_SDQ30
DDRA_SDQ23
DDRA_SDQ32
DDRA_SDQ24
DDRA_SDQ43
DDRA_SDQ31
DDRA_SDQ28
DDRA_SDM2
D D R A _ S D Q S 4
DDRA_SDQ47
DDRA_SDM5
D D R A _ S D Q S 2
DDRA_SDM4
DDRA_SDQ21
DDRA_SDQ26
DDRA_SDQ19
DDRA_SDQ36
DDRA_SDQ27
DDRA_SDQ17
D D R A _ S D Q S 5DDRA_SDQ41
DDRA_SDQ34
DDRA_SDQ45
DDRA_SDQ38
DDRA_SDQ50
DDRA_SDQ59
D D R A _ S D Q S 6
DDRA_SDQ48
DDRA_SDQ57DDRA_SDQ56
DDRA_SDQ61
DDRA_SDM6
DDRA_SDQ52
DDRA_SDQ60
DDRA_SDQ63
DDRA_SDQ54
DDRA_SDQ9
D D R A _ S D Q S 1
DDRA_SDQ11
DDRA_SDQ13
DDRA_SDM1
DDRA_SDQ15DDRA_SDQ0
DDRA_SDQ2DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ6DDRA_SDQ7
D D R A _ C K E 2
D D R A _ S R A S #
D D R A _ C K E 3
DDRA_SMA13DDRA_SMA10
D D R A _ S M A 7D D R A _ S M A 5
DDRA_SMA15
D D R A _ S M A 6D D R A _ S M A 4
DDRA_SMA14DDRA_WE# D D R A _ S W E #
D D R A _ R A S # D D R A _ S R A S #
DDRA_CS#3 DDRA_SCS#3DDRA_ADD15DDRA_SMA15
DDRA_SDQ[0..63]<9,14,16>
DDRA_SDQS[0..7]<9,14,16>
DDRA_ADD[0..15]<9,14,16>
SMB_CK_CLK2<14,24,27>SMB_CK_DAT2<14,24,27>
DDRA_CLK3<9>DDRA_CLK3#<9>
DDRA_CLK4# <9>
DDRA_WE#<9,14,16>
DDRA_CS#2<9,16>
D D R A _ C K E _ R 2<9,16>
D D R A _ R A S #<9,14,16>
D D R A _ C A S #<9,14,16>
DDRA_CS#3<9,16>
D D R A _ C K E _ R 3<9,16>
+2.5V
+3VS
+2.5V+2.5V+2.5V
+3VS
LA-1811
DDR-SODIMM SLOT2
15 66Wednesday, September 24, 2003
Compal Electronics, Inc.
System Memory Decoupling caps
DIMM1
Group 6 sweep Group 7
Group 0 sweep Group 1
Group 0 sweep Group 1
DDRB_VREF trace width of20mils and space20mils(min)
L
STANDARD
R401 10_0402_5%
R1122 10_0402_5%
C406
0.1U_0402_10V6K
R471
1K_0603_1%
R390 10_0402_5%
C408
0.1U_0402_10V6K
RP39
R393 10_0402_5%
C410
0.1U_0402_10V6K
C399
0.1U_0402_10V6K
C392
RP26
C404
0.1U_0402_10V6K
C396
0.1U_0402_10V6K
C3930.1U_0402_10V6K
C401
10U_0805_6.3V6M
R392 10_0402_5%
RP32
C402
10U_0805_6.3V6M
R1121 10_0402_5%
C403
0.1U_0402_10V6K
C407
0.1U_0402_10V6K
R396 10_0402_5%
C394
22U_1206_10V4Z
RP38
1K_0603_1%
C409
0.1U_0402_10V6K
RP29
R402 10_0402_5%
C398
0.1U_0402_10V6K
RP42
C397
0.1U_0402_10V6K
C405
0.1U_0402_10V6K
C400
0.1U_0402_10V6K
RP35
C395
0.1U_0402_10V6K
R391 10_0402_5%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDRA_SDM[0..7]
DDRA_ADD[0..15]
DDRA_SDQS[0..7]
DDRA_SDQ8
DDRA_SDQ13
DDRA_SDQ21
DDRA_SDQ16
DDRA_SDQ11DDRA_SDQ15
DDRA_SDQ14
DDRA_SDQ19DDRA_SDQ23
DDRA_SDQ22
DDRA_SDQ54DDRA_SDQ55DDRA_SDQ51
DDRA_SDQ49D D R A _ S D Q S 6
DDRA_SDQ63DDRA_SDQ52
DDRA_SDQ62
DDRA_SDQ58D D R A _ S D Q S 7
DDRA_SDQ60
DDRA_SDQ57
DDRA_SDM5DDRA_SDQ41
DDRA_SDQ45
DDRA_SDQ42DDRA_SDQ43
DDRA_SDQ35DDRA_SDQ39
DDRA_SDQ38
DDRA_SDQ34DDRA_SDM4
DDRA_SDQ32
DDRA_SDQ37
DDRA_SDQ25D D R A _ S D Q S 3
DDRA_SDQ18DDRA_SDM2
DDRA_SDQ6
DDRA_SDQ2DDRA_SDQ7
DDRA_SDQ1D D R A _ S D Q S 0
DDRA_SDQ10DDRA_SDM1
DDRA_CS#0
DDRA_SDQ30
DDRA_SDQ27
D D R A _ C K E _ R 1
D D R A _ A D D 2
DDRA_ADD10D D R A _ A D D 1
D D R A _ A D D 0DDRA_ADD14D D R A _ R A S #
DDRA_ADD12
DDRA_CS#1DDRA_CS#2
DDRA_WE#
D D R A _ A D D 3D D R A _ A D D 7D D R A _ A D D 5
D D R A _ C K E _ R 3D D R A _ C K E _ R 2
D D R A _ A D D 4
DDRA_SDQ[0..63]<9,14,15>
DDRA_ADD[0..15]<9,14,15>
DDRA_SDM[0..7]<9,14,15>
DDRA_CS#0 <9,14>
D D R A _ C K E _ R 0 <9,14>D D R A _ C K E _ R 1 <9,14>
DDRA_CS#3 <9,15>
D D R A _ R A S # <9,14,15>
DDRA_CS#1 <9,14>
DDRA_WE# <9,14,15>
D D R A _ C K E _ R 3 <9,15>D D R A _ C K E _ R 2 <9,15>
D D R A _ C A S # <9,14,15>
+2.5V
+2.5V
+1.25VS +1.25VS
+2.5V
+1.25VS
+1.25VS
+1.25VS
+1.25VS
+1.25VS
+1.25VS
LA-1811
DDR Termination Resistors
16 66Wednesday, September 24, 2003
Compal Electronics, Inc.
DDR Termination resistors & Decoupling caps
C466
0.1U_0402_10V6K
C486
C469
0.1U_0402_10V6K
C470
0.1U_0402_10V6K
33_0402_5%
RP73
C472
0.1U_0402_10V6K
C458
0.1U_0402_10V6K
C495
0.1U_0402_10V6K
RP91
56 _0804_8P4R_5%
33_0404_4P2R_5%
RP70
56 _0804_8P4R_5%
RP68
56 _0804_8P4R_5%
56 _0804_8P4R_5%
C494
0.1U_0402_10V6K
56 _0804_8P4R_5%
C460
0.1U_0402_10V6K
0.1U_0402_10V6K
RP78
C463
0.1U_0402_10V6K
C484
RP85
56 _0804_8P4R_5%
C490
C473
0.1U_0402_10V6K
C474
0.1U_0402_10V6K
RP84
33_0804_8P4R_5%
C465
0.1U_0402_10V6K
C471
0.1U_0402_10V6K
C496
0.1U_0402_10V6K
C467
0.1U_0402_10V6K
C464
0.1U_0402_10V6K
RP79
56 _0804_8P4R_5%
RP88
RP92
33_0404_4P2R_5%
C493
0.1U_0402_10V6K
C455
0.1U_0402_10V6K
C483
C461
0.1U_0402_10V6K
RP81
33_0804_8P4R_5%
C452
0.1U_0402_10V6K
C462
0.1U_0402_10V6K
56 _0804_8P4R_5%
RP75
33_0804_8P4R_5%
C468
0.1U_0402_10V6K
+ C491
@100U_D2_10M_R45
RP72
33_0404_4P2R_5%
C489
RP90
56 _0804_8P4R_5%
C457
0.1U_0402_10V6K
+ C492
100U_D2_10M_R45
RP86
56 _0804_8P4R_5%
0.1U_0402_10V6K
C459
0.1U_0402_10V6K
C497
4.7U_0805_16V6K
0.1U_0402_10V6K0.1U_0402_10V6K
RP83
56 _0804_8P4R_5%
0.1U_0402_10V6K
RP71
33_0404_4P2R_5%
0.1U_0402_10V6K
C456
0.1U_0402_10V6K
C451
0.1U_0402_10V6K
RP76
56 _0804_8P4R_5%
0.1U_0402_10V6K
C453
0.1U_0402_10V6K
C454
0.1U_0402_10V6K
C485 C488
RP74
56 _0804_8P4R_5%
RP69
33_0404_4P2R_5%
C487
0.1U_0402_10V6K
RP77
56 _0804_8P4R_5%
RP93
56 _0804_8P4R_5%
56 _0804_8P4R_5%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
STRAP_S
STRAP_A
STRAP_L
STRAP_F
FREQOUT
STRAP_E
AGP_AD[0..31]
STRAP_M
STRAP_O
STRAP_N
STRAP_D
STRAP_B
AGP_ST[0..2]
AGP_SBA[0..7]
AGP_CBE#[0..3]
STRAP_R
STRAP_J
XTALIN_SSFREQOUT
STRAP_G
XTALIN
STRAP_T
XTALIN_SS
ENABLT#
CRT_R
TV_LUMA
AGP_REQ#
AGP_AD12
AGP_RSET
TXA0-
STRAP_E
AGP_SBA7
AGP_SBA2
NB_RST#
AGP_AD22
AGP_AD2
CRT_HSYNC
TXBCLK+
VREFG
STRAP_J
SSOUT
TV_CRMA
AGP_ADSTB0
AGP_AD27
AGP_AD16
DVOMODE
STRAP_M
AGP_SBSTB#
AGP_ST0
AGP_RBF#
AGP_DEVSEL#
AGP_AD23
AGP_AD17
AGP_AD8
TXB0+
AGP_AD5
TXA2+
TXA1+
STRAP_B
TV_COMPS
AGP_SBA4
AGP_BUSY#
AGP_AD10
TXBCLK-
AGP_SBA1
AGP_PAR
AGP_CBE#3
AGP_AD15
AGP_AD1
STRAP_K
CRT_G
STRAP_A
STRAP_K
AGP_ADSTB0#
AGP_IRDY#
AGP_AD20
AGP_AD11
STRAP_O
XTALIN
AGP_DBI_HI/PIPE#
AGP_ST2
AGP_SBA3
AGP_STP#
AGP_AD29
AGP_AD19
AGP_AD4
CRT_B
AGP_DBI_LO
AGP_ST1
AGP_AD14
3VDDCCL
TXB1-
MCLK_SPREAD
STRAP_F
AGP_CBE#1AGP_CBE#0
AGP_AD18
AGP_AD9
TXB2+TXB2-
TXA1-
STRAP_D
SUSSTAT#
AGP_AD26AGP_AD25
TXACLK-
STRAP_G
SSIN
AGP_SBA0
AGP_ADSTB1
CLK_AGP_EXT_66M
AGP_CBE#2
AGP_AD31
AGP_AD0
SUSSTAT#
TXA0+
STRAP_T
STRAP_N
AGP_SBA5
AGP_FRAME#
AGP_AD24
AGP_AD3
STRAP_H
3VDDCDA
TXB1+
TXACLK+
STRAP_L
AGP_ADSTB1#
AGP_GNT#
AGP_AD30
AGP_AD28
AGP_AD21
AGP_AD7
CRT_VSYNC
ENAVDD
TXB0-
STRAP_H
AGP_STOP#
TXA2-
AGP_SBSTB
AGP_SBA6
AGP_TRDY#
AGP_AD13
AGP_AD6
DRAM128M
DRAM128M
STRAP_SSTRAP_R
AGP_AD[0..31]<10>
AGP_SBA[0..7]<10>
AGP_CBE#[0..3]<10>
AGP_ST[0..2]<10>
CLK_AGP_EXT_66M<24>
AGP_BUSY#<10,27>AGP_STP#<10,27>
VREF_8X_IN<10>
AGP8X_DET#<10>
ENABLT# <10,25>
TV_LUMA<11,41,48>
AGP_RBF#<10>
PCI_PIRQA#<10,26,31,35,36>
AGP_WBF#<10>
CRT_B <11,25>CRT_HSYNC <11,25>
AGP_ADSTB0<10>
AGP_REQ#<10>
3VDDCCL <11,25>
AGP_TRDY#<10>
AGP_STOP#<10>
AGP_IRDY#<10>
AGP_ADSTB1<10>
3VDDCDA <11,25>
AGP_SBSTB#<10>
TV_COMPS<11,41,48>
AGP_ADSTB1#<10>AGP_ADSTB0#<10>
CRT_R <11,25>
CRT_VSYNC <11,25>
AGP_DBI_HI/PIPE#<10>
AGP_PAR<10>
AGP_SBSTB<10>
AGP_DBI_LO<10>
AGP_GNT#<10>
NB_RST#<8,26,39>
CRT_G <11,25>
TV_CRMA<11,41,48>
AGP_DEVSEL#<10>
AGP_FRAME#<10>
SSOUT<10>
SSIN<10>
M10_BKOFF# <25>
TXACLK- <25>
TXB0+ <25>
TXBCLK- <25>
TXA0- <25>TXA0+ <25>
TXB1- <25>
TXA2- <25>
TXB1+ <25>
TXA1- <25>
TXA2+ <25>
TXB2+ <25>TXB2- <25>
TXBCLK+ <25>
TXB0- <25>
TXA1+ <25>
TXACLK+ <25>
ENAVDD <10,25,46>
DDC_DAT <10,25>D D C _ C L K <10,25>
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+1.5VS
+3VS
+3VS
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
ATI M10-P & M9+X (AGP BUS)
17 66Wednesday, September 24, 2003
Compal Electronics, Inc.
GPIO0
GPIO6
GPIO5
GPIO4
VGA_Disable
3.3V OSC out for W180
GPIO7
1.5V OSC out for M9+X1.2V OSC out for M10-P
ID_Disable
Rb
Divider Circuit for 1.2V/(1.5)dc XTALIN from 3.3Vdc OSC out
GPIO8
Ra
Leave These Pin No Connecting, WhenUsing M10-P Internal Spread Spectrum
GPIO3
GPIO13
GPIO2
GPIO12
GPIO11
GPIO9
GPIO1
AGP, DAC & LVDS INTERFACE
AGP8X_DET#Low:AGP3.0
(15mil)
(25mil)
(15mil)
(15mil)
(25 mil)
SS%
(Closed to M26)
If M10+P POP 47_0603_1%If M9+P POP 137_0603_1%
Note: PLACE CLOSE TO U6 (VGA M9+X/M10-P)L
Ra 261_0603_1%150_0402_5%150_0402_5%
180_0603_5%M10-PM9+X
Rb
Fin>Fout>Fin-3.75%
Spread % Setting for Freq. RangeFin>Fout>Fin-1.25%0
1
Selection Table For W180
SS%
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
For VGA DDR spread sprum
CLK
DATA
For 8Mx32 VGA DRAM only
PIR LAYOUT 92.09.01
PIR LAYOUT 92.09.01 PIR LAYOUT 92.09.01
R235 @1K_0402_5%
R267 100K_0402_5%
R247 @10K_0402_5%
R270 10K_0402_5%
C184 @10P_0402_50V8K
R268 22_0402_5%
R234
M10@1K_0603_1%
R238 @10K_0402_5%
U7
W180-01GT_SO8
C189
0.1U_0402_10V6K
R257 @10K_0402_5%
R258 0_0402_5%
R250 @10K_0402_5%
R272 499_0402_1%
R236 @10K_0402_5%
R233 @10K_0402_5%
R244 @10K_0402_5%
R242 @10K_0402_5%
R232 @10K_0402_5%
R239
M10@1K_0603_1%
R243 M10@10K_0402_5%
R271 @10K_0402_5%
R274 10K_0402_5%
R264 137_0603_1%
L13
FCM2012C-800_0805
R830 M10@0_0402_5%
R829M9@0_0402_5%
R246 @10K_0402_5%
[email protected]_0402_5%
C1912.2U_0603_6.3V4Z
R266 715_0603_1%
C1860.1U_0402_10V6K
R248 @10K_0402_5%
R276 1K_0603_5%
C188
0.1U_0402_10V6K
R265M9-M10@1K_5%
R269 10K_0402_5%
C185
0.1U_0402_10V6K
R249 @10_0402_5%
R259 @10K_0402_5%
R1149@10K_0402_5%
R245 @10K_0402_5%
R254 @10K_0402_5%
R241 M10@10K_0402_5%
R252 @10K_0402_5%
R26110K_0402_5%
R260 @10K_0402_5%
C187
@15P_0402_50V8J
X1
27MHZ_15P
R275 1K_0603_5%
R262 180_0603_5%
PC
I/AG
PA
GP
8X
CL
K
ZV
PO
RT
/ E
XT
TM
DS
/ G
PIO
/ R
OM
LV
DS
TM
DS
DA
C1S
SC
DA
C2
M10-P/(M9+X) (1/6)
THRM
U 6 A
SA002160E00(0301021300)
R263150_0402_5%
R2370_0402_5%
R955@10K_0402_5%
R240 @10K_0402_5%
R253
10K_0402_5%
R256 @10K_0402_5%
C190
0.1U_0402_10V6K
R273
10K_0402_5%
R255 @10K_0402_5%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NDQSA3
NMDA13
NMDA26
NMDA32
NMDA7
NDQSA0
NMAA6
NMDA12
NDQMA1
NMDA59
NMDA16
NMDA43
MVREFS
NMDA30
NMDA27
NDQMA4
NMDA3
NMDA1
NMAA11
NMDA25
NMAA12
NDQSA7
NMDA11
NMDA46
NMDA50
NMDA2
NDQMA0
NMAA4
NMDA52
NMDA55
NDQSA5
NDQMA3
NMDA24
NMAA0
NMDA45
NMDA48
NDQSA2
NMDA49
NDQMA7
NMDA33
NMDA19
NMCASA#
NMDA18
NMDA28
NMDA38
NMAA2
NMDA41
NMDA47
NMDA35
NMAA10
NMCLKA0#
NMDA14
NMDA31
NMDA15
NMDA20
NMDA56
NDQSA4
NMAA[0..13]
NMDA54
MVREFD
NMDA58
NMDA51
NMDA37
NMDA42
NMDA6
NMDA34
NMAA9NMDA10
NMDA60
NMDA62
NDQMA6
NMCKEA
NMDA4
NMWEA#
NMDA36
NMDA61
NDQMA[0..7]
NMDA44NMCSA0#
NDQMA5
NMDA39
NMDA63
NMDA0
NMDA17
NDQSA6
MVREFD
NMAA8
NMDA29
NDQMA2
NMAA7
NMDA[0..63]
NMAA3
NDQSA1
NMCLKA1
NMAA1
NMAA13
NMDA57
NMDA21
NMDA5
NMDA9
MVREFS
NMAA5
NMDA23NMDA22
NMDA53
NMDA40
NMDA8
NDQSA[0..7]
NMCLKA1#
NMRASA#
NMCLKA0
NMCSA1#
NMCLKA0# <22>
NMCASA# <22>
NMDA[0..63]<22>
NMCSA0# <22>
NDQMA[0..7]<22>
NMCLKA1 <22>
NMAA[0..13]<22>
NMWEA# <22>
NDQSA[0..7]<22>
NMCLKA1# <22>
NMCKEA <22>
NMRASA# <22>
NMCLKA0 <22>
NMCSA1# <22>
+2.5VS
+2.5VS
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
ATI M10-P/M9+X DDR-A
18 66Wednesday, September 24, 2003
Compal Electronics, Inc.
Poped for M10-PDepoped forM9+X
MEMORYINTERFACE A
(25 mil)
(25 mil)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
R475
1K_0402_1%
R486
M10@1K_0402_1%
R478
1K_0402_1%
R487
M10@1K_0402_1%
C498
0.1U_0402_10V6K
ME
MO
RY
INT
ER
FA
CE
A
M10-P/(M9+X) (2/6)
U 6 B
SA002160E00(0301021300)
C503
[email protected]_0402_16V4Z
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NMDB26
NMDB40
NMAB5
NMDB62
NMDB[0..63]
NMDB44
NMDB48
NMDB18
NMDB54
NDQSB3
NMDB49
NMDB63
NMAB0
NMAB11
NDQSB4
NDQSB7
NMDB39
NMDB22
NMDB36
NMAB7
NMDB12
NMDB21
NMDB31
NMCLKB0#
NMDB42
NMAB2
NMAB4
NMDB34
NMDB43
NMCLKB0
NMDB19
NDQMB6
NMDB20
NMDB11
NMDB29
NDQMB1
NMCASB#
NDQMB4
NMDB53NMDB52
NMDB14
NMAB12
NDQMB0
NMAB[0..13]
NMDB10
NMDB38
NMDB46
NMDB35
NMDB45
NMDB51NMCLKB1#
NMDB61
NMDB13
NMAB1
NMDB50
NDQMB[0..7]
NMDB60
NMDB25
NMDB2
NMDB4
NMWEB#
NMDB16
NMDB23
NMDB7
NMAB3
NMAB10
NMDB59
NMDB41
NMDB24
NMDB3
NMDB58
NDQMB7
NMDB30
NMDB57
NMAB6
NMDB8
NDQSB1
NDQSB6
NDQMB5
NMAB13
NMDB28NMDB27
NMAB9
NDQSB[0..7]
NMAB8
NMCSB0#
NMDB47
NDQMB2
NMDB6
NMDB55
NMDB9
NMDB33
NMDB56
NMDB15
NDQSB0
NMDB5
NMDB17
NMDB32
NMDB37
NMRASB#
NDQMB3
NMDB1NMDB0
NDQSB5
NDQSB2
NMCKEB
NMCLKB1
NMCSB1#
NMCASB# <23>
NMWEB# <23>
NMCLKB0 <23>
NMDB[0..63]<23>
NMCKEB <23>
NDQMB[0..7]<23>
NMCSB0# <23>
NMAB[0..13]<23>
NMCLKB0# <23>
NDQSB[0..7]<23>
NMRASB# <23>
NMCLKB1# <23>NMCLKB1 <23>
NMCSB1# <23>
+1.8VS
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
ATI M10-P/M9+X DDR-B
19 66Wednesday, September 24, 2003
Compal Electronics, Inc.
(15mil)
MEMORYINTERFACE B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ME
MO
RY
INT
ER
FA
CE
B
M10-P/(M9+X) (3/6)
U 6 C
SA002160E00(0301021300)
R509 4.7K_0402_5%R510 4.7K_0402_5%
R511 47_0603_1%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+LVDDR+VDDC1.5
+1.8VS
+VDD_DAC1.8
+VDD_DAC2.5
+VDD_PNLIO1.8
+VDD_PNLIO1.8
+VDD_PNLIO2.5
+3VS
+2.5VDDRH
+VDD_PLL1.8
+VDD_PNLIO2.5
+2.5VS
+VDD_PNLPLL1.8
+VDD_DAC1.8
+3VS
+2.5VS
+VDD_MEMPLL1.8
+1.8VS
+VDD_PNLIO1.8
+2.5VS
+1.8VS
+1.8VS
+2.5VS
+2.5VS
+VDD_MEMPLL1.8
+VDD_DAC1.8
+VDD_PNLPLL1.8
+VDD_PNLPLL1.8
+2.5VDDRH
+VDD_PNLIO1.8
+1.8VS
+VDD_DAC1.8+VDD_DAC2.5
+VDD_PLL1.8
+1.8VS
+1.5VS
+1.5VS
+1.5VS
+VDDC1.5 +LVDDR
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
ATI M10-P/M9+X POWER-A
20 66Wednesday, September 24, 2003
Compal Electronics, Inc.
(20 mil)
As close as possible to related pin
Poped for M9+X
(20 mil)Poped for M10-P
Poped for M10-P
(20 mil)
POWERINTERFACE
(20 mil)
(20 mil)
Poped for M9+X
(20 mil)
(20 mil)
(20 mil)
Poped forM10-P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Note: PLACE CLOSE TO U6 (VGA ATI M10P/M9+X)L
C215
0.1U_0402_10V6K
C869
0.1U_0402_10V6K
C199
0.1U_0402_10V6K
C194
0.1U_0402_10V6K
C203
0.1U_0402_10V6K
C209
10U_0805_6.3V6M
C220
0.1U_0402_10V6K
R280 M10@0_0603_5%
C2022.2U_0603_6.3V4Z
C863
0.1U_0402_10V6K
C192
22U_1206_10V4Z
C868
0.1U_0402_10V6K
C208
0.1U_0402_10V6K
C201
0.01U_0402_16V7K
L17
CHB1608U301_0603
C217
0.1U_0402_10V6K
C213
0.1U_0402_10V6K
L20
CHB1608U301
R281 M9@0_0603_5%
C862
0.1U_0402_10V6K
C870
0.1U_0402_10V6K
C216
0.1U_0402_10V6K
C200
0.01U_0402_16V7K
L21
CHB1608U301
C193
0.1U_0402_10V6K
C865
0.1U_0402_10V6K
C212
0.1U_0402_10V6K
C205
0.1U_0402_10V6K
C207
0.1U_0402_10V6K
C196
0.01U_0402_16V7K
C871
0.1U_0402_10V6K
C968
0.1U_0402_10V6K
C214
10U_0805_6.3V6M
C866
0.1U_0402_10V6K
C195
0.01U_0402_16V7K
R278 M10@0_0402_5%
L15
CHB1608U301_0603
C967
0.1U_0402_10V6K
L14
CHB1608U301_0603
C210
0.1U_0402_10V6K
C92
0.1U_0402_10V6K
C197
22U_1206_10V4Z
I/O
PO
WE
R
M10-P/(M9+X) (4/6)
U 6 D
SA002160E00(0301021300)
C9312.2U_0603_6.3V4Z
C219
0.1U_0402_10V6K
C204
1U_0603_10V6K
R282 M9@0_0805_5%
L16
CHB1608U301_0603
C970
0.1U_0402_10V6K
R279 M10@0_0805_5%
C211
10U_0805_6.3V6M
C198
0.1U_0402_10V6K
L19
CHB1608U301_0603
C867
0.01U_0402_16V7K
C969
0.1U_0402_10V6KC218
10U_0805_6.3V6M
C206
10U_0805_6.3V6M
L18
CHB1608U301_0603
R277 M10@0_0402_5%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+2.5VS
+VGA_CORE
+VGA_CORE
+VGA_CORE
+VGA_CORE_CI
+VGA_CORE_CI
+2.5VS
+VGA_CORE
+1.2VS_VGA
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
ATI M10-P/M9+X POWER-B
21 66Wednesday, September 24, 2003
Compal Electronics, Inc.
As close as ppossible to related pin
(20 mil)
POWERINTERFACE
As close as ppossible to related pin
480MIL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(12A,480mils ,Via NO.=24)
+ C221
@47U_D2_6.3VM
C2390.01U_0402_16V7K
C2300.01U_0402_16V7K
C2380.01U_0402_16V7K
C2360.1U_0402_10V6K
CO
RE
PO
WE
R
M10-P/(M9+X) (5/6)
U 6 E
SA002160E00(0301021300)
C2480.1U_0402_10V6K
C2450.1U_0402_10V6K
C2270.1U_0402_10V6K
L22
CHB1608U301
JOPEN5PAD-OPEN 4x4m
C2370.1U_0402_10V6K
C2290.01U_0402_16V7K
C2500.01U_0402_16V7K
CO
RE
PO
WE
R
M10-P/(M9+X) (6/6)
M10-P&M9+XCOMMON
M10-PONLY
M9+XONLY
U6F
SA002160E00(0301021300)
C2440.1U_0402_10V6K
C2350.1U_0402_10V6K
C2340.1U_0402_10V6K
C2280.1U_0402_10V6K
C2460.1U_0402_10V6K
C2470.1U_0402_10V6K
C2420.1U_0402_10V6K
C2310.01U_0402_16V7K
C22322U_1206_10V4Z
C23222U_1206_10V4Z
C24322U_1206_10V4Z
C22422U_1206_10V4Z
C2250.1U_0402_10V6K
C240
10U_0805_6.3V6M
+C222
100U_D2_10M_R45
C2410.1U_0402_10V6K
C2330.1U_0402_10V6K
C2490.01U_0402_16V7K
C2260.1U_0402_10V6K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NMDA30
NMDA7
NDQSA3
NDQMA3
NMAA2NMDA52
NMDA17
NMCLKA1#
NDQMA7
NMRASA#
NMDA43
NMAA5NMDA49
NDQSA4
NMDA56
VREF_2
NDQMA5
NMDA21
NMDA61
NMDA41NMDA10
NMAA5
NMDA34
NMAA12
NMAA10
NMWEA#
NMDA[0..63]
NMDA38
NMCSA0#
NMAA8
NMAA6
NMAA1
NMDA19
NMDA22
NMAA9
NMAA7
NMDA1
NMDA44
NMCLKA1
NMDA57
NMDA4
NMDA50
NDQMA1
NMAA13
NMDA13
NMAA13
NMAA7
NMDA42
NMDA2
NMAA4
NMDA29
NDQSA1
NMDA14
NMAA12
NMDA53NMAA3
NMDA62
NMDA28
NMAA1NMAA2
NMDA35
NMCKEA
NMDA3
NDQMA2
NMDA54
NMRASA#
NMDA51
NDQSA[0..7]
NMAA8
NMDA45
NMDA47
NMDA39
NMAA4
NMDA24
NMDA15
NMCSA0#
NMDA25
NMAA11
NMDA36
NMDA6
NMDA9
NDQSA5
NDQSA7
NMDA31
NMDA27
NMDA16
NMCASA#
NMAA0
NMDA26
NDQSA0
NMCKEA
NMCASA#
NMAA0
NMDA18
NMDA55
NMDA37
NMDA46
NMDA32
NDQMA0
NMCLKA0
NMDA11
NMDA59
NMDA23
NMDA0
VREF_1
NMAA[0..13]
NMAA11
NDQSA6
NMAA9
NMDA40
NMDA20 NMAA3
NMDA8NMWEA#
NMAA6
NMDA33
NDQMA[0..7]
NDQSA2
NMDA58
NMDA5
NMDA48NMDA63
NDQMA4
NMDA12
NMAA10
NDQMA6
NMDA60
NMCLKA0#
NMCSA1#
NMCSA1#
NMCLKA1#<18>
NMCLKA1<18>
NDQSA[0..7]<18>
NMCSA0#<18>NMWEA#<18>
NMCLKA0<18>
NDQMA[0..7]<18>
NMAA[0..13]<18>
NMCKEA<18>
NMDA[0..63]<18>
NMRASA#<18>
NMCLKA0#<18>
NMCASA#<18>
NMCSA1#<18>
+2.5VS+2.5VS
+2.5VS+2.5VS
+2.5VS +2.5VS
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
VGA DDR FOR CHANNEL A
22 66Wednesday, September 24, 2003
Compal Electronics, Inc.
(25mil)
VGA DDR FOR CHANNELA
As close as ppossible to related pin
(25mil)
As close as ppossible to related pin
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
C5060.1U_0402_10V6K
C504
10U_0805_10V3MC5120.1U_0402_10V6K
U28
K4D263238A-GC
C507
10U_0805_10V3M
R62656.2_0402_1%
C5150.1U_0402_10V6K
R489
1K_0402_1%
R488
1K_0402_1%
C5160.1U_0402_10V6K
R62756.2_0402_1%
R491
1K_0402_1%
U29
K4D263238A-GC
C62910P_0402_50V8K
R490
1K_0402_1%
C510
10U_0805_10V3M
C628
10P_0402_50V8K
C5080.1U_0402_10V6K
C5090.1U_0402_10V6K
C5050.1U_0402_10V6K
C513
10U_0805_10V3M
C5110.1U_0402_10V6K
C5170.1U_0402_10V6K
R62556.2_0402_1%
C5140.1U_0402_10V6K
R62856.2_0402_1%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NMDB5
NMDB49
NDQSB3
NMAB4
NMDB8NMDB33
VREF_4NMDB53
NMAB8
NMAB6
NMDB25
NMAB10NMAB11
NMDB12
NDQMB4
NMDB57
NMDB43NMAB4
NMDB40
NDQMB7
NMAB2
NMDB28
NMDB1
NMAB10
NMDB6
NMDB22NMAB9
NMDB9
NMAB6
NMAB13
NMDB34
NDQMB2
NMDB54
NMDB41
NMDB50NMDB26
NMDB13
NMDB44
NMAB12
NMDB56
NDQMB1
NDQMB5
NMDB32
NDQMB[0..7]
NMAB0
NMDB29VREF_3
NMDB2
NDQSB1
NMDB37
NMDB7
NMCKEB
NMAB5
NMDB62NMDB23
NMDB10NDQSB0
NMDB55
NMAB3
NDQSB2NMDB35
NMDB19
NMDB45
NMDB63NMAB7
NDQMB3
NMDB30
NMAB1
NMCLKB1NMCLKB0
NMAB11
NMDB16
NMAB5NMDB3
NMDB51
NMAB1
NMAB[0..13]
NMCASB#
NMDB59
NDQMB0
NMAB9
NMDB38
NMDB36
NMDB14
NDQSB[0..7]
NMDB31
NDQSB4
NMDB20
NMAB0NMDB46
NMDB17
NMRASB#
NMDB39
NMAB12
NMCASB#NMWEB#
NMDB42
NDQSB6
NMDB60
NDQSB7
NMAB2NMDB4
NMDB48NMRASB#
NMAB8
NMCKEB
NMDB15
NMDB21
NMDB52
NMAB7
NMDB58
NMDB24
NMAB13
NMDB61
NMDB11
NMAB3
NMDB47
NDQMB6
NMDB18
NMDB27
NMCSB0#
NMDB0
NDQSB5
NMDB[0..63]
NMCLKB0# NMCLKB1#
NMCSB1# NMCSB1#
NMWEB#NMCSB0#
NMRASB#<19>
NMCLKB1#<19>
NMCKEB<19>
NMCSB0#<19>
NMCASB#<19>
NDQMB[0..7]<19>
NMCLKB0<19> NMCLKB1<19>
NDQSB[0..7]<19>
NMCLKB0#<19>
NMAB[0..13]<19>
NMWEB#<19>
NMDB[0..63]<19>
NMCSB1#<19>
+2.5VS
+2.5VS
+2.5VS
+2.5VS
+2.5VS
+2.5VS
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
VGA DDR FOR CHANNEL B
23 66Wednesday, September 24, 2003
Compal Electronics, Inc.
(25mil)
As close as ppossible to related pinAs close as ppossible to related pin
VGA DDR FOR CHANNELB
(25mil)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
C5390.1U_0402_10V6K
C63110P_0402_50V8K
C5370.01U_0402_16V7K
U30
K4D263238A-GC
C5290.1U_0402_10V6K
C5350.1U_0402_10V6K
R632
56.2_0402_1%
C53322U_1206_10V4Z
R494
1K_0603_1%
C5320.01U_0402_16V7K
C5380.1U_0402_10V6K
R62956.2_0402_1%
C63010P_0402_50V8K
U31
K4D263238A-GC
C5190.1U_0402_10V6K
C5200.1U_0402_10V6K
C52822U_1206_10V4Z
C5250.1U_0402_10V6K
R63056.2_0402_1%
C5340.1U_0402_10V6K
C5240.1U_0402_10V6K
C5220.01U_0402_16V7K
R497
1K_0603_1%
C5270.01U_0402_16V7K
R495
1K_0603_1%
C5300.1U_0402_10V6K
R631
56.2_0402_1%
R496
1K_0603_1%
C5310.01U_0402_16V7K
C52322U_1206_10V4Z
C5210.01U_0402_16V7K
C5260.01U_0402_16V7K
C5360.01U_0402_16V7K
C51822U_1206_10V4Z
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
CLK_BCLK#
MEM_66MCLK_48M
AGP_66M
FS3
+3V_VDD
CLK_BCLK
CLK_NB#
CLK_NB
VSSA
SMB_CK_DAT2SMB_CK_CLK2
CLK_IREF
PCI33/66#
FS1
FS2FS3
PCI33/66#
CLK_BCLK
CLK_BCLK#
AGP_EXT_66M
FS4
FS0
FS4
XTALIN_CLK
XTALOUT_CLK
24/48#
CLK_SD
FS2
CK_BCLK
CK_BCLK#
FS1FS0
CLK_NB_BCLK <11>
CLK_NB_BCLK# <11>
CK_BCLK <4>
CK_BCLK# <4>
CLK_SB_48M<27>CLK_MEM_66M <11>
CLK_ALINK_SB <26>
CK_ITP <5>
CK_ITP# <5>
CLK_SD_48M<31>
SMB_CK_DAT2<14,15,27>SMB_CK_CLK2<14,15,27>
CLK_AGP_66M <11>CLK_AGP_EXT_66M <17>
VTT_PWRGD<27,46,48>
CLK_14M_CODEC<37>CLK_SB_14M<27>
REFCLK1_NB<11>
CLK_LPC_48M<39>
BSEL0<5,13>
BSEL1<5,13>
CLK_14M_APIC<26>
+3VS
+3VS
+3V_CLK
+3V_CLK
+3VS
+3V_CLK
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
Clock Generator
24 66Wednesday, September 24, 2003
Compal Electronics, Inc.
Width=40 mils
133
0 0 0 1 0
PCI33/66# = HIGH
FS2 MEMFS1
200
FS3
200
A-LINK FREQ
Note: 0 = PULL LOW1 = PULL HIGH
66MHZ
PCI33/66# = LOW 33MHZ
CLOCK FREQUENCY SELECT TABLE
FS0
133
CPUFS4 With Spread Enabled…
0 0 0 0 1 *
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0 0 0 0 0 100 100
Spreaf OFF OR Center spread +/-0.3%
PIR BOM 92.09.01
PIR BOM 92.09.01
L12
CHB2012U121_0805
R224
4.7K_0402_5%
R196 49.9_0402_1%
R228
@10K_0402_5%
R202 49.9_0402_1%
R201 33_0402_1%
C127 10P_0402_50V8K
R213 33_0402_1%
R219
10K_0402_5%
C120
0.1U_0402_10V6K
R1068 @33_0402_1%
C124
0.1U_0402_10V6K
R996 68_0402_5%R215 33_0402_1%
R210 M9_M10@33_0402_1%
R1056 10K_0402_5%
R197 49.9_0402_1%
C130 10P_0402_50V8K
C125
0.1U_0402_10V6K
R221
@10K_0402_5%
R998
10K_0402_5%
C123
0.1U_0402_10V6K
R962 10K_0402_5%
C122
0.1U_0402_10V6K
U5
ICS951402AGT_TSSOP48
R226
10K_0402_5%
R209 33_0402_1%
R963
@1M_0402_5%
R997 33_0402_1%
R193 @0_0402_5%
R204 33_0402_1%
R227
10K_0402_5%
C118
10U_0805_6.3V6M
R223
10K_0402_5%
R195 33_0402_1%
R203 49.9_0402_1%
D83 RB751V_SOD323
C126
0.1U_0402_10V6K
R999
4.7K_0402_5%
Y2
14.318MHZ
C119
0.1U_0402_10V6K
R225
10K_0402_5%
R194 @0_0402_5%
R206 33_0402_1%
D84 RB751V_SOD323
R1111 10K_0402_5%
R220
@10K_0402_5%
R200 33_0402_1%
R218
475_0402_1%
L11
HB-1M2012-121JT03_0805
R205 33_0402_1%
C128
0.1U_0402_10V6K
R208 33_0402_1%
C121
0.1U_0402_10V6K
R222
@10K_0402_5%
C129
10U_0805_6.3V6M
R207 33_0402_1%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CRT_G
3VDDCCL
CRT_R
CRT_B
3VDDCDA
3VDDCCL
3VDDCDA
ENABLT#
DISPOFF#
CRTL_G
CRTL_B
CRTL_RM_SEN#
CRT_VCC
TXB1-
TXA1-TXB0+
TXACLK+
TXB2-
TXACLK-
TXB0-
LCDVDD_A
TXA2-
TXBCLK+
TXB1+
TXA0+
TXB2+TXBCLK-
TXA1+
TXA2+
TXA0-
TXB2+_NB
TXB0+_NB
TXBCLK+_NBTXBCLK-_NB
TXB1-_NB
TXB0-_NB
TXA2+_NB
TXB2-_NB
TXA0-_NB
TXB1+_NB
TXACLK-_NB
TXA2-_NB
TXA1+_NBTXA1-_NB
TXA0+_NB
TXACLK+_NB
DISPOFF#
DAC_BRIGINVT_PWMDISPOFF#
D D C _ C L KDDC_DAT
D D C _ C L KDDC_DAT
ENAVDD
LCDVDD_A
CRT_HSYNCRFL
CRT_VSYNCRFL
CRT_HSYNC
CRT_VSYNC
CRT_R<11,17>
CRT_G<11,17>
CRT_B<11,17>
3VDDCDA<11,17>
3VDDCCL<11,17>
ENABLT#<10,17>
BKOFF#<46>
ENAVDD<10,17,46>
M_SEN#<46>
M10_BKOFF#<17>
TXA1-<17>TXA1+<17>
TXA0-<17>
TXB0+ <17>
TXBCLK- <17>
TXA2+<17>
TXB1+<17>TXB1-<17>
TXBCLK+ <17>
TXA2-<17>
TXB2+<17>TXB2-<17>
TXA0+<17>
TXB0- <17>
TXACLK-<17>TXACLK+<17>
TXA0+_NB<11>
TXA2-_NB<11>
TXB1-_NB<11>
TXA1-_NB<11>
TXB1+_NB<11>
TXACLK-_NB<11>
TXB0-_NB <11>
TXBCLK-_NB <11>
TXA2+_NB<11>
TXB2-_NB<11>TXBCLK+_NB <11>
TXB0+_NB <11>
TXB2+_NB<11>
TXACLK+_NB<11>
TXA0-_NB<11>
TXA1+_NB<11>
INVT_PWM <46>DAC_BRIG <46>
DDC_DAT <10,17>D D C _ C L K <10,17>
CRT_HSYNC<11,17>
CRT_VSYNC<11,17>
+3VS
+3VS
R_CRT_VCC+5VS CRT_VCC
INVPWR_B+
+12VALW+5VS
+3VS
LCDVDD
+12VALW
LCDVDD
+3VS+12VALW
B+
+5VS
LCDVDD
INVPWR_B+
INVPWR_B+
+3VS
+3VS
+3VS
+3VS
CRT_VCC
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
LCD,CRT,TV-OUT & Inverter BD CONN.
Custom25 66Wednesday, September 24, 2003
Compal Electronics, Inc.
LCD CONN
CRT CONNECTOR
SI2302DS: N CHANNELVGS: 4.5V, RDS: 85 mOHMVGS: 2.5V, RDS: 115mOHMId(MAX): 2.8AVGS(MAX): +-8V
SI2301DS: P CHANNELVGS: -4.5V, RDS: 130 mOHMVGS: -2.5V, RDS: 190mOHMId(MAX): 2.3AVGS(MAX): +-8V
TFT LCD CONN.
TFT LCD CONN.
AT LEAST 60 MIL
AT LEAST 60 MIL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR BOM & LAYOUT 92.09.01
D43
DAN217_SOT23
C117
220P_0402_25V8K
R1013
M9@10K_5%
C108
10P_0402_50V8K
C890.047U_0402_16V4Z
G
D
S
Q8
M9@2N7002 1N_SOT23
R185
75_0402_5%
D21DAN217_SOT23
G
D S
Q13
2N7002 1N_SOT23
C101
10P_0402_50V8K
R191
4.7K_0402_5%
C87
0.1U_0402_10V6K C90
0.1U_0402_10V6K
D23DAN217_SOT23
G
D S
Q14
2N7002 1N_SOT23
C618
10U_0805_10V3M
F1
FUSE_1A
C107
220P_0402_25V8K
R115320_0402_5%
R187
75_0402_5%
L5 FCM2012C-800_0805
R175
100K_0402_5%
C620
0.01U_0402_50V7K
R1007
2.2K_0402_5%
C116
220P_0402_25V8K
D16 RB751V_SOD323
D17
RB411D_SOT23
R182100K_0402_5%
L9
FBM-L10-160808-300LM-T
C91
4.7U_0805_10V4Z
R1118
4.7K_0402_5%
G
D
SQ10
2N7002_SOT23
JP6
SUYIN_7849S-15G2T-HC
C100
10P_0402_50V8K
R180
1K_0402_1%
L6 FCM2012C-800_0805
C102
10P_0402_50V8K
C993
27P_0402_50V8J
C104
22P_0402_25V8K
G
D
SQ112N7002_SOT23
C619
1000P_0402_50V8J
R115420_0402_5%
U5874AHCT1G125GW
R192
4.7K_0402_5%
C970.1U_0402_10V6K
C864.7U_0805_10V4Z
C109
10P_0402_50V8K
R1008
2.2K_0402_5%
R1117
4.7K_0402_5%
R174
4.7K_0402_5%
R181
150K_0402_5%
D22DAN217_SOT23
L2
KC FBM-L11-201209-221LMAT_0805
L41
KC FBM-L11-201209-221LMAT_0805
R186
75_0402_5%
C103
22P_0402_25V8K
C994
27P_0402_50V8J
L10
FBM-L10-160808-300LM-T
D42
DAN217_SOT23
U57 74AHCT1G125GW
C105
22P_0402_25V8K
G
D
S Q9SI2302DS 1N_SOT23
L3 FCM2012C-800_0805
22K
22K Q12
DTC124EK_SOT23
JP27
M9-M10@JST BM40B-SRDS
C88
0.1U_0402_10V6K
D41 M10@RB751V_SOD323
R1115
2.2K_0402_5%
JP28
NAGP@JST BM40B-SRDS
R1150
1K_0402
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
A_AD[0..31]
A_CBE#[0..3]
PCI_FRAME#
PCI_PAR
PCI_SERR#
PCI_TRDY#PCI_DEVSEL#PCI_STOP#
PCI_IRDY#
PCI_PERR#
PCI_PIRQD#PCI_PIRQC#PCI_PIRQB#PCI_PIRQA#
PCI_REQ#3
PCI_GNT#2
PCI_REQ#1
PCI_GNT#4
PCI_GNT#0
PCI_REQ#4
PCI_GNT#1
PCI_REQ#0
PCI_REQ#2
PCI_GNT#3
LPC_AD3LPC_AD2LPC_AD1
LPC_DRQ#0
LPC_AD0
CLK_ALINK_SB
H_CPUSLP#
H_SMI#
H_A20M#
H_INTR
H_IGNNE#
H_NMI
H_STPCLK#
H_NMI
H_INTR
LPC_FRAME#
LPC_DRQ#1
SIRQ
PCI_CLKRUN#
H_INIT#
H_INIT#
PCI_RST#
NBRST# NB_RST#
CPURSTIN#
OVCUR#5
H_A20M#
A_SERR#
SBCLK_STP#
CLK_14M_APIC
PCI_CLK_R
PCI_AD4
PCI_USB20
PCI_CBE#3
A_SBREQ#
A_CBE#0
A_AD19
LPC_DRQ#1
PCI_AD25
PCI_AD21
PCI_AD16
PCI_AD12
PCI_AD0
LPC_FRAME#
PCI_CBE#2
PCI_MINI
PCI_PIRQC#
A_OFF#
A_AD29
A_AD21
A_AD5
H_CPUFERR#
PCI_AD26
H_A20M#
RTCX2
A_CBE#2
A_AD30
A_AD8
A_AD0
GPIO0
PCI_REQ#4
PCI_AD31
PCI_AD20
PCI_AD13
PCI_AD10
PCI_AD5
LPC_AD1
PCI_IRDY#
H_CPUFERR#
A_ACAT#
A_AD26
PCI_AD17
PCI_LAN
SBCLK_STP#
A_AD16
RTCX2
PCI_AD18
PCI_AD8PCI_AD7
PCI_AD2
PCI_SIO
A_PAR
A_AD22
A_AD14
PCI_GNT#4
PCI_AD24
PCI_GNT#2
PCI_REQ#2
SB_APIC_D0OVCUR#5
A_STROBE#
A_AD28
NBRST#
CLK_ALINK_SB
PCI_AD28
PCI_AD15
PCI_AD9
SIRQ
LPC_AD3LPC_AD2
PCI_PERR#
PCI_CBE#1
PCI_PIRQA#
A_AD25
PCI_AD3
LPC_AD0
PCI_PCM
A_AD18
PCI_AD22
LPC_DRQ#0
PCI_STOP#
PCI_CBE#0
PCI_1394
PCICLK_STP#
A_DEVSEL#
A_AD20
A_AD13A_AD12
RTCX1
PCI_AD19
PCI_GNT#1
PCI_AD11
PCI_GNT#3
A_AD15
PCI_AD27
PCI_FRAME#
RTCX1
A_SERR#
A_AD27
A_AD17
PCI_AD[0..31]
PCIRST#
PCI_AD1
PCI_DEVSEL#
A_END#
A_AD23
A_AD9
A_AD7
A_AD1
PCI_CBE#[0..3]PCI_AD30
PCI_AD6
PCI_EC
PCI_GNT#0
PCI_REQ#3
PCI_TRDY#
OVCUR#4
A_CBE#1
A_AD31
A_AD10
A_AD2
PCI_AD23
PCI_REQ#1
SB_APIC_D1
CPURSTIN#
A_SBGNT#
A_CBE#3
A_AD11
PCI_AD29
PCI_AD14
PCI_CLKRUN#
PCI_SERR#PCI_REQ#0
PCI_PAR
PCI_PIRQD#
A_AD24
A_AD6
A_AD3
GPIO2
A_AD4PCI_CLK_FB
PCIRST#
PCI_PIRQB#
GPIO1
OVCUR#4
GPIO0
GPIO2
A_SBREQ#<10>
A_AD[0..31]<10,13>
A_CBE#[0..3]<10,13>
A_STROBE#<10>
A_SBGNT#<10>
A_DEVSEL#<10>A_ACAT#<10>A_END#<10>
A_PAR<10,13>
PCI_PIRQA#<10,17,31,35,36>
H_STPCLK#<5>
H_PWRGOOD<5>
H_A20M#<5>H_IGNNE#<5>
H_INIT#<5>
PCI_CBE#[0..3] <31,34,35,36,43>
PCI_AD[0..31] <29,31,34,35,36,43>
H_INTR<5>
H_FERR#<5>
PCI_RST# <11,30,31,34,35,36,43,46>
NB_RST# <8,17,39>
DPRSLPVR<56>
H_RESET#<5,8>
PCI_PIRQC#<36,43>PCI_PIRQD#<34,36>
CLK_PCI_1394 <35>
CLK_PCI_SIO <39>CLK_PCI_EC <46>CLK_PCI_MINI <43>CLK_PCI_PCM <31>CLK_PCI_LAN <34>
CLK_PCI_USB20 <36>
CLK_14M_APIC<24>
CPUCLK_STP#<5,11,56>
PCI_GNT#2 <31>PCI_GNT#1 <34>
PCI_PERR# <31,34,35,36,43>
LPC_AD0 <39,46>
PCI_GNT#4 <36,43>
PCI_REQ#0 <35>
LPC_DRQ#1 <39>
LPC_AD2 <39,46>
PCI_PIRQB#<31>
CLK_ALINK_SB<24>
PCI_REQ#2 <31>
H_NMI<5>
PCI_SERR# <31,34,35,36,43>
PCI_STOP# <31,34,35,36,43>
LPC_FRAME# <39,46>
PCI_REQ#4 <36,43>
H_SMI#<5>LPC_AD1 <39,46>
PCI_GNT#0 <35>
PCI_FRAME# <31,34,35,36,43>
PCI_CLKRUN# <31,34,35,36,43>
PCI_DEVSEL# <31,34,35,36,43>
H_CPUSLP#<5>
PCI_GNT#3 <36,43>
SIRQ <31,39,46>
PCI_IRDY# <31,34,35,36,43>
PCI_REQ#1 <34>
A_OFF#<10>
PCI_PAR <31,34,35,36,43>PCI_TRDY# <31,34,35,36,43>
LPC_AD3 <39,46>
PCI_REQ#3 <36,43>
H_PROCHOT# <5,51>
CHGRTC
+VCC_CORE
+RTCVCC
BATT1.1
+3VS
+3VS
+3V
+3VALW +3VALW
+3VALW
+VCC_CORE
+VCC_CORE
+3VS
+3VS
+3VS
+RTCVCC
+3VS
Title
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
SB200M(1/4)- PCI/CPU/LPC
26 66Wednesday, September 24, 2003
Compal Electronics, Inc.
+
W=15mils
No short
-
Layout note:Trace length of PCI_CLK_R + PCI_CLK_FB shouldbe less than 200 mils.
W=20mils
PULL DOWN FOR S3
PLACE CLOSE TO CPU SOCKET
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
W=20mils
PIR BOM 92.09.01
RP17
8.2K _8P4R_0804_5%
R1066 @300_0402_1%
R152 200_0402_5%
R124 39_0402_5%
R1155 10K_0402_5%
R1156 10K_0402_5%
R154 200_0402_5%
C973@15P_0402_50V8J
D93RB751V_SOD323
C872
0.1U_0402_10V6K
Y1
32.768KHZ_12.5P_MC-306
U45F
SN74LVC14APWLE_TSSOP14
RP13810K_0804_8P4R_5%
R126 39_0402_5%
R1067 1K_0402_1%
R150 200_0402_5%
R1151
10K_0402_5%
R125 8.2K_0402_5%
R1000
470_0402_5%
C76 @22P_0402_50V8J
R138
8.2K_0402_5%
R168
1K_0402_5%
R1059 10K_0402_5%
R40
1K_0402_5%
R149 200_0402_5%
Q5 MMBT3904_SOT23
R1143@10_0402_5%
C82
12P_0402_50V8K
C78 180P_0603_50V8J
RP14
8.2K _8P4R_0804_5%
R132
470_0402_5%
R171
20M_0603_5%
R131330_0402_5%
RP15
8.2K _8P4R_0804_5%
R127 39_0402_5%
G
D
S
Q118@2N7002_SOT23
U 4 5 E
SN74LVC14APWLE_TSSOP14
R134
@10_0402_5%
R1157 10K_0402_5%
Q98 @MMBT3904_SOT23
RP18
8.2K _8P4R_0804_5%
R128 39_0402_5%
RP21
100K_1206_8P4R_5%
R130 39_0402_5%
R145
@4.7K_0402_5%
U45D
SN74LVC14APWLE_TSSOP14
R146 4.7K_0402_5%
C79 180P_0603_50V8J
R172
20M_0603_5%
C617 180P_0603_50V8J
R122 39_0402_5%
R921
4.7K_0402_5%
C80
1U_0603_10V6K
R137
8.2K_0402_5%
R169
330_0402_5%
R1064 10K_0402_5%
C77
@15P_0402_50V8J
R1002 47K_0402_5%
R158 200_0402_5%
C81
12P_0402_50V8K
R946 8.2K_0402_5%
C956 180P_0603_50V8J
R1021 39_0402_5%
R153 200_0402_5%
RP16
8.2K _8P4R_0804_5%
R156 200_0402_5%
JOPEN1
R123 39_0402_5%
R151 200_0402_5%
R966
10K_0402_5%
A-LI
NK IN
TERF
ACE
Part 1 of 3SB200 SB
PCI IN
TERF
ACE
LPC
RT
CCP
UXT
AL
PCI C
LKS
U 3 A
South bridge SB200
U 4 5 B
SN74LVC14APWLE_TSSOP14
R100147K_0402_5%
BATT1
RTCBATT
R1065 10K_0402_5%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LPC_SMI#
AC97_SDOUT_R
AC97_RST#
AC97_SDIN0
CLK_SB_48M
AC97_BITCLK
AC97_SYNC_R
LPC_PME#SB_AC_IN
SB_SCI#
USB_RCOMP
SUS_STAT#
SB_EC_SMI#
SB_TEST1
SB_PM_BATLOW#
SB_PWRGD
SLP_S5#SLP_S3#
PWRBTN_OUT#
SB_TEST0
SB_LID_OUT#
OVCUR#1
OVCUR#1
USB20P5-
PWR_STRP
AC97_SDIN1AC97_SDIN0
AC97_RST#
PCI_ACT_REQ#
SB_EC_SWI#
SB_GA20SB_KBRST#
LPC_SMI#
LPC_PME#
IDESAA0IDESAA1IDESAA2
IDEIORDYAIDEIRQA
IDEDA7
IDEDA13
IDEDA9
IDEDA0IDEDA1
IDEDA15IDEDA14
IDEDA8
IDEDA4IDEDA5IDEDA6
IDEDA12
IDEDA10IDEDA11
IDEDA2IDEDA3
IDEDACK#AIDEREQAIDEIOR#AIDEIOW#AIDECS#A1IDECS#A3
IDEREQBIDEDACK#B
IDESAB1
IDEIRQBIDEIORDYB
IDESAB0
IDEIOR#B
IDECS#B3
IDEIOW#BIDECS#B1
IDESAB2
IDEDB0IDEDB1IDEDB2IDEDB3
IDEDB7
IDEDB4IDEDB5IDEDB6
IDEDB11
IDEDB8IDEDB9IDEDB10
IDEDB15
IDEDB12IDEDB13IDEDB14
AC97_SDOUT
AC97_SDIN1
SB_SPKR
AC97_SDIN2AC97_SYNC
AC97_SDIN2
USB20P3-
USB20P0-
IDERSTHD#
CLK_SB_14M
EC_RSMRST#
32KHZ_S5_OUT
MII_TXD3MII_TXD2MII_TXD1MII_TXD0
MII_TXEN
SB_EEDOSB_EECLK
SPDIF_OUT
SMB_CK_CLK2_SBSMB_CK_DAT2SMB_CK_CLK2
SMB_CK_DAT2_SB
CLK_SB_48M
AC97_BITCLK
IDERSTCD#
SB_SCI#
SB_LID_OUT#SB_EC_THERM#SB_PM_BATLOW#
AGP_BUSY#_RAGP_STP#_R
USB20P5+
SB_AC_IN
SB_EC_SMI#SB_EC_SWI#
SB_EC_THERM#
SB_KBRST#
SB_GA20
SUS_STAT#
PCI_ACT_REQ#
SLP_S3#PWRBTN_OUT#
SLP_S5#
AGP_STP#_R
VGATE
CLK_SB_14M
G H I
AGP_BUSY#AGP_BUSY#_R
AGP_BUSY#_R
USB20P0+USB20P1-USB20P1+
USB20P0-
USB20P1-
USB20P0+
SB_PM_BATLOW#
SB_EC_THERM#
SB_EC_SWI#
PM_BATLOW#
EC_THERM#
EC_SWI#
ACINSB_AC_IN
SB_KBRST#
SB_GA20 GA20
KBRST#
EC_SMI#
LID_OUT#SB_LID_OUT#
SB_EC_SMI#
SB_SCI# SCI#
IDERSTHD#
IDERSTCD#
AGP_STP#
SB_TEST0SB_TEST1
AGP_BUSY#AGP_STP#
LPC_SMI# USB_SMI#
USB20P4-
USB20P2+
USB20P2-
USB20P1+
USB20P3+
USB20P4+
SMB_CK_DAT2SMB_CK_CLK2_SBSMB_CK_DAT2_SB
SMB_CK_CLK2
EC_FLASH#
IDERST_HD#
IDERST_CD#
G H I
USB20P3-
USB20P2-USB20P3+
USB20P2+
USB20P5+USB20P5-
USB20P4+USB20P4-
AC97_BITCLK
SLP_S5# <46>SLP_S3# <46>
PWRBTN_OUT# <46>SB_PWRGD <48>
SUS_STAT# <8>
AC97_SYNC <29,37,44>AC97_RST# <37,44>
AC97_BITCLK <37,44>
AC97_SDIN1 <44>
AC97_SDOUT <29,37,44>AC97_SDIN0 <37>
SB_SPKR<37>
CLK_SB_48M<24>
USB20P5-<44>
USB20P5+<44>
CLK_SB_14M<24>
EC_RSMRST#<46>
OVCUR#0<44>
32KHZ_S5_OUT<29>
SB_EEDO<29>
SPDIF_OUT <29,37>
MII_TXD1<29>
SB_EECLK<29>
MII_TXEN<29>
MII_TXD2<29>
MII_TXD0<29>
MII_TXD3<29>
EC_FLASH#<47>
IDEIOR#A <30>
IDESAA0 <30>IDEIRQA <30>
IDECS#A1 <30>
IDEDACK#A <30>
IDEIORDYA <30>
IDESAA1 <30>IDESAA2 <30>
IDECS#A3 <30>
IDEREQA <30>
IDEIOW#A <30>
IDESAB2 <30>
IDEREQB <30>
IDECS#B3 <30>IDECS#B1 <30>
IDEIOR#B <30>IDEIOW#B <30>
IDESAB1 <30>
IDEIORDYB <30>IDEIRQB <30>IDESAB0 <30>
IDEDACK#B <30>
IDEDB[0..15] <30>
IDEDA[0..15] <30>
OVCUR#1<44>
AGP_BUSY# <10,17>
IDERST_CD#<30>
IDERST_HD#<30>
AGP_STP#<10,17>
VTT_PWRGD <24,46,48>
USB_SMI# <36>
EC_THERM# <46>
PM_BATLOW# <46>
EC_SWI# <46>
GA20 <46>
KBRST# <46>
ACIN <46,50,53>
EC_SMI# <46>
SCI# <46>
LID_OUT# <46>
USB20P0+<44>
USB20P0-<44>
USB20P2-<44>
USB20P2+<44>
USB20P3-<44>
USB20P4-<41>
USB20P4+<41>
USB20P3+<44>
USB20P1-<44>
USB20P1+<44> PWR_STRP <29>
CPU_GHI#<5>
SMB_CK_CLK2 <14,15,24>SMB_CK_DAT2 <14,15,24>
+3VS
+2.5V
+3V
+3V
+3VALW
+3VS
+3VS
+3VS
+5VS
+3V
Title
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
SB200M(2/4) - IDE/USB/MII
27 66Wednesday, September 24, 2003
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Note: Place close to U3 (ATI SB)For ATI USB2.0 only .
L
PIR BOM 92.09.02
R952@10K_0402_5%
R120 10K_0402_5%
RP107
10K_0804_8P4R_5%
RP12 2.2K_0804_8P4R_5%
RP108
10K_0804_8P4R_5%
R951 10K_0402_5%
R71
@10_0402_5%
RP13 8.2K _8P4R_0804_5%
R68 10K_0402_5%
D7 RB751V_SOD323
D77RB751V_SOD323
D4 RB751V_SOD323
D6 RB751V_SOD323C73
@15P_0402_50V8J
R6312.4K_0603_1%
D11 RB751V_SOD323
R950 10K_0402_5%
RP11 10K_0804_8P4R_5%
R948 10K_0402_5%
G
D S
Q89 2N7002 1N_SOT23
D9 RB751V_SOD323
RP112
15K_1206_8P4R_5%
RP109
10K_0804_8P4R_5%
SECO
NDAR
Y AT
A 66
/100
PR
IMA
RY
ATA
66/
100
ACPI
/ WAK
E UP
EVE
NTS
Part 2 of 3SB200 SB
AC97
USB
INTE
RFAC
EET
HERN
ET M
IIEE
PROM
CLK
/ RST
GPIO
GPIO
_XTR
A
U 3 B
South bridge SB200
R1176 8.2K_0402_5%
D3 RB751V_SOD323
D8 RB751V_SOD323
D10 RB751V_SOD323
RP110
10K_0804_8P4R_5%
R92
@10_0402_5%
R117 33_0402_5%
R1003
33_0402_5%
D13 RB751V_SOD323
R119 33_0402_5%
D14 RB751V_SOD323
R112 100K_0402_5%
R1062 0_0603_5%
R934 1K_0603_5%
R947 10K_0402_5%
C74
@15P_0402_50V8J
RP111
15K_1206_8P4R_5%
R111 8.2K_0402_5%
D2 RB751V_SOD323
RP113
15K_1206_8P4R_5%
R121 10K_0402_5%
D5 RB751V_SOD323
R64
@10_0402_5%
R69 4.7K_0402_5%
RP140 8.2K _8P4R_0804_5%
C75
@15P_0402_50V8J
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+3VS +3VS
+2.5VS
+2.5V
+3V
+2.5VS
+2.5VALW
+3VALW
+2.5VS
+3V_AVDDUSB
+3V_AVDDUSB
+3V_AVDDC
+3V_AVDDC
+2.5V_AVDDCK
+2.5VS
+2.5V_AVDDCK
+3V
+3V
+3V
+2.5V
+3VS
+2.5VS
+3V
+3V_AVDDUSB
+3V_AVDDC
+2.5V_AVDDCK
+2.5V
+5VS
+3VS
Title
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
SB200M(3/4) - PWR
28 66Wednesday, September 24, 2003
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI request
ATI request
ATI request
ATI request
ATI request
ATI request
ATI requestCLOSE TOL6,H6,J6
PIR BOM 92.09.01
PIR BOM 92.09.01
PIR BOM 92.09.01
PIR BOM 92.09.01
PIR BOM 92.09.01
PIR BOM 92.09.01
PIR BOM 92.09.01
C35
0.1U_0402_10V6K
C887
@10U_0805_10V6K
C34
0.1U_0402_10V6K
C46
0.1U_0402_10V6K
+C888
@47U_B_6.3VM
C24
22U_1206_16V4Z_V1
R1114
0_0402_5%
C27
0.1U_0402_10V6K
C66
0.1U_0402_10V6K
C63
0.1U_0402_10V6K
C64
0.1U_0402_10V6K
C51
0.1U_0402_10V6K
C982
0.01U_0402_16V7Z
C49
22U_1206_16V4Z_V1
C53
0.1U_0402_10V6K
C877
0.1U_0402_16V7Z
R62 0_0805_5%
Part 3 of 3SB200 SB
PO
WE
R
U 3 C
South bridge SB200
C40
22U_1206_16V4Z_V1
C69
0.1U_0402_10V6K
C47
0.1U_0402_10V6K
C983
1000P_0402_16V7K
C67
0.1U_0402_10V6K
C59
1U_0603_10V6K
C30
0.1U_0402_10V6K
C882
@0.1U_0402_16V7K
C55
0.1U_0402_10V6K
C32
0.1U_0402_10V6K
C980
0.01U_0402_16V7Z
C878
0.1U_0402_16V7Z
C62
22U_1206_16V4Z_V1
C28
0.1U_0402_10V6K
C72
0.1U_0402_10V6K
C880
0.1U_0402_16V7Z
C874
0.1U_0402_16V7Z
C65
0.1U_0402_10V6K
C39
0.1U_0402_10V6K
C70
0.1U_0402_10V6K
C981
1000P_0402_16V7K
C29
0.1U_0402_10V6K
C883
@0.1U_0402_16V7K
C42
0.1U_0402_10V6K
C58
0.1U_0402_10V6K
C48
0.1U_0402_10V6K
C57
0.1U_0402_10V6K
C44
0.1U_0402_10V6K
C843
1U_0603_10V6K
C886
0.1U_0402_16V7K
C876
0.1U_0402_16V7Z
C881
0.1U_0402_16V7Z
C36
0.1U_0402_10V6K
C885
0.1U_0402_16V7K
C25
0.1U_0402_10V6K
C873
0.1U_0402_16V7Z
C60
0.1U_0402_10V6K
C43
0.1U_0402_10V6K
C68
0.1U_0402_10V6K
C37
0.1U_0402_10V6K
C966
0.1U_0402_16V7K
D90
RB751V_SOD323
C56
0.1U_0402_10V6K
R61 0_0805_5%
C879
0.1U_0402_16V7Z
C26
0.1U_0402_10V6K
C71
1U_0603_10V6K
R60 0_0805_5%
C50
0.1U_0402_10V6K
C875
0.1U_0402_16V7Z
C45
0.1U_0402_10V6K
C41
0.1U_0402_10V6K
C2322U_1206_16V4Z_V1
C889
@22U_1206_16V4Z_V1
C31
0.1U_0402_10V6K
C54
22U_1206_16V4Z_V1
C52
0.1U_0402_10V6K
C33
0.1U_0402_10V6K
C38
0.1U_0402_10V6K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PWR_STRP<27>SB_EEDO<27>
SB_EECLK<27>AC97_SYNC<27,37,44>
AC97_SDOUT<27,37,44>SPDIF_OUT<27,37>
MII_TXEN<27>MII_TXD3<27>MII_TXD2<27>MII_TXD1<27>MII_TXD0<27>
32KHZ_S5_OUT<27>
PCI_AD26<26,31,34,35,36,43>
+3VS+3VALW +3V +3V +3VS +3VS +3V +3V +3V +3V +3V +3VALW
+3VS
Title
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
SB200M(4/4) - STRAPS
29 66Wednesday, September 24, 2003
Compal Electronics, Inc.
SIO 24MHzUSEDEBUGSTRAPS
CPU_STP#
STRAPHIGH
ROM ONLPCBUS
ROM ONPCI BUS
D E F A U L T
INIT ACTIVEHIGH
D E F A U L T
PROCESSOR FREQ MULTIPLIER
SIO 48MHzAUTOPWRON
ETHERNET TXD[3:0]AC_SDOUT SPDIF_OUTPWR_STRP
ENABLESPEEDSTEP
DISABLESPEEDSTEP
D E F A U L T
REQUIRED SYSTEM STRAPS AC_SYNC
INIT ACTIVELOW (PIII)
33MHz NBBUS
EEDO
D E F A U L T
D E F A U L T D E F A U L T
EECK
HI SPEEDA-LINKSTRAP
LOW
IGNOREDEBUGSTRAPS
D E F A U L T
DISABLECPU FREQSETTING
ENABLE CPUFREQSETTING
TX_ENIGN DEBUG SPEEDSTEP FREQLTCH
MANUALPWR ON
D E F A U L T
32KHZ_S5
32KHZOUTPUTFROM SB200(INT RTC)
32KHZ INPUTTO SB200(EXT RTC)
D E F A U L T
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
R967
10K_0402_5%
R42
10K_0402_5%
R48
10K_0402_5%
R37
@10K_0402_5%
R44
10K_0402_5%
R35
@10K_0402_5%
R39
@10K_0402_5%
R59
@10K_0402_5%
R45
10K_0402_5%
R57
@10K_0402_5%
R41
10K_0402_5%
R54
@10K_0402_5%
R50
10K_0402_5%
R51
10K_0402_5%
R58
@10K_0402_5%
R46
10K_0402_5%
R953
@10K_0402_5%
R43
10K_0402_5%
R52
10K_0402_5%
R55
@10K_0402_5%
R34
10K_0402_5%
R36
@10K_0402_5%
R38
@10K_0402_5%
R56
@10K_0402_5%
R47
@10K_0402_5%
R49
10K_0402_5%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SD_D15
IDEDA[0..15]
PD_A2
SD_SBA2
SD_SIOW#
PD_IRQA
PD_DACK#
SD_D1
PD_A1
PD_CS#3IDESAA2
SD_D2
PD_IOR#
SD_DACK#
PD_A0
SD_SBA1
SD_SIOR#
SD_SBA0
PD_IOW#
SD_SCS3#
SD_DREQ
SD_D4
IDESAB1
SD_D14
SD_D12
PD_DREQ#
IDESAB0
SD_D3
SD_D11
SD_D9
SD_IDERST#
SD_D0
HD_IDERST#
SD_D13
IDECS#A3
SD_D5
SD_D8SD_D7
SD_D10SD_D6
IDESAA0IDESAA1
HDD_LED#
CDLED#
PD_D4PD_D5
PD_A2
PD_D12
PD_A0PD_A1
PD_D14
HDD_LED#
PD_D11
PCSEL
HD_IDERST#
PD_IOR#
PD_DACK#
PD_D3
PD_IOW#
PD_D9
PD_D1
PD_D6
PD_D2
PD_DREQ#
PD_CS#3
PD_D15
PD_D13
PD_CS#1
PD_D10
PD_D8
PD_IRQA
PD_IORDY
PD_D7
PD_D0
SD_DREQ
CDROM_L
SD_D9
SD_SIOW#
SD_D4
CDLED#
SD_IDERST#
SD_DACK#
SD_SBA2
SD_D11
SD_D3
SD_CSEL
SD_D8
SD_D2
SD_D6
SD_SIORDY
SD_D0
SD_IRQ15
SD_D12
SD_SCS3#SD_SCS1#
SD_D1SD_D14SD_D15
SD_D7
SD_SBA1
CD_AGND
SD_D13
SD_D10
SD_SIOR#
CDROM_R
SD_DREQ
SD_SBA0
SD_D5
IDEDB[0..15]
IDEDB0
IDEDB10
IDEDB7
IDEDB2
IDEDB3
IDEDB5
IDEDB1IDEDB14
IDEDB11
IDEDB13
IDEDB15
IDEDB6
IDEDB9
IDEDB8
IDEDB12
IDEDB4
PD_D14PD_D1
PD_D0PD_D15
IDEDA6IDEDA9
IDEDA8IDEDA7
PD_D9
PD_D8PD_D6
PD_D7
IDEDA3IDEDA12
IDEDA2IDEDA13
PD_D3PD_D12
PD_D2PD_D13
PD_IORDY
SD_SIORDY
SD_SCS1#
PD_CS#1
SD_IRQ15
IDEDA10
IDEDA14
IDEDA4IDEDA11
IDEDA1
IDEDA0
IDEDA5
IDEDA15
PD_D11PD_D10PD_D5
PD_D4
IDECS#A3<27>
IDEIOW#A<27>
IDEIRQA<27>
IDEREQA<27>
IDEDA[0..15]<27>
IDEDACK#A<27>
PCI_RST#<11,26,31,34,35,36,43,46>
IDERST_CD#<27>
IDERST_HD#<27>
IDEIOR#A<27>
IDESAA0<27>IDESAA1<27>IDESAA2<27>
ACT_LED# <45>
CD_AGND <37>
CDROM_R <37>CDROM_L<37>
IDECS#B3<27>
IDESAB0<27>
IDESAB2<27>
IDEIRQB<27>
IDEIOW#B<27>IDEIOR#B<27>
IDESAB1<27>
IDEREQB<27>
IDEDACK#B<27>
IDEDB[0..15]<27>
IDEIORDYA<27>
IDEIORDYB<27>
IDECS#B1<27>
IDECS#A1<27>
+5VS
+5VS
+5VS+5VS
+5VS
+5VS
+5VS
+5VS
+5VS+5VS
+5VS
+5VS +5VS+5VS
+5VS+5VS
+3VS
+3VS
+5VS
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
HDD & CDROM Connector
30 66Wednesday, September 24, 2003
Compal Electronics, Inc.+5VCD trace to CONN W=100mils
W=100mils
HDD/CD-ROM Module
Placea caps. near CDROM CONN.
W=100mils
+5VCD trace to CONN W=100milsPlacea caps. near CDROM CONN.
Placea caps. near HDD CONN.
W=80mils
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
R970 33_0402_5%
C5
0.1U_0402_10V6K
C12@47P_0402_25V8K
C2
10U_0805_16V4Z
R26 33_0603_1%
C17
1000P_0402_50V7K
U 1 C
74HCT08PW_TSSOP14
RP3 33_0804_8P4R_5%
R613 @100K_0402_5%
C84.7U_0805_10V4Z
U 1 B
74HCT08PW_TSSOP14
R9 470_0402_5%RP4 33_0804_8P4R_5%
RP9 33_0804_8P4R_5%
R31 33_0603_1%
U 1 A
74HCT08PW_TSSOP14
R310K_0402_5%
C19
1U_0603_10V6K
RP7 33_0804_8P4R_5%
R338.2K_0402_5%
JP1
SUYIN_200006FA044S503ZU
R15
10K_0402_5%
C3
10U_0805_16V4Z
R32
5.6K_0402_5%
RP124 33_0804_8P4R_5%
R614470_0402_5%
RP1 33_0804_8P4R_5%
C18
10U_0805_16V4Z
R1110 @10K_0402_5%
C21
1000P_0402_50V7K
JP2
CD-ROM CONN.
C20
0.1U_0402_10V6K
RP8 33_0804_8P4R_5%
R24
10K_0402_5%
C14
10U_0805_16V4Z
C11 @10U_0805_6.3V6M
RP2 33_0804_8P4R_5%
RP10 33_0804_8P4R_5%
R18 33_0603_1%
R25
4.7K_0402_5%
R969 33_0402_5%
U 1 D
74HCT08PW_TSSOP14
R11 33_0603_1%
C2233P_0402_25V8K
C1
1000P_0402_50V7K
C15
1U_0603_10V6K
RP5 33_0804_8P4R_5%
R84.7K_0402_5%
R9688.2K_0402_5%
C6
4.7U_0805_10V4Z
RP125 33_0804_8P4R_5%
C91U_0603_25V4Z
R19
5.6K_0402_5%
R4 33_0402_5%
C4
1U_0603_10V6K
RP6 33_8P4R_0804_5%
C16
0.1U_0402_10V6K
R61110K_0402_5%
C7
1U_0603_25V4Z
C610 0.1U_0402_10V6K
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
S2_D[0..15]
S2_A[0..25]
S1_A[0..25]
S1_D[0..15]
PCI_AD[0..31]
PCI_CBE#[0..3]
S1_A21
S1_A7
S2_D7
S2_A4
S1_A18
S1_A10
PC
I_C
BE
#0
PCI_
AD3
PC
I_A
D16
PC
I_A
D19
PC
I_A
D23
S2_D15
S2_A20
S2_A12
S1_D8
PC
I_A
D24
S2_D12
S2_D2
S1_D12
S1_D2
S1_A19
S1_A4
PC
I_C
BE
#3
PCI_
AD0
PC
I_A
D10
PC
I_A
D28
S2_A8
S1_A1
PCI_
AD1
PC
I_A
D11
S2_D0
S2_A15
S2_A23
S1_A9
S1_A17
S1_A24
S1_A2
PCI_
AD2
PC
I_A
D15
PC
I_A
D31
S2_D10
S2_A10
S2_A3S2_A2
PC
I_A
D20
_R
S1_D7
S1_A11
PCI_
AD6
PC
I_A
D22
S2_D11
S2_D1
S2_A19
S2_A11
S1_D11
S1_D1
S1_A13
PC
I_C
BE
#2
PCI_
AD9
PC
I_A
D27
PC
I_A
D30
S2_D5
S2_A6
S1_D15
S2_A7
S1_D6
S1_D0
S1_A16S1_A15
S1_A23
PC
I_A
D14
S2_D9
S2_A14
S2_A22
S1_A5
S1_A3
PCI_
AD5
PC
I_A
D12
PC
I_A
D18
PC
I_A
D21
S2_D14
S2_A9
S2_A1
S1_D10
PC
I_C
BE
#1
PCI_
AD8
PC
I_A
D26
PC
I_A
D29
S2_A18
S2_D4
S2_A25
S1_D14
S1_D4
S2_A5
S1_D5
S1_A22
S1_A8
S1_A25
S1_A6
S1_A0
PC
I_A
D13
S2_D13
S2_D8
S2_A21
S2_A13S1_A14
PCI_
AD4
PCI_
AD7
PC
I_A
D17
PC
I_A
D20
S2_A0
S1_D9
PC
I_A
D25
S2_D3
S1_D13
S1_D3
S1_A20
S1_A12
S2_D6
S2_A16S2_A17
S2_A24
CLK_PCI_PCM
PCI_AD20
PCI_REQ#2 <26>
PCM_PME# <34,36,43,46,47>
PCI_PAR <26,34,35,36,43>PCI_FRAME# <26,34,35,36,43>PCI_TRDY# <26,34,35,36,43>PCI_IRDY# <26,34,35,36,43>PCI_STOP# <26,34,35,36,43>PCI_DEVSEL# <26,34,35,36,43>
PCI_PERR# <26,34,35,36,43>PCI_SERR# <26,34,35,36,43>
PCI_GNT#2 <26>CLK_PCI_PCM <26>PCI_RST# <11,26,30,34,35,36,43,46>
S2_INPACK#<32,33>
S2_WAIT#<32,33>
S2_CE1#<32,33>
S2_WP<32>
S2_CE2#<32>
S2_WE#<32,33>
S2_IORD#<32>
S2_OE#<32,33>S2_REG#<32,33>
S2_RST<32,33>
S2_VS1<32,33>S2_VS2<32,33>
S2_CD1#<32,33>S2_CD2#<32,33>
S2_BVD1<32,33>
S2_BVD2<32,33>
S1_BVD2 <32>
S1_WP <32>
S1_VS2 <32>
S1_IOWR# <32>
S1_RDY# <32>
S1_CD1# <32>
S1_BVD1 <32>
S1_VS1 <32>
S1_INPACK# <32>
S1_WAIT# <32>
S1_RST <32>
S1_OE# <32>
S1_WE# <32>
S1_REG# <32>S1_IORD# <32>
S2_IOWR#<32>
PCM_SUSP#<46>
PCI_CLKRUN#<26,34,35,36,43>
SIRQ<26,39,46>
S2_RDY#<32,33>
CLK_SD_48M <24>
PCI_PIRQA#<10,17,26,35,36>PCI_PIRQB#<26>
CARD_LED#<42>
S2_D[0..15]<32,33>
S2_A[0..25]<32,33>
S1_D[0..15]<32>
PCI_CBE#[0..3]<26,34,35,36,43>
R T C C L K<32>
S1_CD2# <32>
SLDATA<32>
SLATCH<32>PCM_SPK#<37>
S1_A[0..25]<32>
PCI_AD[0..31]<26,29,34,35,36,43>
S1_CE1# <32>S1_CE2# <32>
G_RST# <32,36,46>
+3V
+S1_VCC
+S2_VCC
+3V+3VS
+3V
+3V
+3V
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
CardBus Controller OZ6912/CB1410 & Socket
31 66Wednesday, September 24, 2003
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
C899
0.01U_0402_16V7K
R8330_0402_5%
C903
0.01U_0402_16V7K
R1018@10K_0402_5%
CARDBUS CONTROLLERPCI1520 PBGA 209
SLOT
B
SLOT
APCI INTERFACE
POWER
GROUND
FUNCTION
U37
PCI1520GHK_PBGA209
C898
0.01U_0402_16V7K
R940@0_0402_5%
C909
@0.1U_0402_10V6K
C845
0.1U_0402_10V6K
C849
0.1U_0402_10V6K
C847
0.1U_0402_10V6K
C850
0.1U_0402_10V6K
C902
0.01U_0402_16V7K
C900
0.01U_0402_16V7K
[email protected]_0402_10V6K
JP24A1
CARDBUS HOUSING
R634
0_0402_5%R1020
@10K_0402_5%
C6350.1U_0402_10V6K
R1098100_0402_5%
C851
0.1U_0402_10V6K
C848
0.1U_0402_10V6K
C901
0.01U_0402_16V7K
C846
0.1U_0402_10V6K
R633
1620@0_0402_5% C633
0.1U_0402_10V6K
R9390_0402_5%
C634
0.1U_0402_10V6K
S1_A[0..25]S2_D[0..15]
S1_D[0..15]
S2_A[0..25]
S1_D10
S1_D11
S1_CD2#
S1_D9
S1_WAIT#
S1_A23
S1_CE2#
S1_IORD#
S1_D14
S1_BVD2S1_REG#
S1_D15
S1_A24
S1_IOWR#S1_A17
S1_D12S1_D13
S1_A21
S1_A22
S1_RST
S1_A20
S1_INPACK#
S1_A25
S1_VS1
S1_BVD1
S1_VS2
S1_A19
S1_D8
S1_A18
S1_D3
S1_A1
S1_A12
S1_RDY#
S1_A15
S1_D4
S1_A6
S1_A2
S1_A10
S1_D6
S1_A0
S1_D2
S1_CE1#
S1_A16
S1_A8
S1_OE#
S1_A4
S1_D5
S1_D7
S1_A9
S1_WE#
S1_WP
S1_A11
S1_A7
S1_A13S1_A14
S1_A5
S1_D1S1_D0
S1_A3
S1_CD1#
S2_A0
S2_A16
S2_D13
S2_D11
S2_A4
S2_A2
S2_RST
S2_A23
S2_CE1#S2_D14
S2_A10
S2_RDY#
S2_A22
S2_D12
S2_A13
S2_D10S2_D1
S2_D8
S2_WE#
S2_A9
S2_WAIT#
S2_A7S2_A12 S2_A24
S2_VS2
S2_D5
S2_A6
S2_OE#
S2_A1
S2_A5
S2_D7
S2_A17
S2_A19
S2_D6
S2_CD1#
S2_BVD1
S2_IORD#
S2_D15
S2_A11
S2_INPACK#
S2_D9
S2_VS1
S2_IOWR#
S2_D4
S2_A8
S2_D2
S2_D3
S2_A3
S2_A25
S2_A21
S2_REG#
S2_A20S2_A14
S2_WP
S2_A15
S2_CD2#
S2_A18
S2_CE2#
S2_D0
S2_BVD2
S1_D[0..15]<31>
S2_D[0..15]<31,33>
S1_A[0..25]<31>
S2_A[0..25]<31,33>
SLDATA<31>R T C C L K<31>
SLATCH<31>G_RST#<31,36,46>
S1_WAIT# <31>S1_RST <31>
S1_CE2# <31>
S1_CD1# <31>
S1_BVD2 <31>
S1_VS1 <31>
S1_INPACK# <31>S1_REG# <31>
S1_CD2# <31>
S1_BVD1 <31>
S1_IOWR# <31>
S1_VS2 <31>
S1_IORD# <31>
S1_WP<31>
S1_CE1#<31>
S1_OE#<31>
S1_WE#<31>S1_RDY#<31>
S2_VS2 <31,33>S2_RST <31,33>
S2_CE2# <31>
S2_WE#<31,33>
S2_WP<31>
S2_IORD# <31>
S2_CD2# <31,33>
S2_IOWR# <31>
S2_BVD1 <31,33>
S2_REG# <31,33>
S2_CD1# <31,33>
S2_CE1#<31,33>
S2_OE#<31,33> S2_VS1 <31,33>
S2_WAIT# <31,33>S2_INPACK# <31,33>
S2_BVD2 <31,33>
S2_RDY#<31,33>
+S1_VCC
+S2_VCC+S2_VPP
+S1_VPP
+5V
+12VALW
+S1_VPP+S2_VPP
+S2_VCC+S1_VPP+S1_VPP
+S1_VCC
+S2_VPP+S2_VPP+S2_VCC +S2_VCC
+S1_VCC
+S1_VCC
+5V
+3V
Title
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
CARD BUS SOCKET
Compal Electronics, Inc.
32 66Wednesday, September 24, 2003
SOCKETCARDBUSPCMCIA POWER CTRL.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PIR BOM & LAYOUT 92.09.01 U38
TPS2224A
C646
4.7U_0805_10V4Z
1
2
C639 4.7U_0805_10V4Z
C648
4.7U_0805_10V4Z
1
2
C644 4.7U_0805_10V4Z
C650
0.1U_0402_10V6K
1
2C653
4.7U_0805_10V4Z
1
2
JP29
FOX_WZ21131-G2-P4
R1004
@0_0603_5%
12
R117747K_0402_5%
12
C647
0.1U_0402_10V6K
1
2
C641 4.7U_0805_10V4Z
C642 4.7U_0805_10V4Z
C640 4.7U_0805_10V4Z
C6541520@1000P_0402_50V7K
1
2
C652
1520@1000P_0402_50V7K
C6491000P_0402_50V7K
1
2
JP30
1520@FOX_WZ21131-G2-P4
C637 @2.2U_0805_10V4Z
C643
4.7U_0805_10V4Z
1
2
C636
1000P_0402_50V8J
C638 4.7U_0805_10V4Z
C645
4.7U_0805_10V4Z
1
2
C651
4.7U_0805_10V4Z
1
2
R6354.7K_0402_5%
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
SM_CLE
SM_WE#
DQRYDRV
SD_CD#
MC_CD#
SQRY4
SD_CMD
SM_WE#
SM_CE#
SD_CLK/MS_CLK
SM_LVD
SM_D4
SM_D7
SM_R/B#
SD_DATA2
SM_WP#
S2_A25
SM_D3/MS_BS
MC_WP#
SM_RE#
SQRY3
SD_CD/DATA3
SD_DATA1SM_RE#
MC_WP#
SM_D6
SM_ALE
SM_D0/MS_RFU7
SM_ALE
MC_WP#
SM_D5
SM_D4
SM_D5
SM_D0/MS_RFU7
SM_WP#
SD_CD#
SD_DATA0
SM_D1/MS_RFU5
S2_A22
SM_R/B#
SD_DATA1
SM_D3/MS_BS
SM_D2/MS_SDIOSM_D6
SM_D1/MS_RFU5SM_D7
SM_LVD
SM_CLESM_CE#
SD_DATA0SD_CLK/MS_CLK
SD_WP
SM_CD#
SD_DATA2SD_CD/DATA3SD_CMD
SQRY6
SQRY2SQRY5
SQRY1
SQRY10SQRY9SQRY8SQRY7
SM_D2/MS_SDIO
MC_CD#S2_A22<31,32>
S2_A25<31,32>
S2_A15<31,32>
S2_A10<31,32>
S2_D15<31,32>
S2_D11<31,32>
S2_D6<31,32>S2_D12<31,32>
S2_A13<31,32>
S2_A14<31,32>
S2_D5<31,32>
S2_D13<31,32>
S2_WE#<31,32>S2_OE#<31,32>
S2_A16<31,32>S2_A19<31,32>
S2_A8<31,32>
S2_D14<31,32>S2_D7<31,32>
S2_A24<31,32>S2_A12<31,32>
S2_CE1#<31,32>
S2_A21<31,32>S2_RDY#<31,32>
S2_A20<31,32>
S2_REG#<31,32>S2_RST<31,32>S2_A18<31,32>
S2_BVD2<31,32>
S2_D9<31,32>S2_D10<31,32>
S2_D8<31,32>S2_BVD1<31,32>
S2_CD1#<31,32> S2_VS1 <31,32>
S2_CD2#<31,32>
S2_VS2<31,32>
S2_INPACK#<31,32>S2_WAIT#<31,32>
+3VS
+S2_VCC
+S2_VCC
+S2_VCC
Title
LA-1811 1.0
4 IN 1 CARD READER SOCKET
33 66Wednesday, September 24, 2003
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R6411620@10K_0402_5%
R639 1620@0_0402_5%
RP146
1620@47K_0804_8P4R_5%
R989 1620@0_0402_5%
RP144
1620@47K_0804_8P4R_5%
C655
[email protected]_0402_10V6K
RP130 1620@0_0804_8P4R_5%
R637
@10K_0402_5%
R665
@0_0402_5%
R638
1620@43K_0402_5%
D45
1620@BAT54C_SOT23~D
R648 1620@0_0402_5%
R646
1620@43_0402_5%RP143
1620@47K_0804_8P4R_5%
RP145
1620@47K_0804_8P4R_5%
JP31
1620@TAI_SOL 4 IN 1 MEMORY CONNECTOR
R6401620@0_0402_5%
RP128 1620@0_0804_8P4R_5%
C656
[email protected]_0402_10V6K
RP131 1620@0_0804_8P4R_5%
R988 1620@0_0402_5%
RP132 1620@0_0804_8P4R_5%
RP133 1620@0_0804_8P4R_5%
R647
1620@10K_0402_5%
RP134 1620@0_0804_8P4R_5%
R649 1620@0_0402_5%
RP129 1620@0_0804_8P4R_5%
R658
1620@0_0402_5%
R987 1620@0_0402_5%
RP141 1620@0_0804_8P4R_5%
Q531620@MMBT3904_SOT23
D441620@BAT54C_SOT23~D
R636
@10K_0402_5%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RJ45_TXX+
LAN_RX-
PCI_AD24
PCI_AD20
EESK
RJ45_RXX-
XTALFBPCI_CBE#0
PCI_AD3
RJ45_TXX-
PCI_AD16
PCI_CBE#[0..3]
PCI_AD26
ACTIVITY#
RJ45_RXX-
PCI_AD27 LAN_RX-
PCI_AD6
CLKOUT
LANGND
PCI_AD29
PCI_CBE#3
ACTIVITY#
LAN_TX-
PCI_AD8
PCI_AD[0..31]
PCI_AD31
LAN_TX-PCI_AD30
PCI_AD19
EEDO
PCI_AD5
LAN_TX+
PCI_AD15
LINK10_100#
LAN_IO
LAN_TX+
RJ45_RXX+
PCI_AD23
PCI_CBE#2
EECS
RJ45_TXX+
PCI_CBE#1
PCI_AD10
PCI_AD25
PCI_AD1
EEDI
PCI_AD17
RJ45_GND
LAN_RX+
PCI_AD2
PCI_AD18
PCI_AD7
PCI_AD19
RJ45_TXX-
PCI_AD13PCI_AD14
LAN_RX+
LINK10_100#
PCI_AD9
PCI_AD0
PCI_AD21
PCI_AD12
PCI_AD28
PCI_AD11
PCI_AD4
RJ45_RXX+
PCI_AD22
ISOB
CLKOUT XTALFB
RJ45_GND
PCI_CBE#[0..3]<26,31,35,36,43>
PCI_CLKRUN#<26,31,35,36,43>
PCI_DEVSEL#<26,31,35,36,43>
PCI_FRAME#<26,31,35,36,43>
RJ45_RXX-<41>
PCI_AD[0..31]<26,29,31,35,36,43>
PCI_RST#<11,26,30,31,35,36,43,46>
PCI_PAR<26,31,35,36,43>
RJ45_TXX-<41>
RJ45_RXX+<41>
PCI_PERR#<26,31,35,36,43>
PCI_REQ#1<26>
PCI_STOP#<26,31,35,36,43>
PCI_TRDY#<26,31,35,36,43>PCI_IRDY#<26,31,35,36,43>
RJ45_TXX+<41>
ONBD_LAN_PME#<31,36,43,46,47>
PCI_GNT#1<26>
PCI_SERR#<26,31,35,36,43>
PCI_PIRQD#<26,36>
CLK_PCI_LAN<26>
RJ45_GND<41>
LANIO
LANIO
LANVDD
LANVDD
LANVDD
LANIO
LANIO
+3VS
LANIO
LANIO+3VALW
LANIO
LANIO
LANVDD
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
LAN RealTech8101BL
34 66Wednesday, September 24, 2003
Compal Electronics, Inc.
1. LAN_RD+, LAN_RD- should be equal length as possible2. LAN_TD+, LAN_TD- should be equal length as possible
CHASSIS GND
4. The distance between RJ45(Conn.) and Magnetic(U24) shouldbe as short as possible
Layout Recommend :
T=10mil
Termination plane should be copledto chassis ground and also dependson safety concern
1:1
3. The Maximum trace length between LAN chip(U22) andMagnetic(U24) is 12cm(4.7")
T=10mil
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Please close to LAN IC
Close to U39 pin58
C658
0.1U_0402_10V6K
C6750.1U_0402_10V6K
C6790.1U_0402_10V6K
L43
KC FBM_L11-201209-601LMT 0805
C674
0.1U_0402_10V6K
C6781000P_1206_2KV7K
C665
1U_0603_10V6K
C661
0.1U_0402_10V6K
Y5
25MHZ_20P_1BX25000CK1A
PCI I/F
Power
Powe
rLA
N I/
FAC
-Lin
k
U39
RTL8101L_LQFP100
C667
10U_0805_10V4Z
R698 5.6K_0402_5%
C663
0.1U_0402_10V6K
R701 15K_0402_5%
C673
0.1U_0402_10V6K
JP32
AMP RJ45 with LED
C660
0.1U_0402_10V6K
C6700.1U_0402_10V6K
R70049.9_0402_1%
C657
0.1U_0402_10V6K
R70749.9_0402_1%
C659
0.1U_0402_10V6K
U41
NS0013_16PR704 5.6K_0603_1%
R702 1K_0402_5%
R70675_0402_1%
R1006
0_0805_5%
R70575_0402_1%
C669
1000P_1206_2KV7K
C676
0.1U_0402_10V6K
C672
0.1U_0402_10V6K
R69675_0402_1%
R695 300_0603_5%
R703 100_0402_5%
R69775_0402_1%
R694 300_0603_5%
R69949.9_0402_1%
C662
0.1U_0402_10V6K
C6770.1U_0402_10V6K
C682@10P_0402_50V8K
C666
1U_0603_10V6K
R709@22_0402_5%
U40
AT93C46-10SI-2.7_SO8
C680
27P_0402_50V8J
C664
0.1U_0402_10V6K
C681
27P_0402_50V8J
R70849.9_0402_1%
C6714.7U_0805_10V4Z
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCI_AD16
CLK_PCI_1394
SCL_1394
XTPB0+XTPA0-
CLK_PCI_1394
SDA_1394
XTPA0+
XTPB0-
XTPBIAS0
PCI_AD[0..31]
PCI_AD30
PCI_AD24
PCI_AD2
PCI_AD7
PCI_AD14
PCI_AD25
PCI_AD11
PCI_AD26
PCI_AD9
PCI_AD29
PCI_AD3
PCI_AD21
PCI_AD10
PCI_AD18
PCI_AD20
PCI_AD16PCI_AD15
PCI_AD13
PCI_AD5PCI_AD4
PCI_AD22
PCI_AD31
PCI_AD1PCI_AD0
PCI_AD23
PCI_AD6
PCI_AD27
PCI_AD17
PCI_AD19
PCI_AD12
PCI_AD8
PCI_AD28
SDA_1394SCL_1394
PCI_IRDY#<26,31,34,36,43>
PCI_PIRQA#<10,17,26,31,36>
PCI_FRAME#<26,31,34,36,43>
PCI_TRDY#<26,31,34,36,43>PCI_DEVSEL#<26,31,34,36,43>
CLK_PCI_1394<26>
PCI_STOP#<26,31,34,36,43>
PCI_GNT#0<26>
PCI_SERR#<26,31,34,36,43>
PCI_PERR#<26,31,34,36,43>
PCI_CLKRUN#<26,31,34,36,43>PCI_PAR<26,31,34,36,43>
PCI_CBE#0<26,31,34,36,43>PCI_CBE#1<26,31,34,36,43>PCI_CBE#2<26,31,34,36,43>PCI_CBE#3<26,31,34,36,43>
PCI_RST#<11,26,30,31,34,36,43,46>
PCI_REQ#0<26>
PCI_AD[0..31]<26,29,31,34,36,43>
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
Title
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
IEEE 1394 CONTROLLER
35 66Wednesday, September 24, 2003
Compal Electronics, Inc.
Near 1394 IC
ID: AD16
CLOSE CHIP
The connector depend ondefferent project
EEPROM cancel,need SystemSupport
Close Chip
30ppm
Connect ToShielding GND
G_RST# connect to PCIRST#
** GPIO2 and GPIO3 defaults as an inputand if it is not implemented, it isrecommended that it be pulled low toground with a 220 ohm resistor.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
RP135
4.7K_1206_8P4R_5%
C687
0.1U_0402_10V6K
1
2
C690
0.1U_0402_10V6K
1
2
C686
0.1U_0402_10V6K
1
2
C683
0.1U_0402_10V6K
1
2
JP33
AMP_440168-2
R711 10K_0402_5%C689
0.1U_0402_10V6K
1
2
R72256.2_0402_1%
12
R72356.2_0402_1%
12
C697
0.01U_0402_16V7K
1
2
C705
0.1U_0402_10V6K
1
2
R717 100_0402_5%
C688
0.1U_0402_10V6K
1
2
C698 22P_0402_25V8K
X324.576MHz_16P_3XG-24576-43E1
12
C703
@10P_0402_25V8K
1
2
C692
1000P_0402_50V7K
1
2
C7000.1U_0402_10V6K
C684
0.1U_0402_10V6K
1
2
R720
56.2_0402_1%
12
C685
0.1U_0402_10V6K
1
2
C699 22P_0402_25V8K
R715 1K_0402_5%
C702
220P_0402_50V7K
1
2
R7166.34K_0603_1%
C704
0.1U_0402_10V6K
1
2
L44BLM21A601SPT_0805
RP142
220_0804_8P4R_5%
C693
1000P_0402_50V7K
1
2
C696
4.7U_0805_10V4Z
1
2
C695
1000P_0402_50V7K
1
2
C694
1000P_0402_50V7K
1
2
C691
1000P_0402_50V7K
1
2
C701
1U_0603_10V6K
1
2
PHY PORT 1
POWER CLASS
EEPROM 2 WIRE BUS
FILTER
OSCILLATOR
BIAS CURRENT
PCI BUS INTERFACE
TSB43AB21/(TSB43AB22)
U42
TSB43AB21_PQFP128
CY
CL
EO
UT
/CA
RD
BU
S8
6
CN
A9
6
TE
ST
17
10
TE
ST
16
11
CY
CL
EIN
87
VD
DP
20
VD
DP
35
VD
DP
48
VD
DP
62
VD
DP
78
PL
LG
ND
18
RE
G_
EN
9
AG
ND
10
9
AG
ND
11
0
AG
ND
11
1
AG
ND
11
7
AG
ND
12
6
AG
ND
12
7
AG
ND
12
8
DG
ND
17
DG
ND
23
RE
G1
83
0
DG
ND
33
DG
ND
44
DG
ND
55
DG
ND
64
DG
ND
68
DG
ND
75
DG
ND
83
RE
G1
89
3
DG
ND
10
3
R726
@10_0402_5%
12
R721
56.2_0402_1%
12
R727
5.11K_0402_1%
12
1
1
2
2
3
3
4
4
5
5
1 1
2 2
3 3
4 4PCI_GNT#PCI_REQ#4PCI_REQ#3
PCI_GNT#4PCI_GNT#3
USB20_NEC_P3-USB20_NEC_P3+USB20_NEC_P4-USB20_NEC_P4+
PCI_CLKRUN#
CLK_PCI_USB20
USB20_NEC_P1-USB20_NEC_P1+
USB20_NEC_P0-USB20_NEC_P0+
USB20_NEC_P2-USB20_NEC_P2+
PCI_AD23
USB20_NEC_P1-_R
USB20_NEC_P4+_R
PCI_AD4
PCI_AD17
PCI_AD20
PCI_PIRQA#
USB20_NEC_P0-_R
PCI_AD7
PCI_IRDY#
PCI_AD19
PCI_GNT#
USB20_NEC_P3+
USB20_NEC_P1-
PCI_AD15
PCI_STOP#
PCI_AD26
PCI_CBE#[0..3]
PCI_PAR
PCI_SERR#
PCI_PIRQC#
OVCUR_USB20#0
PCI_AD0
PCI_AD3
PCI_AD6
PCI_CBE#2
PCI_AD30
OVCUR_USB20#3
PCI_AD1
PCI_AD24
PCI_AD28
PCI_AD13
PCI_AD21
PCI_PIRQD#
PCI_REQ#
PCI_FRAME#
PCI_AD22
PCI_AD[0..31]
USB20_NEC_P2+_R
PCI_AD9
PCI_CBE#3
PCI_AD27
OVCUR_USB20#1
PCI_AD5
PCI_AD8
PCI_AD16
OVCUR_USB20#4
PCI_AD2
PCI_PERR#
PCI_AD25
PCI_AD31
USB20_NEC_P3+_R
USB20_NEC_P3-_R
PCI_AD12
PCI_AD14
PCI_AD23
USB20_NEC_P4-_R
PCI_CBE#0
PCI_AD10
PCI_CBE#1
PCI_DEVSEL#PCI_REQ#
USB20_NEC_P2-_R
USB20_NEC_P0+_R
PCI_TRDY#
PCI_AD18 USB20_NEC_P1+_R
CLK_PCI_USB20
PCI_AD11
PCI_AD29
USB20_NEC_P1+
USB20_NEC_P4-USB20_NEC_P4+
USB20_NEC_P2-
USB20_NEC_P0+
USB20_NEC_P2+
USB20_NEC_P3-
USB20_NEC_P0-
PCI_REQ#3<26,43>PCI_REQ#4<26,43>PCI_GNT#3<26,43>PCI_GNT#4<26,43>
PCI_PIRQA#<10,17,26,31,35>PCI_PIRQC#<26,43>PCI_PIRQD#<26,34>
USB20_NEC_P1- <44>
USB20_NEC_P2- <44>
USB20_NEC_P3- <44>
USB20_NEC_P4- <41>
PCI_AD[0..31]<26,29,31,34,35,43>
PCI_CLKRUN#<26,31,34,35,43>
USB20_PME#<31,34,43,46,47>
PCI_CBE#[0..3]<26,31,34,35,43>
PCI_FRAME#<26,31,34,35,43>
PCI_DEVSEL#<26,31,34,35,43>
PCI_IRDY#<26,31,34,35,43>PCI_TRDY#<26,31,34,35,43>
PCI_PAR<26,31,34,35,43>
PCI_STOP#<26,31,34,35,43>
CLK_PCI_USB20<26>
PCI_SERR#<26,31,34,35,43>OVCUR_USB20#1 <44>
USB20_NEC_P0- <44>
PCI_RST#<11,26,30,31,34,35,43,46>
G_RST#<31,32,46>
USB_SMI#<27>
USB20_NEC_P1+ <44>
USB20_NEC_P3+ <44>
USB20_NEC_P0+ <44>
PCI_PERR#<26,31,34,35,43>
USB20_NEC_P2+ <44>
OVCUR_USB20#0 <44>
USB20_NEC_P4+ <41>
+3V +3V_USB20
+3V +3V_USB20
+3V
+3V
+3V
+3V_USB20
+3V
+3VS+3V
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
NEC uPD720101 - USB2.0 Controller
36 66Wednesday, September 24, 2003
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
L Note: PLACE CLOSE TO U54 .For NEC USB2.0 only .
LNote: PLACE CLOSE TO U54 .For NEC USB2.0 only .
C965NEC@16P_0603_50V8J
R1037 NEC@15K_0402_5%
R1031 [email protected]_0603_1%
R1042 [email protected]_0402_5%
R1033 [email protected]_0603_1%
C929
NEC@10U_0805_10V4Z
R1030 [email protected]_0603_1%
C923
[email protected]_0402_10V6K
R1026 NEC@36_0603_1%
R1105NEC@100_0402_5%
R1039 NEC@10K_0402_5%
C919
[email protected]_0402_10V6K
Y7NEC@30MHZ_30PPM
R1035 [email protected]_0603_1%
R1060 NEC@0_0402_5%
R1112 NEC@100_0402_5%
RP148
NEC@15K_1206_8P4R_5%
U55
@AT24C02N-10SC-2.7_SO8
C964NEC@16P_0603_50V8J
R1025 NEC@36_0603_1%
RP147
NEC@15K_1206_8P4R_5%
C920
[email protected]_0402_10V6K
R1061 @0_0402_5%
[email protected]_0402_5%
R1048 @0_0402_5%R1046 @1.5K_0402_5%
C928
NEC@10U_0805_10V4Z
R1029 [email protected]_0603_1%
R1052 @0_0402_5%
C927
[email protected]_0402_10V6K
USB 2.0 CONTROLLERuPD720101F1-EA8FBGA144
U54
NEC@UPD720101F1-EA8_FBGA144
R1032 [email protected]_0603_1%
R1036 NEC@15K_0402_5%
C925
NEC@10U_0805_10V4Z
R1028
@10_0402_5%
R1034 [email protected]_0603_1%
R1051 NEC@0_0402_5%C926
[email protected]_0402_10V6K
C915
@15P_0402_50V8J
R1038
[email protected]_0402_1%
R1040 NEC@10K_0402_5%
C922
[email protected]_0402_10V6K
R1050 @0_0402_5%
R1049
NEC@0_0603_5%
C924
NEC@10U_0805_10V4Z
R1024 @0_0402_5%
R1045 [email protected]_0402_5%
R1043 [email protected]_0402_5%
R1054NEC@0_0603_5%
C918
@0.1U_0402_10V6K
C916
@0.1U_0402_10V6K
R1041 [email protected]_0402_5%
C917
@0.1U_0402_10V6K
R1027 [email protected]_0603_1%
R1047 NEC@0_0402_5%
C921
[email protected]_0402_10V6K
R1053 NEC@0_0402_5%
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
AFILT3AFILT2
LINE_OUTR
LINE_OUTL
CLK_14M_CODECC D G N D A
MDMIC
AFILT1
CDROM_R_R
C D _ G N A
AFILT4
CDROM_R_L
CDROM_RC_R
CDROM_RC_L
MONO_IN
MONO_INR
MONO_INRMONO_IN1
MD_SPKR MD_SPKRC
+5VAMP_CODEC
AUD_REF
PCM_SPK#<31>
SPDIFO<41>
AC97_SYNC<27,29,44>
MUTE_LED<38,44>
AC97_SDIN0 <27>
AC97_BITCLK <27,44>
AC97_RST#<27,44>
CLK_14M_CODEC <24>
SB_SPKR<27>
L _ H P <38>
R _ H P <38>CDROM_L<30>
MIC1<38>
CDROM_R<30>
AC97_SDOUT<27,29,44>
MD_SPK<44>
CD_AGND<30>
LINE_OUTR <38>
LINE_OUTL <38>
MD_MIC <44>
BEEP#<46>
MIC2<38>
HPS<38>
CONA#<41,46>
SPDIF_OUT<27,29>
G N D A <38,41>
+3VALW
+3VALW
CODEC_REF
+3VALW
VDDA_CODEC
+5VS
VDDA_CODEC+5VAMP_CODEC
+3VALW
+3VALW
+3VS
+3VS
+5VAMP_CODEC
Title
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
AC97 CODEC
Custom37 66Wednesday, September 24, 2003
Compal Electronics, Inc.
External
X
External
X
14.318MHZ
X
R767 R766 FREQ. SEL
Stuff
48MHZ
Crystal
Stuff
24.576MHZ
W=40Mil
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
StuffPIR BOM & LAYOUT 92.09.01
GND GNDA
PIR BOM & LAYOUT 92.09.01
PIR BOM 92.09.01
PIR BOM 92.09.01
C991 680P_0402_25V8K
C743 @15P_0402_50V8J
C726
10U_0805_6.3V6M
C731 1U_0603_25V4Z
C735 2.2U_0603_6.3V4Z
C730
10U_0805_10V4Z
R11680_1206_5%
R733
10K_0402_1%
G
DSQ101 2N7002_SOT23
C749
@0.1U_0402_16V4Z
R7540_0402_5%
C722
1U_0603_10V6K
R752 4.7K_0402_5%
C904 1U_0603_10V6K
R748 4.7K_0402_5%
C992 680P_0402_25V8K
C717
4.7U_0805_10V4Z
C724
0.1U_0402_10V6K
JOPEN6
U46
SI9182DH-AD_MSOP8
C712
1U_0603_10V6K
R739
560_0402_5%
R755 2.7K_0402_5%
D46
RB751V_SOD323
R757 2.7K_0402_5%
C984 220P_0402_25V8K
C750
270P_0402_50V7K
JOPEN7
C719
1U_0603_25V4Z
R1063
39K_0603_1%
R750 27_0402_5%
R956
10K_0402_5%
R740
0_0805_5%
R749 4.7K_0402_5%
C905
@0.1U_0402_16V4Z
C725
0.1U_0402_10V6K
R766 4.7K_0402_5%
C752 270P_0402_50V7K
C714 1U_0603_10V6K
L104 CHB1608B121_0603
R73710K_0603_1%
C
BE
Q56
2SC2411K_SOT23
C747
0.1U_0402_16V4Z
JOPEN8
C728
0.1U_0402_10V6K
R751 4.7K_0402_5%
U45C
SN74LVC14APWLE_TSSOP14
C734 2.2U_0603_6.3V4Z
R1103
@0_0402_5%
U 4 5 A
SN74LVC14APWLE_TSSOP14
C985 220P_0402_25V8K
C751 270P_0402_50V7K
C737 1U_0603_10V6K
U 1 8 B
SN74LVC32APWLE_TSSOP14
R762 @4.7K_0402_5%R761 @0_0402_5%
C729
0.1U_0402_10V6K
C718
0.1U_0402_10V6K
R742@10K_0402
R736
30K_0603_1%
C744
270P_0402_50V7K
C746
0.1U_0402_10V6K
R732
560_0402_5%
R731
10K_0402_1%
C987 470P_0402_25V8K
R767 4.7K_0402_5%
R763 0_0402_5%
R7462.2K_0402_5%
C723
0.1U_0402_10V6K
C986 220P_0402_25V8K
U32F
SN74LVC14APWLE_TSSOP14
R729
@100K_0402_1%
R741
560_0402_5%
L98
CHB1608B121_0603
C713
0.22U_0603_10V7K
C988 470P_0402_25V8K
C721
1U_0603_10V6K
C736 2.2U_0603_6.3V4Z
R758
@10_0402_5%
C7270.1U_0402_10V6K
R753 27_0402_5%
L99
CHB1608B121_0603
C745
1U_0603_10V6K
R11670_1206_5%
C715
4.7U_0805_10V4Z
C990 680P_0402_25V8K
R738
10K_0402_5%
R764 0_0402_5%
U47
AD1981B_LQFP48
C742 0_0402_5%
C720
0.01U_0402_16V7KC979
0.1U_0402_10V6K
C716
0.1U_0402_10V6K
C989 470P_0402_25V8K
R771
4.7K_0402_5%
R735
10K_0402_1%
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SPKR+
SPKL+
SPKR-
SPKL-
INTSPK_CL+
LINE_C_OUTR
LINE_C_OUTL
INTSPK_CR+INTSPK_CL+
INTSPK_CR+
SPKR-SPKR+SPKL-SPKL+
LINE_OUTL<37>
LINE_OUTR<37>
EC_MUTE#<46>
L _ H P<37>
R _ H P<37>
MIC2<37>
DOCK_LOUT_R<41>DOCK_LOUT_L<41>
VOLBTN+# <41,44,46>VOLBTN-# <41,44,46>WIRELESS_BTN <42,46>
WIRELESS_LED# <42,43,44>MUTE_LED <37,44>
HPS <37>
MIC1<37>
+5VAMP
+5VAMP+5VAMPP
+3VS
+5VS +5VAMP
CODEC_REF+5VS
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
AMP & Audio Jack
38 66Wednesday, September 24, 2003
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AUDIO CONNECTOR
HEADPHONE OUT/LINE OUT
Av(inv)
1
GAIN1
1
Gain Settings
1 0
GAIN0
0
0 6 dB0
1
21.6 dB
15.6 dB
10 dB
10 dB
PIR BOM & LAYOUT 92.09.01
R973
100K_0402_5%
C762
470P_0402_50V8J
L100 BLM11A121SPT_0805
D78RB751V_SOD323
U52
TI6017A2_TSSOP20
C894 0.1U_0603_16V7K
R975 0_0402_5%
L101 BLM11A121SPT_0805
C763
470P_0402_50V8J
C761
470P_0402_50V8J
+C774 100U_D2_10VM
R1164
1K_0402_5%
L57
0_1206
C896 0.1U_0603_16V7K
C893
0.047U_0603_10V7K
R971
@100K_0402_5%
L102 BLM11A121SPT_0805
R972
100K_0402_5%
C8970.47U_0603_10V7K
L103 BLM11A121SPT_0805C892
0.1U_0402_10V6KC764
470P_0402_50V8J
R974
@100K_0402_5%
R1158
1K_0402_5%
C895
0.047U_0603_10V7K
+C773 100U_D2_10VM
R734
0_1206_5%
C891
0.1U_0402_10V6KJP34
ACES_85205-0400
C890
10U_0805_10V3M
JP41
ACES_88028-1600_16P
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CLK_PCI_SIO CLK_LPC_48M
SOUT2
RTS1# DTR1# SOUT1
RI1#
CTS2#DSR2#
SOUT2SIN2
DCD1#
SOUT1
SIN1
DTR1#
RTS1#
DSR1#
CTS1#
LPD0LPD1LPD2LPD3LPD4LPD5LPD6LPD7
LPTSTB#
LPTINIT#LPTAFD#
LPTBUSYLPTACK#
LPTSLCTIN#LPTERR#
LPTPE
LAD0LAD1LAD2LAD3 TRACK0#
RDATA#WP#
DSKCHG#
CLK_LPC_48M
INDEX#CLK_PCI_SIOSERIRQ
LFRAME#
HWMVCC
HWMVCC
CTS1#
RI1#
DCD2#
RI2#
SIN2
SIN1
DCD2#RI2#
CTS2#DSR2#
DSR1#DCD1#
LPTSLCT
FIR_DET#
IRTXOUT <45>IRRX <45>
IRMODE <45>
LPD0 <40>LPD1 <40>LPD2 <40>LPD3 <40>LPD4 <40>LPD5 <40>LPD6 <40>LPD7 <40>
LPTAFD# <40>LPTINIT# <40>
LPTSTB# <40>
LPTPE <40>
LPTERR# <40>
LPTBUSY <40>
LPTSLCTIN# <40>
LPTACK# <40>
LPC_AD0<26,46>LPC_AD1<26,46>LPC_AD2<26,46>LPC_AD3<26,46>
CLK_LPC_48M <24>
CLK_PCI_SIO<26>SIRQ<26,31,46>
NB_RST#<8,17,26>
LPC_FRAME#<26,46>
HDSEL# <40>
TRACK0# <40>
3MODE# <40>
INDEX# <40>
DRV0# <40>
RDATA# <40>WP# <40>
FDDIR# <40>STEP# <40>
WGATE# <40>
DSKCHG# <40>
WDATA# <40>
MTR0# <40>
MDC_DET#<44>
LPC_DRQ#1<26>
LPTSLCT <40>
RI1# <41>
DCD1# <41>
SOUT1 <41>
SIN1 <41>
DTR1# <41>
RTS1# <41>
DSR1# <41>
CTS1# <41>
+3VS+3VS+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
Size Document Number Rev
LA-1811 1.0
LPC SUPER I/O VIA VT1211
39 66Wednesday, September 24, 2003
Compal Electronics, Inc.
Base address 1:2Eh/2FhBase address 0:4Eh/4Fh 1:Test Mode
0:Normal Opreation1:Enable Flash Rom0: Enable ROM I/F as GPIO
Super I/O strapping for VT1211For Winbond 48M strapping
W
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C788
@15PF_0402
R794
@10K_0402
R11084.7K_0402_5%
R784@10K_0402
C784
0.1U_0402_10V6K
R79710K_0402_1%
R792
@10K_0402
RP151 4.7K_0804_8P4R_5%
C7820.1U_0402_10V6K
R7962.2K_0402_5%
R1174
FIR@10K_0402
R783
@4.7K_0402_5%
C781
10U_0805_10V4Z
RP152 4.7K_0804_8P4R_5%
R1173
10K_0402
LPC
PARALLEL PART
GAME PORTSERIAL POART 1
SERIAL POART 2
IR
FDD
HARDWARE MONITOR
U51
VT1211_LQFP128
R79510K_0402_1%
C789
@10P_0402_50V8J
C786
0.1U_0402_10V6K
R793
@10K_0402
R11094.7K_0402_5%
L55
0_0805_5%
C787
0.1U_0402_10V6K
C785
0.1U_0402_10V6K
R790
@33_0402
R791
@10_0402_5%
R787 4.7K_0402_5%
R798
4.7K_0402_5%
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FD6
LPTAFD# AFD/3M#
LPTSTB#
FD0
FD7
LPTERR#
FD5
LPD2
LPTSLCT
LPD3
LPD7
SLCTIN#
LPTACK#
PWRPRN
FD5
LPTINIT#
FD3
PRNINIT#
FD7
FD0
FD5
LPTERR#
LPTSLCTIN#
LPD[0..7]
FD1
LPTPEAFD/3M#
FD2
LPD0
LPD6
FD6
AFD/3M#
FD1
PRNINIT#
FD7
FD4
FD4
LPD4
SLCTIN#
FD4LPD5
SLCTIN#
LPTACK#
LPTBUSY
FD2
FD3
LPTERR#
LPTPE
LPD1
LPTSLCT
PRNINIT#
FD6
LPTBUSY
DSKCHG#
TRACK0#WP#INDEX#
FD4
FD7
FD5FD6
FD1
FD3
FD0
FD2
FD1FD2
FD0
FD3
LPTACK#LPTBUSY
LPTSLCTLPTPE
INDEX#
DRV0#
DSKCHG#
3MODE#
MTR0#
FDDIR#
WDATA#
HDSEL#
WGATE#
WP#
TRACK0#
RDATA#
STEP#
RDATA#
WDATA#
FDDIR#MTR0#
DRV0#DSKCHG#
HDSEL#
TRACK0#
RDATA#WP#
WDATA#
3MODE#
WGATE#
STEP#
INDEX#
LPD[0..7]<39>
LPTACK#<39>
LPTINIT#<39>
LPTSLCTIN#<39>
LPTSTB#<39>
LPTAFD#<39>
LPTBUSY<39>
LPTERR#<39>
LPTSLCT<39>
LPTPE<39>
INDEX#<39>
FDDIR#<39>
DSKCHG#<39>
RDATA#<39>
MTR0#<39>
HDSEL#<39>
3MODE#<39>
WDATA#<39>
WGATE#<39>
TRACK0#<39>
WP#<39>
STEP#<39>
DRV0#<39>
+5V_PRN
+5V_PRN
+5V_PRN
+5V_PRN
+5VS
+5V_PRN
+5V_PRN
+5VS
+5VS
+5VS
+5VS
+5VS
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 1.0
Pallel port and FDD
B
40 66Wednesday, September 24, 2003
w=10mils
w=10
mils
Parallel Port FDD CONN.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Compal Electronics, Inc.
PIR LAYOUT 92.09.01
RP123
68_1206_16P8R_5%
R801
33_0402_5%
JP38
ACES_85201-2605
CP13
220P_1206_8P4C_50V8K
C792
47P_0402_50V8J
CP11
220P_1206_8P4C_50V8K
C975
220P_0402_25V8K
R1160
330_0402_5%
R803 33_0402_5%
C793
0.1U_0402_10V6K
1
2
R1159
330_0402_5%
CP17
220P_1206_8P4C_50V8K
CP12
220P_1206_8P4C_50V8K
R800 33_0402_5%
C790
4.7U_0805_10V4Z
1
2
CP16
220P_1206_8P4C_50V8K
C976
220P_0402_25V8K
JP39SUYIN_070536FR025S204AU
CP14
220P_1206_8P4C_50V8K
C794
0.1U_0402_10V6K
1
2
C791
0.1U_0402_10V6K
1
2
CP15
220P_1206_8P4C_50V8K
RP122
2.7K_1206_10P8R_5%
D48
1SS355_SOD323
RP120
2.7K_1206_10P8R_5%
R802 33_0402_5%
RP119
330_0804_8P4R_5%
R799
2.7K_0402_5%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SPDIFO_L
DOCK_LOUT_L
USB4+
DOCK_LOUT_RDOCK_PRESENT
TV_GND
USB20_NEC_P4-USB20_NEC_P4+
USB20P4+USB20P4-
USB4-
USB4-USB4+
DOCK_PRESENT
SPDIFO SPDIFO_L
RTS1# <39>CTS1# <39>
RI1# <39>
TV_LUMA<11,17,48>TV_COMPS<11,17,48>
DSR1# <39>RJ45_RXX-<34>RJ45_RXX+<34>
TV_CRMA<11,17,48>
SOUT1 <39>SIN1 <39>
DCD1# <39>DTR1# <39>RJ45_GND<34>
TV_GND<48>
RJ45_TXX-<34>RJ45_TXX+<34>
DOCK_LOUT_L <38>DOCK_LOUT_R <38>
JACK_DET# <46>
USB20P4+<27>USB20P4-<27>
USB20_NEC_P4-<36>USB20_NEC_P4+<36>
VOLBTN-#<38,44,46>
CONA#<37,46>
VOLBTN+# <38,44,46>
SPDIFO<37>
USB_VCCA
DOCKVINDC_IN
+5VS
USB_VCCA
DOCKVINDOCKVIN
+3V
+3VALW
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
SPR Connector
41 66Wednesday, September 24, 2003
Compal Electronics, Inc.
SPR 36 PIN For X7
RJ45_GND TRACE AT LEAST 20 MIL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Note: PLACE CLOSE TO SPR PORT (JP40)L
Note: PLACE CLOSE TO SPR PORT (JP40)
L
PIR BOM & LAYOUT 92.09.01
EMI Clip PAD
PIR BOM & LAYOUT 92.09.01
H18HOLEA
CF5
H1HOLEA
H10HOLEA
R880
470_0402_5%
H20HOLEA
H28HOLEA
R1090 ATI@0_0402_5%
CF16
CF4
H22HOLEA
C804
1000P_0402_50V7K
C805
1000P_0402_50V7K
C971
1000P_0402_50V7K
C801
@1000P_0402_50V7K
R1093 NEC@0_0402_5%
FM5
CF2
CF15
H8HOLEA
CF25
H30HOLEA
CF20
C798
@10U_0805_16V4Z_V1
H17HOLEA
FM3
H6HOLEA
R1092 NEC@0_0402_5%
H31HOLEA
R1141 200_0402_5%
CF6
CF18
CF7
H19HOLEA
H23HOLEA
CF13
H27HOLEA
CF11
JP40
FOX_QL11183-C6HQ
C800
0.1U_0402_10V6K
CF27
L105
KC FBM_L11-160808-601LMT 0603
R1139 @10K_0603_5%CF17
C972
1000P_0402_50V7K
H24HOLEA
R879
10K_0402_5%
CF9
FM2
CF21
EP1EMI-126X142
FM1
R1140200_0402_5%
L56
KC FBM-L18-453215-900LMA90T_1812
H13HOLEA
FM6
H7HOLEA
H9HOLEA
CF24
CF3
R1131 1K_0603_5%
Q65MMBT3904_SOT23
CF8
H3HOLEA
CF1
CF22
H14HOLEA
C963
0.01U_0402_50V7K
CF19
H4HOLEA
H12HOLEA
H26HOLEA
R1161
0_0805_5%
H25HOLEA
FM4
H2HOLEA
CF14
CF12
CF26
H21HOLEA
CF23
H16HOLEA
H5HOLEA
R1091 ATI@0_0402_5%
CF10
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
KSI0KSO16
PWR_BACK#
KSI1
KSI2
WIRELESS_BTN
KSI3
WIRELESS_LED#
PWR_ACTIVE_PAV#
CARD_LED#
PRES_LEDVCC
PAV_LEDVCC
PAV_LEDVCC
PAV_LEDVCC
PAV_LEDVCC
PRES_LEDVCC
PAV_LEDVCC
PRES_LEDVCC
PWR_ACTIVE_PRES#
PRES_LEDVCC
PAV_LEDVCC
PAV_LEDVCC
PAV_LEDVCC
TP_OFF_LED#<46>
PWR_BACK#<46>
KSO16<46>
KSI1 <45,46>
KSI0 <45,46>
KSI2 <45,46>
KSI3 <45,46>
WIRELESS_BTN <38,46>
WIRELESS_LED#<38,43,44>
PWR_ACTIVE_PAV#<46>
CARD_LED#<31>
NUMLED#<46>
PRES_LEDVCC <44,46>
PAV_LEDVCC <44>CAPSLED#<46>
PWR_ACTIVE_PRES#<46>
+3VS
+5V
Title
Size Document Number Rev
Date: Sheet o f
LA-1811 1.0
LED INDICATOR
B
42 66Wednesday, September 24, 2003
FOR POWER BUTTONBACKLIGHT ( PAV)
FOR 3 PROGRAMINGBUTTON BACKLIGHT(PAV)
FOR CARDREADER INDICATOR ( PAV /PRES )
FOR WIRLESS LED( PAV )
3 FORPROGRAMING
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
FOR TP ON OFF
FOR WIRELESS ON OFF
Compal Electronics, Inc.
FOR POWER BUTTONBACKLIGHT ( PRES )
PIR BOM 92.09.01
PIR BOM 92.09.01
PIR BOM 92.09.01
PIR BOM 92.09.01
R1057
PAV@1K_0402_5%
12
R882
27_0402_5%
D52PAV@HSMB-C172 BLUE_0805
C842
@.1UF_04021
2
Q68
PDTA114EK_SC59
C1
E3
B2
Q62
PAV@PDTA114EK_SC59
C1
E3
B2
R881 PAV@91_0402_5%
D53
PAV@HSMB-C172 BLUE_0805
C810
@.1UF_0402
12
C811
@.1UF_0402
12
D65
PAV@HSMB-C172 BLUE_0805
D55
PAV@HSMB-C172 BLUE_0805
SW4 PAV@TC010-PS11CET_5P
5
D56PRES@HSMG-C170_GRN_0805
D63PRES@HSMG-C170_GRN_0805
R889PAV@91_0402_5%
12
R1014
10K_0402_5%
12
D58PRES@HSMG-C170_GRN_0805
D61PRES@HSMG-C170_GRN_0805
D92
PAV@HSMB-C172 BLUE_0805
C831
@.1UF_0402
12
D60
PAV@HSMB-C172 BLUE_0805
SW7 TC010-PS11CET_5P
5
D64
PAV@HSMB-C172 BLUE_0805
R1136130_0402_5%
12
R1138
10K_0402_5%
12
SW5 PAV@TC010-PS11CET_5P5
C809
@.1UF_0402
12
R888
130_0402_5%
Q66
PDTA114EK_SC59
C1
E3
B2
Q71
PDTA114EK_SC59
C1
E3
B2
Q70
PAV@MMBT3904_SOT23
31
SW6 PAV@TC010-PS11CET_5P
5
Q69
PDTA114EK_SC59
C1
E3
B2
D59
PAV@HSMB-C172 BLUE_0805
D62PAV@HSMB-C172 BLUE_0805
21
R1058
PAV@10K_0402_5%
12
Q116
MMBT3904_SOT23
31
R890
130_0402_5%
R1137
1K_0402_5%
R885
130_0402_5%
Q117
PRES@PDTA114EK_SC59
C1
E3
B2
R1146 PRES@300_0402_5%
SW3 PAV@TC010-PS11CET_5P
5
D57
PRES_1520@12-21SYGC/S530-E1/TR8_GRN
D54
PAV@HSMB-C172 BLUE_0805
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
MDM_PME#
PCI_AD18
PCI_AD18
CLK_PCI_MINI
MINIPCI_AD22
PCI_AD22
CLK_PCI_MINI
PCI_PIRQC#
WL_ON
MINIPCI_PME#
PCI_AD14<26,31,34,35,36>
PCI_GNT#3 <26,36>
PCI_CLKRUN#<26,31,34,35,36>
PCI_AD18 <26,31,34,35,36>
PCI_PERR#<26,31,34,35,36>
PCI_AD16 <26,31,34,35,36>
PCI_AD3<26,31,34,35,36>
PCI_AD29<26,31,34,35,36>
PCI_AD21<26,31,34,35,36>
PCI_PAR <26,31,34,35,36>PCI_AD20 <26,31,34,35,36>
PCI_PIRQC#<26,36>
PCI_AD15 <26,31,34,35,36>
PCI_AD17<26,31,34,35,36>
PCI_AD5<26,31,34,35,36>
PCI_CBE#2<26,31,34,35,36>
PCI_SERR#<26,31,34,35,36>
PCI_AD11 <26,31,34,35,36>
PCI_AD23<26,31,34,35,36>
PCI_AD8<26,31,34,35,36>
MDM_PME# <31,34,36,46,47>
PCI_AD28 <26,31,34,35,36>
PCI_STOP# <26,31,34,35,36>
PCI_AD2 <26,31,34,35,36>
PCI_AD12<26,31,34,35,36>
PCI_AD26 <26,29,31,34,35,36>
PCI_AD9 <26,31,34,35,36>
PCI_AD31<26,31,34,35,36>
PCI_RST# <11,26,30,31,34,35,36,46>
PCI_AD30 <26,31,34,35,36>
PCI_AD7<26,31,34,35,36>
PCI_AD25<26,31,34,35,36>
PCI_AD10<26,31,34,35,36>
PCI_REQ#3<26,36>
PCI_IRDY#<26,31,34,35,36>
PCI_AD6 <26,31,34,35,36>
PCI_AD24 <26,31,34,35,36>
PCI_CBE#0 <26,31,34,35,36>
PCI_AD0 <26,31,34,35,36>
PCI_DEVSEL# <26,31,34,35,36>
PCI_FRAME# <26,31,34,35,36>
PCI_CBE#3<26,31,34,35,36>
PCI_GNT#4 <26,36>PCI_REQ#4<26,36>
PCI_TRDY# <26,31,34,35,36>
PCI_AD27<26,31,34,35,36>
PCI_AD13 <26,31,34,35,36>
PCI_AD22 <26,31,34,35,36>PCI_AD19<26,31,34,35,36>
PCI_AD4 <26,31,34,35,36>
PCI_AD1<26,31,34,35,36>
CLK_PCI_MINI<26>
PCI_CBE#1<26,31,34,35,36>
WL_ON<44,46>
WIRELESS_LED#<38,42,44>
MINIPCI_AD22<44>
MINIPCI_PME# <44>
+5VS
+3VS
+3VALW
+5VS
+5VS
+3VALW
+3VALW
+5VS
+3VS
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
Mini PCI Slot
43 66Wednesday, September 24, 2003
Compal Electronics, Inc.
W=40mils
W=40mils
LAN RESERVED LAN RESERVEDTIP
W=40mils
W=40mils
IDSEL : AD18
RING
W=30mils
W=30mils
W=30mils
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
R302
@10_0402_5%
C275
@15P_0402_50V8J
D88 1N4148_SOT23
C286
1000P_0402_50V7K
KEY KEY
JP12
AMP_1318644-1
C284
4.7U_0805_10V4Z
C272
0.1U_0402_10V6K
C285
0.1U_0402_10V6K
D89 RB751V_SOD323
C278
1000P_0402_50V7K
C281
4.7U_0805_10V4Z
R304 @10K_0402_5%
C269
0.1U_0402_10V6K
C277
0.1U_0402_10V6K
C274
0.1U_0402_10V6K
C276
4.7U_0805_10V4Z
C280
4.7U_0805_10V4Z
C270
1000P_0402_50V7K
C282
@1000P_0402_50V7K
C271
0.1U_0402_10V6K
C273
1000P_0402_50V7K
R301 100_0402_5%
+5VMDC
ACT_LED
MRING
USB2-
USB0-USB0+
BT_VCC
USB20_NEC_P0+USB20_NEC_P0-
USB20P0-USB20P0+
USB20P2+USB20P2-
USB20_NEC_P2+USB20_NEC_P2-
USB2+
USB20P1+USB1-USB20P1-USB1+
USB20_NEC_P1-USB20_NEC_P1+
BT_VCC
USB3-
USB5+USB5-
USB3+
USB5-
USB5+
TIP
MD_MIC<37>
MDC_DET# <39>
AC97_SYNC <27,29,37>AC97_SDIN1 <27>
AC97_RST#<27,37>
MD_SPK <37>
AC97_BITCLK <27,37>
AC97_SDOUT<27,29,37>
TP_DATA<46>TP_CLK<46>
BATLED_0<45>
PMLED_1<45>
WL_ON<43,46>
WIRELESS_LED#<38,42,43>
USB20_NEC_P0-<36>USB20_NEC_P0+<36>
USB20P0+<27>USB20P0-<27>
USB20P1+<27>
USB20P2+<27>USB20P2-<27>
USB20_NEC_P2-<36>USB20_NEC_P2+<36>
USB20_NEC_P1-<36>USB20_NEC_P1+<36>
USB20P1-<27>
OVCUR_USB20#1 <36>
OVCUR#0 <27>
OVCUR#1 <27>
OVCUR_USB20#0 <36>
MINIPCI_AD22<43>MINIPCI_PME#<43>
USB20P3+<27>USB20P3-<27>
USB20P5-<27>USB20P5+<27>
VOLBTN+#<38,41,46>
VOLBTN-#<38,41,46>
ACT_LED<45>
MUTE_LED<37,38>
PAV_LEDVCC<42>
USB20_NEC_P3-<36>
USB20_NEC_P3+<36>
PRES_LEDVCC<42,46>
PMLED_1#<45,46>
BATLED_0#<45,46>
+3VS+5VS
+3V
+3VS
+3V
+3VS
+5V
+5V
+5V USB_VCCB
USB_VCCA+5V
USB_VCCA
USB_VCCB
USB_VCCB
+3VS
+3V
+3VS
+3VS
+5VS
+5VS
+5VALW
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
MDC , Bluetooth & USB CONN.
44 66Wednesday, September 24, 2003
Compal Electronics, Inc.
MDC Conn.
RJ11 CONN.
Note: PLACE CLOSE TO EACH USB PORT
USB KEY
TP CONNECTOR
Front Board CONNECTORPavilion only
PRESARIO only
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BT CONNECTOR
W=40mils
RIGHT USB CONNECTOR 0
W=40mils
LEFT USB CONNECTOR 1
W=40mils
LEFT USB CONNECTOR 2
L
L Note: PLACE CLOSE TO EACH USB PORT (JP18)
L Note: PLACE CLOSE TO EACH USB PORT (JP19)
L Note: PLACE CLOSE TO EACH USB PORT (JP20)
L Note: Place close to JP43.1
L Note: Place close to JP43
L Note: Place close to JP46
Front Board CONNECTOR
PIR BOM 92.09.01
PIR BOM 92.09.01
PIR BOM 92.09.01
JP44
ACES_87152-0807
C299
@0.1U_0402_10V6K
C313
0.1U_0402_10V6K
R1080 0_0603_5%
R895
330K_0402_5%
C309
1000P_0402_50V7K
R1073 NEC@0_0402_5%
R809
4.7K_0603_1%
R1077 NEC@0_0402_5%
L80PAV@CHB1608B121_0603
L88PAV@CHB1608B121_0603
L90 PRES@CHB1608B121_0603
JP46
ACES_85201-0405
L86PAV@CHB1608B121_0603
R323 10K_0402_5%
R976 ATI@0_0402_5%
R1074 NEC@0_0402_5%
R1084 100_0402_5%
JP18
suyin_020167mr004s511zu_4p
JP16
FOXCONN_JM34613-L002-TR
R1070 NEC@0_0402_5%
R320
100K_0402_5%
R319 @0_0805_5%
C977
@220PF_3KV_1808
L81PAV@CHB1608B121_0603
+C312
100U_D2_6.3VM
C308
0.1U_0402_10V6K
C958
0.1U_0402_10V6K
L95 CHB1608U301_0603
L91 PRES@CHB1608B121_0603
R325 22_0402_5%
L87PAV@CHB1608B121_0603
R1075 ATI@0_0402_5%
C832
1000P_0402_50V7K
R896
560K_0402_5%
R1055 10K_0402_5%
D87 1N4148_SOT23
L84PAV@CHB1608B121_0603
JP47
MOLEX_53398_0290
C978
@220PF_3KV_1808
C304
0.1U_0402_10V6K
R979 ATI@0_0402_5%
+C315
100U_D2_6.3VM
R981 ATI@0_0402_5%
JP43
ACES_85201-0805
C955
0.1U_0402_10V6K
R894
560K_0402_5%
C311
0.1U_0402_10V6K
R326 22_0402_5%
R1072 NEC@0_0402_5%
C310
0.1U_0402_10V6K
L92 PRES@CHB1608B121_0603
L89PAV@CHB1608U301_0603
C298
@1000P_0402_50V7K
+C307
100U_D2_6.3VM
C314
1000P_0402_50V7K
L96CHB1608B121_0603
C954
1000P_0402_50V7K
C813
0.47U_0603_10V7K
C812
0.47U_0603_10V7K
G
D
SQ1002N7002_SOT23
C302@1000P_0402_50V7K
L83PAV@CHB1608B121_0603
R977 ATI@0_0402_5%
R1071 ATI@0_0402_5%
C305@22P_0402_25V8K
C301
0.1U_0402_10V6K
JP19
suyin_020167mr004s511zu_4p
L93 PRES@CHB1608B121_0603
Q99
SI2301DS_SOT23
L97 CHB1608B121_0603
R1076 NEC@0_0402_5%
R980 ATI@0_0402_5%
R1069 NEC@0_0402_5%
R982 ATI@0_0402_5%
R1083 100_0402_5%
U14
AATI4610GV-T1_SOT23_5
C316
0.1U_0402_10V6K
U13
AATI4610GV-T1_SOT23_5
R810
4.7K_0603_1%
L79PAV@CHB1608B121_0603
R978 ATI@0_0402_5%
L85PAV@CHB1608B121_0603
R1082 NEC@0_0402_5%
C300
1000P_0402_50V7KC303
4.7U_0805_10V4Z
C957
10U_0805_10V3M
JP42
PAV@ACES_85201-1405
L94 PRES@CHB1608U301_0603C833
1000P_0402_50V7K
R983 ATI@0_0402_5%
R1079 0_0603_5%
R327@10_0402_5%
JP20
suyin_020167mr004s511zu_4p
R893
330K_0402_5%
C317
1000P_0402_50V7K
R1081 NEC@0_0402_5%
JP45
PRES@ACES_85201-0805
R1078 NEC@0_0402_5%
JP17
ACES_88021-3000
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
IRRX
IRTXOUTIRMODE
ON/OFFBTN#
+5V
S_F
IR
EC_ON
ON/OFF#
KSI[0..7]
KSO[0..15]
ON/OFFBTN#
KSO1
KSI1
KSO7
KSO13
KSO3
KSO2
KSO10
KSO8
KSI2
KSI7
KSO0
KSO12
KSO15
KSI0
KSO4
KSI6
KSO5
KSO11
KSO9
KSI3
KSO14
KSO6
KSI5KSI4
KSO10KSO15
KSO11KSO14
KSO6KSO3KSO12KSO13
KSO7
KSO2
KSO8
KSO4
KSO1KSI0
KSI3KSO5
KSI4
KSO0KSI2
KSI5
KSI7KSI1
KSI6KSO9
IRTXOUT <39>IRMODE <39>
IRRX <39>
EC_PWR_ON# <51>
ON/OFF# <46>
LID_SW# <46>
EC_ON<46>
KSO[0..15] <46>
KSI[0..7] <42,46>
BATLED_0#<44,46>
ACT_LED#<30>
PMLED_1#<44,46>
ACT_LED <44>
PMLED_1 <44> BATLED_0 <44>
+5VS
+3VS
+3VALW
+3VALW
+5VS
+3VALW
+3VALW
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
KBD,ON/OFF,T/P,LED & FIR
45 66Wednesday, September 24, 2003
Compal Electronics, Inc.
FIR Module
T = 12mil
T = 12milT = 12mil
T = 40mil
T = 20mil
Power BTN
WHEN R=33K,Vbe=0.8VWHEN R=0,Vbe=1.35V
INT_KBD CONN.
Touch Pad & Status LED Conn.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR BOM 92.09.01
22K
22K
Q21DTC124EK_SOT23
D29
RLZ20A_LL34
R306
470_0402_5%
R308
FIR@10_1206_5%
SW8PRES@TC010-PS11CET_5P
R923 220_0402_5%
R307 0_0402_5%
D27 @PSOT03C
CP4
100P_1206_8P4C_50V8
SW9
ESE11MV9_4P
D28
DAN202U_SC70
R305 100K_0402_5%
C291
FIR@22U_1206_16V4Z
D30 @PSOT03C
SW1PAV@TC010-PS11CET_5P
R924 220_0402_5%
C294
[email protected]_0402_10V6K
CP1
100P_1206_8P4C_50V8
+ C292
FIR@10U_0805_6.3VM
JP13
ACES_85201-2405
10K
10KC
BE
Q93DTA114EK
R925 130_0402_5%
CP2
100P_1206_8P4C_50V8
10K
10KC
BE
Q94DTA114EK
C290
[email protected]_0402_10V6K
CP5
100P_1206_8P4C_50V8
10K
10KC
BE
Q92DTA114EK
C293
[email protected]_0402_10V6KU12
FIR@IR_VISHAY_TFDU6101E-TR4_8P
C289
1000P_0402_50V7K
G
D
S
Q112@2N7002_SOT23
CP3
100P_1206_8P4C_50V8
R309
FIR@10_1206_5%
CP6
100P_1206_8P4C_50V8
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
EC_SMD_2
EC_SMC_1
ADB[0..7]
LID_SW#
SELIO#FRD#
KBA3
KBA[0..19]FSEL#
KBA5
EC_SMI#
KBA1
ECAGND
EC_SMD_1EC_SMC_2
CLK_PCI_EC
KBA2
M_SEN#
PMLED_1#
KSO16
EC_TDO
EC_TMS
EC_TCK
EC_TDI
EC_TINIT#
KSO17
BID
VOLBTN+#
VOLBTN-#
SCI#
PRES_DETECT
PS2_DATAPS2_CLK
KBD_DATAKBD_CLK
TP_DATATP_CLK
KBA19
KBA17
KBA9
CRY2
KSI0
ECAGND
KBA15
KBA5
ADP_IR
TP_CLK
KBD_DATAKBD_CLK
KSO9
ECAGND
PWR_ACTIVE_PAV#
KSO14
KSO8
GA20
KBA18
KBA13
KBA7
TP_OFF_LED#
PRES_DETECT
KSO[0..15]
FSEL#
KBA11
EC_SMC_1
KSI5
SCI#
PWR_ACTIVE_PRES#
EC_SMD_1
KSO13KSO12
KSO2
EC_SMI#
KSO16
EC_TINIT#
KSO15
KSO6KSO5
KSI1
KBA10
KBA8
ADB1
EC_SMD_2
PMLED_1#
ADB6
KBA3
KBA1
M_SEN#
KSO4
CLK_PCI_ECEC_RST#
ADB3
KSO17
KSO0
KSI3
KSI[0..7]
KBA16
EC_TCK
KSO7
VOLBTN+#
SELIO#
PS2_CLK
AC_IN
ADB5
ADB0
KBA6
KBA4
EC_SMC_2
PS2_DATA
KBA14
ADB7
ADB2
FANSPEED1
KSO3
MMO_ON KBA12
FWR#
ADB4
VOLBTN-#
TP_DATA
KSO1
KSI6
FRD#
KBA2
KBA0
LID_SW#
CRY1
KSI4
BID
KBRST#
EC_TMS
KSO11
AC_IN
EC_TDOEC_TDI
KSI7
KSI2
KSO10
LPC_FRAME#<26,39>
ADB[0..7] <47>
LPC_AD1<26,39>LPC_AD2<26,39>
LPC_AD0<26,39>
KBA[0..19] <47>
SIRQ<26,31,39>
LPC_AD3<26,39>
ADP_I <51,52>
CLK_PCI_EC<26>
KSO[0..15]<45>KSI[0..7]<42,45>
TP_DATA<44>
FSEL#<47>
SUSP#<47,49>
EC_SWI#<27>
ENAVDD<10,17,25>
EC_SMI#<27>
VR_ON<55>
BKOFF#<25>
SYSON<49>
ACIN <27,50,53>
GA20<27>
EC_RSMRST#<27>PCM_SUSP#<31>
SCI#<27>
PCI_RST# <11,26,30,31,34,35,36,43>
PME_EC# <31,34,36,43,47>
PMLED_1# <44,45>
BATLED_0#<44,45>
PWR_BACK#<42>
PWR_ACTIVE_PAV#<42>
VTT_PWRGD <24,27,48>
PWR_ACTIVE_PRES#<42>
PRES_LEDVCC <42,44>
VOLBTN-# <38,41,44>
ON/OFF# <45>
CAPSLED# <42>
EC_THERM# <27>
TP_OFF_LED# <42>
EC_ON <45>
DAC_BRIG <25>
INVT_PWM <25>
CONA# <37,41>
EN_FAN2 <7>
FRD# <47>
SLP_S5# <27>
WIRELESS_BTN <38,42>
JACK_DET# <41>
FWR# <47>
M_SEN# <25>
BEEP# <37>
FSTCHG <52>
PWRBTN_OUT# <27>
LID_SW#<45>
EN_FAN1 <7>
EC_MUTE#<38>
BATT_OVP <52>
FANSPEED2 <7>
FANSPEED1 <7>
NUMLED# <42>
KSO16 <42>
EC_SMD_2 <7>
LID_OUT# <27>
EC_SMC_1 <47,51>
KBRST#<27>
SLP_S3# <27>
G_RST#<31,32,36>
WL_ON <43,44>
SELIO# <47>
PM_BATLOW# <27>
EC_SMD_1 <47,51>
EC_SMC_2 <7>
ACOFF <52>
TP_CLK<44>
BATT_TEMPA <51>
IREF <52>
VOLBTN+# <38,41,44>
+3VALW
EC_AVCC
+5VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW+3VS
+3VS
+5VALW
+3VALW
+3VS
+3VALW
+5VS +5VS
+5V
BATT1.1EC_AVCC
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
KBD EC CTRL-NS PC87591L
46 66Wednesday, September 24, 2003
Compal Electronics, Inc.
(BADDR1)
1 1
0
ENV0
(BADDR0)
1 0
PROG
0 1
0
DEV
0 0
0
OBD
(ENV1)
TRIS
BADDR1-0
1
IRE
I/O Address
1
TRIS=1: While in IRE and OBD, float all the signals for clip-on ISE use
(SHBM)
1
Reserved
EC DEBUG port
(HCFGBAH, HCFGBAL)+1
SHBM=1: Enable shared memory with host BIOS
1
(HCFGBAH, HCFGBAL)
0
4F2F
0
4E
Data
*
0
2E
*
0
Index
0
ENV1
EEPROM/BATTERY
THERMAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
C3221U_0603_10V6K
R337
@10_0402_5%
R345 10K_0402_5%
C9111U_0603_10V6K
R929@1K_0402_5%
R333
10K_0402_5%
R331
10K_0402_5%
C326
0.1U_0402_10V6K Host interface
Key matrix scan
JTAG debug port
PS2 interface
AD Input
DA output
PWMor PORTA
PORTB
PORTC
PORTE
PORTH
PORTI
PORTJ-1
PORTD-1
PORTD-2 PORTJ-2
PORTK
PORTL
PORTM
U15
PC87591L-VPCN01 A2_LQFP176
RP24
10K_0804_8P4R_5%
L32
MURATA BLM11A20PT_0603
R114810K_0402_5%
R1175
1K_0402_5%
R340 20M_0603_5%
R986
@0_0402_5%
R926 @0_0603_5%
J1 JOPEN
C320
0.1U_0402_10V6K
JP21
@96212-1011S
R332
10K_0402_5%
R985 @0_0402_5%
R335
10K_0402_5%
R1169 10K_0402_5%
R336 10K_0402_5%
R342 20K_0402_5%
C318
4.7U_0805_6.3V6K
R96010K_0402_5%
C327
1000P_0402_50V7K
C33110P_0402_50V8K
C321
0.01U_0402_16V7K
R1170 10K_0402_5% D36 RB751V_SOD323
L33MURATA BLM11A20PT_0603
C325 0.01U_0402_16V7K
C319
0.1U_0402_10V6K
R1171 10K_0402_5% R1162 10K_0402_5%
R95910K_0402_5%
R9311K_0402_5%
RP23
10K_0804_8P4R_5%SD309100200
R984 0_0402_5%
R1172 10K_0402_5%
C329
@15P_0402_50V8J
C3280.22U_0603_10V7K
C33010P_0402_50V8K
C323
4.7U_0805_6.3V6K
R1147
6.2K_0402_5%
R338 10K_0402_5%
R344
10K_0402_5%
R113533_0402_5%
Y3
32.768KHZ_12.5P_MC-306
R341120K_0402_5%
R927 0_0603_5%
R334
@10K_0402_5%
R1163 10K_0402_5%
R1123@10K_0402_5%
@
C324
0.1U_0402_10V6K
KBA5
FWE#
KBA12
KBA[0..19]
ADB2
FWE#
KBA3
KBA8
KBA0
KBA17
ADB5
KBA1
ADB0
KBA11
KBA6KBA13
ADB1
KBA15
ADB6
KBA10
ADB7
KBA4
FSEL#
KBA7
ADB[0..7]
ADB3
KBA16
KBA2
KBA9
KBA14
KBA18
ADB4
FRD#
ADB5
ADB1
ADB4
ADB2ADB3
KBA2
ADB0
ADB7
SELIO#
ADB6
LARST#
ADB3ADB2
KBA19
RESET#
KBA13
KBA9
ADB4
KBA0
ADB6
KBA15
FSEL#KBA2
KBA6
ADB7
ADB5
FRD#KBA4
KBA10KBA11
KBA5
KBA7
KBA1
KBA12
ADB1
KBA18
KBA16
KBA8FWE#
KBA3
KBA17
KBA14
ADB0
KBA17
ADB7
KBA2
KBA18
ADB4
ADB0
KBA12
KBA10
RESET#
KBA7
ADB6
KBA16
FSEL#
ADB3
KBA15
FWE#
KBA14
ADB1
KBA19
KBA3KBA4
KBA9
KBA6
ADB5
KBA5
KBA0
KBA13
KBA8
ADB2
KBA1
KBA11
FRD#
EC_SMC_1<46,51>
ADB[0..7]<46>
EC_FLASH# <27>
FWR# <46>
EC_SMD_1<46,51>
KBA[0..19]<46>
MDM_PME#<31,34,36,43,46>ONBD_LAN_PME#<31,34,36,43,46>
PME_EC# <31,34,36,43,46>WLAN_PME#<31,34,36,43,46>
PCM_PME#<31,34,36,43,46>
FSEL#<46>FRD#<46>
SELIO#<46>
USB20_PME#<31,34,36,43,46>
SUSP# <46,49>
+3VALW
+3VALW+3VALW
+3VALW +3VALW +3VALW
+3VALW
+5VALW
+3VALW
+3VALW
+3VALW
+3VALW
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
BIOS & EC I/O Port
47 66Wednesday, September 24, 2003
Compal Electronics, Inc.
OUTPUT
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
U 1 8 ASN74LVC32APWLE_TSSOP14
R360@100K_0402_5%
C333 @0.1U_0402_16V7K
R3564.7K_0402_5%
R354
10K_0402_5%
JP22
@SUYIN-80065A-040G2T
U20
@SST39VF080-70_TSOP40
U19
512K8-90_PLCC32
U18CSN74LVC32APWLE_TSSOP14
G
D S
Q29 2N7002 1N_SOT23
R359100K_0402_5%
C338
0.1U_0402_10V6K
R357100K_0402_5%
R358100K_0402_5%
C334
@1U_0603_10V6K
U21
AT24C164-10SC_SO8
R352
@20K_0402_5%
U17
@SN74HCT273PW_TSSOP20
C336
0.1U_0402_10V6K
C337
0.1U_0402_10V6K
TV_COMPS
TV_LUMAL
TV_CRMATV_COMPSLTV_CRMAL
TV_LUMA
SUSP
NB_PWRGD <8>
SB_PWRGD <27>
TV_COMPS<11,17,41>TV_CRMA<11,17,41>
TV_GND<41>
TV_LUMA<11,17,41>
VCORE_PWRGD<56>
SUSP<49,55>
VTT_PWRGD <24,27,46>
+3VALW
+2.5VS
+3VALW +3VALW+3VALW
+3VS
+3VALW
+3VS
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
POWER GOOD & P/S2 CKT
48 66Wednesday, September 24, 2003
Compal Electronics, Inc.
TV_OUT CONNECTOR
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR BOM 92.09.01
R188
75_0402_5%
D20
DAN217_SOT23
U 3 2 E
SN74LVC14APWLE_TSSOP14
R603
330K_0603_5%
C111
@68P_0402_50V8K
R1106
330K_0402_5%
L7 CHB1608B121_0603
R610
47K_0402_5%
R1107
1K_0402_5%
R608
1K_0402_5%
U18D
SN74LVC32APWLE_TSSOP14
L8 CHB1608B121_0603
R190
75_0402_5%
R961
0_0603_5%
U32D
SN74LVC14APWLE_TSSOP14
R189
75_0402_5%
G
D
S
Q110
@2N7002_SOT23
G
D
S
Q52
2N7002_SOT23
C110
@68P_0402_50V8K
R605
1M_0402_5%
U 3 2 B
SN74LVC14APWLE_TSSOP14
U32C
SN74LVC14APWLE_TSSOP14
C606
0.1U_0402_16V7K
C115
@68P_0402_50V8K
R601
10K_0402_5%
R606
10K_0402_5%
R604 47_0603_5%
D19
DAN217_SOT23
C607
0.47U_0603_10V7K
L4 CHB1608B121_0603
G
D
S
Q111
@2N7002_SOT23
C114
@68P_0402_50V8K
C112
@68P_0402_50V8K
C113
@68P_0402_50V8K
JP7
SUYIN_35138S-07T1-DF
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SYSON
SUSP SUSP
SUSP
SUSP
SYSON#
SUSPSUSP
SUSP
SYSON#
SYSON# SUSP
SUSP SUSP
SUSP
SYSON#
SUSP SYSON# SYSON#SYSON#
SUSP#<46,47>
SUSP<48,55>
SYSON<46>
+2.5VALW
+3VALW
+1.8VS
+2.5V
+5VALW
+2.5VS
+5VS
+12VALW
+5VALW
+3VS
+2.5VS
+5VALW
+3VS +5VS+1.25VS
+12VALW
+2.5VALW
+3V+3VALW
+5V+5VALW
+12VALW
+12VALW +12VALW
+12VALW
+1.5VSP +1.5VS+12VALW
+1.2VS_VGA+2.5V+5V+1.5VS +3V
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
DC/DC Circuits
49 66Wednesday, September 24, 2003
Compal Electronics, Inc.
+3VALW to +3VS Transfer
+2.5VALW to +2.5V Transfer
Discharge circuit
+5VALW to +5VS Transfer
+2.5V to +2.5VS Transfer
+3VALW to +3V Transfer
+5VALW to +5V Transfer
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(6A,240mils ,Via NO.= 12)
+1.5VSP to +1.5VS Transfer
Place close to PJP4L(0.5A(VGA)+0.83A(VGA_RAM)+0.14A(SB)=1.5A,60mils,)
G
D
S
Q39
2N7002 1N_SOT23
C350
10U_0805_6.3V6M
U23
SI4800DY_SO8
C959
10U_0805_6.3V6M
R362
100K_0402_5%
R1101
68K_0402_5%
G
D
S
Q43
2N7002 1N_SOT23
C346
10U_0805_6.3V6M
R1102
470_0402_5%
R1094
470_0402_5%
G
D
S
Q41
2N7002 1N_SOT23
G
D
S
Q382N7002 1N_SOT23
G
D
S
Q40
2N7002 1N_SOT23
R376
470_0402_5%
R369
10K_0402_5%
U56
SI4800DY_SO8
G
D
S
Q322N7002 1N_SOT23
C355
10U_0805_6.3V6M
C347
0.1U_0402_10V6K
G
D
S
Q102
2N7002 1N_SOT23
C627
0.1U_0402_10V6K
U24
SI4800DY_SO8
G
D
S
Q109
2N7002 1N_SOT23
C357
10U_0805_6.3V6M
C342
10U_0805_6.3V6M
R373
10K_0402_5%
C344
10U_0805_6.3V6M
R363
95.3K_0603_1%
G
D
S
Q42
2N7002 1N_SOT23
G
D
S
Q732N7002 1N_SOT23
R902
95.3K_0603_1%
G
D
S
Q742N7002 1N_SOT23
C844
0.1U_0402_10V6K
C358
0.1U_0402_10V6K
U25
SI4800DY_SO8
U22
SI4800DY_SO8
C352
0.1U_0402_10V6K
R372
470_0402_5%
R1095
470_0402_5%
C359
10U_0805_6.3V6M
C625
0.1U_0402_10V6K
R904
47K_0402_5%
C356
0.1U_0402_10V6K
C354
0.1U_0402_10V6K
C360
0.1U_0402_10V6K
C341
10U_0805_6.3V6M
R375
470_0402_5%
C960
0.1U_0402_10V6K
C353
10U_0805_6.3V6M
U26
SI4800DY_SO8C343
0.1U_0402_10V6K
G
D
S
Q115
2N7002 1N_SOT23
G
D
S
Q36
2N7002 1N_SOT23G
D
S
Q103
2N7002 1N_SOT23
C351
10U_0805_6.3V6M
R374
470_0402_5%
G
D
S
Q762N7002 1N_SOT23
R901
6.8K_0402_5%
C626
10U_0805_6.3V6M
C961
10U_0805_6.3V6M
U36
SI4800DY_SO8
C962
0.1U_0402_10V6K
R378
470_0402_5%
G
D
S
Q752N7002 1N_SOT23
C348
0.1U_0402_10V6K
R377
470_0402_5%
R1116
470_0402_5%
R903
100K_0402_5%
C345
0.1U_0402_10V6K
G
D
S
Q312N7002 1N_SOT23
G
D
S
Q108
2N7002 1N_SOT23
C624
10U_0805_6.3V6M
G
D
S
Q342N7002 1N_SOT23
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
ADPIN
PACIN PACIN
ACIN <27,46,53>
PACIN <52>
MAINPWON<7,51,53>
DCSRD<52>
DC_IN
VL B+
DC_IN DC_IN
VS
VL
VS
ADPIN
+5VALW
RTCVREF
Size Document Number R e v
Date: Sheet o f
1.0
Detector
50 66Wednesday, September 24, 2003
Compal Electronics, Inc.
Detector
Vin Detector
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
ACIN
Precharge detector16.421 15.817 15.22914.108 13.657 13.002
BATT
detector15.029 14.095 13.18712.636 11.850 10.860
17.788 17.438 17.09017.277 16.928 16.585
PIR POWER 92.08.04
3.3V
PR682.5K_0603_0.1%
G
D
S
PQ46
2N7002_SOT23
PR81K_0603_5%
PC
1010
00P
_060
3_16
V7K
PR5
499K
_060
3_1%
PC2
1000
P_0
402_
50V
7K
PR3432K_0603_1%
PC1
100P
_060
3_50
V8J
PJP18
PAD-OPEN 4x4m
PD22
RB751V_SOD323
PZD1
RLZ4.3B_LL34
PU1BLM393M_SO8
PCN1
FOX_JDP1021
PR1410K_0603_5%
PR21M_0402_1%
PR710K_0603_5%
PR192
47K_0603_5%
PR110K_0603_5%
PR1210K_0603_5%
PC8
1000
P_0
603_
16V
7K
PC9
1000
P_0
603_
50V
7K
PJP17PAD-OPEN 4x4m
PC6
1000
P_0
402_
50V
7K
PD43
SBM1040-13_POWERMITE3
100K
100K
PQ47
DTC115EKA_SOT23
PC50.01U_0603_50V7K
PR1010K_0603_5%
PC4
1000
P_0
402_
50V
7K
PC7
0.1U
_060
3_16
V7K
PR41M_0603_0.5%
PR
191
499K
_060
3_1%
PU1ALM393M_SO8
PC3
100P
_060
3_50
V8J
PR915K_0603_0.5%
PD1
RB751V_SOD323
PR
1120
K_0
603_
0.1%
PL1FBM-L18-453215-900LMA90T_1812
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
EC_SMCAEC_SMDATS_A
N1C H G R T C P
N3
N2
EC_SMC_1 <46,47>
BATT_TEMPA <46>
EC_SMD_1 <46,47>
EC_PWR_ON#<45>
MAINPWON <7,50,53>
H_PROCHOT# <5,26>ADP_I<46,52>
BATT+
VMB
+3VALWP
+5VALWP
RTCVREF
DC_IN
CHGRTC
BATT+
B+
VS
VS
VL
VL
VREF
VREF
VS
Title
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
BATTERY CONN / OTP
51 66Wednesday, September 24, 2003
Compal Electronics, Inc.
PH2 near main Battery CONN :
Recovery at 45 degree CBAT. thermal protection at 84 degree C
3.3V
PR23200K_0603_1%
PR38
100K_0603_5%
12
PR2147K_0603_5%
12
PR29
1.5K_1206_5%
PC180.1U_0805_25V7K
12
PR17
1M_0603_1%
PC17
0.22U_1206_25V7K
12
PR27
1.5K_1206_5%
PR39
22K_0603_5%
PC
2110
00P
_040
2_50
V7K
1
2
PR230
200_0603_5%
PR19
100_0603_5%
12
PD10
RLZ16B_LL34
21
PR3616.9K_0603_1%
PR3247K_0402_1%
G
D
S
PQ12N7002_SOT23
13
PC111000P_0603_50V7K
12
PR22
11.5K_0603_1%
PD5@BAS40-04_SOT23
@
1
32PC141000P_0603_50V7K
12
PR25
100K_0603_1%
12
PH1
10K
_TH
11-3
H10
3FT
_060
3_1%
12
PR24
25.5K_0603_1%
PL2
C8B BPH 853025_2P
PR42150K_0402_1%
12
PR193
75K_0603_1%
PD9
RLZ3.6B_LL34
PD6
1N4148_SOD80
PU2A
LM393M_SO8
P8
G4
PC
201U
_080
5_16
V7K
12
PU2B
LM393M_SO8
P8
G4
PC151000P_0603_50V7K
12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
PC120.01U_0603_50V4Z
12
PR41
200_0603_5%
12
PR261K_0603_5%
12
PD4
@BAS40-04_SOT23@
1
3 2
PC2310U_1206_10V4Z
12
PR302.15K_0603_1%
12
PC970.01U_0603_50V4Z
12
PR18100_0603_5%
12
PD3@BAS40-04_SOT23
@
PR28
1.5K_1206_5%
PC22
1U_0805_50V4Z
12
PU3S-81233SGUP-T1_SOT89
11
PD7
1N4148_SOD80 1
2
PR43
200_0603_5%
PCN2
SUYIN_200275MR009G130ZL
PR40
150K_0402_1%
PC130.1U_0603_50V4Z
12
PD8
RB751V_SOD323
PR31
47_1206_5%
12
PQ2TP0610T_SOT23 2
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
CHGSS
N18
LXCHRG
DCSRD
ACOFF#
PACIN
ACOFF#
CHGSS
ACOFF <46>
IREF<46>
BATT_OVP<46>
FSTCHG<46>
ADP_I<46,51>
PACIN<50>
DCSRD <50>
DC_IN
BATT+
P3B+ B++
VMB +3VALWP
VL
VREF
DC_INP2
Title
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
CHARGER
52 66Wednesday, September 24, 2003
Compal Electronics, Inc.
Iadp=0~6A
CC=0.5~3ACV=16.8V(12 CELLS LI-ION)
IREF=0.73~3.3VIREF=1.1*Icharge
4.2V
OVP voltage : LI
(BAT_OVP=0.1111 *VMB)
4S3P : 18V--> BATT_OVP= 2.0V3S4P/3S3P : 13.5V--> BATT_OVP= 1.5V
PIR POWER 92.08.04PR62
10K_0603_1%
PC31
0.1U_0805_25V7K
PU4
MB3887_SSOP24
PR47
200K
_060
3_5%
12
PR64
174K_0603_1%
PR50
0_0603_5%
12
PQ3
AOS4407_SO8PL3
HCB4532K-800T90_1812
PC36
1500P_0603_50V7K
PR63
47K_0603_1%
PC39
4.7U
_121
0_25
V6K
12
PC41
4.7U
_121
0_25
V6K
12
PC34
0.1U_0603_50V4Z
PR
195
@47
K_0
402_
5%
@
12
100K
100K PQ8
DTC115EKA_SOT23
13
PR68
47K_0603_5%
12
PR54
31.6K_0603_1%
12
PR61
0.02_2512_1%
PC26
@4.7U_1210_25V6K@
12
PC38
1500P_0603_50V7K
PC42
0.1U_0603_16V4Z
12
PR5247K_0603_1%
PU5A
LM358A_SO8
P8
G4
10K
47KPQ48
@DTA144YKA_SC70
@
13
PR65
100K_0603_1%
12
100K
100K
PQ11
DTC115EKA_SOT23
13
PC24
4.7U_1210_25V6K
12
PR24715K_0603_5%
12
PQ4
AOS4407_SO8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.
PQ49@DTC115EUA_SC70@
13
G
D
S
PQ10
2N7002_SOT23
13
PC450.01U_0603_50V4Z
12
PR44
0.01_2512_1%(1W)
PR58
3K_0603_5%
G
D
S
PQ50
@2N7002_SOT23 @
13
PR240
@1K
_060
3_5%
@
12
PR60
68K_0603_5%
PR66
49.9K_0603_0.1%
PQ6
SI4835DY_SO8
365 7 8
2 1
PR72
105K_0603_0.5%
12
PC33
4700P_0603_50V7K
G
D
S
PQ9
2N7002_SOT23
13
PC
320.
1U_0
603_
16V
4Z
12
PC
98
@0.
1U_0
603_
25V
7K
@
12
PR67
150K_0603_0.1%
PR69340K_0603_1%
12
PC25
4.7U_1210_25V6K
12
PD14
SKS30-04AT_TSMA21
PC430.1U_0603_50V4Z
12
PC
350.
1U_0
603_
16V
4Z
12
PR57
1K_0603_1%
PL4
15U_SPC-1204P-150_4A_20%
PR59
1K_0603_1%PD13
1SS355_SOD323
PR51
10K_0603_5%
12
PR48
47K_0603_5%
PR70499K_0603_1%
12
PC30 2200P_0603_50V7K
PR56
10K_0603_1%
12
PC
29
@0.
47U
_080
5_25
V4Z
_V1
@
12
PC37
0.1U_0805_25V7K
PC40
4.7U
_121
0_25
V6K
12
PC28
2200
P_0
402_
50V
7K
12
PR53150K_0603_1%
12
PD30
@1SS355_SOD323
@
12
PQ5
AOS4407_SO8
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
DH3
BST51
LX3
FLYBACKSNB
DH31
DH51D H 5
DL3
BST31
LX5
DL5
ACIN
ACIN<27,46,50>
MAINPWON <7,50,51>
VS
VL
B++++
B++++
VL
+12VALWP
B+
+3VALWP
VS
2.5VREF
VL
+5VALWP
Title
Size Document Number R e v
Date: Sheet o f
1.0
5V/3.3V/12V
Compal Electronics, Inc.
53 66Wednesday, September 24, 2003
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTYOF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT ASAUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NORTHE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
INC.
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
PIR POWER 92.08.04
PIR POWER 92.08.04
PD18
SKS10-04AT_TSMA
21
PR850_0402_5%
PC
57
4.7U
_121
0_25
V6K
12
PC800.47U_0603_16V7K
12
PR91
3.32K_0603_1% 1
2
PR94@0_0402_5%
PC600.1U_0805_25V7K
12
PQ14
SI4810DY_SO8
S1
S2
S3
G4
D8
D7
D6
D5
PC
544.
7U_1
206_
10V
7K
12
PR811.27K_0603_1%
+
PC74
@15
0U_D
_6.3
VM
1
2
PR750_0402_5%
12
PR96
10.2K_0402_1%
12
PC464.7U_1210_25V6K
PC56
2200P_0402_50V
7K
12
PC68
0.47U_0603_16V7K
12
PR790_0402_5%
12
PR242620_0402_5%
PC724.7U_1206_10V7K
12
PD17
SKS10-04AT_TSMA
21
PT1
9U_SDT-1204P-100-132A_5A_30%
14
32
PC
52
@4.
7U_1
210_
25V
6K
12
PD16DAP202U_SOT323
1
2 3
PC
51
4.7U
_121
0_25
V6K
12
+
PC69
@15
0U_D
_6.3
VM
@
1
2
PR74
0_0402_5%
PC
58
4.7U
_121
0_25
V6K
12
+PC70
150U
_D2_
6.3V
M
1
2
PC47470P_0805_100V7K 1
2
PR100
10K_0402_1%
12
PC67
0.47U_0603_16V7K
12
EC11FS2PD15
12
PR950_0402_5%
PR831M_0402_5% 1
2
G
D
S
PQ51
2N7002_SOT23
13
PD19
1SS355_SOD323 12
PR243698_0402_1%
12
PQ13SI4800DY
365 7 8
2 1
PQ15SI4810DY_SO8
S1
S2
S3
G4
D8
D7
D6
D5
PL5HCB4532K-800T90_1812
12
PC73680P_0402_50V7K
12
PR78
1.54K_0603_1%
12
PC61
4.7U
_121
0_25
V6K
12
PU6
MAX1632_SSOP28
GN
D8
VL
21
V+
22
PC48
0.1U_0805_25V7K
+ PC76
150U
_D2_
6.3V
M
1
2PR9947K_0402_5%
12
PC53
0.1U_0805_25V7K
PC50
2200P_0402_50V
7K
12
PL6
10U_SPC-1204P-100_4.5A_20%
12
PR770_0402_5%
12
[email protected]_0603_16V7K
12
PR2411.27K_0603_1%
12
PC71
100P_0402_50V8J
12
PR101
100K_0603_1%
12
PR9710K_0402_1%
12
PR92300K_0402_5%
12
PC63
47P
_040
2_50
V8J
12
PC75100P_0402_50V8J
12
PR8910K_0402_5%
PR822M_0402_1%
12
PR800_0402_5%
PR
239
2.7K
_120
6_5%1
2
PR7322_1206_5%
PC6547P_0402_50V8J
12
PQ12SI4800DY
36 578
21
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCC_MAX1845
VCC_MAX1845
B+
+5VALWP
+1.5VSP +2.5VALWP
+3VALW
+2.5VALW
+VCCVID
+2.5VALWP
+12VALW
+5VALW
+1.25VS
+5VALWP
+VCCVIDP
+12VALWP
+1.25VSP
+3VALWP
+1.8VS+1.8VSP
+5VALWP
+5VALWP
Title
Size Document Number R e v
Date: Sheet o f
1.0
DDR POWER 2.5V & 1.5V
Compal Electronics, Inc.
54 66Wednesday, September 24, 2003
BMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
(150mA,40mils ,Via NO.= 2)
(120mA,20mils ,Via NO.= 1)
(2A,80mils ,Via NO.= 4)(6A,240mils ,Via NO.= 12)
(6A,240mils ,Via NO.= 12)
(8A,480mils ,Via NO.=24)
(1.5A,120mils ,Via NO.= 6)
L The related parts will be placed close to power PU7.11
PIR POWER 92.04.16
PIR POWER 92.04.16
PC890.1U_0805_50V7M
PD21
SKS10-04AT_TSMA
PC844.7U_1210_25V6K
PC834.7U_1210_25V6K
PQ18SI4810DY_SO8
PL9
4.7U_SPC-1204P4R7_5.7A_20%PQ19SI4810DY_SO8
PR2490_0402_5%
PR1050_0603_5%
PJP1PAD-OPEN 4x4m
PR1080_0603_5%
PJP8
PAD-OPEN 2x2m
PR1070_0603_5%
PR236
0_0603_5%
PC
99
0.22
U_0
603_
16V
7K
PC
964.
7U_0
805_
6.3V
6K
PC920.1U_0805_50V7M
PR
117
100K
_060
3_1%
PC
944.
7U_0
805_
6.3V
6K
PD20DAP202U_SOT323
PR115100K_0603_1%
PJP10
PAD-OPEN 3x3m
PJP16PAD-OPEN 4x4m
PC812200P_0402_50V7K
PR104
20_0603_1%
+PC
9522
0U_D
2_4V
M
PR1020_0603_5%
PC
8522
00P
_040
2_50
V7K
PC
900.
1U_0
805_
50V
7M
PR1060_0603_5%
PC884.7U_0805_10V4Z
PL7
FBM-L11-322513-151LMAT_1210
PJP3
PAD-OPEN 4x4m
PC
874.
7U_1
210_
25V
6K
PU7
MAX1845EEI_QSOP28
PR1030_0603_5%
PJP2PAD-OPEN 4x4m
PL8
4.7U_SPC-1204P4R7_5.7A_20%
PJP4
PAD-OPEN 3x3m
PD
23S
KS
10-0
4AT_
TSM
A
PQ17SI4800DY_SO8
PC
91
1U_0
805_
16V
7K
+
PC93220U_D2_4VM
PQ16
SI4800DY_SO8
PJP5
PAD-OPEN 4x4m
PJP6
PAD-OPEN 2x2m
PR116127K_0603_1%
PR248
@0_0402_5%
PR11416.9K_0603_1%
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SUSP <48,49>
VR_ON<46>
VID_PWRGD<5,56>
+1.2VS_VGA
+5VS_1.2V
+2.5VS +1.8VSP
2.5VREF
+VCCVIDP
+3VALWP
+1.25VREF
+2.5VS
+2.5VS
+1.25VSP
VL
+5VS_1.2V+5VS
Title
Size Document Number R e v
Date: Sheet o f
1.0
1.2V/1.8V/VCCVID/1.25V
Compal Electronics, Inc.
55 66Wednesday, September 24, 2003B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
(1.25V)
PIR POWER 92.04.16
PR124//PR202 = 5.08K_0603_1%M9+
M10
VGA_CORE
1.5V
PR124 = 9.09K_0603_1%1.2V
PC1770.1U_0402_10V6K
PC17610U_1206_10V4Z
PC18422U_1210_6.3V6M
PR127
5.1K_0402_5%
PC107
10P_0402_50V
8K
+ PC
103
220U
_D_2
VM
PR129
3.9K_0603_1%
PC1740.1U_0402_10V6K
PR126100_0603_5%
PQ21
SI4800DY_SO8
PC
1120.01U
_0402_16V7K
PU5BLM358A_SO8
PU27
MIC5258_SOT23-5
PR2350_0603_5%
PR1224.64K_0603_1%
C
BE
PQ242SC4672_SOT89
PC106
470P_0402_50V
7K
PL10
2.2UH_SPC-1205P-2R2B_13A_30%
PR218100K_0402_1%
G
D
S
PQ25
2N7002_SOT23
PR1190_0603_5%
PR
124
9.09
K_0
603_
1%
+
PC
173
150U
_D2_
6.3V
M
PC1750.1U_0402_10V6K
PR128
15_0603_5%
PD24
1SS355_SOD323
PC111560P_0402_50V7K
[email protected]_0603_1%@
+ PC
104
220U
_D_2
VM
PC110
68P_0402_50V8J
PC1724.7U_0805_10V4Z
PC10022U_1210_6.3V6M
PR121
180K_0603_1%
PC102
10U_0805_6.3V
4Z
PU8
MAX1954
PR123
0_0603_5%
PR
125
5.1K_0402_5%
PJP15
PAD-OPEN 4x4m
PC179
0.1U_0402_10V6K
PU16
NE57814
PC1010.1U_0402_10V6K
PR130
10K_0603_1%
PQ23 SI4810D
Y_S
O8
PC1781U_0603_10V6K
PC1714.7U_0805_10V4Z
PR2170_0603_5%
CM-
CM+
BSTM
CORE_REF
BSTM
OAIN-
OAIN+
OAIN+
FB
OAIN-
FB
OAIN+
OAIN+
OAIN+
OAIN-
FB
SKIP#
CORE_REF
VID5<5>
VID4<5>
VID3<5>
VID1<5>
VID2<5>
VID0<5>
VCCSENSE<5>
CORE_REF<57>
VID_PWRGD<5,55>
DLM<57>
CM+ <57>CM- <57>
D L S<57>
VSSSENSE<5>
VCORE_PWRGD<48>
CPUCLK_STP# <5,11,26>
CORE_REF <57>
H_BOOTSELECT<4>
CS- <57>
CS+ <57>
DPRSLPVR<26>
SKIP# <57>
VCCSENSE <5>
+CPU_B+
B+
+CPU_B+
+VCC_CORE
+VCC_CORE
+5VS_CORE
+VCCVID
+5VS_CORE
+5VS +5VS_CORE
+5VS_CORE
+VCC_CORE
+5VS_CORE
Title
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
CPU_CORE(1)
A3
56 66Wednesday, September 24, 2003
(120mA,20mils ,Via NO.= 1)
PIR POWER 92.04.16
PIR POWER 92.04.16
PIR POWER 92.04.18
H_BOOTSELECT=1
H_BOOTSELECT=0
PRESCOTT
NORTHWOOD
1. When mode control signal ishigh/ low, the VR will operate toNorthwood/ Prescott load line. 2. VID5(12.5) should be pulledhigh, when the VR operates toNothwood load line.
PIR POWER 92.08.04
PD29
SKS30-04AT_TSMA
21
PC
118
4.7U
_121
0_25
V6K
12
PR1582.87K_0603_1%
12
PR246
0_0402_5%
PR2240_0402_5%
PD28
CH
P202U
_SC
70
1
32
PC
116
4.7U
_121
0_25
V6K
12
PR2450_0402_5%
PR2220_0402_5%
PR138
@0_0402_5%
PR
180
2.87K_0603_1%
12
PQ26
MM
BT
3904
_SO
T23
C1
E3
B2
PR164499_0402_1%
12
PR1461K_0603_1%
12
PQ31IRF7832_S
O8
365 7 8
2 1
PC
133
4.7U
_121
0_25
V6K
12
PC136470P_0402_50V7K
12
PR227
0_0402_5%
PR13730.1K_0603_1%
PR136
100K_0402_1%
12
PR109@100K_0402_1%
PR111
22.6_0402_1%
PC
131
4.7U
_121
0_25
V6K
12
[email protected]_0402_1%
@
PR2230_0402_5%
PR1689.31K_0603_1%
PC1280.22U_0402_10V4Z
12
PR1660_0402_5%
PC
125
2.2U_0805_16V
4Z
12
PR1450.001_2512_5%
PR159100K_0402_1%
PR165100K_0402_1%
12
PQ30SI7392DP_SO8
3 2 1
5
PR132
0_0402_5%
PR
133
10K
_040
2_5%
12
PR149@0_0402_5%
@
12
PQ27SI7392DP_SO8
3 2 1
5
PC141
0.47U_1206_16V7K
PR153499_0402_1%
12
PC
117
4.7U
_121
0_25
V6K
12
PC142@100P_0603_50V8G
@
12
PC129@4700P_0402_25V7K
@
12
PC
120
0.1U
_080
5_25
V7K
12
PR1630_0402_5%
+PC130
100U_25V_M
1
2
PR154
100K_0402_1%
PU9
MAX1546
PC124
0.47U_1206_16V7K
PC1150.22U_0402_10V4Z
PR2210_0402_5%
PC
126
1000
P_0
402_
50V
7K
12
PC
134
2200
P_0
402_
50V
7K
12
PR144
47K_0402_1%
12
PC180
100P_0402_50V8J
PC1140.22U_0603_10V7K
12
PR
148
0_0402_5%
12
G
D S
PQ43
2N7002_SOT23
2
PC1821000P_0402_50V7K
12
PR167
100K_0402_1%
12
PD26
SKS30-04AT_TSMA
21
PJP14
PAD-OPEN 2x2m
PC139
0.022U_0603_50V
4Z
12
PR1570_0402_5%
PQ45
2N70
02_S
OT
23
D1
S3
G2
PR171
1k_0603_1%
PQ29
IRF7832_SO8
365 7 8
2 1
PR14710_0603_1%
PR141
0_0402_5%
PR140100K_0402_1%
12
PC122
270P_0402_50V
7K
12
PR1621K_0603_1%
12
PR1560_0402_5%
PQ28
IRF7832_S
O8
365 7 8
2 1
PL11FBM-L18-453215-900LMA90T_1812
PC
132
4.7U
_121
0_25
V6K
12
PR244
@0_0402_5% @
PL130.7U_ETQP2H0R7BFA_21A_20%
PR161
150K_0402_1%
PR1700_0402_5%
12
PC
119
2200
P_0
402_
50V
7K
12
PR110
10.2_0402_1%
12
PR2250_0402_5%
PD27SKS30-04AT_TSMA
21
PR150_0402_5%
12
PR160
20K_0402_1%
PC140
100P_0603_50V
8J
12
PR155
0_0603_5%
PC138
100P_0603_50V
8J
12
G
D
SPQ33
2N7002_SOT23
13
PR2200_0402_5%
PR143
0_0603_5%
PR173
1k_0603_1%
G
D
S
PQ202N7002_SOT23
13
PC
135
0.1U
_080
5_25
V7K
12
PR135
100K_0402_1%
12
PQ32IRF7832_S
O8
365 7 8
2 1
PC181470P_0402_50V7K
12
PL120.7U_ETQP2H0R7BFA_21A_20%
PQ44
2N70
02_S
OT
23
D1
S3
G2
PR139
0_0402_5%
PC1231U_0603_10V6K
12
G
D
S
PQ402N7002_SOT23
13
SKIP#
CS- <56>
CS+ <56>
CORE_REF<56>
CM- <56>
CM+ <56>
DLM<56>
SKIP# <56>
D L S<56>
+VCC_CORE
+CPU_B+
+CPU_B+
+VCC_CORE
+VCC_CORE
+VCC_CORE
+5VS_CORE
+5VS_CORE
Title
Size Document Number R e v
Date: Sheet o f
1.0
+CPU_CORE(2)
Compal Electronics, Inc.
57 66Wednesday, September 24, 2003
PC
146
4.7U
_121
0_25
V6K
12
PQ
35
IRF7
832_
SO
8
S1
S3
G4
D8
D7
D6
D5
S2
PC
160
4.7U
_121
0_25
V6K
12
PR2010_0603_5%
PC1510.22U_0603_16V7K
12
PC170
100P_0603_50V8J
12
PC154
1000P_0603_16V7K
12
PU10
MAX1980
DD
/1
3T
RIG
20
PD36
SKS30-04AT_TSMA
21
PU11
MAX1980
DD
/1
3T
RIG
20
PR21049.9K_0603_1%
12
PL14
0.7U_ETQP2H0R7BFA_21A_20%
PR1780_0603_5%
PC
158
2.2U
_080
5_16
V4Z
12
PC
159
4.7U
_121
0_25
V6K
12
PR18949.9K _0402_1%
12
PR20620K_0603_1%
PC166
0.47U_1206_16V7K
PC
156
100P
_060
3_50
V8J
12
PC1672200P_0402_50V7K
PR196
0_0603_5%
PR174
0_0603_5%PC1500.22U_0603_16V7K
12
PR172
0_0603_5%
PR
181
1K_0
603_
1%1
2
PC155
1000P_0603_16V7K
12
PC
161
4.7U
_121
0_25
V6K
12
PQ37SI7392DP_SO8
3 2 1
5
PQ
39
IRF7
832_
SO
8
S1
S3
G4
D8
D7
D6
D5
S2
PC
145
4.7U
_121
0_25
V6K
12
PC164
0.22U_0603_16V7K
12
PC168
1000P_0603_16V7K
12
PR18320K_0603_1%
PC1630.1U_0805_25V7K
12
PC152
0.47U_1206_16V7K
PL15
0.7U_ETQP2H0R7BFA_21A_20%
PD33
1SS355_SOD323
PC162
2200
P_0
402_
50V
7K
12
PR19810_0603_1%
12
PC
149
2.2U
_080
5_16
V4Z
12
PC169
1000P_0603_16V7K
12
PC
147
4.7U
_121
0_25
V6K
12
PC165
0.22
U_0
603_
16V
7K
12
PD35
@1SS355_SOD323
PD42SKS30-04AT_TSMA2
1
PC
144
0.1U
_080
5_25
V7K
12
PR1870_0603_5%
12
PR1880_0603_5%
12
PQ
38
IRF7
832_
SO
8
S1
S3
G4
D8
D7
D6
D5
S2
PR200
0_0603_5%
PC
148
2200
P_0
402_
50V
7K
12
PQ
36
IRF7
832_
SO
8
S1
S3
G4
D8
D7
D6
D5
S2PR184
200K_0603_1%
12
PR1990_0603_5%
PR17610_0603_1%
12
PD41
@1SS355_SOD323
PR1770_0603_5%
PR
204
1K_0
603_
1%
12
PC1532200P_0402_50V7K
PR207
200K_0603_1%
12
PQ34SI7392DP_SO8
3 2 1
5
PD39
1SS355_SOD323
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
58 66Wednesday, September 24, 2003
Compal Electronics, Inc.
Changed-List History-1
Version Change List ( P. I. R. List ) for Power CircuitItem Issue Descr ipt ionDate
RequestOwner Solution Description Rev.Page#
1 0.2
0.2
Tit l e
2
3
change to correct layout pad on PU7, PU8, PU9, PU10, PU11, PU16 and PQ24
54,55, 56,57
03/25/2003 Compal
DPRSLPVR56 03/25/2003Reserve two resistors for voltage of Deep-sleeper mode Reserver PR231, PR232, PR233, PR234
for deeper-sleeper mode voltage setting
03/25/2003 Reserve a jumper for power consumption measurement56 CPU VR-Cont.
4
Add PJP14
57 Compal Change Netname of +5VS_CORE
5 51 RTC charger Add PR230
wrong layout pad
wrong layout pad
Compal
Compal
CPU VR-Cont. 03/25/2003 Change the netname +5VS_CORE for powerconsumption measurement
03/25/2003 Compal use two resistors for RTC charger protection
0.2
0.2
0.2
6 re-located both PL10 and PQ21, PQ23 as well as 1.2VS_VGA related power circitry
55 1.2VS_VGA 03/25/2003 Compal re-layout 1.2V_VGA requested by ME
7 55 1.2VS_VGA 03/26/2003 Compal Reserve a jumper for power consumption measurement Add PJP15
0.2
0.2
8 55 +1.25VSP 03/26/2003 Compal Change power time-sequence of 1.25VSP input power Change VD, and VDD of PU16 from +2.5VALWPto +2.5VS; Connect PR235.2 to +2.5VSadd a resistor PR235 for Stand/By pin for test
0.2
9 03/27/2003 Compal Add PR237, PR238 for force PWM function control, and add PR236 for SUSP# signal
54 +1.5VALWP Reserve Force PWM function of 1.5V/2.5V and add a PR236 for SUSP# signal 0.2
1
1
2
2
3
3
4
4
5
5
1 1
2 2
3 3
4 4
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
H/W2 EE Dept. PIR SHEET(1)
59 66Wednesday, September 24, 2003
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
----PLEASE SEE NEXT PAGE
BHR60 from DB-1 to DB-2 STEP LA-1811 REV:0.1 -> 0.2 Modify <92.03.17.~92.03.24. >
-Add U53(SI9185),C913,R1023,C912,C914 and related net . (Modify CKT,BOM&Layout)1.Add an independent power source for VGA chip because of ATI request . <Page 12> 92.03.17.
-Add U54(NEC_uPD720101F1-EA8),R1024~R1047,R1049,R1051,R1053,R1054,C915~C929,U55(AT24C02),RP147,RP148,R102,R1059,R1062;Del RP127 . (Modify CKT,BOM&Layout)
3.Change the USB2.0 Controller chip from ATI to NEC and modify the net for Customer request . <Page 26,27,36,44> 92.03.18.
-Add R1063(39K_0603_1%);Del R768(0_1206_5%) . (Modify CKT,BOM&Layout)4.Modify the Audio related schematic for Customer request . <Page 37,38> 92.03.20.
-Change C894,C896 from 1U_0603_10V6K to 0.1U_0603_16V7K . (Modify CKT&BOM)-Change R974 from @100K_0402_5% to 100K_0402_5% . (Modify CKT&BOM)
-Add R1048,R1050,R1052 . (Modify CKT&Layout)
2.Modify the Audio related schematic for Customer request . <Page 37> 92.03.17.-Add Q101(2N7002);Del R948(2.2K_0402_5%);Modify R746(2.2K_0402_5%) . (Modify CKT,BOM&Layout)
-Change JP41.3 from GNDA to +5VAMP. (Modify CKT&Layout)
15.Modify the schematic after rev0.1 debug by Brian . <Page 12,17,26,29> 92.03.24.
-Add R1071,R1075,R1090,R1091(ATI@0_0402_5%) . (Modify CKT&Layout)
-Add RP149(@0_0404_4P2R_5%) . (Modify CKT&Layout)9. Add the power source +5V and +1.5VS discharge circuit for ATI request . <Page 49> 92.03.23.
-Add C937~C946,C862,C863,C865~C871(0.1U_0402_10V6K) . (Modify CKT,BOM&Layout)
-Add R1094,R1095(470_0402_5%),Q102,Q103(2N7002 1N_SOT23) . (Modify CKT,BOM&Layout)
6.Modify the USB2.0 related for Compal ATI/NEC Dual Layout request . <Page 27,44> 92.03.21.
5.Modify the MiniPCI and BlueTooth conn related schematic for Customer request . <Page 43,44> 92.03.21.-Add R1083,R1084,R1085(@0_0402_5%) . (Modify CKT&Layout)-Change R300 from 100_0402_5% to @100_0402_5% . (Modify CKT&BOM)
-Change R976,R977,R978,R979,R982,R983 from 0_0402_5% to ATI@0_0402_5% and the net . (Modify CKT,BOM&Layout)
-Change R1083,R1084 from @0_0402_5% to 100_0402_5% . (Modify CKT&BOM)-Add C957(10U_0805_10V3M),C958(0.1U_0402_10V6K) . (Modify CKT,BOM&Layout)
12. Del Via Hole on schematic for ME modify . <Page 41> 92.03.24.-Del H15(H_C374D295),H29(H_C197D91) . (Modify CKT,BOM&Layout)
7.Add De-coupling capacitor for AGP power pins on RC300M and VGA chip because of ATI request . <Page 10> 92.03.21.
10. Modify the ON1 related to speed up the power sequence for ATI request . <Page 48,54> 92.03.23.
8. Reserve the SMBus1/2 swap Resistors for ATI request . <Page 27> 92.03.23.-Add RP150(0_0404_4P2R_5%) . (Modify CKT,BOM&Layout)
-Add R1069,R1070,R1072,R1073,R1074,R1076,R1077,R1078,R1092,R1093(NEC@0_0402_5%) . (Modify CKT,BOM&Layout)
-Change C347,C360 from 0.1U_0402_10V6K to 3900P_0402_50V7K;C356,C348 from 0.01U_0402_16V7K to 2200P_0402_25V7K . (Modify CKT&BOM)
14.Swap the USB20*P3* and USB20*P5* for Customer request . <Page 44> 92.03.24.-Modify R1079~R1082,JP43,R980,R981's connection . (Modify CKT&Layout)
13.Modify the MiniPCI and BlueTooth conn related for Customer request . <Page 43,44> 92.03.24.
-Add C956(180P_0603_50V8J) . (Modify CKT,BOM&Layout)
A-TEST SMT BUILT
-Change R1010 from @0_0603_5% to 0_0603_5%;R1011 from 0_0603_5% to @0_0603_5%;Q15 from 2SC2411K_SOT23 to @2SC2411K_SOT23;R145 from 4.7K_0402_5% to @4.7K_0402_5%;R146 from @4.7K_0402_5% to 4.7K_0402_5%;R967 from @10K_0402_5% to 10K_0402_5%;R833 from @0_0402_5% to 0_0402_5% . (Modify CKT&BOM)
-Add R1096,R1097(10K_0402_5%),Q1043(2N7002 1N_SOT23),Q105(DTC124EK_SC59);Del PR113(47K),PC183(0.1U) . (Modify CKT,BOM&Layout)
11. Modify power source CAP.'s value by Brian . <Page 26,49> 92.03.24.
-Change R972 from 100K_0402_5% to @100K_0402_5% . (Modify CKT&BOM)
16.Modify the schematic H_BOOTSELECT related by Power Team . <Page 04> 92.03.25.-Add Q106(2SC2411K_SC59),Q107(MMBT3904_SOT23),R1099,R1100(47K_0402_5%) . (Modify CKT,BOM&Layout)-Change R899 from 0_0402_5% to 22K_0402_5%,R900 from @0_0402_5% to 100K_0402_5% . (Modify CKT&BOM)
17.Add a power transfer circuit to fix +1.5VS leakage issue . <Page 49> 92.03.25.-Add U56(SI4800DY_SO8),Q108(2N7002 1N_SOT23),R1101(100K_0402_5%),C960(0.1U_0402_10V6K),C961(10U_1206_6.3V6M),C962(3900P_0402_50V7K) . (Modify CKT,BOM&Layout)
-Change C347,C360,C962 from 3900P_0402_50V7K to 0.1U_0402_10V6K;C356,C348 from 2200P_0402_25V7K to 0.1U_0402_10V6K;C627,C844 from 1000P_0402_50V7K to 0.1U_0402_10V6K . (Modify CKT&BOM)
18. Modify power source Resistor and CAP.'s value for power sequence . <Page 49> 92.03.26.
-Change R903,R362 from 100K_0402_5% to 91K_0402_5% . (Modify CKT&BOM)-Change R902,R363 from 100K_0402_5% to 95.3K_0603_1% . (Modify CKT,BOM&Layout)
19. Modify the ON1 related to speed up the power sequence for ATI request by Brian/James/CT . <Page 48,54> 92.03.26.-Del R1096,R1097(10K_0402_5%),Q1043(2N7002 1N_SOT23),Q105(DTC124EK_SC59) . (Modify CKT,BOM&Layout)
20. Add the power source +3VS discharge circuit by Brian . <Page 49> 92.03.26.-Change Q42 from @2N7002 1N_SOT23 to 2N7002 1N_SOT23 . (Modify CKT&BOM)
21. Change the Resistor's value for ATI recommend . <Page 17 > 92.03.26.-Change R264 from 169_0603_1% to 2N7002 1N_SOT23 . (Modify CKT&BOM)
23. Add the power source +3V discharge circuit for ATI request . <Page 49> 92.03.27.-Add R1102(470_0402_5%),Q109(2N7002 1N_SOT23) . (Modify CKT,BOM&Layout)
22. Correct material layout footprint and pin define . <Page 26,34 > 92.03.26.-Change Y1,Y3 PCB Footprint and JP32 pin define . (Modify CKT&Layout)
24. Change the power sequence related part's power source by Brian . <Page 5,37,48> 92.03.27.-Change U32's power source from +3VS to +3VALW . (Modify CKT&Layout)
25. Modify the power sequence related schematic for timing by Brian . <Page 48> 92.03.27.-Change R605 from 1M_0402_5% to @1M_0402_5%;C606 from 1U_0603_10V6K to @1U_0603_10V6K . (Modify CKT&BOM)-Add Q110(2N7002_SOT23) . (Modify CKT,BOM&Layout)
26. Modify the SPDIF related schematic for Customer request . <Page 37,41> 92.03.28.-Add R1103(0_0402_5%),C963(0.01U_0402_50V7K) . (Modify CKT,BOM&Layout)
27. Modify the NEC USB2.0 Controller Chip related schematic for Customer request . <Page 36> 92.03.28.-Add Y7(30MHZ_30PPM),R1105(100_0402_5%),C964(12P_0402_50V8J),C965(10P_0402_50V8K) . (Modify CKT,BOM&Layout)-Add R1104(@0_0402_5%) . (Modify CKT&Layout)-Change R1024 from 0_0402_5% to @0_0402_5% . (Modify CKT&BOM)
28. Update the material's Layout Footprint for error correction . <Page 36> 92.03.28.-Update JP29,JP14,SW1,SW3~SW8,JP40,Q65 . (Modify CKT&Layout)
29. Modify the related schematic after Brian Review <Page 7,24,26,29,30,39,43,45> 92.03.31.-Del R288(56_0402_5%) . (Modify CKT,BOM&Layout)
30. Modify the related schematic after Layout check <Page 44> 92.03.31.-Modify JP16(RJ11 Conn.).5 and JP16.6 from GND to NC . (Modify CKT&Layout)
31. Update the material's Layout Footprint for error correction . <Page 41> 92.04.02.-Update JP40 . (Modify CKT&Layout)
32. Modify the schematic for cost down . <Page 10,12,26,37,> 92.04.04.-Change to @(R1005,D79~D82,U53,C912,C913,R1023,Q98,R769,R771,) . (Modify CKT&BOM)
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Size Document Number R e v
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LA-1811 1.0
H/W2 EE Dept. PIR SHEET(2)
60 66Wednesday, September 24, 2003
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
----PLEASE SEE NEXT PAGE
BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 EE Modify <92.04.08.~92.04.18. >
-Change JP33 sequence JP33.4->JP33.1, JP33.3->JP33.2, JP33.2->JP33.3, JP33.1->JP33.4. (Modify EECircuit)
1.1394 Connector JP33 Pin define sequence error. <Page 35> 92.04.08. 1.FDD Connector JP38 PCB Footprint error. <Page 40> 92.04.09.-Check JP38 ACES_85201-2605_26P. (Modify Layout)
2.Power Switch U53 PCB Footprint error. <Page 12> 92.04.09.-Change U53 SI9185_MLP33-8->MSOP8. (Modify Layout)
3.Crystal Y4 PCB Footprint error. <Page 11> 92.04.09.-Change Y4 Y_TXC_6X1430004201_20P->KDS_DSX840GA. (Modify Layout)
4.USB Key Connector JP46 Part error. <Page 44> 92.04.09.-Change JP46 S W-CONN ACES 85205-0400 4P P1.25(ACES_85205-0400_4P)->S H-CONN ACES85201-0405 4P P1.0(ACES_85201-0405_4P). (Modify Layout)
2.LED Circuit to Power Button(PRES)modify . <Page 42, Page 46> 92.04.09.-Move Q66.1-R883-D56 -> Q62.1-R883-D56(PRES). (Modify EE Circuit)-Rename Q62.2 net PWR_BACK# change to PWR_ACTIVE# connect to EC U15.119. (Modify EE Circuit)
3.Add +1.2VS_VGA Discharge Circuit. <Page 49> 92.04.09.-Add +1.2VS_VGA Discharge Circuit(R1116 , Q115 to SUSP). (Modify EE Circuit)
BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 Layout Modify <92.04.08.~92.04.18. >
4.Add 3VDDCDA & 3VDDCCL pull hing CRT_VCC circuit. <Page 25> 92.04.09.-Add Q13.1-R1117 to +CRT_VCC & Q14.1-R1118 to CRT_VCC. (Modify EE Circuit)
5.PCMCIA U37 NET S1_CE2# & S1_CE1# Sweep. <Page 31> 92.04.09.
6. MDC(JP17) Net AC97_SData_In1/AC97_SData_In2 to AC97_Data_In. <Page 44> 92.04.10.-Update BOM add R326. (Modify EE Circuit)
7. Change NB DDR Bus Net for basic on ATI NB DDR Bus Layout rule. <Page 9, 14, 15, 16> 92.04.11.-Add R1122(DDRA_CKE_R3), R1121(DDRA_CKE_R2). (Modify EE Circuit)-Del R399(DDRA_CS#0), R400(DDRA_CS#2). (Modify EE Circuit)
8. Check BOM USB OUVUR R893&R895 470K change to 330K. <Page 44> 92.04.12.
9. Add SUSP# pull Down. <Page 46> 92.04.14.-Add EC U15.115 to SUSP# pull Down @R1123 to GND. (Modify EE Circuit)
10. Add CPUCLK_STP# pull High Circuit. <Page 26, 5> 92.04.14.-BOM Q113 -> @ , Add R1124 to Q113.1 & Q113.3. (Modify EE Circuit)-Add CPUCLK_STP# pull High @R1126 to +3VS . (Modify EE Circuit)
12. SIO Circuit All Power Plan +3V -> +3VS. <Page 39> 92.04.15.
-Add CPUCLK_STP# serial resistor R1125 to Q96.2. (Modify EE Circuit)
11. Change BOM R585 75 -> 0 & R996 33 -> 68(REFCLK1_NB). <Page 11, 24> 92.04.15.
5. Change BOM & Layout LED D57 Footprint . <Page 42> 92.04.15.-Change D57 HSMG-C170 to LED_12-21SYGC_S530-E1_TR8. (Modify Layout)
13. Add NEC USB Corstralor U54.P19(SRMOD) pull Low. <Page 36> 92.04.16.-Add USB Constralor U54.P19(SRMOD) pull Low R1127 to GND. (Modify EE Circuit)-Update BOM R1046 -> @. (Modify EE Circuit)
6. Change Layout Keyboard Connector JP13 Footprint. <Page 45> 92.04.15.-Change JP13 ACES_85201-2402_24P -> ACES_85201_2405_24P. (Modify Layout)
7. Change Layout FrontSideboard Connector JP42 Footprint. <Page 44> 92.04.15.-Change JP42 ACES_85201-1402_14P -> ACES_85201_1405_14P. (Modify Layout)
16. Change BOM R380 430 -> 412(U27.A9/CPU_RSET#). <Page 8> 92.04.17.
15. Change BOM C364, C23, C24, C40, C798 47U -> 22U. <Page 8,28,41> 92.04.17.
18. Change BOM C191 4.7U -> 2.2U. <Page 17> 92.04.17.
19. Change BOM C202,C931 10U -> 2.2U. <Page 20> 92.04.17.
20. Change BOM R636 100K-> @10K, R637 100K-> @10K, R665 -> @. <Page 33> 92.04.17.
21. Change MC_CD# - D44.3(SA_A25) -> D45.2, D44.2(SA_A22). <Page 33> 92.04.17.
14. Add @R1132 pull High +3V(RTS1#) & @RP153 pull High +3V(CTS1#/DSR1#/DCD1#/RI1#). <Page 39> 92.04.16.
17. Change BOM D57 HSMG-C170 -> 12-21SYGC/S530-E1, R1014 @ -> Del @. <Page 42> 92.04.17.
24. Change BOM Q67 -> @, R884 -> @(CARD_LED#). <Page 42> 92.04.18.
23. Add R1136, Q116, R1137, R1138 for pull High +3VS(CARD_LED#). <Page 42> 92.04.18.
22. Add R1135 -> VTT_PWRGD(U15.165). <Page 46> 92.04.18.
25. Change BOM C966 22U -> 0.1U. <Page 18> 92.04.18.
26. Change BOM C916 -> @, C917 -> @. <Page 36> 92.04.18.
27. Change BOM R1019 -> @(U47.17 JS1) pull High. <Page 37> 92.04.18.
28. Change BOM R264 47 -> 137(U6.PM27 AGPTEST). <Page 17> 92.04.18.
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Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
H/W2 EE Dept. PIR SHEET(2)
61 66Wednesday, September 24, 2003
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
----PLEASE SEE NEXT PAGE
BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 EE Modify <92.04.08.~92.04.18. >
BHR60 from DB-2 to SI-1 STEP LA-1811 REV:0.3 -> 0.4 Layout Modify <92.04.08.~92.04.18. >
35. Add @R1142 pull High(DOCK_LOUT_R). <Page 38> 92.04.21.
32. Change SPR JP40 33,34 DOCKVIN -> GND , JP35,36 GND -> DOCKVIN, . <Page 41> 92.04.21.
36. Add C971 & R1140 for VOLBTN+#, R1141 & C972 for VOLBTN-#, R1131 pull High +5VS, @R1139 pullHigh +3V. <Page 41> 92.04.21.
33. Change BOM Q65 DTC124EK_SC59 -> MMBT3904_SOT23. <Page 41> 92.04.21.
29. Change U13.P1 <-> U13.P5, U14.P1 <-> U14.P5. <Page 43> 92.04.21.
30. Change R994.1 - AGP_DEVSEL# -> AGP_SBA1(DDC_DAT), R995.1 AGP_IRDY# ->AGP_SBA0(DDC_CLK). <Page 10> 92.04.21.
31. Add CLK_14M_APIC Terminte R,C @R1143 10/@C973 15P. <Page 26> 92.04.21.
34. Del @R1104, @R1089, @C953(CLK_SB_48M). <Page 36> 92.04.21.
37. Add R520 @ -> Del @(JP8.AE26 COMPAT#). <Page 5> 92.04.23.
38. Change BOM R539, R540 61.9 -> 51.1 (JP8.L24/P1 COMP0/COMP1). <Page 5> 92.04.23.
39. Change BOM R553 100 -> 49.9, R558 169 -> 100. <Page 5> 92.04.23.
40. Change BOM R383 100 -> 49.9, R384 169 -> 100. <Page 8> 92.04.23.
41. Add R1001 @4.7K -> Del @, 100K pull Low(DPRSLPVR). <Page 26> 92.04.23.
42. Change BOM R40 @ -> Del @, R53 -> @. <Page 29> 92.04.23.
43. Change BOM R792 -> @, R795 @ -> Del @. <Page 39> 92.04.23.
44. Change BOM R230 -> @. <Page 4> 92.04.23.
45. EMI add R1144 for SSOUT. <Page 10> 92.04.24.
46. EMI change D73, D74, D75, D76 part. <Page 38> 92.04.24.
47. Add C974 pull Low for +NB_AGP. <Page 17> 92.04.24.
48. Change BOM R623 10K -> 0. <Page 25> 92.04.28.
49. Change BOM R622, R619 10K ->@. <Page 25> 92.04.28.
BHR60 SI STEP LA-1811 REV:0.4 EE MEN <92.04.28. >
1. Change C781 SE077106M00 -> SE054106Z10. <Page 39> 92.04.28.2. Change C963 -> @. <Page 41> 92.04.28.3. Change C974 -> @. <Page 17> 92.04.28.4. Change C742 -> (SD028000000) 0 Ohm. <Page 37> 92.04.28.5. Add R771 -> (SD028470100) 4.7K Ohm. <Page 37> 92.04.28.6. Add C747 -> (SE070104Z00) 0.1U. <Page 37> 92.04.28.7. DEL R761,R762 <Page 37> 92.04.28.
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Size Document Number R e v
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LA-1811 1.0
H/W2 EE Dept. PIR SHEET(2)
62 66Wednesday, September 24, 2003
Compal Electronics, Inc.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BHR60 from SI-1 to DB(15.4") LA-1811 REV:0.4 -> 0.5 HW PIR <92.05.07.~92.05.30. >
0.5Add Nets: NMCSA1# and NMCSB1#18, 19,22, 236 Add CS1# for Hynix 8Mx32 VGA DRAM
1 Prevent CPUCLK_STP# abnormal state happened 5 Change R1125 from 4.7K to 12K
26 Delete R1126
29 Change R40 from 10K to 1K
7 Change the power of U8 from +3VS to +3VALW
M.B. Ver.
0.5
0.5Prevent power leakage
Power saving 7 Change the power of Fans from +5VALW to +5VS 0.5
2
3
Reason for change PAGE Modify ListFixed IssueItem
ATI recommendation 8 Add C974 0.54
Add VGA DRAM size detect function5 17 Add R1149 for 128MB VGA DRAM (un-populate for 64MB) 0.5
7 Change M9+X VGA_CORE from +1.5VS to individual power source 21 Delete JOPEN3 0.5
8 Delete useless components
25 Delete C96
0.5
25 Change R619.1 and R622.1 net from +5VS to CRT_VCC 0.5Solve power leakage from CRT9
2610 Prevent DPRSLPVR abnormal state happened Change R1001 from 100K to 47K, R1002 from 0 to 47K 0.5
11 Using rechargeable RTC battery for HP's request Delete D66, D71 and D72; Add D91 (BAS40-04, the same as LA-1761 D30); ChangeBATT1 from CR1220 to ML1220 (the same as LA-1761 BATT1)
0.526
12 Prevent +5V drop while plug SPR for HP's request 41 Change JP40.3, C798.1, C800.1 and C801.1 net from +5V to USB_VCCA; Change C798from 22u to @10u; Change C801 from 1000p to @1000p
0.5
5 Delete R538
13 Enhance brightness of blue LEDs 0.5Delete Q67, R883, R884, R942 and R943; Add Q117 and R1146; Change R881, R882,R885, R888, R889, R890, R925 and R1136 to 220
42, 45
Change JP42.2 from BATLED_0 to BATLED_0#; Change JP42.7 from N.C. to +5VALW;Change JP42.12 from PAV_GND to PAV_LEDVCC; Change JP42.13 from PMLED_1 toPMLED_1#; Change JP42.14 from PAV_GND to +5VS; Change JP45.7 from PRES_GND toPRES_LEDVCC; Change JP45.8 from PRES_GND to +5VS
44
14 Solve PWR_ACTIVE LED function fail issue 42 Change power from +3VS to +5V for PWR_ACTIVE LED (D52 and D56) 0.5
46 Add R1147 and R1148; Change U15.76 net from N.C. to PWR_ACTIVE_PRES#; ChangeU15.87 net from N.C. to PRES_DETECT; Change U15.119 net from PWR_ACTIVE# toPWR_ACTIVE_PAV#
15 Solve M10 can't power up issue 49 Change R1101 from 100K to 56K; Change R901 from 91K to 27K 0.5
16 Add discharge components 49 Add R372, R1095, R1102, Q36, Q103 and Q109 0.5
17 Material change for ME's request 44 Change JP47 from ACES_88231_0200 to MOLEX_53398_0290 (the same as LA-1761 JP2) 0.5
18 Using NEC USB2.0 to support BT for HP's request 44 Change R1082.2 net from USB3+ to USB5+; Change R1081.2 net from USB3- to USB5- 0.5
27 Delete Q114, Add R1145
19 Increase MONO_IN voltage level 37 Change R738 from 2.4K to 10K 0.5
20 Decrease Audio AMP Gain 38 Change R971 from 100K to @100K; Change R973 from @100K to 100K 0.5
Update with Item23
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Size Document Number R e v
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LA-1811 1.0
H/W2 EE Dept. PIR SHEET(2)
63 66Wednesday, September 24, 2003
Compal Electronics, Inc.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BHR60 from SI-1 to DB(15.4") LA-1811 REV:0.4 -> 0.5HW PIR <92.05.07.~92.05.30. >
21 RTL8101L no need transistor for 3.3V to 2.5V anymore 34 Delete Q55, R944 and C668
44Change PCB Footprint from SUYIN_020167MR004SX01ZR_4P tosuyin_020167mr004s511zu_4p for JP18, JP19 and JP20
M.B. Ver.
0.5
0.5Connector Spec. change for ME's request
Solve Tr and Tf of H-sync/V-sync over Spec issue for high resolution CRT 25 Delete Q68, Q64, R619, R620, R621 and R612; Add U57, U58 and R1150 0.5
22
23
Reason for change PAGE Modify ListFixed IssueItem
Change R704 from 5.6K_0402_5% to 5.6K_0402_1%REALTEK recommendation
Delete useless components with BOM 10 Delete R574, R1086 and C952 0.524
24 Delete R210 for UMA only
Add SB to control H_PROCHOT# for HP's request 26 Add Q118 and R1151 0.525
Add components for EMI 37 Add R1152 0.526
40 Add L65 ~ L78
Solve DOS cold-boot shunt down issue 7 Delete C256 0.527
40 Add L79 ~ L97
Decrease overshoot & undershoot 25 Add R1153 and R1154 0.628
Change SB GPIO0 and GPIO2 pull-down to GND 26 Delete RP126; Add R1155~ R1157 0.629
Only 0603 size in SAP for 5.6K_1% 34 Change component size of R704 from 0402 to 0603 0.630
40The pin-definition of FDD conn. was error on rev0.5 M/B31 0.6Correct the pin-definition for JP38
4032 0.6Change RP119 from 1K to 330; Delete RP121; Add R? and R?VIA recommendation
4133 0.6Change R880 from 10K to 470Enhance brightness of Docking LEDs
0.634 44To support wake-up function with TP Change TP power from +5VS to +5V
0.635 5Delete useless components Delete R535, R536, R991 and R992
12 Delete U53, C912~C914, D79~D82, R954, R1010~R1012 and R1023
17 Delete Q15 and R251
20 Delete R1022
24 Delete R211 and R216
25 Delete C93~C95 and C930
26 Delete Q113, R1124 and D91; Add D93
0.6
27 Delete RP149, RP150, R1145 and Q114
29 Delete R53
37 Delete L45, R1019, Y6, R756, C740 and C741
Add components for EMI38 37 Add L98 and L99 0.6
38 Delete R1142
40 Add C975, C976, CP15~CP17
0.636 To improve RTC accuracy 26 Change Y1 from +/-20ppm to +/-10ppm
37 Solve Cardbus controller can't reset well issue 31 Delete R905, R941 and C906; Connect U37.C11 to G_RST#
39 Improve Audio quality38 Add R1158 and R1164; Exchange the nets of JP41.2 and JP41.3
0.6
39 Delete RP153 and R1132
41 Add R1161
40 42 Add D92Add components for ID & ME
41 Change R904 from 91K to 47K49Modify +5V power-up timing to lead +3V
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BHR60 from DB to SI LA-1811 REV:0.5 -> 0.6HW PIR <92.06.20.~92.07.03. >
Delete C753~C756; Add R1165~R1168 and C97937
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Size Document Number R e v
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LA-1811 1.0
H/W2 EE Dept. PIR SHEET(2)
64 66Wednesday, September 24, 2003
Compal Electronics, Inc.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BHR60 from SI-1 to PV LA-1811 REV:0.6 -> 0.7HW PIR <92.07.03.~92.08.08. >
42 Correct Y1 and Y3 pin-out 26 Using pin-1 and pin-2 of these crystals
44Delete R65, R66, R67, R70, R72, R75, R79, R82, R86. R89, R94 and R95
M.B. Ver.
0.7
0.7ATI Product Advisory, refer to PA_218IXP0T1
Solve CD-ROM audio noise issue 30 Delete C11 0.7
43
44
Reason for change PAGE Modify ListFixed IssueItem
Solve audio noise issue 37 Change R733.1 from +5VS to +5VAMP_CODEC 0.745
For EMI 38 Add L100, L101, L102 and L103 0.746
For FIR detect 39 Add R1173(no fir) and R1174(with FIR) 0.747
ATI recommendation 27 Change RP12 from 10K to 2.2K 0.748
Delete useless components 46 Delete D69 and D70 0.749
To support wake-up function with TP 46 Delete RP154; Add R1169, R1170, R1171 and R1172 0.750
Solve M10 can't power up issue 49 Delete C844 0.751
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
46
46 Add R1175
Improve Tr and Tf of H-sync/V-sync for high resolution CRT 25 Decrease the R,L,C value 0.752
Modify brightness of LEDs 42 Change Transistors from BJT to PMOS and Resisters value for Pav; Change Resisters value for Pre. 0.753
45
Fast power on for battery only 45 Change R306 from 100K to 470; Delete Q112 0.754
Change R901 from 27K to 6.8K
Improve contact Move JP2(CD-ROM conn.) right 0.65mm 0.755
Correct Caps. LED and Numl. LED placement Exchange the placement of these LEDs 0.756
Solve audio noise issue Cut the bridge between AGND and DGND in GND1 layer 0.757
Reserve for EMI Add JOPEN6, JOPEN7 and JOPEN8 0.758 37
Improve USB2.0 signal quality Change R1027, R1029, R1030, R1031, R1032, R1033, R1034 and R1035 to 42.2 0.759 36
Reserve VRAM detect function for ATI recommendation Connect R256/R257 to ZV_DATA0/ZV_DATA1, and pull-up to +3VS 1.060 17
For EMI Change C761~C764 to 470pF and pull-down to D-GND; Change L100~L103 to MCK2012221YZT(2A) 1.061 38
Reduce GHI# "LOW" voltage level Change R527 to 300 ohm 1.062 5
Delete C110~C1154836 Change L89, R1079 & R1080 to CHB1608U3017 Add C855, C856, C907 and C90824 Change L11 & L12 to MBV2012301YZT26 Change PCI clock damping resisters to 39 ohm28 Add C873~C881, C980~C983; Change R60~R62 to MBV2012301YZT37 Delete R769 & R770; Add C984~C992 & L104
Fix "Pop" sound during boot up 1.0Add C97963 37
41 Add L105
For PCBA skew reducing 1.064 42 Change R885, R888, R890, R1136 and R925 to 13045
25 Add C993 & C994
TI recommendation 1.065 32 Add R1177
Solve audio L/R swap issue 1.066 37 Change R750 & R753 to 27 ohm
44 Delete R327 & C305
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LA-1811 1.0
65 66Wednesday, September 24, 2003
Compal Electronics, Inc.
Changed-List History-1
Version Change List ( P. I. R. List ) for Power CircuitItem Issue Descr ipt ionDate
RequestOwner Solution Description Rev.Page#
1 0.2
0.3
Tit l e
2
3
change to correct layout pad on PU7, PU8, PU9, PU10, PU11, PU16 and PQ24
54,55, 56,57
03/25/2003 Compal
DPRSLPVR56 03/25/2003Reserve two resistors for voltage of Deep-sleeper mode Reserver PR231, PR232, PR233, PR234
for deeper-sleeper mode voltage setting
03/25/2003 Reserve a jumper for power consumption measurement56 CPU VR-Cont.
4
Add PJP14
57 Compal Change Netname of +5VS_CORE
5 51 RTC charger Add PR230
wrong layout pad
wrong layout pad
Compal
Compal
CPU VR-Cont. 03/25/2003 Change the netname +5VS_CORE for powerconsumption measurement
03/25/2003 Compal use two resistors for RTC charger protection
6 re-located both PL10 and PQ21, PQ23 as well as 1.2VS_VGA related power circitry
55 1.2VS_VGA 03/25/2003 Compal re-layout 1.2V_VGA requested by ME
7 55 1.2VS_VGA 03/26/2003 Compal Reserve a jumper for power consumption measurement Add PJP15
8 55 +1.25VSP 03/26/2003 Compal Change power time-sequence of 1.25VSP input power Change VD, and VDD of PU16 from +2.5VALWPto +2.5VS; Connect PR235.2 to +2.5VSadd a resistor PR235 for Stand/By pin for test
9 03/27/2003 Compal Add PR237, PR238 for force PWM function control, and add PR236 for SUSP# signal
54 +1.5VALWP Reserve Force PWM function of 1.5V/2.5V and add a PR236 for SUSP# signal
10 54 +1.5VALWP04/16/2003 Compal
11 04/16/2003 Compal
Compal
Change power time-sequence of 1.5VSP input power
Add two transistor PQ44,PQ45 for voltage of Deep-sleeper mode
12 Change power JUMP SIZE to follow new jump role
56 CPU DPRSLPVR
565554
PWR JUMP
13 CPU DPRSLPVR56
04/16/2003
04/18/2003 Compal Reserve DPRSLPVR function and add a PR136 for +5VS_CORE signal
14
15
50 Vin DETECTOR 04/30/2003 CompalChange PR8 form 10k_0603 to 0K_0603
50 Precharge 04/30/2003 Compal Change PR1 from 10k_0603 to 100k_0603
16 04/30/2003 CompalChange PC20 from .22u to 1u ;PR40&PR42 from 100k to150k; PC80 from 1u to .47u
Battery OTP
to make ACIN to enable to pull low
BOM error
To change feekbeck time
17
51
51 04/30/2003 Compal change component Change PU3 from S-81233SGUP-T1 to S-812C33AUA-C2N
18 52 Battery_OVP 04/30/2003 Compal To avoide the BATT_OVP output to oscillate Delet PC44&PR71
19 53 5V/3.3V/12V 04/30/2003 Compal BOM error Change PD16 from EC31Q04 to EC11FS2
04/30/2003 Compal To improve the 3V output ripple Voltage Delet PC7720 53 5V/3.3V/12V
change 1.5V time sequence
Change DPRSLPVR design
For DFX issuse
Change DPRSLPVR design
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.3
0.3
0.3
0.3
0.3
0.3
0.3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number R e v
Date: Sheet o f
LA-1811 1.0
66 66Wednesday, September 24, 2003
Compal Electronics, Inc.
Changed-List History-1
Version Change List ( P. I. R. List ) for Power CircuitItem Issue Descr ipt ionDate
RequestOwner Solution Description Rev.Page#
210.4
Tit l e
Change PR121 from 511k to 180k;PR122 form 9.09k to 4.64k55 04/30/2003 Compal1.2VS_VGA BOM errors
22 50Prechargedetector
05/16/2003 Compal System can't power on by battery
AddPR191(909K_0603),PR192(47k_0603),PRPQ46(2N7002)&PQ47(DTC115EUA_SC70)
Change PR5 from 150k to 180k0.5
23 51Colok THROTTLING
05/16/2003 CompalTo modify the circuit Add PR193(73.2k) ,PC97(0.01U_0603); change PR22 form
84.5K to 11.5K
24 56,57 CPU_CORE(1&2) 05/16/2003 Compal Change the freqeuce 300k to 200k delet PR138 ; add PR187(0_0603)&PR188(0_0603)
0.5
0.5
25 52 Charger 05/16/2003 Compal To modify the charger circuit 0.5Add PR194(1K),PC98(0.1U_0603),PR195(47K),PQ48(DTA144EUA),PQ49(DTC115EUA),PQ50(2N7002),PD30(1SS355)
26 55 1.2VS_VGA 05/16/2003 Compal To modify the circuit for 1.2VS_VGA &1.5VS_VGA add PR124(11.5k_0603) 0.5
27
56 CPU_CORE
07/4/2003 CompalTo modify the DCR sense Add PR81(3.4k) ,PR78(3.4K),PR79(0_0402)
,PR85(0_0402),PC67(0.1U_0603) ,PC68(0.1U_0603);deletPR86,PR88,PR90,PR93
0.6
28
53 3V/5V/12V
07/4/2003 Compal To modify THE CPU Load line form -1.5mV/A to -2.2mV/AChange PR158,PR180 from 2k to 3.4k 0.6
29 56,57CPU_CORE(1&2) 07/4/2003
CompalTo improve the CPU_CORE effecient
Change PL12,PL13,PL14,PL15 from TOHO to PANASONIC 0.6
30
31
32
0.7
0.7
50 DC_in 08/4/2003 Compal For Gibson issue ,add two schottky diodes add PD43(SBM1040-13_powermite3) ,PD44(SBM1040-13_powermite3)
Charger 08/4/2003 Compal
53 3V/5V/12V 08/4/2003 Compal To solve the DCR sense for 5V OCP issuechange PR81(1.27k) ,PR78(1.54K),PR79(0_0402),PR85(0_0402),PC67(0.47U_0603) ,PC68(0.47U_0603);addPR241(1.24k),PR242(620 ohm),PR243(698 ohm)
33 56 CPU_CORE 08/4/2003 Compal To modify THE CPU Load line form -2.2mV/A to-1.5mV/A, and senes CPU VCC and VSS
Change PR158,PR180 from 3.4k to 2.2k and add PR244 (0 ohm)and PR245(0 ohm)
0.7
0.7
52Add PD30(1SS355_SOD323) ,PC98 (0.1U_0603),PR195(47K_0402),PQ49(DTC115EUA_SC70),PQ50(2N7002) ,delete PR46,PR37,PR55,PQ7PR49
34 52 Charger 08/4/2003 Compal
To modify the Precharge circuit
To improve the charger feedback loop for charger noise issue Change PR52 (47k_0603),PR57(1K_0603),PC36(1500P_0603) 0.7
