Scheduling and Communication Synthesis for Distributed ...paupo/publications/Pop2000ab-Scheduling...

1 of 30June 14, 2000

Scheduling and Communication Synthesis for Distributed Real-Time Systems

Paul PopDepartment of Computer and Information Science

Linköpings universitet

Scheduling and Communication Synthesis for Distributed Real-Time SystemsPaul Pop

2 of 30June 14, 2000

Outline

n Motivation

n System Model and Architecture

n Scheduling and Communication Synthesisn Time Driven Systemsn Event Driven Systems

n Real Life Example

n Conclusions


3 of 30June 14, 2000

1%

99%

Embedded Systems

General purpose systems Embedded systems

Microprocessor market shares in 1999


4 of 30June 14, 2000

Distributed Real-Time Systems

n Safety critical applications (e.g. Drive-by-Wire): n timing constraints,n data and control dependencies.

n Communication protocols: Time Triggered Protocol (TTP),

Controller Area Network (CAN).

n Scheduling of processes and communication of messages:

guaranteeing timing constraints.


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Hardware/Software Codesign

SystemSpecification

Architecture Selection

Scheduling

Integration

Hardware Synthesis

Partitioning

Software Synthesis

Goals of the thesis:

n Scheduling...

Scheduling of processes and messages for

distributed hard real-time applications with

control and data dependencies in the context

of a given communication protocol.

n Communication synthesis...

Optimization of the parameters of the

communication protocol so that the overall

system performance is increased and the

imposed timing constraints are satisfied.


6 of 30June 14, 2000

Related Work

n Scheduling:

n Static cyclic non-preemptive scheduling:

P. Eles, G. Fohler, D. D. Gajski, H. Kasahara,

H. Kopetz, K. Kuchcinski, J. Madsen, J. Xu.

n Fixed priority preemptive scheduling:

J. Axelsson, S. Baruah, A. Burns, J. W. Layland, C. L. Liu,

K. Tindell, J. A. Stankovic, , W. Wolf , T. Y. Yen.

n Communication synthesis:

G. Borriello, R. Ernst, H. Hansson, J. Madsen, R. B. Ortega, K. Tindell.


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Characteristics and Message

n Distributed hard real-time applications.

n Heterogeneous system architectures.

n Systems with data and control dependencies.

n Scheduling of processes:

Time triggered: Static cyclic non-preemptive scheduling,

Event triggered: Fixed priority preemptive scheduling.

n Communications using the time-triggered protocol (TPP).

n The performance of the system can be significantly improved

by considering the communication protocol and the

control dependencies during scheduling.


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Outline

n Motivation

Ô System Model and Architecture

n Scheduling and Communication Synthesisn Time Driven Systemsn Event Driven Systems

n Real Life Example

n Conclusions


9 of 30June 14, 2000

Conditional Process Graph (CPG)

P4P4 P5

P5

P7P7

P13P13

P15P15

n First processorn Second processorn ASIC

CC

DD

P0

P18

P1P1

P2P2 P3

P3

P6P6

P8P8 P9

P9

P10P10

P11P11

P12P12

P14P14 P16

P16

P17P17

C

KK

P0

P18

P1

P2 P3

P6

P8 P9

P10

P11

P12

P14 P16

P17

Subgraph corresponding to D∧C∧K


10 of 30June 14, 2000

Hardware Architecture

n Hard real-time distributed systems.

n Nodes interconnected by a broadcast communication channel.

n Nodes consisting of: TTP controller, CPU, RAM, ROM, I/O interface.

n Communication between nodes is based on the time-triggered protocol.

I/O Interface

TTP Controller

CPU

RAM

ROM

ASIC

Node


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Time Triggered Protocol

n H. Kopetz, Technical University of Vienna.

n Intended for distributed real-time controlapplications that require high degree ofdependability and predictability.

n Recommended by the X-by-Wire Consortiumfor use in safety critical applications invehicles.

n Integrates all the services required in thedesign of fault-tolerant distributed real-timesystems.

S0 S1 S2 S3 S0 S1 S2 S3

TDMA RoundCycle of two rounds

Slot

n Bus access scheme: time-division multiple-access (TDMA).

n Schedule table located in each TTP controller: message descriptor list (MEDL).

I/O Interface

TTP Controller

CPU

RAM

ROM

ASIC

Node


12 of 30June 14, 2000

Outline

n Motivation


Ô Scheduling and Communication Synthesis

è Time Driven Systemsn Event Driven Systems

n Real Life Example

n Conclusions


13 of 30June 14, 2000

Time Triggered Processes

Inputn Safety-critical application with several operating modes.

n Each operating mode is modelled by a CPG.

n The system architecture and mapping of processes to nodes are given.

n The worst case delay of each process is known.

Outputn Local schedule tables for each node and the MEDL for the TTP

controllers.

n Delay on the system execution time for each operating mode,so that this delay is as small as possible.

Problem Formulation

Noten Processes scheduled with static cyclic non-preemptive scheduling,

and messages according to the TTP.


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Scheduling Example

P1P1

P4P4

P2P2 P3P3

m1 m2

m3 m4

S1 S0

Round 1 Round 2 Round 3 Round 4 Round 5

P1 P4

P2

m1 m2 m3 m4

P324 ms

Round 1

P1

Round 2 Round 3 Round 4

S1S0 m1 m2m3 m4

P2 P3

P4

22 ms

Round 1 Round 2 Round 3

S1S0

P2 P3

P4P1

m1 m2 m3 m4

20 ms


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1. The scheduling algorithm has to take into consideration the TTP.

n Priority function for the list scheduling.

2. The optimization of the TTP parameters is driven by the scheduling.

n Sequence and lengths of the slots in a TDMA round aredetermined to reduce the delay.

n Two approaches: Greedy heuristic, Simulated Annealing (SA).

n Two variants: Greedy 1 tries all possible slot lengths,Greedy 2 uses feedback from the scheduling algorithm.

n SA parameters are set to guarantee near-optimal solutions ina reasonable time.

Scheduling Strategy


16 of 30June 14, 2000

Experimental Results

0

10

20

30

40

50

60

80 160 240 320 400

Naive DesignerGreedy 1Greedy 2

Deviations from the near-optimal schedule lengths obtained by SA:

Number of processes

Ave

rage

Per

centa

ge

Devia

tio

n[%

]


17 of 30June 14, 2000

Outline

n Motivation


Ô Scheduling and Communication Synthesis

n Time Driven Systemsè Event Driven Systems

n Real Life Example

n Conclusions


18 of 30June 14, 2000

Inputn An application modelled using conditional process graphs.

n Each process has an execution time, a period, a deadline, and a priority.

n The system architecture and mapping of processes are given.

Outputn Schedulability analysis for systems modelled using CPGs.

n Schedulability analysis for the time-triggered protocol.

n The MEDL for the TTP controllers so that the process set is schedulableon an as cheap (slow) as possible processor set.

Event Triggered ProcessesProblem Formulation

Noten Processes scheduled with fixed priority preemptive scheduling,

and messages according to the TTP.


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Example

P3P3

P5P5

C

P0P0

P1P1

P6P6

P2P2

P7P7

P4P4

P8P8

C

27

30

24

19

25

30

22

Γ1: 200

P11P11

P12P12

P9P9

P10P1025 32

Γ2: 150

Worst Case DelaysCPG

No conditions Conditions

Γ1 120 100

Γ2 82 82

Deadline: 110


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0

20

40

60

80

100

80 160 240 320 400

Ave

rage

Perc

enta

ge

Devia

tio

n[%

]

Number of processes

Relaxed Tightness 2

Relaxed Tightness 1

Conditions Separation

Brute Force

Ignoring Conditions

Cost function: degree of schedulability


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Experimental Results (Cont.)

0

90

180

270

360

450

80 160 240 320 400

Ave

rage

exec

ution t

ime

[s]

Number of processes

Relaxed Tightness 2

Relaxed Tightness 1Conditions Separation

Brute Force

Ignoring Conditions


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Scheduling of Messages over TTP

1. Single message per frame, allocated statically:Static Single Message Allocation (SM)

2. Several messages per frame, allocated statically:Static Multiple Message Allocation (MM)

m1 m2 m5m3 m4

Round 1 Round 2 Round 3S0 S1

messages are dynamically produced by the processesframes are statically determined by the MEDL

3. Several messages per frame, allocated dynamically:Dynamic Message Allocation (DM)

4. Several messages per frame, split into packets, allocated dynamicallyDynamic Packets Allocation (DP)


23 of 30June 14, 2000


Dynamic Message

Single Message

Dynamic Packets

Multiple Messages

Ad-hoc

0

4

8

12

16

80 160 240 320 400

Ave

rage

Perc

enta

ge

Devia

tio

n[%

]

Number of processes

Cost function: degree of schedulability


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Optimizing Bus Access (SM and MM)

m1 m2

p1

p2

p3

m2 m1

p1

p2

p3

Swapping m1 with m2:all processes meet their deadlines.

m1 m2

p1

p2

p3

Putting m1 and m2 in the same slot:all processes meet their deadline,the communication delays are reduced.

Process p2 misses its deadline!


25 of 30June 14, 2000

OptimizeDMOptimizeDM

for each node Ni do

MinSizeSi = max(size of messages mj

sent by node Ni)

end for

for each slot Si

BestSizeSi = MinSizeSi

for each SlotSize in [MinSizeSi...MaxSize] do

calculate the CostFunction

if the CostFunction is best so far then

BestSizeSi = SlotSizeSi

end if

end for

sizeSi = BestSizeSi

end for

end OptimizeDM

Initialization:the size of a slot in a TDMA roundhas to accommodate the largestmessage sent by the corresponding node.

Greedy heuristic: finds the local optimum for each slot.

Local optimum:find the best size for this slot,the size that leads to the“best so far” cost function.

OptimizeDM: Find the slot sizes that maximize the “degree of schedulability”

for each node Ni do

MinSizeSi = max(size of messages mj

sent by node Ni)

end for

for each slot Si

BestSizeSi = MinSizeSi

for each SlotSize in [MinSizeSi...MaxSize] do

calculate the CostFunction

if the CostFunction is best so far then

BestSizeSi = SlotSizeSi

end if

end for

sizeSi = BestSizeSi

end for

end OptimizeDM


26 of 30June 14, 2000


The quality of the greedy optimization heuristics:

0

0,5

1

1,5

2

80 160 240 320 400

OptimizeSMOptimizeMMOptimizeDMOptimizeDP

Avera

ge p

erc

en

tag

e d

evia

tion

s [%

]

Number of processes


27 of 30June 14, 2000

Outline

n Motivation


n Scheduling and Communication Synthesisn Time Driven Systemsn Event Driven System

Ô Real Life Example

n Conclusions


28 of 30June 14, 2000

Real Life Example

n Vehicle cruise controller.n Modelled with a CPG of

32 processes and two conditions.n Mapped on 5 nodes:

CEM, ABS, ETM, ECM, TCM.

n Time triggered processes: (deadline 400 ms)n Ad-hoc: 429 msn Greedy 1: 314 msn Greedy 2: 323 msn SA: 302 ms

n Event triggered processes: (no messages, deadline 130 ms)n Ignoring Conditions: 138 msn Conditions Separation: 132 msn Relaxed Tightness 1, 2: 124 msn Brute Force: 124 ms


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Conclusions and Future WorkTime triggered processes:

n Extension to static scheduling for CPGs to handle TTP.

n Improved schedule quality by using new priority function thatconsiders the time triggered protocol.

n Significant performance improvements can be obtained by optimizingthe access to the communication channel.

Event triggered processes:

n Schedulability analysis with the TTP: four message schedulingapproaches compared based on the issue of schedulability.

n Significant improvements to the “degree of schedulability” throughthe optimization of the bus access scheme.

n The pessimism of the analysis can be drastically reduced by considering the conditions.

Mapping of processes and architecture selection.


30 of 30June 14, 2000

Contributions

Time triggered processes:

n Static scheduling strategy for systems with

both control and data dependencies.

n Optimization strategies for the synthesis of the

bus access scheme.

Event triggered processes:

n Less pessimistic schedulability analysis for hard real-time

systems with both control and data dependencies

n Schedulability analysis for the time-triggered protocol.

n Optimization strategies for the synthesis of the

bus access scheme.

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