Schedule
1
Tentative Plan of Lectures EEE425/591: Digital Systems and Circuits; 3:00pm-4:15pm, M/W Instructor: Y. Kevin Cao, [email protected] Office hour: 1:30pm-2:30pm, M/W Week Date Class Schedule Homework Labortary 1 8/25/2014 1 Introduction 8/27/2014 2 Logic Gate Basics HW1 2 9/1/2014 Labor Day 9/3/2014 3 CMOS Technology Lab 1 3 9/8/2014 4 Layout and Design Rules 9/10/2014 5 CMOS Modeling (1) 4 9/15/2014 6 CMOS Modeling (2) HW2 9/17/2014 7 Inverter Design 5 9/22/2014 8 Gate Delay and Power Consumption Lab 2 9/24/2014 9 Technology Scaling 6 9/29/2014 Midterm I 10/1/2014 10 Combinational Static Logic 7 10/6/2014 11 Timing Analysis in Logic Design 10/8/2014 12 Gate Sizing: Logical Efforts (1) HW3 8 10/13/2014 Fall Break 10/15/2014 13 Gate Sizing: Logical Efforts (2) Lab 3 9 10/20/2014 14 Gate Sizing: Logical Efforts (3) 10/22/2014 15 Pass Gate Logic HW4 10 10/27/2014 16 Dynamic Logic (1) 10/29/2014 17 Dynamic Logic (2) 11 11/3/2014 Midterm II 11/5/2014 18 Adder Design Lab 4/5 12 11/10/2014 19 Multipliers and Shifters 11/12/2014 20 Sequential Circuits Design HW5 13 11/17/2014 21 Latches and Flip Flops 11/19/2014 22 Timing Issues in Latches and FFs (1) 14 11/24/2014 23 Timing Issues in Latches and FFs (2) HW6 11/26/2014 24 Clocking and Synchronous Design 15 12/1/2014 25 Interconnect Technology and Timing 12/3/2014 Final Exam 16 12/10/2014 Final Exam (12:10-2:00pm) * The date of homework and project is when the assignment starts, not the due date.
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Tentative Plan of Lectures
EEE425/591: Digital Systems and Circuits; 3:00pm-4:15pm, M/W
Instructor: Y. Kevin Cao, [email protected]
Office hour: 1:30pm-2:30pm, M/W
Week Date Class Schedule Homework Labortary
1 8/25/2014 1 Introduction
8/27/2014 2 Logic Gate Basics HW1
2 9/1/2014 Labor Day
9/3/2014 3 CMOS Technology Lab 1
3 9/8/2014 4 Layout and Design Rules
9/10/2014 5 CMOS Modeling (1)
4 9/15/2014 6 CMOS Modeling (2) HW2
9/17/2014 7 Inverter Design
5 9/22/2014 8 Gate Delay and Power Consumption Lab 2
9/24/2014 9 Technology Scaling
6 9/29/2014 Midterm I
10/1/2014 10 Combinational Static Logic
7 10/6/2014 11 Timing Analysis in Logic Design
10/8/2014 12 Gate Sizing: Logical Efforts (1) HW3
8 10/13/2014 Fall Break
10/15/2014 13 Gate Sizing: Logical Efforts (2) Lab 3
9 10/20/2014 14 Gate Sizing: Logical Efforts (3)
10/22/2014 15 Pass Gate Logic HW4
10 10/27/2014 16 Dynamic Logic (1)
10/29/2014 17 Dynamic Logic (2)
11 11/3/2014 Midterm II
11/5/2014 18 Adder Design Lab 4/5
12 11/10/2014 19 Multipliers and Shifters
11/12/2014 20 Sequential Circuits Design HW5
13 11/17/2014 21 Latches and Flip Flops
11/19/2014 22 Timing Issues in Latches and FFs (1)
14 11/24/2014 23 Timing Issues in Latches and FFs (2) HW6
11/26/2014 24 Clocking and Synchronous Design
15 12/1/2014 25 Interconnect Technology and Timing
12/3/2014 Final Exam
16 12/10/2014 Final Exam (12:10-2:00pm)
* The date of homework and project is when the assignment starts, not the due date.
