SCAS295T –JANUARY 1993–REVISED JULY 2014 · PDF fileSCAS295T –JANUARY...

OE

To Seven Other Channels

1

11

3

2

LE

1D

C1

1D1Q

Pin numbers shown are for the DB, DGV, DW, FK, J, N, NS, PW, RGY, and W packages.

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Folder

Sample &Buy

Technical

Documents

Tools &

Software

Support &Community

SN54LVC373A, SN74LVC373ASCAS295T –JANUARY 1993–REVISED JULY 2014

SNx4LVC373A Octal Transparent D-Type Latches With 3-State Outputs1 Features 2 Applications1• Operate From 1.65 V to 3.6 V • Network Switches• Inputs Accept Voltages to 5.5 V • TV Set-top Boxes• Max tpd of 6.8 ns at 3.3 V • Motor Drives• Typical VOLP (Output Ground Bounce) • PCs and Notebooks

<0.8 V at VCC = 3.3 V, TA = 25°C3 Description• Typical VOHV (Output VOH Undershoot)The SN54LVC373A octal transparent D-type latch is>2 V at VCC = 3.3 V, TA = 25°Cdesigned for 2.7-V to 3.6-V VCC operation, and the• Supports Mixed-Mode Signal OperationSN74LVC373A octal transparent D-type latch ison All Ports designed for 1.65-V to 3.6-V VCC operation.(5-V Input/Output Voltage With 3.3-V VCC)

• Ioff Supports Live-Insertion, Partial-Power-Down Device Information(1)

Mode, and Back-Drive Protection PART NUMBER PACKAGE BODY SIZE (NOM)• Latch-Up Performance Exceeds 250 mA Per SSOP (20) 7.20 mm × 5.30 mm

JESD 17 SOIC (20) 12.80 mm × 7.50 mm• ESD Protection Exceeds JESD 22 SNx4LVC373A PDIP (20) 24.33 mm 6.35 mm

– 2000-V Human-Body Model (A114-A) TSSOP (20) 6.50 mm × 4.40 mmVQFN (20) 4.50 mm × 3.50 mm– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101) (1) For all available packages, see the orderable addendum atthe end of the data sheet.• On Products Compliant to MIL-PRF-38535,

All Parameters Are Tested Unless OtherwiseNoted. On All Other Products, ProductionProcessing Does Not Necessarily Include Testingof All Parameters.

4 Simplified Schematic

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

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SN54LVC373A, SN74LVC373ASCAS295T –JANUARY 1993–REVISED JULY 2014 www.ti.com

Table of Contents1 Features .................................................................. 1 9 Detailed Description .............................................. 9

9.1 Overview ................................................................... 92 Applications ........................................................... 19.2 Functional Block Diagram ......................................... 93 Description ............................................................. 19.3 Feature Description................................................. 104 Simplified Schematic............................................. 19.4 Device Functional Modes........................................ 105 Revision History..................................................... 2

10 Application and Implementation........................ 116 Pin Configuration and Functions ......................... 310.1 Application Information.......................................... 117 Specifications......................................................... 410.2 Typical Application ............................................... 117.1 Absolute Maximum Ratings ..................................... 4

11 Power Supply Recommendations ..................... 127.2 Handling Ratings....................................................... 412 Layout................................................................... 127.3 Recommended Operating Conditions ...................... 5

12.1 Layout Guidelines ................................................. 127.4 Thermal Information .................................................. 512.2 Layout Example .................................................... 127.5 Electrical Characteristics........................................... 6

13 Device and Documentation Support ................. 137.6 Timing Requirements, SN54LVC373A ..................... 613.1 Related Links ........................................................ 137.7 Timing Requirements, SN74LVC373A ..................... 613.2 Trademarks ........................................................... 137.8 Switching Characteristics, SN54LVC373A ............... 713.3 Electrostatic Discharge Caution............................ 137.9 Switching Characteristics, SN74LVC373A ............... 713.4 Glossary ................................................................ 137.10 Operating Characteristics........................................ 7

14 Mechanical, Packaging, and Orderable7.11 Typical Characteristics ............................................ 7Information ........................................................... 138 Parameter Measurement Information .................. 8

5 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision S (May 2005) to Revision T Page

• Updated document to new TI data sheet format. ................................................................................................................... 1• Removed Ordering Information table. .................................................................................................................................... 1• Changed Ioff Feature. .............................................................................................................................................................. 1• Added Military Disclaimer to Features.................................................................................................................................... 1• Added Applications. ................................................................................................................................................................ 1• Added Handling Ratings table. ............................................................................................................................................... 4• Changed MAX ambient temperature from 85°C to 125°C. .................................................................................................... 5• Added Thermal Information table. .......................................................................................................................................... 5• Added Typical Characteristics. .............................................................................................................................................. 7• Added Detailed Description section........................................................................................................................................ 9

2 Submit Documentation Feedback Copyright © 1993–2014, Texas Instruments Incorporated

Product Folder Links: SN54LVC373A SN74LVC373A



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GQN OR ZQN PACKAGE(TOP VIEW)

1 2 3 4

A

B

C

D

E

SN54LVC373A . . . FK PACKAGE

(TOP VIEW)

3 2 1 20 19

9 10 11 12 13

4

5

6

7

8

18

17

16

15

14

2D

2Q

3Q

3D

4D

1D

1Q

OE

5Q

5D

8Q

4Q

GN

D

LE

VC

C

8D

7D

7Q

6Q

6D

SN74LVC373A . . . RGY PACKAGE

(TOP VIEW)

1 20

10 11

2

3

4

5

6

7

8

9

19

18

17

16

15

14

13

12

8Q

8D

7D

7Q

6Q

6D

5D

5Q

1Q

1D

2D

2Q

3Q

3D

4D

4Q

LE

V

GN

D

CC

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

OE

1Q

1D

2D

2Q

3Q

3D

4D

4Q

GND

VCC

8Q

8D

7D

7Q

6Q

6D

5D

5Q

LE

SN54LVC373A . . . J OR W PACKAGE

SN74LVC373A . . . DB, DGV, DW, N,

NS, OR PW PACKAGE

(TOP VIEW)

OE

SN54LVC373A, SN74LVC373Awww.ti.com SCAS295T –JANUARY 1993–REVISED JULY 2014

6 Pin Configuration and Functions

Pin FunctionsPIN

I/O DESCRIPTIONNO. NAME1 OE I Enable Pin2 1Q O Output 13 1D I Input 14 2D I Input 25 2Q O Output 26 3Q O Output 37 3D I Input 38 4D I Input 49 4Q O Output 410 GND – Ground Pin11 LE I Latch Enable12 5Q O Output 513 5D I Input 514 6D I Input 615 6Q O Output 616 7Q O Output 717 7D I Input 718 8D I Input 819 8Q O Output 820 VCC – Power Pin

Table 1. Pin Assignments1 2 3 4

A 1Q OE VCC 8QB 2D 7D 1D 8DC 3Q 2Q 6Q 7QD 4D 5D 3D 6DE GND 4Q LE 5Q

Copyright © 1993–2014, Texas Instruments Incorporated Submit Documentation Feedback 3




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7 Specifications

7.1 Absolute Maximum Ratings (1)

over operating free-air temperature range (unless otherwise noted)MIN MAX UNIT

VCC Supply voltage range –0.5 6.5 VVI Input voltage range (2) –0.5 6.5 VVO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 VVO Voltage range applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 VIIK Input clamp current VI < 0 –50 mAIOK Output clamp current VO < 0 –50 mAIO Continuous output current ±50 mA

Continuous current through VCC or GND ±100 mA

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.(3) The value of VCC is provided in the Recommended Operating Conditions table.

7.2 Handling RatingsMIN MAX UNIT

Tstg Storage temperature range –65 150 °CHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001, all 0 2000pins (1)

V(ESD) Electrostatic discharge VCharged device model (CDM), per JEDEC specification 0 1000JESD22-C101, all pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.





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7.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted) (1)

SN54LVC373A SN74LVC373AUNIT

MIN MAX MIN MAXOperating 2 3.6 1.65 3.6

VCC Supply voltage VData retention only 1.5 1.5VCC = 1.65 V to 1.95 V 0.65 × VCC

VIH High-level input voltage VCC = 2.3 V to 2.7 V 1.7 VVCC = 2.7 V to 3.6 V 2 2VCC = 1.65 V to 1.95 V 0.35 × VCC

VIL Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 VVCC = 2.7 V to 3.6 V 0.8 0.8

VI Input voltage 0 5.5 0 5.5 VHigh or low state 0 VCC 0 VCCVO Output voltage V3-state 0 5.5 0 5.5VCC = 1.65 V –4VCC = 2.3 V –8

IOH High-level output current mAVCC = 2.7 V –12 –12VCC = 3 V –24 –24VCC = 1.65 V 4VCC = 2.3 V 8

IOL Low-level output current mAVCC = 2.7 V 12 12VCC = 3 V 24 24

Δt/Δv Input transition rise or fall rate 10 10 ns/VTA Operating free-air temperature –55 125 –40 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, (SCBA004).

7.4 Thermal InformationSN74LVC373A

THERMAL METRIC (1) PW UNIT20 PINS

RθJA Junction-to-ambient thermal resistance 102.5RθJC(top) Junction-to-case (top) thermal resistance 35.9RθJB Junction-to-board thermal resistance 53.5

°C/WψJT Junction-to-top characterization parameter 2.2ψJB Junction-to-board characterization parameter 52.9RθJC(bot) Junction-to-case (bottom) thermal resistance n/a

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.





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7.5 Electrical Characteristicsover recommended operating free-air temperature range (unless otherwise noted)

SN54LVC373A SN74LVC373APARAMETER TEST CONDITIONS VCC UNIT

MIN TYP (1) MAX MIN TYP (1) MAX1.65 V to 3.6 V VCC – 0.2

IOH = –100 µA2.7 V to 3.6 V VCC – 0.2

IOH = –4 mA 1.65 V 1.2VOH IOH = –8 mA 2.3 V 1.7 V

2.7 V 2.2 2.2IOH = –12 mA

3 V 2.4 2.4IOH = –24 mA 3 V 2.2 2.2

1.65 V to 3.6 V 0.2IOL = 100 µA

2.7 V to 3.6 V 0.2IOL = 4 mA 1.65 V 0.45

VOL VIOL = 8 mA 2.3 V 0.7IOL = 12 mA 2.7 V 0.4 0.4IOL = 24 mA 3 V 0.55 0.55

II VI = 0 to 5.5 V 3.6 V ±5 ±5 µAIoff VI or VO = 5.5 V 0 ±10 µAIOZ VO = 0 to 5.5 V 3.6 V ±15 ±10 µA

VI = VCC or GND 10 10ICC IO = 0 3.6 V µA

3.6 V ≤ VI ≤ 5.5 V (2) 10 10One input at VCC – 0.6 V,ΔICC 2.7 V to 3.6 V 500 500 µAOther inputs at VCC or GND

Ci VI = VCC or GND 3.3 V 4 12 4 pFCo VO = VCC or GND 3.3 V 5.5 12 5.5 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.(2) This applies in the disabled state only.

7.6 Timing Requirements, SN54LVC373Aover recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)

SN54LVC373AVCC = 3.3 VPARAMETER VCC = 2.7 V UNIT± 0.3 V

MIN MAX MIN MAXtw Pulse duration, LE high 3.3 3.3 nstsu Setup time, data before LE↓ 2 2 nsth Hold time, data after LE↓ 2 2 ns

7.7 Timing Requirements, SN74LVC373Aover recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)

SN74LVC373AVCC = 1.8 V VCC = 2.5 V VCC = 3.3 VPARAMETER VCC = 2.7 V UNIT± 0.15 V ± 0.2 V ± 0.3 V

MIN MAX MIN MAX MIN MAX MIN MAXtw Pulse duration, LE high 9 4 3.3 3.3 nstsu Setup time, data before LE↓ 6 4 2 2 nsth Hold time, data after LE↓ 4 2 1.5 1.5 ns





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VCC - V

TP

D -

ns

0 0.5 1 1.5 2 2.5 3 3.50

1

2

3

4

5

6

7

8

D003

TPD in ns

Temperature (qC)

TP

D -

ns

-100 -50 0 50 100 1500

1

2

3

4

5

6

D001

TPD in ns


7.8 Switching Characteristics, SN54LVC373Aover recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)

SN54LVC373AFROM TO VCC = 3.3 VPARAMETER VCC = 2.7 V UNIT(INPUT) (OUTPUT) ± 0.3 V

MIN MAX MIN MAXD 8.5 1 7.5

tpd Q nsLE 9.5 1 8.5

ten OE Q 8.7 1 7.7 nstdis OE Q 8 0.5 7 ns

7.9 Switching Characteristics, SN74LVC373Aover recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)

SN74LVC373AFROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 VPARAMETER VCC = 2.7 V UNIT(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V

MIN MAX MIN MAX MIN MAX MIN MAXD 1 19.1 1 9.6 7.8 1.5 6.8

tpd Q nsLE 1 22.8 1 10.5 8.2 2 7.6

ten OE Q 1 20 1 10.5 8.7 1.5 7.7 nstdis OE Q 1 19.3 1 7.8 7.6 1.5 7 ns

tsk(o) 1 1 1 1 ns

7.10 Operating CharacteristicsTA = 25°C

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 VTESTPARAMETER UNITCONDITIONS TYP TYP TYPOutputs enabled 61 56 46Power dissipation capacitanceCpd f = 10 MHz pFper latch Outputs disabled 3 3 3

7.11 Typical Characteristics

Figure 1. SN74LVC373A LE to Q TDP Figure 2. SN74LVC373A LE to QVCC vs TPD at 25°C Across Temperature at 3.3-V VCC





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VM

thtsu

From OutputUnder Test

CL(see Note A)

LOAD CIRCUIT

S1VLOAD

Open

GND

RL

RL

Data Input

Timing InputVI

0 V

VI

0 V0 V

tw

Input

VOLTAGE WAVEFORMSSETUP AND HOLD TIMES

VOLTAGE WAVEFORMSPROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMSPULSE DURATION

tPLH

tPHL

tPHL

tPLH

VOH

VOH

VOL

VOL

VI

0 VInput

OutputWaveform 1S1 at VLOAD(see Note B)

OutputWaveform 2

S1 at GND(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

VLOAD/2

0 V

VOL + V∆

VOH - V∆

≈0 V

VI

VOLTAGE WAVEFORMSENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

Output

tPLH/tPHLtPLZ/tPZLtPHZ/tPZH

OpenVLOADGND

TEST S1

NOTES: A. CL includes probe and jig capacitance.B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.D. The outputs are measured one at a time, with one transition per measurement.E. tPLZ and tPHZ are the same as tdis.F. tPZL and tPZH are the same as ten.G. tPLH and tPHL are the same as tpd.H. All parameters and waveforms are not applicable to all devices.

OutputControl

VM VM

VM VM

VM VM

VM

VM VM

VM

VM

VM

VI

VM

VM

1.8 V ± 0.15 V2.5 V ± 0.2 V

2.7 V3.3 V ± 0.3 V

1 kΩ500 Ω500 Ω500 Ω

VCC RL

2 × VCC2 × VCC

6 V6 V

VLOAD CL

30 pF30 pF50 pF50 pF

0.15 V0.15 V0.3 V0.3 V

V∆

VCCVCC2.7 V2.7 V

VI

VCC/2VCC/21.5 V1.5 V

VMtr/tf

≤2 ns≤2 ns

≤2.5 ns≤2.5 ns

INPUTS


8 Parameter Measurement Information

Figure 3. Load Circuit and Voltage Waveforms





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OE

To Seven Other Channels

1

11

3

2

LE

1D

C1

1D1Q

Pin numbers shown are for the DB, DGV, DW, FK, J, N, NS, PW, RGY, and W packages.


9 Detailed Description

9.1 OverviewWhile the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Qoutputs are latched at the logic levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high orlow logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive thebus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lineswithout interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be enteredwhile the outputs are in the high-impedance state.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables theoutputs, preventing damaging current backflow through the devices when they are powered down.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translatorsin a mixed 3.3-V/5-V system environment.

9.2 Functional Block Diagram





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9.3 Feature Description• Wide operating voltage range

– Operates from 1.65 V to 3.6 V• Allows down voltage translation

– Inputs accept voltages to 5.5 V• Ioff feature

– Allows voltages on the inputs and outputs when VCC is 0 V

9.4 Device Functional Modes

Table 2. Function Table (Each Latch)INPUTS OUTPUT

QOE LE DL H H HL H L LL L X Q0

H X X Z





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µC or

System Logic

OE V

GND

CLK

1D

8D

1Q

8Q

Regulated 3.3 V

µC

System Logic

LEDs

CC


10 Application and Implementation

10.1 Application InformationThe SN74LVC373A is a high-drive CMOS device that can be used for a multitude of bus-interface typeapplications where the data needs to be retained or latched. It can produce 24 mA of drive current at 3.3 V.Therefore, this device is ideal for driving multiple outputs and for high speed applications up to 100 Mhz. Theinputs are 5.5 V tolerant allowing it to translate down to VCC.

10.2 Typical Application

Figure 4. Typical Application Diagram

10.2.1 Design RequirementsThis device uses CMOS technology and has balanced output drive. Care should be taken to avoid buscontention because it can drive currents that would exceed maximum limits. The high drive will also create fastedges into light loads; therefore, routing and load conditions should be considered to prevent ringing.

10.2.2 Detailed Design Procedure1. Recommended Input Conditions

– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.– Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.

2. Recommend Output Conditions– Load currents should not exceed 50 mA per output and 100 mA total for the part.– Outputs should not be pulled above VCC.





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Vcc

Unused Input

Input

Output

Input

Unused Input Output

ICC - V

Fre

quen

cy -

MH

z

0 10 20 30 40 50 600

0.5

1

1.5

2

2.5

3

D003

ICC 1.8 VICC 2.5 VICC 3.3 V


Typical Application (continued)10.2.3 Application Curves

Figure 5. ICC vs Frequency

11 Power Supply RecommendationsThe power supply can be any voltage between the MIN and MAX supply voltage rating located in theRecommended Operating Conditions table.

Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a singlesupply, 0.1 μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for eachpower pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and a1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin aspossible for best results.

12 Layout

12.1 Layout GuidelinesWhen using multiple bit logic devices inputs should never float.

In many cases, functions or parts of functions of digital logic devices are unused, for example, when only twoinputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not beleft unconnected because the undefined voltages at the outside connections result in undefined operationalstates. Figure 6 specifies the rules that must be observed under all circumstances. All unused inputs of digitallogic devices must be connected to a high or low bias to prevent them from floating. The logic level that shouldbe applied to any particular unused input depends on the function of the device. Generally they will be tied toGND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,unless the part is a transceiver.

12.2 Layout Example

Figure 6. Layout Diagram





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13 Device and Documentation Support

13.1 Related LinksThe table below lists quick access links. Categories include technical documents, support and communityresources, tools and software, and quick access to sample or buy.

Table 3. Related LinksTECHNICAL TOOLS & SUPPORT &PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY

SN54LVC373A Click here Click here Click here Click here Click hereSN74LVC373A Click here Click here Click here Click here Click here

13.2 TrademarksAll trademarks are the property of their respective owners.

13.3 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

13.4 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.





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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

5962-9757301Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-9757301Q2ASNJ54LVC373AFK

5962-9757301QRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9757301QRASNJ54LVC373AJ

5962-9757301QSA ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9757301QSASNJ54LVC373AW

SN74LVC373ADBR ACTIVE SSOP DB 20 2000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 LC373A

SN74LVC373ADBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS& no Sb/Br)


SN74LVC373ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS& no Sb/Br)


SN74LVC373ADW ACTIVE SOIC DW 20 25 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 LVC373A

SN74LVC373ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS& no Sb/Br)


SN74LVC373ADWR ACTIVE SOIC DW 20 2000 Green (RoHS& no Sb/Br)


SN74LVC373AN ACTIVE PDIP N 20 20 Pb-Free(RoHS)

CU NIPDAU N / A for Pkg Type -40 to 85 SN74LVC373AN

SN74LVC373ANSR ACTIVE SO NS 20 2000 Green (RoHS& no Sb/Br)


SN74LVC373ANSRG4 ACTIVE SO NS 20 2000 Green (RoHS& no Sb/Br)


SN74LVC373APW ACTIVE TSSOP PW 20 70 Green (RoHS& no Sb/Br)


SN74LVC373APWE4 ACTIVE TSSOP PW 20 70 Green (RoHS& no Sb/Br)


SN74LVC373APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS& no Sb/Br)


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Addendum-Page 2

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

SN74LVC373APWR ACTIVE TSSOP PW 20 2000 Green (RoHS& no Sb/Br)

CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 LC373A

SN74LVC373APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS& no Sb/Br)


SN74LVC373APWT ACTIVE TSSOP PW 20 250 Green (RoHS& no Sb/Br)


SN74LVC373APWTE4 ACTIVE TSSOP PW 20 250 Green (RoHS& no Sb/Br)


SN74LVC373ARGYR ACTIVE VQFN RGY 20 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 85 LC373A

SN74LVC373AZQNR ACTIVE BGAMICROSTAR

JUNIOR

ZQN 20 1000 Green (RoHS& no Sb/Br)

SNAGCU Level-1-260C-UNLIM -40 to 85 LC373A

SNJ54LVC373AFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-9757301Q2ASNJ54LVC373AFK

SNJ54LVC373AJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9757301QRASNJ54LVC373AJ

SNJ54LVC373AW ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9757301QSASNJ54LVC373AW

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.










http://www.ti.com/productcontent



Addendum-Page 3

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54LVC373A, SN74LVC373A :

• Catalog: SN74LVC373A

• Automotive: SN74LVC373A-Q1, SN74LVC373A-Q1

• Enhanced Product: SN74LVC373A-EP, SN74LVC373A-EP

• Military: SN54LVC373A

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

http://focus.ti.com/docs/prod/folders/print/sn74lvc373a.html

http://focus.ti.com/docs/prod/folders/print/sn74lvc373a-q1.html

http://focus.ti.com/docs/prod/folders/print/sn74lvc373a-q1.html

http://focus.ti.com/docs/prod/folders/print/sn74lvc373a-ep.html

http://focus.ti.com/docs/prod/folders/print/sn74lvc373a-ep.html

http://focus.ti.com/docs/prod/folders/print/sn54lvc373a.html



Addendum-Page 4

• Military - QML certified for Military and Defense Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

SN74LVC373ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1

SN74LVC373ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

SN74LVC373ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1

SN74LVC373ANSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1

SN74LVC373APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

SN74LVC373APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

SN74LVC373APWT TSSOP PW 20 250 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

SN74LVC373ARGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1

SN74LVC373AZQNR BGA MI CROSTA

R JUNI OR

ZQN 20 1000 330.0 12.4 3.3 4.3 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 6-May-2017

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN74LVC373ADBR SSOP DB 20 2000 367.0 367.0 38.0

SN74LVC373ADGVR TVSOP DGV 20 2000 367.0 367.0 35.0

SN74LVC373ADWR SOIC DW 20 2000 367.0 367.0 45.0

SN74LVC373ANSR SO NS 20 2000 367.0 367.0 45.0

SN74LVC373APWR TSSOP PW 20 2000 364.0 364.0 27.0

SN74LVC373APWR TSSOP PW 20 2000 367.0 367.0 38.0

SN74LVC373APWT TSSOP PW 20 250 367.0 367.0 38.0

SN74LVC373ARGYR VQFN RGY 20 3000 367.0 367.0 35.0

SN74LVC373AZQNR BGA MICROSTARJUNIOR

ZQN 20 1000 336.6 336.6 28.6

PACKAGE MATERIALS INFORMATION

www.ti.com 6-May-2017

Pack Materials-Page 2

http://www.ti.com/lit/slua271

MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN

14

3,70

3,50 4,90

5,10

20DIM

PINS **

4073251/E 08/00

1,20 MAX

Seating Plane

0,050,15

0,25

0,500,75

0,230,13

1 12

24 13

4,304,50

0,16 NOM

Gage Plane

A

7,90

7,70

382416

4,90

5,103,70

3,50

A MAX

A MIN

6,606,20

11,20

11,40

56

9,60

9,80

48

0,08

M0,070,40

0°–8°

NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.D. Falls within JEDEC: 24/48 Pins – MO-153

14/16/20/56 Pins – MO-194

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

4040065 /E 12/01

28 PINS SHOWN

Gage Plane

8,207,40

0,550,95

0,25

38

12,90

12,30

28

10,50

24

8,50

Seating Plane

9,907,90

30

10,50

9,90

0,38

5,605,00

15

0,22

14

A

28

1

2016

6,506,50

14

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65 M0,15

0°–8°

0,10

0,090,25

NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.D. Falls within JEDEC MO-150

www.ti.com

PACKAGE OUTLINE

C

TYP10.639.97

2.65 MAX

18X 1.27

20X 0.510.31

2X11.43

TYP0.330.10

0 - 80.30.1

0.25GAGE PLANE

1.270.40

A

NOTE 3

13.012.6

B 7.67.4

4220724/A 05/2016

SOIC - 2.65 mm max heightDW0020ASOIC

NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.5. Reference JEDEC registration MS-013.

120

0.25 C A B

1110

PIN 1 IDAREA

NOTE 4

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL ATYPICAL

SCALE 1.200

www.ti.com

EXAMPLE BOARD LAYOUT

(9.3)

0.07 MAXALL AROUND

0.07 MINALL AROUND

20X (2)

20X (0.6)

18X (1.27)

(R )TYP

0.05

4220724/A 05/2016


SYMM

SYMM

LAND PATTERN EXAMPLESCALE:6X

1

10 11

20

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METALSOLDER MASKOPENING

NON SOLDER MASKDEFINED

SOLDER MASK DETAILS

SOLDER MASKOPENING

METAL UNDERSOLDER MASK

SOLDER MASKDEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

(9.3)

18X (1.27)

20X (0.6)

20X (2)

4220724/A 05/2016


NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.

SYMM

SYMM

1

10 11

20

SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL

SCALE:6X

IMPORTANT NOTICE

Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to itssemiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyersshould obtain the latest relevant information before placing orders and should verify that such information is current and complete.TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integratedcircuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products andservices.Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and isaccompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduceddocumentation. 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Designer represents that, withrespect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerousconsequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm andtake appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer willthoroughly test such applications and the functionality of such TI products as used in such applications.TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended toassist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in anyway, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resourcesolely for this purpose and subject to the terms of this Notice.TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TIproducts, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specificallydescribed in the published documentation for a particular TI Resource.Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications thatinclude the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISETO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTYRIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, orother intellectual property right relating to any combination, machine, or process in which TI products or services are used. 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IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES INCONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEENADVISED OF THE POSSIBILITY OF SUCH DAMAGES.Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, suchproducts are intended to help enable customers to design and create their own applications that meet applicable functional safety standardsand requirements. Using products in an application does not by itself establish any safety features in the application. Designers mustensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products inlife-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., lifesupport, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, allmedical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applicationsand that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatoryrequirements in connection with such selection.Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-compliance with the terms and provisions of this Notice.

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