Scanning FM Receiver 525.742.31 SOC FPGA Design Lab Project by Marc Chiesa.

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Scanning FM Receiver 525.742.31 SOC FPGA Design Lab Project by Marc Chiesa

Transcript of Scanning FM Receiver 525.742.31 SOC FPGA Design Lab Project by Marc Chiesa.

Page 1: Scanning FM Receiver 525.742.31 SOC FPGA Design Lab Project by Marc Chiesa.

Scanning FM Receiver525.742.31 SOC FPGA Design LabProject by Marc Chiesa

Page 2: Scanning FM Receiver 525.742.31 SOC FPGA Design Lab Project by Marc Chiesa.

Overview

We have an SDR interface from Lab 6 that can play tones from a tuned “receiver”.

Expand the idea to search for tones using tuning capability and an FFT.

If an actual receiver is used, we can find “interesting signals” and attempt to FM demodulate them.

Page 3: Scanning FM Receiver 525.742.31 SOC FPGA Design Lab Project by Marc Chiesa.

FFT Block

Takes complex data in, so take the incoming IF and mix it down to baseband with both sine and cosine.

To find magnitude of a bin using complex output, take square root of sum of squares for real and imaginary.

Uses a relatively large number of DSP blocks, but there are plenty available on the Spartan 3A.

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FFT Interface

Need a block to help process the output of the FFT

Can assert the proper signals to start the FFT process and collect the data as it streams out.

Will use relative magnitudes of adjacent bins to help solve “spectral leakage” problem.

Alerts FM demod block when a signal has been found

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FM Demod Block

Will consist of multiple sub-blocks.

Need to channel select and filter(mix the channel down and low-pass filter)

FM demod can use CORDIC IP Core to compute arctangent of Q/I

Differentiate result of CORDIC block

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DAC Block

No real changes from previous labs except how it is enabled only when audio samples are being generated

Audio samples will also stream via Ethernet.

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Microblaze

Want to ensure good throughput and responsiveness for both user and system tasks.

Using an RTOS is a good compromise between the two goals.

A port for Microblaze exists, just needs to be tweaked for specific setup.

Will handle interfaces much the same as previous labs, but without round-robin looping overhead.

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External Receiver

Will provide an IF frequency to the ADC

Our job is to tune the receiver using the necessary interface

Once tuned, try to find signals, and if we reach the end of the band, retune receiver to next chunk of spectrum and scan again

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Still to discover

How much averaging of FFT results will need to be done to get a reliable guess for signal location

What (if any) windowing needs to be done with the FFT to minimize spectral leakage

How to get interface with on-board LCD for feedback to user.

Page 10: Scanning FM Receiver 525.742.31 SOC FPGA Design Lab Project by Marc Chiesa.

Nov 10-17

Implement FFT engine, dump bin results via Ethernet

Start to revamp Microblaze code for better command and control (results can be rolled into Lab 6)

Modularize other software blocks for easier debugging and general cleanliness

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Nov 17-24

Get FFT scanning and detection working properly (must be able to at least find a quiet carrier)

Implement FM demodulation block

Implement RTOS for Microblaze

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Nov 24 - Dec 1

Integrate receiver module into design

Implement any averaging and windowing that needs to be done for FFT results

Finalize FM demod block

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Dec 1 - 8

Finalize any signal detection results.

Implement any other features (LCD display, locking a frequency so that search is paused until user restarts, etc).