SAR ADC Algorithm with Redundancy
Transcript of SAR ADC Algorithm with Redundancy
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SAR ADC Algorithm with
Redundancy
T. Ogawa, H. Kobayashi, M. Hotta,
Y. Takahashi, H. San, N. Takai
Gunma University, Tokyo City University
Supported by STARC
Presentation at Shenyang University of Chemical Technology
Recent Research ResultsSept. 2011
Published in
T. Ogawa, H. Kobayashi, et. al.,
“SAR ADC Algorithm with Redundancy and Digital Error Correction”,
IEICE Trans. Fundamentals, vol.E93-A, no.2, (Feb. 2010).
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SamplingQuantization in time domain
― Analog signal
● Sampling point
time
Take data ● and discard the other data.
What is digital signal ?
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Quantization of Signal Level
― Analog signal
― Digital signal
What is digital signal ?
time
Round the signal level to an integer.
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t
(a) Analog Signal
(b) Sampling
tT
MSB
111
110
101
100
011
010
001
LSB
t
t
(c)Quantization
(d)Quantization Noise
110
1111
11
11
11
11
110
011
010
001
001
001
001
010
MSB
LSB
(e)Encodingt
Analog-to-Digital Conversion
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ADC is for Digital Signal Processing
ServoVideo
Sound
Pressure
Temperature
Analog
in real worldDigital
In computer
SOC:
System On a Chip5
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Outline
• Research purpose
• SAR ADC
• Binary search algorithm
• Non-binary search algorithm
• Proposed non-binary search algorithm
• DAC incomplete settling
• Conclusion
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Outline
• Research purpose
• SAR ADC
• Binary search algorithm
• Non-binary search algorithm
• Proposed non-binary search algorithm
• DAC incomplete settling
• Conclusion
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Research purpose
• Automotive electronics is the spotlight now.
• High speed, reliable SAR ADCs in
microcontroller are important there.
• Optimal digital error correction algorithm
for their realization.
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Outline
• Research purpose
• SAR ADC
• Binary search algorithm
• Non-binary search algorithm
• Proposed non-binary search algorithm
• DAC incomplete settling
• Conclusion
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SAR ADC Block
Sample Hold
DAC
SAR
Logic
Analog
input
Digital
output
ComparatorCLK
SAR ADC is digital centric.
→ Suitable for fine CMOS implementation.
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SAR ADC Characteristics
• High resolution (10-14bit)
• Middle sampling speed (10-40 MS/s)
• Small die area
• Low power (a few mW)
• Not use OP-amp
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Outline
• Research purpose
• SAR ADC
• Binary search algorithm
• Non-binary search algorithm
• Proposed non-binary search algorithm
• DAC incomplete settling
• Conclusion
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Binary search algorithm
Vin 8
421
“Principle of a balance”
0
8
16
Vin
Vin = 8
4_
21
= 9
1
Comparison
Comparator output
0 0 1
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Problem of binary search algorithm
0
8
16
Vin
Error
Search result has error.
Digital output has error.
0 1 1 1
No redundancy
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Outline
• Research purpose
• SAR ADC
• Binary search algorithm
• Non-binary search algorithm
• Proposed non-binary search algorithm
• DAC incomplete settling
• Conclusion
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Non-binary search algorithm
0
8
16
Vin
Error
Vin
0
8
16
1 0
Correction
Redundancy
0 1 0 1
Redundancy
1 1 1 1
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Non-binary search algorithm
Binary search algorithm(4-bit 4-step)
Conventional non-binary search algorithm
(4-bit 5-step)
dk : +1 or -1
2
5.05.01222 4321
23 ddddDout
5.05.012 5432
2
1
33 dddddDout
Binary (Radix :2)
Radix : γ43
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Principle of error correction
Binary search algorithm
Comparator output : 1 0 0 1
Non-binary search algorithm
Comparator output : 1 0 1 0 1
Comparator output : 0 1 1 1 1
Dout = 8 + 4 – 2 – 1 + 0.5 – 0.5 = 9
Dout = 8 + 3 – 2 + 1 – 1 + 0.5 – 0.5 = 9
Dout = 8 – 3 + 2 + 1 + 1 + 0.5 – 0.5 = 9
Only one
Multiple
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Outline
• Research purpose
• SAR ADC
• Binary search algorithm
• Non-binary search algorithm
• Proposed non-binary search algorithm
• DAC incomplete settling
• Conclusion
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Proposed non-binary search algorithm
Conventional non-binary search algorithm
5.05.012 5432
2
1
33 dddddDout
Generalized non-binary search algorithm
dk : +1 or -1
5.05.02 545342312
3 ddpdpdpdpDout
Flexible (not restricted to γ )
243
Radix : γ
Proposed
Optimal design
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1
1
222M
i
i
iNM q
1
1
11
1 22M
ki
i
kikM
kk qqp
Design redundancy.
qk : Redundancy at k-th step
N-bit, M-step (M>N)
Design method of proposed algorithm
pk : Step of reference voltage at k-th step
Calculate step of reference voltage.
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Proposed algorithm Example 1
0
8
16
Vin
0
8
16
0
Redundancy
p2
p2=3
p3=2
p4=1
p5=1
Error
q1=2
q2=1
q3=1
p3
p4
p5
1 1 1 1
Correction
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Proposed algorithm Example 2
0
8
16
Vin
0
16
0
Redundancy
p2
p5
Error
8
p2=2
p3=2
p4=2
p5=1
q1=4
q2=2 p3
p4
1 1 1 1
Correction
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Outline
• Research purpose
• SAR ADC
• Binary search algorithm
• Non-binary search algorithm
• Proposed non-binary search algorithm
• DAC incomplete settling
• Conclusion
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Settling of DAC output
0 1 2 3 4 50
1
2
3
4
Outp
ut o
f D
AC
[LS
B]
Settling time [τ]Short
Long
1/2LSB
Last step
First step
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Conversion time of each algorithm
Step1 Step2 Step3 Step4
Step
1
Step
2
Step
3
Step
4
Step
5
Step
6
Binary search algorithm
Non-binary search algorithm
Exact DAC settling → Long
time
Incomplete DAC settling → Short
time
A/D conversion time
Correct incomplete settling error.
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0 50 1001
1.1
1.2
1.3x 10
4
Simulation of AD Conversion Ttime
A/D conversion time
Binary algorithm
14-bit,14-step
Step time : 9.1 τ
Proposed algorithm
14-bit, 22-step
Step time : 1.2 τ
25.2 τ 118.3 τTime [τ]
Ou
tput of D
AC
[LS
B]
Proposed algorithm
Binary algorithm
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0
40
80
120
Comparison of ADC speedConversion time of each algorithm (14-bit)
Binary
algorithm
Conventional
non-binary
algorithm
Proposed
non-binary
algorithm
AD
C tim
e [
τ]
Proposed algorithm 20% faster
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Outline
• Research purpose
• SAR ADC
• Binary search algorithm
• Non-binary search algorithm
• Proposed non-binary search algorithm
• DAC incomplete settling
• Conclusion
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Conclusion
SAR ADC for automotive
• Generalized non-binary algorithm.
• Optimal redundancy design method.
→ Reliable, Faster SAR ADC
• Digital Error Correction
→ Suitable for fine CMOS implementation.
20% faster than
conventional non-binary algorithm
only with ROM contents modification.
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Non-Binary SAR ADC
Implementation and Measurement Results
SNDR comparison of
10step (binary) and 12step (non-binary)
Fin:100kHz
0.18um CMOS
2.5mm x 2.5mm
with two SAR ADCs
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Lesson from 老子
Redundancy
makes ADC performance
better
「無用」之「用」
Un-useful things are actually useful.
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