Samsung 3D TSV Stacked DDR4 DRAM 2015 teardown reverse costing report published by Yole...

DISCLAIMER : System Plus Consulting provides cost studies based on its knowledge of the manufacturing and selling prices of electronic components and systems. The given values are realistic estimates which do not bind System Plus Consulting nor the manufacturers quoted in the report. System Plus Consulting is in no case responsible for the consequences related to the use which is made of the contents of this report. The quoted trademarks are property of their owners.

© 2015 by SYSTEM PLUS CONSULTING, all rights reserved. 1

Electronic Costing & Technology Experts

www.systemplus.fr21 rue la Nouë Bras de Fer44200 Nantes – France Phone : +33 (0) 240 180 916 email : [email protected]

July 2015 – Version 1 – Written by Romain Fraux

http://www.systemplus.fr/index.php?lang=ge&page=home.php

http://www.systemplus.fr/index.php?lang=ge&page=home.php

mailto:[email protected]

mailto:[email protected]

Samsung 3D TSV DRAM

Return to TOC


Glossary

1. Overview / Introduction 4

– Executive Summary

– Reverse Costing Methodology

2. Company Profile 7

– Samsung Electronics

3. Physical Analysis 12

– Synthesis of the Physical Analysis

– Physical Analysis Methodology

– Module 15

– RDIMM Module Views & Dimensions

– Package 19

– View, Dimensions & Marking

– Package Opening

– Package PCB Line/Space

– DRAM Die 26

– View, Dimensions & Marking

– Bond Pads & TSVs

– Die Delayering

– TSV Details

– Cross-Section 36

– Package Cross-Section

– Micro-bumps Cross-Section

– TSV Cross-Section

– Flip-Chip Bumps Cross-Section

4. Manufacturing Process Flow 61

– Global Overview

– TSV & Bumping Process Flow

– Flip-Chip & Stacking Process Flow

– Package Assembly Unit

6. Cost Analysis 77

– Main steps of economic analysis

– Yields Hypotheses

– DRAM Front-End Cost

– TSV Manufacturing Cost

– TSV Manufacturing Cost per Process Steps

– Micro-Bumping Manufacturing Cost

– Micro-Bumping Cost per Process Steps

– Flip-Chip Bumping Manufacturing Cost

– Flip-Chip Bumping Cost per Process Steps

– DRAM Die Cost

– Final Packaging Cost

– Final Packaging Cost per Process Steps

– Component Cost

Contact 98

Samsung 3D TSV DRAM

Return to TOC


• This full reverse costing study has been conducted to provide insight on technology data,

manufacturing cost and selling price of the Samsung 3D TSV Stacked DRAM PRocess.

• 3D TSV technology is expected to reach $4.8B in revenues by 2019, mainly driven by 3D stacked

DRAM and followed by 3D Logic/Memory and Wide I/O according to Yole Développement.• With 40% share in the DRAM market, Samsung is by far the number 1 player. By introducing 3D TSV

stacking in their latest 64GB DDR4, Samsung allows this technology to enter in the main stream.

• This registered dual Inline memory module (RDIMM) includes 36 DDR4 DRAM chips (ref.

K4AAG045WD), each of which consists of four 4Gb DDR4 DRAM dies (Ref. K4A4G085WD). The chips

are manufactured using Samsung’s 20nm process technology and 3D TSV via-middle packagetechnology.

• As a result, the new 64GB TSV module performs twice as fast as a 64GB module that uses wirebonding packaging, while consuming approximately half the power.

• On the process side, Samsung used a temporary bonding approach using adhesive glue material andcopper via-filled using bottom up filling. Also, System Plus paid particular attention in identifying all

technical choices made by Samsung on process and equipment (wafer bonding, DRIE via etching, via

filling, bumping, underfill…).

• The report includes a complete physical analysis and cost estimation of the 3D packaging process, as

well as a detailed description of the manufacturing process.

Samsung 3D TSV DRAM

Return to TOC


• 3D Stacking Technology: TSV technology for 3DS enables DRAM stacking with better electrical

characteristics

Samsung 3D TSV DRAM

Return to TOC


Samsung 3D TSV DRAM

Return to TOC


• The registered dual Inline memory module(RDIMM) includes 36 DDR4 DRAM chips (ref.K4AAG045WD), each of which consists of four4Gb DDR4 DRAM dies (Ref. K4A4G085WD).

DDR4 DRAM Chip

Samsung 3D TSV DRAM

Return to TOC


RDIMM Module Dimensions (from datasheet)

Samsung 3D TSV DRAM

Return to TOC


• Package: FBGA 78-ball

• Dimensions: 7.5 x 11.0 x 1.1mm

• Bal Pitch: 0.8mm

Package top view Package bottom view

Package Side View

7.5mm

1.1mm

11mm

• Marking:

SEC513

K4AAG04

5WD4CRB

Y5H0330H

Samsung 3D TSV DRAM

Return to TOC


• Part number description:

K4AAG045WD4CRB

Density AG = 16Gb

DRAM Type A = DDR4 SDRAM

Memory Type 4 = DRAM

SAMSUNG Product K = Memory

Bit Organization 04 = x 4

# of Internal Banks 5 = 16 Banks

Interface (Vdd, Vddq) W = POD (1.2V, 1.2V)

Revision D = 5th Gen.

Package Type 4 = FBGA (Halogen-free & Lead-free, TSV 4High)

Temp & Power C = Commercial Temp. ( 0°C ~ 85°C) & Normal Power

Speed RB = DDR4-2133 (1066MHz @ CL=17, tRCD=15, tRP=15)

Samsung 3D TSV DRAM

Return to TOC


Samsung 3D TSV DRAM

Return to TOC


• The dies marking includes the logo of Samsung and:

2013

K4A4G085WD

Dies Marking

Samsung 3D TSV DRAM

Return to TOC


Samsung 3D TSV DRAM

Return to TOC


DRAM Front-End Cost(FEOL + BEOL)

DRAM Middle-End Cost(TSV + Bumping)

DRAM Die CostProbe Test & Dicing

Flip-Chip BGAPackaging Cost

• We perform the economic analysis of the Packaging with the 3D Package CoSim+ tool.

4

Samsung 3D TSV DRAM

Return to TOC


Samsung 3D TSV DRAM

Return to TOC


Reverse costing analysis represents the best cost/price evaluation given the publically available data, and estimates completed by industry experts.

Given the hypothesis presented in this analysis, the major sources of correction would lead to a +/- 10% correction on the manufacturing cost (if all parameters are cumulated).

These results are open for discussion. We can reevaluate this circuit with your information. Please contact us:

Samsung 3D TSV Stacked DDR4 DRAM 2015 teardown reverse costing report published by Yole...

Technology

Transcript of Samsung 3D TSV Stacked DDR4 DRAM 2015 teardown reverse costing report published by Yole...