sample ques vlsi
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1) Design a CMOS inverter circuit of following parameters: VT0 n = 0.6V, μ n C ox = 60μA/V 2 , (W/L) n = 8, VT0 p = -0.7V, μ p C ox = 25μA/V 2 , (W/L) p =12.Supply voltage = 3.3 volt. Channel length of both transistor is 0.8μm. Determine (W n /W p ) ratio so that switching threshold voltage of inverter circuit V th =1.4 volt. 2) A company has access to a CMOS fabrication process with the following device parameters listed below: μ n C ox =120 μA/V 2 , μ p C ox =60 μA/V 2 , L=0.6μm for both NMOS and PMOS, VT0 n =0.8V, VT0 p = -1.0V, Combined load capacitance value= 300fF and W min = 1.2μm.Design a CMOS inverter by determining channel width W n and W p of NMOS and PMOS transistors such that propagation delay times t PHL ≤ 0.2ns and t PLH ≤ 0.15ns. 3) Find the region of operation for the transistor M4 and M5 in the given configuration. All the transistors have identical sizes. Assume VDD = 2.5 V, and VTn = 0.4 V, W = 1μm, L = 0.25 μm, kn’ = 115 μA/V 2 .
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Transcript of sample ques vlsi
1) Design a CMOS inverter circuit of following parameters: VT0n= 0.6V, µnCox= 60µA/V2, (W/L)n= 8,
VT0p = -0.7V, µpCox = 25µA/V2, (W/L)p=12.Supply voltage = 3.3 volt. Channel length of both
transistor is 0.8µm. Determine (Wn/Wp) ratio so that switching threshold voltage of inverter circuit
Vth=1.4 volt.
2) A company has access to a CMOS fabrication process with the following device parameters listed
below:
µnCox=120 µA/V2, µpCox=60 µA/V
2, L=0.6µm for both NMOS and PMOS, VT0n=0.8V, VT0p= -1.0V,
Combined load capacitance value= 300fF and Wmin= 1.2µm.Design a CMOS inverter by determining
channel width Wn and Wp of NMOS and PMOS transistors such that propagation delay times tPHL ≤
0.2ns and tPLH ≤ 0.15ns.
3) Find the region of operation for the transistor M4 and M5 in the given configuration. All the
transistors have identical sizes. Assume VDD = 2.5 V, and VTn = 0.4 V, W = 1μm, L = 0.25 μm,
kn’ = 115 μA/V2.
