Samanta PaperReview2

7/25/2019 Samanta PaperReview2

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Name: SOURAV SAMANTA

ASU ID: 1207860455

Paper Review Assignment 2

MOTIVATION

The motivation behind writing the paper BDS: A BDD-Based Logic Optimization System may be attributed

to the fact that traditional logic optimization methodology, based on algebraic factorization [2], although

produced near optimal results for AND/OR-intensive functions of control and random logic, but could not

produce satisfactory results for arithmetic and XOR-intensive logic functions. Although, methods based on

Boolean factorization offered better results but they proved inefficient due to the usage of inappropriate datastructure which resulted in high computational complexity. The Boolean operations such as MUX and XOR

intensive logic functions received much less attention since the cube representation favoured algebraic

methods over the Boolean ones.

GOALS

The goal of the paper [1]was to come up with a practical logic synthesis, BDS and a novel logic decomposition

theory which is based on a new binary decision diagrams (BDD) technique that would prove effective for both

algebraic and Boolean class of functions. It would also have the capability to handle very large circuits and

would provide superiority in terms of runtime over traditional logic synthesis systems.

PROBLEMS & SOLUTIONS

The traditional functional decomposition methods of Ashenhurst [3]-Curtis [4] which are based on thedecomposition charts are computationally in-efficient since the number of columns in the chart grows

exponentially with the number of bound set variables, and testing decomposition with each bound set is

possible only after constructing its decomposition chart. Moreover, finding a cut that separates the bound

variables from the free variables possess a serious limitation in all such decomposition methods.

So, the paper [1]is based on the methods that makes use of the structure of BDD to identify good divisors and

directly guides the decomposition process. The paper is inspired by the work of Karplus [6] who introduced

the concept of 1- and 0-dominator and showed their relationship to algebraic AND/OR decomposition. The

methods proposed by Bertacco and Damiani[7] performed recursive decomposition directly on the BDD and

was fast and for some circuits generated much better results than SIS [5]but failed to detect complex disjoint

decompositions. The methods proposed by Stanion and Sechen [8] were able to extract XORs but the

effectiveness of such Boolean division over SIS showed marginal improvement since the methods lacked an

efficient way to generate good Boolean divisors. The existing BDD-based decomposition techniques could only

detect bidecompositions for a variable order consistent with their partitioning but failed to detect algebraic

or quasi-algebraic decomposition and required reordering of variables. The paper [1] makes use of the

methods involved with the structure of BDDs to address this problem and thus leads to efficient multi-level

logic implementations.

ASSUMPTIONS

The logic synthesis and logic decomposition technique is based on certain assumptions which are as follows:

1. The current work [1] is based on completely specified Boolean functions i.e. functions :

, = {0,1}that can be uniquely defined by its onset and offset.

2. The BDDs used in the current work refers to reduced, ordered BDDs (ROBDDs) which may have

complement edges assigned to the 0-edge for maintaining the canonicity property of ROBDDs. Thedrawings will have the positive cofactor represented by a solid 1-edge and the negative co-factor by a

dashed 0-edge.

3.

The BDD-based logic decomposition method makes use of the structure of the BDD to identify good

decompositions.

4. The BDD decomposition method prescribed in the paper detects both algebraic and Boolean

decompositions without the need for any specific variable order that is consistent with variable

partitioning.

5.

The heuristics based on the RESTRICT operator of Coudert and Madre [9]are used for BDD minimisation

with dont cares for large functions.

6. The cuts used for partitioning the set of BDD nodes are restricted to horizontal ones since the use of non-

horizontal cuts tends to increase the computational complexity.


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ASU ID: 1207860455


DESIGN STYLE AND ITS LIMITATIONS

The paper is based on two fundamental theories of BDD decomposition namely conjunctive and disjunctive

decomposition and there is no restriction with respect to algebraic or Boolean decomposition.

APPROACH

The paper [1]proposes new BDD decomposition theory to support a wide variety of decomposition styles

(AND, OR, XOR, MUX) of both algebraic and Boolean type. It describes the process of constructing a

generalized dominator by applying a cut to the BDD of a function. The cut partitions the set of BDD nodes of

the function F into D and (V - VD). The generalized dominator GD(F) of F is a specialized graph that is obtained

by copying the portion of the BDD defined by nodes VDand connecting the edges to 1(0) if the edge points to

a leaf edge of 1 (0) while keeping the internal edges (also known as free edges) as dangling.

The paper establishes lemmas for both conjunctive and disjunctive Boolean decomposition.

The Lemma 1 [1]applicable for conjunctive (AND) decomposition (F = D.Q) states that for a given

generalized dominator GD(F) of function F, the Boolean divisor D is obtained from GD(F) by redirecting

its free edges to 1. The quotient Q is obtained from F by redirecting the 0-leaf edges of D in F to dont

care nodes.

The Lemma 2 [1] applicable for disjunctive (OR) decomposition (F = G+H) states that for a given

generalized dominator GD(F) of function F, the Boolean term G can be obtained by redirecting the free

edges of GD(F) to 0. The Boolean term H is obtained from F by redirecting the 1-leaf edges of G in F to

dont care nodes.

Since, the number of possible cuts that

should be examined is too large, the

paper[1]describes a mechanism to limit

the number of cuts. It considers only

those cuts as valid cuts which contain at

least one leaf edge that can lead to

nontrivial Boolean decomposition. The

number of valid cuts are further reduced

by identifying them as 1- or 0-equivalent

cuts. The theorem 4 of the paper [1]

states that all Boolean divisors of a

conjunctive decomposition, obtained

from 0-equivalent cuts, are identical.

Similarly, all Boolean terms of a

disjunctive decomposition, obtained

from 1-equivalent cuts, are identical.

Figure 1: A simple example of conjunctive Boolean decomposition Figure 2: A simple example of disjunctive Boolean decomposition

Figure 3: (a) Various cuts on a BDD. (b), (c) Equivalent cuts.


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ASU ID: 1207860455


The paper [1] describes techniques for XOR

decomposition on a BDD with complement edges

since XOR-intensive and arithmetic functions have

very few or no leaf edges. In order to identify an

algebraic XOR decomposition, the x-dominator ina BDD is defined as a node that is contained in

every path of the BDD. The theorem 5 of the paper

[1] states that for a node v identified as the x-

dominator, the BDD can be algebraically

decomposed as F = G XNOR H, where G is a BDD

rooted at v; BDD of H is obtained from F by

redirecting the regular edges pointing to node v

to terminal 1 and the complement edges

pointing to node v to terminal 0.

The algebraic XOR decomposition of a function F may not exist but there exists many Boolean XOR

decompositions. The theorem 6 of the paper [1]states that for a Boolean function F and an arbitrary Booleanfunction G, there always exists a Boolean function H, such that F = G XNOR H. Since, finding out all possible

combinations of G and H is not feasible, a set of good candidates of G can be detected directly from the BDD

by identifying a generalized x-dominator, G. Once it is identified in the BDD, H = G XNOR F is computed using

a standard apply operator from a BDD package.

The paper [1] also describes a functional MUX

based decomposition strategy where the control

signal is a function instead of a single input variable.

The theorem 7 of the paper [1] states that for a

BDD structure, in which two nodes, u and v, cover

all paths of the BDD. The BDD can then be

decomposed as F = h.f + h.g, where f and g arefunctions rooted at nodes u and v, respectively, and

h is obtained from the BDD of F by redirecting node

u to 1, and node v to 0.

BDS SYSTEM Implementation

The synthesis flow adopted by BDS system although similar in nature to SIS [2]differs in the representation of

Boolean nodes and the way individual optimization procedure is carried out on it. The BDS system employs

network partitioning and performs decompositions on local BDDs.

It uses a sweep procedure to remove the initial redundancy and removes functionally equivalent nodes

thereby improving the runtime complexity.

Since, the application of logic optimization techniques only to a global or local BDD may not produce significant

results in terms of runtime or removal of redundancy, BDS uses an iterative elimination [12]procedure similar

to SIS [2]to partially collapse the Boolean network into a set of super nodes and synthesise it. It uses the

number of BDD nodes as the cost function for elimination. Due to BDD variable reordering, the BDD manager

has to keep track of a large number of intermediate variables which becomes unused after first iteration in

most cases. These large number of unused variables degrades the overall runtime performance. So, instead

of reordering the BDD manager with all the variables, the BDS system uses a new BDD manager which contains

only the used variables that are initialized. After reconstructing the BDDs in the new BDD manager, the BDDs

isomorphic to the original ones but in more compact in the range of indexes is obtained and this process is

referred to as a BDD mapping [11].

The BDD decomposition engine comprises of steps that involve logic simplification through BDD variable

ordering [13] which is then subjected to an iterative BDD decomposition followed by a construction and

processing of the factoring trees. The logic sharing from multi-BDDs and between different factoring trees is

detected to further optimize the synthesis results.

Figure 4: Algebraic XNOR decomposition based on x-dominator.

Figure 5: Functional MUX decomposition: F = hf + h'g


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ASU ID: 1207860455


ANALYSIS OF EXPERIMENTAL RESULTS

The experimental results obtained for both small and medium circuits as well as large circuits shows

tremendous improvements. BDS uses less gates but more area than SIS and consumes less time for AND/OR

(random logic) circuits. BDS consumes less memory and is much faster than SIS for LGSynth91 test case suite.

Since BDS does not perform node simplification with local and satisfiability dont cares derived from the

network, BDS performs poorly in terms of circuit area and delay as compared to the results obtained from SIS.The optimization results obtained for large circuits shows tremendous improvement in terms of computational

time. But the synthesized circuit is slightly larger as compared to SIS since BDS does not perform satisfiability

dont care minimization and only a small fraction of XORs and MUXs are actually mapped to XOR and MUX

gates because of the usage of tree based technology mapper of SIS in the experiment.

CONCLUSION & FUTURE WORK

The paper [1]rightly describes a novel decomposition theory and a practical logic synthesis system, BDS with

the experimental results supporting the fact that BDD-based logic decomposition is indeed a promising

alternative to existing logic optimization approaches. It offers significant improvement in terms of superior

runtime and is beneficial for large circuits. But at the same time, the paper [1]presents a lot of opportunity

for future work to make the current approach a truly successful synthesis method by eliminating the existingproblems.

The paper [1] rightly describes the different challenging aspects that needs to be addressed such as:

1. The need to develop BDD-based logic minimization with satisfiability dont caresso as to reduce the

area of synthesized random logic circuits.

2.

Developing methods to minimize the BDDs with dont care nodesso as to improve the results.

3.

Tuning the cost function so as to balance the factoring tree which is needed for delay minimization.

4. Analysing the BDD decomposition algorithms so that they could be applied for FPGA synthesis.

5. The caching technique proposed in [10]could be used to handle the incompletely specified functions.

REFERENCES

[1] Congguang Yang and Maciej Ciesielski BDS: A BDD-Based Logic Optimization System", IEEE Transactions

on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 7, July 2002.[2] R. K. Brayton, G. D. Hachtel, and A. Sangiovanni-Vincentelli, Multilevel logic synthesis, Proc. IEEE, pp.

264300, Feb 1990.

[3] R. L. Ashenhurst, The decomposition of switching functions, in Proc. Int. Symp. Theory of Switching, vol.

XXIX, Ann. Computation Lab. Univ., Cambridge, MA, 1959, pp. 74116.

[4] H. A. Curtis,A New Approach to the Design of Switching Circuits. Boston, MA: D. Van Nostrand, 1962.

[5] E. Sentovich et al., SIS: A System for Sequential Circuit Synthesis, ERL, Dept. EECS, Univ. California,

Berkeley, UCB/ERL M92/41, 1992.

[6] K. Karplus, Using if-then-else DAGs for multi-level logic minimization,Univ. California, Santa Cruz, UCSC-

CRL-88-29, 1988.

[7] V. Bertacco and M. Damiani, The disjunctive decomposition of logic functions, in IEEE Int. Conf. Computer-

Aided Design, 1997, pp. 7882.[8] T. Stanion and C. Sechen, Boolean divisionand factorization using binary decision diagrams, IEEE Trans.

Computer-Aided Design, vol. 13, pp. 11791184, Sept. 1994.

[9] O. Coudert and J. C. Madre, A unified framework for the formal verification of sequential circuits, in Proc.

ICCAD, 1990, pp. 126129.

[10] A. Mishchenko, B. Steinbach, and M. Perkowski, An algorithm forbi-decomposition of logic functions,

in Proc. Design Automation Conf., 2001, pp. 103108.

[11] BDS: A BDD-based logic optimization system, in Proc. Design Automation Conf., 2000, pp. 9297.

[12] R. Chaudhry, T. Liu, A. Aziz, and J. Burns, Area -oriented synthesis for pass-transistor logic, in Int. Conf.

Computer Design, 1998, pp. 160167.

[13] R. Rudell, Dynamic variable ordering for ordered binary decision diagrams,in IEEE Int. Conf. Computer-

Aided Design, 1993, pp. 4247.Note:All the figures have been taken from [1]

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