Improving on Board Integrated Circuits Testing using One Shared Test Access Port and Single Bidirectional Test Data Line

SALIM AHMAD JAYOUSI

Doctor of Philosophy (Computer Engineering)

2015

IMPROVING ON BOARD INTEGRATED CIRCUITS TESTING USING ONE

SHARED TEST ACCESS PORT AND SINGLE BIDIRECTIONAL TEST DATA LINE

SALIM AHMAD JAYOUSI

A thesis submitted in fulfillment of the requirement for the award of

Degree of Doctor of Philosophy (Computer Engineering)

Faculty of Engineering

UNIVERSITI MALAYSIA SARAWAK

2015

i

ACKNOWLEDGEMENT

First of all, I thank Allah (SWT) for giving me strength and health to continue

this work and making it possible to see the completion of my PhD program. This

thesis is the end of my journey in obtaining my PhD. This thesis has been

successfully completed with the support and encouragement of numerous people

including my friends and colleagues.

At this moment of accomplishment, I am extremely indebted to my

supervisor, Associate Professor Dr. Mohd Saufee Muhammad. This work would not

have been possible without his guidance, support and encouragement. Under his

guidance, I successfully overcame many difficulties and learned a lot. Despite of his

temporarily ill health, he used to review my thesis progress, give his invaluable

suggestions and made corrections. His unflinching courage and conviction will

always inspire me, and I hope to continue to work with his noble thoughts.

I also would like to express my warmly thanks to Dr. Siti Kudnie Sahari and

Dr. Rohana Sapawi for their invaluable advice, constructive criticism and their

extensive discussions around my work. They willingly devoted so much time in

giving guidance to me especially in my hardware work, writing process and all the

help in all the other stages of this work.

No words can express my thanks and gratitude to all the members of my

family. All the thanks go to my merciful mother and beloved father, to whom I owe

all the achievements in my life, for their continuous encouragement, support and

patience. Great thanks also go to my wife Areej, and my sons Yazan and Ahmad, for

the love and support they always give me.

ii

ABSTRAK

Peralatan pengujian dan pengukuran tradisional yang bergantung kepada

penyambungan probe luaran tidak lagi berkemungkinan memandangkan pengecutan

papan litar bercetak (PCB) terkini. Memandangkan penggunaan probe amat sukar,

kaedah lain perlu diterokai. Satu pendekatan baru dan boleh dipercayai bagi

pengujian PCB dibentangkan dalam penyelidikan ini yang menyediakan satu

penyelesaian elegan bagi masalah ini. Kaedah ini dibangunkan berdasarkan piawaian

IEEE 1149.1 untuk pengujian dan penyahpepijatan. Ia mentakrifkan seni bina

pengujian litar bersepadu (IC) moden ke atas PCB tanpa penyambungan probe

luaran. PCB yang mematuhi pendekatan ini mengandungi satu capaian antara muka

yang dikongsi untuk capaian pengujian logik. Cip yang mematuhi teknik ini

mengandungi pintasan pendaftar sahaja, manakala cip yang mematuhi piawaian

IEEE 1149.1 mengandungi empat jenis pendaftar. Pengkongsian capaian antara

muka yang dipanggil ujian capaian port (TAP), mempunyai antara muka port bas

bersiri semestsa (USB). Cip di atas PCB dihubungkan dengan TAP yang dikongsi

menggunakan topologi bintang. Hanya satu talian data dwi-arah digunakan untuk

menyambung setiap IC. TAP dikawal oleh perisian sumber terbuka dan mesra

pengguna yang dibangunkan menggunakan aplikasi Arduino. Perisian ini boleh

mengakses IC logik dan menghasilkan corak data pengujian automatik. Ia

mengendalikan butiran logik agar pengguna boleh memberi tumpuan kepada ujian

sebenar tanpa perlu bimbang atau perlu mengetahui butiran pelaksanaan di peringkat cip.

Reka bentuk litar logik ini telah di simulasi dan prototaip perkakasan telah dibina

dengan jayanya. Reka bentuk baru ini mempunyai ciri-ciri yang kurang kompleks,

lebih murah dan lebih dipercayai daripada rekabentuk yang mematuhi piawaian

IEEE 1149.1. Kaedah yang dicadangkan berjaya melaksanakan 99% ujian imbasan

terhadap IC logik, manakala liputan kesalahan adalah 96% untuk IC yang sama.

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ABSTRACT

Traditional test and measurement equipment that relies on connecting external

probes is no longer possible given the state of the art of today’s shrinking printed

circuit boards (PCBs). Since probing is extremely difficult, other methods must then

be explored. A new and reliable approach for testing PCBs is presented in this

research that provides an elegant solution for this problem. The approach is

developed based on IEEE Std. 1149.1 for testing and debugging. It defines the

architecture for testing modern integrated circuits (ICs) over PCBs without external

probing. PCBs compliant with this approach will contain one shared access interface

to access testing logic. Chips compliant with this technique will contain bypass

registers only, whereas the chips that are compliant with IEEE Std. 1149.1 contain

four types of registers. The shared access interface, which is called test access port

(TAP), has a universal serial bus (USB) port interface. The chips over the PCB are

connected with the shared TAP using the star topology. Only one bidirectional data

line was used to connect each IC. The TAP has been totally controlled by an open

source and user friendly software that has been developed using the Arduino

application. The software is able to access the IC logic and to generate automatic test

patterns. It handled the details of the logic such that users can focus on the actual

testing without having to worry about or needing to know the implementation details

at chip level. The logic circuit of this design has been simulated and the hardware

prototype has been built successfully. The new design has the distinct feature of

being less complex, less expensive, and more reliable than those compliant with

IEEE Std. 1149.1. The proposed method succeeded in performing 98% of the scan

testing on logical ICs, whereas the fault coverage was 96% for the same ICs.

iv

TABLE OF CONTENTS

ACKNOWLEDGEMENT i

ABSTRAK ii

ABSTRACT iii

TABLE OF CONTENTS iv

LIST OF TABLES ix

LIST OF FIGURES xi

LIST OF ABBREVIATIONS xvii

CHAPTER 1: INTRODUCTION 1

1.1 Research Overview 1

1.2 Problem Statement and Hypothesis 5

1.3 Research Objectives 6

1.4 Research Contributions 6

1.5 Design Scope and Limitations 9

1.6 Thesis Outline 10

CHAPTER 2: LITERATURE REVIEW 12

2.1 Introduction 12

2.2 Design for Testability (DFT) 13

2.3 Test Pattern Generator (TPG) 14

2.4 Direct Contact Testing for PCB 15

2.4.1 Analog Signature Analysis (ASA) 16

2.4.2 In-Circuit Testing (ICT) 21

2.4.3 Automated Test Equipment (ATE) 24

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2.5 Contactless Testing for PCB 28

2.6 Direct Contact Testing for ICs 34

2.6.1 Built In Self-Testing (BIST) 35

2.6.2 “The Launch to Capture” Testing 40

2.7 Contactless Testing for ICs 41

2.8 Computer Controlled Testing 46

2.8.1 Computer Aided Multimeter 47

2.8.2 Computer Aided Oscilloscope 48

2.8.3 Computer Aided ATE for IC Testing 49

2.8.4 Computer Aided Probe Card Testing 51

2.8.5 Computer Based IC Tester 52

2.8.6 Computer Testing Using LPT Port 54

2.8.7 Computerized Testing Using ARM Integrator 55

2.8.8 Computer Testing Using Smart Applications 58

2.8.9 Computer Analogue IC Tester (AICT) 60

2.9 Boundary Scan Testing and JTAG 61

2.9.1 JTAG Overview 61

2.9.2 JTAG Internal Test Architecture 63

2.9.3 JTAG Testing Functionality 67

2.9.4 JTAG TAP Controller 70

2.9.5 JTAG Multi Site Star Testing 73

2.9.6 IEEE Std. 1149.7 75

2.9.7 JTAG Advantages and Disadvantages 78

2.10 Arduino Uno Board and Software 79

2.10 Characteristics of the Current Testing Methods 81

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2.12 Conclusion 83

CHAPTER 3: PROPOSED ONE SHARED ACCESS TAP 85

CONTROLLER DEVELOPMENT

3.1 Introduction 85

3.2 System Architecture 89

3.3 System Simulation 91

3.4 Test Data Packet Format 94

3.5 Sharing the TAP 97

3.5.1 Bypass Unit 98

3.5.2 Transmission and Reception Counters 105

3.5.3 Test and Response Patterns Routing 111

3.6 Conclusion 116

CHAPTER 4: HARDWARE IMPLEMENTATION OF ON BOARD 118

ICs TESTING

4.1 Introduction 118

4.2 Bi-Directional Data Transfer 120

4.3 Boundary Scan Circuit 124

4.3.1 TDI Driver and Forwarder 125

4.3.2 TDO Transmitter Unit 128

4.4 Computer Interfacing 132

4.4.1 Arduino Software and Source Code 133

4.4.1.1 Clock Pulse Generation 135

4.4.1.2 Address Definition and Transmission 137

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4.4.1.3 Transmitting and Counts 138

4.4.2 Transmitting Test Data Pattern 139

4.4.3 Receiving the Response Pattern 142

4.5 Case Study Example 143

4.6 JTAG Simulation 148

4.7 Conclusion 150

CHAPTER 5: RESULTS AND DISCUSSIONS 151

5.1 Introduction 151

5.2 Bypass Unit Implementation Results 152

5.2.1 Bypass Unit Functionality Results 153

5.2.2 Bypass Unit Initialization Time Results 156

5.2.3 Bypass Unit Complexity 166

5.3 Counter Implementation Results 167

5.3.1 Counters Functionality 167

5.3.2 Counting Time Results 170

5.3.3 Counters Design Complexity 172

5.4 Data Router Implementation Results 174

5.4.1 Router Functionality 174

5.4.2 Routing Time Results 177

5.4.3 Router Complexity 179

5.5 DTC Unit 179

5.5.1 DTC Functionality 180

5.5.2 DTC Time 185

5.5.3 DTC Complexity 186

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5.6 Boundary Scan Circuit 186

5.6.1 Boundary Scan Circuit Functionality 187

5.6.2 Boundary Scan Time Results 193

5.6.3 Boundary Scan Circuit Complexity 195

5.7 System Integrity Results 195

5.8 The New Method and IEEE Std. 1149.1 Method 199

5.8.1 Functionality Comparison 200

5.8.2 Structural Comparison 206

5.9 Hardware Prototype Image 207

5.10 Conclusion 208

CHAPTER 6: CONCLUSION AND FUTURE WORKS 209

6.1 Conclusion 209

6.2 Future Works 211

REFERENCES 214

APPENDIX A: LIST OF PUBLICATIONS 237

APPENDIX B: ARDUINO UNO BOARD R3 DATASHEET 239

APPENDIX C: ATMEGA328 DATASHEET 247

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LIST OF TABLES

Table Page

1.1 Significant Improvements in the Proposed Method 3

2.1 Arduino Uno Specification Table 80

‎‎2.2 Main Characteristics of the Current Testing Methods 82

‎3.1 Test Data Packet Description 99

‎3.2 Bypass Unit Shift Register Truth Table 102

‎3.3 Functional Tables of the Bypass Unit Octal Buffer 104

‎3.4 Bypass Unit Octal Buffer Operating Conditions 105

‎3.5 Truth Table of the TAP Counters 110

‎3.6 Recommended Operating Conditions of the TAP Counters 110

‎3.7 Test Router Truth Table 112

‎3.8 Test Router Demultiplexer Time Table 114

‎3.9 Router Demultiplexer Operating Conditions 116

‎4.1 DTC Buffer Functional Table 123

‎4.2 DTC Buffer Operating Conditions 124

‎4.3 TDO Transmitter Shift Register Operating Conditions 131

‎4.4 TDO Transmitter Shift Register Limiting Values 132

‎‎‎ 5.1 for Initializing Number of ICs 157

‎‎‎ 5.2 for Initializing IC with Number of Inputs 160

‎‎‎ 5.3 for Processing IC with Number of Outputs 161

‎‎‎ 5.4 According to Different Frequencies 163

‎‎‎ 5.5 Functional Table of DTC Unit 180

‎‎‎ 5.6 Data Transition over the Bi-Directional Line 181

‎‎‎ 5.7 Test Data Transition Time Table for the TDI Driver Unit 188

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‎‎‎ 5.8 Response Data Transition Table 190

‎‎‎ 5.9 Functional Analysis for IEEE Std. 1149.1 Compliant System 201

‎‎‎ 5.10 Functional Analysis for the New Method 204

‎‎‎ 5.11 Functional Comparison Summary 205

‎‎‎ 5.12 Structural Comparison Results 206

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LIST OF FIGURES

Figure Page

‎1.1 JTAG Testing Circuit Combination 2

‎‎‎1.2 Proposed System Block Diagram 8

‎‎‎2.1 Typical ASA Testing Instrument 16

‎‎‎2.2 Analog Signatures of the Four Basic Elements 17

‎‎‎2.3 Signatures of Normal and Defective Resistor 18

‎‎‎2.4 IC Testing System using ASA Technique 19

‎‎‎2.5 Multiple Input Signature Register 20

‎‎‎2.6 ICT System with Nails Probing PCB under Test 21

‎‎‎2.7 Microcontroller-Driven ICT 23

‎‎‎2.8 Operational Flow of the ATE Scan Test 25

‎‎‎2.9 Technique for ATE PCB Press 26

‎‎‎2.10 EMI Tester Design 30

‎‎‎2.11 Board under Test with Short Circuit Fault 30

‎‎‎2.12 Resultant Curves of Faulty and Non-Faulty Boards 31

‎2.13 EMI Approach for Testing PCBs 32

‎‎‎2.14 Resultant Curve of Unbroken Conductor 32

‎‎‎2.15 Resultant Curve of a Broken Conductor 33

‎‎‎2.16 BIST Architecture 35

‎‎‎2.17 Example of LFSR Circuit 36

‎‎‎2.18 Combination Method for Testing Time Reduction 37

‎‎‎2.19 IC with Embedded Programmable Clock Generator 40

‎‎‎2.20 Computer-Aided Multimeter System Block Diagram 47

‎‎‎2.21 Architecture of the Computer-Aided ATE Tester 50

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‎2.22 Miller’s‎Tester‎Block‎Diagram 51

‎‎‎2.23 Conceptual Framework of Agawin’s Tester 53

‎‎‎2.24 Agawin’s Tester Architecture 53

‎‎‎2.25 LPT Port Pinout Diagram 54

‎‎‎2.26 Tester Socket Combination with the LPT Port 55

‎‎‎2.27 ARM-Based IC Tester 56

‎‎‎2.28 IC Tester Operation 57

‎‎‎2.29 Pin Configuration Screen 59

‎‎‎2.30 System 8 AICT 60

‎‎‎2.31 IEEE Std. 1500 IC Wrapper 62

‎‎‎2.32 Boundary Scan Circuit Architecture 63

‎‎‎2.33 JTAG Boundary Scan Path 64

‎‎‎2.34 Boundary Scan Tester Interface 65

‎‎‎2.35 JTAG Compliant IC Block Diagram 67

‎‎‎2.36 Basic Boundary-Scan Cell 69

‎‎‎2.37 JTAG Interaction Flow Block Diagram 70

‎‎‎2.38 TAP State Diagram 71

‎‎‎2.39 TAP Accessible and DFT Features 72

‎‎‎2.40 MSTAR Block Diagram 74

‎‎‎2.41 IEEE Std. 1149.7 Intellectual Property 76

‎‎‎2.42 Data Exchange between DTS - TAP.7 and EPU-TS 77

‎‎‎2.43 TAP Driving of TDI and TDO Signals 77

‎‎‎3.1 Methodology Flow Chart of Developing One Shared TAP 87

‎‎‎3.2 New Method Block Diagram 91

‎‎‎3.3 Word Generator Instrument in Multisim Software 92

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‎3.4 Word Generator Setting Screen 93

‎‎‎3.5 Multisim Logic Analyzer Icon 94

‎‎‎3.6 Test Data Packet Format 96

‎‎‎3.7 Test Data Packet Example 97

‎‎‎3.8 TAP Architecture 97

‎‎‎3.9 Bypass Unit Block Diagram 99

‎‎‎3.10 Bypass Unit Circuit Diagram 100

‎3.11 Bypass Unit Shift Register Timing Diagram 101

‎‎‎3.12 Functional Diagram of Bypass Unit Shift Register 102

‎‎‎3.13 Bypass Signals Timing Diagram 103

‎‎‎3.14 Bypass Unit Octal Buffer Logic Diagram 104

‎‎‎3.15 Reciprocal Relation between the Counters 106

‎‎‎3.16 Transmission and Reception Counters Timing Diagram 107

‎‎‎3.17 Transmission and Reception Counters Circuit Diagram 108

‎‎‎3.18 74HC163 Pinout Diagram 109

‎‎‎3.19 TAP Counters Timing Diagram 109

‎‎‎3.20 TAP Router Block Diagram 112

‎‎‎3.21 TAP Router Circuit Diagram 113

‎‎‎3.22 74HC139 Demultiplexer Pinout Diagram 115

‎‎‎3.23 Router Demultiplexer Diagrams 115

‎‎‎4.1 Methodology Flow Chart for Developing On Board Testing Circuit 119

‎‎‎4.2 DTC Block Diagram 122

‎‎‎4.3 DTC Circuit Diagram 123

‎‎‎4.4 Boundary Scan Circuit 125

‎‎‎4.5 TDI Driver State Diagram 126

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‎4.6 TDI Driver Block Diagram 127

‎‎‎4.7 TDI Driver Logic Circuit Diagram 127

‎‎‎4.8 TDO Transmitter Block Diagram 129

‎‎‎4.9 TDO Transmitter Circuit Diagram 130

‎‎‎4.10 TDO Transmitter Shift Register Timing Diagram 132

‎‎‎4.11 Combination Diagram for Arduino Interfacing 133

‎‎‎4.12 Driving the TAP Interface using Arduino Board 134

‎‎‎4.13 Arduino Board Interface 135

‎‎‎4.14 Calculating Clock Signal Variables 136

‎‎‎4.15 Arduino Clock Pulse Generation Algorithm 136

‎‎‎4.16 Address Declaration using Arduino Software 137

‎‎‎4.17 Transmitting the Address Bits to Arduino Terminals 137

‎‎‎4.18 and Counts Declaration 138

‎‎‎4.19 and Counts Transmission Algorithm 139

‎‎‎4.20 Flow Chart of Masking and Transmitting TDI 141

‎‎‎4.21 Masking and Transmitting TDI Algorithm 142

‎‎‎4.22 Receiving TDO Algorithm 143

‎‎‎4.23 IC Number Selection Screen 144

‎‎‎4.24 Test Frequency Inquiry Screen 144

‎‎‎4.25 IC Address Inquiry Screen 145

‎4.26 Transmission Period Inquiry Screen 145

‎‎‎4.27 Reception Period Inquiry 146

‎‎‎4.28 Sending TDI patterns and Receiving TDO Patterns 147

‎‎‎4.29 JTAG Simulation 149

‎‎‎5.1 Bypass Unit Signals Timing Diagram 153

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‎‎‎5.2 Bypass Unit Output Signals 155

‎‎‎5.3 vs. Curve 158

‎‎‎5.4 vs. Curve 161

‎‎‎5.5 vs. Curve 162

‎‎‎5.6 vs. Curve 164

‎‎‎5.7 Relationship between and 166

‎‎‎5.8 and Counters Output Signals 168

‎‎‎5.9 and Output Signals 169

‎5.10 vs. 171

‎‎‎5.11 vs. 171

‎‎‎5.12 vs. Curve 173

‎‎‎5.13 Router Timing Diagram 175

‎‎‎5.14 Router Transmission and Reception Process 176

‎‎‎5.15 vs. 177

‎‎‎5.16 vs. 178

‎‎‎5.17 Data Transition Graph over the Bi-Directional Line 183

‎‎‎5.18 TDI and TDO Traffic Timing Diagram 184

‎‎‎5.19 TDI and TDO Traffic over the Bi-Directional Line 184

‎‎‎5.20 Data Transition through the TDI Driver Unit 188

‎‎‎5.21 Response Data Transition Diagram 190

‎‎‎5.22 Output Data of the TDI Driver Unit (First Page) 192

‎‎‎5.23 Output Data of the TDI Driver Unit (Second Page) 192

‎‎‎5.24 Operating Frequency vs. Driving and Capturing Time 194

‎‎‎5.25 Testing the First IC 196

‎‎‎5.26 Testing the Second IC 197

xvi

‎5.27 Testing the Defected 74HC00 IC 198

‎5.28 Full Prototype Hardware Design 207

xvii

LIST OF ABBREVIATIONS

ADC - Analog digital converter

AICT - Analogue integrated circuit tester

AOI - Automated optical inspection

ARM - Acorn RISC machines

ASA - Analog signature analysis

ATE - Automated test equipment

ATG - Automatic test generation

BAST - Built in self-testing aided scan test

BGA - Ball grid array

BIST - Built in self-testing

BS - Boundary scan

BSDL - Boundary scan description language

BST - Boundary state method

BUT - Board under test

CCD - Charge-coupled device

CCU - Clock control unit

CDMA - Code division multiple access

CMOS - Complementary metal oxide silicon

CPLD - Complex programmable logic device

CPU - Central processing unit

CRC - Cyclic redundancy check

CUT - Circuit under test

xviii

DFT - Design for testability

DFU - Device firmware upgrade

DIMM - Dual in-line memory module

DLL - Dynamic link library

DPM - Defective per million

DR - Data register

DTC - Data traffic control

DTS - Debug/test system

DUT - Device under test

EBT - Electron beam testing

ECT - Eddy current testing

EFM - Electric Force Microscopy

EMF - Electromagnetic field

EMI - Electromagnetic induction

EPLD - Erasable programmable logic device

EPU - Extended protocol unit

EXPIM - Extension pin connector

FPGA - Field programmable gate array

FRU - Field replaceable unit

FRUID - Field replaceable unit with identification

FSK - Frequency shift keying

GPIO - General purpose input/output

GUI - Graphical user interface

HOY - Hypothesis, odyssey, and yield

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HWB - Hardware bootloader

IC - Integrated circuit

ICE - In-circuit emulation

ICSP - In-circuit serial programming

ICT - In circuit testing

ID - Identification

IDE - Integrated development environment

IEEE - Institute of Electrical and Electronics Engineers

IJTAG - Internal JTAG

I/O - Inputs/Outputs

IR - Instruction register

JEDEC - Joint Electron Device Engineering Council

JETAG - Joint European Test Action Group

JTAG - Joint Test Action Group

LEOSLC - Light emission from off state leakage current

LFSR - Linear feedback shift register

LPT - Line printing terminal

LSTTL - Low power Schottky TTL

MCM - Multi-chip module

MIMO - Multiple input multiple output

MR - Master Reset

MSTAR - Multi-site star test architecture

MSTARC - MSTAR controller

NA - Numerical aperture

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NI - National Instruments

NIR - Near infrared light

PCB - Printed circuit board

PCI - Peripheral component interconnect

PE - Primary electron

PLD - Programmable logic device

PMT - Photo multiplier tube

PWB - Printed wiring board

PWM - Pulse width modulation

RAM - Random access memory

RC - Resistance-capacitance

RE - Reflected electrons

RF - Radio frequency

RISC - Reduced instruction set computing

RO - Ring oscillator

RPS - Repaid prototyping system

SC - Scan chain

SDRAM - Standard dynamic random access memory

SE - Secondary electrons

SEM - Scanning electron microscope

SMT - Surface mount technology

SOC - Systems on chips

SPAD - Single photon avalanche diode

SPD - Single point detector

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STT - Star test topology

TAP - Test access port

TCK - Test clock

TDI - Test data in

TDO - Test data out

TMS - Test mode select

TMSC - Test mode select compact

TPG - Test pattern generator

TRST - Test reset signal

TS - Target systems

TTL - Transistor-transistor logic

UBW - Ultra bandwidth

USB - Universal serial bus

VHDL - Very high density logic

VLSI - Very large scale integration

VLSIC - Very large scale integrated circuits

WIP - Wrapper interface port

WPI - Wrapper Multi-input port

WPO - Wrapper Multi-output port

WSI - Wrapper one bit serial input port

WSO - Wrapper one bit serial output port

WVT - Wavelet transform

1

CHAPTER 1

INTRODUCTION

1.1 Research Overview

The conventional testing methods for printed circuit boards (PCBs) and

integrated circuits (ICs) are suffering from many deficiencies. The incredible

shrinking and complexity in the new PCBs and ICs have made the traditional testing

methods unreliable or even inapplicable [1-3].

In 1985, new attempts emerged [4-6]. The Joint Test Action Group (JTAG)

developed a creative method for testing finished PCBs after manufacturing. In 1990,

the Institute of Electrical and Electronics Engineers (IEEE) codified the JTAG

method as a standard with the designation IEEE Std. 1149.1-1990 entitled “Standard

Test Access Port and Boundary-Scan Architecture”.

Although IEEE Std. 1149.1 facilitates the testing process, it is still suffering

from the following disadvantages and deficiencies:

i. It requires adding additional circuitry such as bypass registers,

instruction registers, identification registers and test access ports

(TAPs) to each IC and PCB. Such additions caused an exaggerated

complexity and cost.