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S07 03 Dean · 2017. 3. 26. · MTBS Daisy Chain (15 x 15 mm die size, Var. pitch 125–240µ)...
Transcript of S07 03 Dean · 2017. 3. 26. · MTBS Daisy Chain (15 x 15 mm die size, Var. pitch 125–240µ)...
SWTW 2004
Celerity ResearchCelerity Research
Probe and Planarize™ --Optimizing Bump Shape and Height at Probe
Vada Dean and Tom NguyenSouthwest Test Workshop 2004
2 SWTW 2004
OverviewOverview
• The Problem -- Flip Chip Device Reliability
• The Solution -- Probe and Planarize™
• Smart PnP Technology™
SWTW 2004
The ProblemThe Problem
Flip Chip Device Reliability
4 SWTW 2004
Flip Chip Device Reliability IssuesFlip Chip Device Reliability Issues
• Probe marks damage bumps on the wafer
• Scratched and penetrated bumps trap contamination and flux
• Bump reflow adds yield risk and cost
• Height variation of wafer bumps hinder interconnect formation
5 SWTW 2004
Bump Damage, ContaminationBump Damage, Contaminationand Reflowand Reflow
Eutectic60 µ OT
Hi Lead60 µ OT
Cu Pillar60 µ OT
Additional Temp Excursion causes:• PMOS transistor damage• Die Yield Loss• Reduced Final Test Yield• Additional $’s for wafer reflow
process
REFLOW WAFER TO ELIMINATE SOLDER DAMAGE (260°C)
• Trapped contaminants and flux weaken flip chip interconnect joints
• Increases variation of bump height
6 SWTW 2004
Typical Bump Height DistributionTypical Bump Height Distribution
12
71
178
381
752
10791124
849
496
232
9449
25 14 6 3 4 1 0 2 1 1 1 0 0 0 0 0 0 1
113 115 117 119 121 123 125 127 128 131 133 135 137 139 141
Chip
Substrate
Ball Height (microns)Avg. = 118.77, Sigma = 2.10, Number Balls = 5376
7 SWTW 2004
Weak Flip Chip InterconnectWeak Flip Chip Interconnect
Inferior Interconnect and Lack of Wetting:• Smaller ball with little or no contact after reflow• Contamination interference
SWTW 2004
The SolutionThe Solution
Probe and Planarize™
9 SWTW 2004
Smart PnP ProbeSmart PnP Probe™™with Probe and with Probe and PlanarizePlanarize™™
Advantages• Reduced variation of bump height
enhances interconnect integrity• Flat surface eliminates trapped
contamination and flux• Textured surface improves reflow
and wetting
Probe and Planarize™ uniformly deforms bumps across the wafer
10 SWTW 2004
Smart PnP ProbeSmart PnP Probe™™Improves Bump Height DistributionImproves Bump Height Distribution
2
10
36
83
61
37
11
4
20
2523 22
32
74
30
8
2
0
10
20
30
40
50
60
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80
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100
70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
Bump Heights (um)
Freq
uenc
y of
Occ
uran
ce
Post-test Avg=76.4um, Sigma=1.17um Pre-test Avg=86.7um, Sigma=2.07um
Distribution Shiftafter Probe and Planarize™
Wafers received from fab have significant bump height variation
Bump height distribution is unpredictable
11 SWTW 2004
Probe & Probe & PlanarizePlanarizeTMTM ResultsResults
Unitive Bump Heights DistrubutionPre-Probe vs. Post-Probe
0
10
20
30
40
50
60
70
80
90
100
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125
Bump Heights (um)
Freq
uenc
y of
Occ
uran
ce
Post-Probe[Avg, Stdev]= 102.28, 1.46 Pre-Probe [Avg, Stdev]= 116.40, 2.94
BeforeAvg. Bump Ht. = 116.40Std. Dev. = 2.94
After Probe & Planarize™Avg. Bump Ht. = 102.28Std. Dev. = 1.46
Vendor A
Lot # 2
High Pb
Celerity Research Bump
Fab
Unitive Bump Heights DistrubutionPre-Probe vs. Post-Probe
0
10
20
30
40
50
60
70
80
90
100
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125
Bump Heights (um)
Freq
uenc
y of
Occ
uran
ce
Post-Probe[Avg, Stdev]= 96.92, 1.68 Pre-Probe [Avg, Stdev]= 109.96, 2.42
BeforeAvg. Bump Ht. = 109.96Std. Dev. = 2.42
After Probe & Planarize™Avg. Bump Ht. = 99.92Std. Dev. = 1.68
Vendor A
Lot # 4
High Pb
Celerity Research Bump
Fab
BeforeAvg. Bump Ht. = 111.16Std. Dev. = 4.58
After Probe & Planarize™Avg. Bump Ht. = 88.24Std. Dev. = 1.13
Unitive Bump Heights DistrubutionPre-Probe vs. Post-Probe
0
10
20
30
40
50
60
70
80
90
100
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125
Bump Heights (um)
Freq
uenc
y of
Occ
uran
ce
Post-Probe[Avg, Stdev]= 88.24, 1.13 Pre-Probe [Avg, Stdev]= 111.16, 4.58
Vendor A
Lot # 3
High Pb
Celerity Research
Bump Fab
12 SWTW 2004
Probe and Probe and PlanarizePlanarize™™ Improves ReliabilityImproves Reliability
Non-PlanarizedBump Structure Weak flip chip
interconnect joint. Will result in reliability failure
of device.
Probe and Planarize™Bump Structure
Preferred flip chip interconnect joint
structure.
13 SWTW 2004
0/500/500/500/500/500/50HTS 165C 500 hrs
0/500/500/500/500/500/50UB-Hast 168 hrs
0/1500/1500/1500/1500/1500/150UB-Hast 96 hrs
11/2500/25019/2500/2508/2500/250TC-B 3000 cycles
52/1000/10057/1000/10011/1000/100TC-B 4500 cycles
0/6000/6000/6000/6000/6000/600MSL L3
ControlPnPControlPnPControlPnP
High PbEutecticCu Pillar
Smart PnP ProbesSmart PnP Probes™™ Reliability StudyReliability Study
MTBS Daisy Chain (15 x 15 mm die size, Var. pitch 125–240µ)TF-Polyimide 31 x 31 mm FC-BGA PackageASE-M / MTBS FC-BGA Assembly Process
SWTW 2004
Smart PnP TechnologySmart PnP Technology™™
15 SWTW 2004
Celerity Research Smart PnP ProbeCelerity Research Smart PnP Probe™™
• Smart PnP Probe™ with unique Probe and Planarize™ technology:• High density capability (up to
10000 pins)• Fine pitch (60 micron or less)• Massively parallel• Superior electrical performance• The only probe technology that
improves the integrity of the flip chip joint interconnect
16 SWTW 2004
Smart PnP ProbesSmart PnP Probes™™
Smart PnP Probes™X-Section
Smart PnP Probes™height variance < 2 µ
• Coplanarity <+/- 2µ.
• Rigid and durable probes
17 SWTW 2004
Smart PnP ProbeSmart PnP Probe™™ PlanarityPlanarity
Coplanarity240 Probes Monitored -- Camtek Falcon
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0 0.5k 1k 5k 10k 50k 100k 500k
Touchdowns
Plan
arity
(um
)
18 SWTW 2004
Smart ProbeSmart Probe TechnologyTechnology™™Utilizes Advanced Design and SimulationUtilizes Advanced Design and Simulation
• Electrical parasitics well defined and modeled with EDA tools and simulators
• Lumped elements can be designed into the Smart PnP Probe™
19 SWTW 2004
DataIn Pins - Diff TDR/TDT response for 25ps input
Output risetime is 27psSkew is less than 0.25ps
PnP ProbePnP Probe™™ TDR/TDTTDR/TDT
20 SWTW 2004
• DataIn PinsEye-diagram at 10 Gb/sec
• Jitter is less than 1ps
• Eye-closure is 6%(measured 30ps after zero crossing)
Smart PnP ProbeSmart PnP Probe™™ Eye DiagramEye Diagram
21 SWTW 2004
Smart PnP ProbeSmart PnP Probe™™ Current CapacityCurrent Capacity
Probe Current Carrying Capacity20 microns overtravel
0.00
2.00
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12.00
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16.00
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20.00
0.00 100.00 200.00 300.00 400.00 500.00 600.00 700.00 800.00 900.00
Curent (mA)
Prob
e Fo
rce
(g)
22 SWTW 2004
Contact Resistance PerformanceContact Resistance Performance
Change in Contact Resistance240 Probes Monitored
-0.5000
-0.4000
-0.3000
-0.2000
-0.1000
0.0000
0.1000
0.2000
0.3000
0.4000
0.5000
0.5k 1k 5k 10k 50k 100k 500k
Touchdowns
Res
ista
nce
(ohm
s)
Wafers tested using Accretech UF200S Proberand Standard Tester Configuration
23 SWTW 2004
Smart PnP ProbeSmart PnP Probe™™Probes After 500k Touchdowns (no clean)Probes After 500k Touchdowns (no clean)
Smart PnP Probe™
Before Touchdown
Smart PnP Probe™
After 500K Touchdowns
24 SWTW 2004
ConclusionsConclusions
• Probe and Planarize™• Optimizes Bump Shape and Height at Probe• Improves Flip-Chip Device Reliability
• Smart PnP Technology™• Provides superior coplanarity• Maintains advanced electrical performance throughout life
of probe card• Provides reproducible low Cres
• Enables fine pitch and massive parallel testing
25 SWTW 2004
AcknowledgementsAcknowledgements
Chainarong Asanasavest -- Celerity Research Director of TechnologyDave Brown -- Celerity Research Design ManagerRandy Chau -- Celerity Research Application EngineerRomi Pradhan -- Accretech Product Manager
This presentation would not have been possible without the support and equipment provided by Accretech, Camtek, and Gigatest