S06 01 Namburi SWTW2013 - · PDF file · 2017-03-26–...

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A Fine Pitch MEMS Probe Card with Built in Ac8ve Device for 3D IC Test Lakshmikanth Namburi Florent Cros Yong Hong Ting Hu Robert Smith ADVANTEST Gary Maier Van Thanh Truong Hsichang Liu Katsuyuki Sakuma IBM

Transcript of S06 01 Namburi SWTW2013 - · PDF file · 2017-03-26–...

Page 1: S06 01 Namburi SWTW2013 - · PDF file · 2017-03-26– Enable*wafer*/*die*manufacturing*testfor*scaled*systems*integraon*into*silicon* – Expand*design*verificaon,*characterizaon*capability*

A  Fine  Pitch  MEMS  Probe  Card  with  Built  in  Ac8ve  Device  for  3D  IC  Test  

Lakshmikanth  Namburi  Florent  Cros  Yong  Hong  Ting  Hu  Robert  Smith  

ADVANTEST    

Gary  Maier  Van  Thanh  Truong  

Hsichang    Liu  Katsuyuki  Sakuma    

IBM  

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Overview  •  3D  Silicon  Technology:    Role  of  Test  •  New  Probing  Challenges  •  Ac8ve  Test  Probe  Benefits  •  The  Probing  Solu8on  •  Test  Results  •  Summary  •  Acknowledgements  

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3D  Silicon  Technology  :  Role  of  Test  •  Why  test  before  stacking?  

–  Design  verificaEon  /  Defect  isolaEon  –  Reduce  yield  loss    –  Enable  integraEon  of  chips  from  different  suppliers  

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 3d  IC    C2W  or  W2W  

 

3d  IC    C2W  or  W2W  

3D Performance Test (After stacking - yield loss)

3d  IC    

3D Performance Test (Before stacking - 100% KGD)

Tester  on  chip  

   

3d  IC  

3d  IC  Socket  or  Laminate  

AcEve  Probe  TradiEonal  Probe  

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New  Probing  Challenges  •  Silicon  and  Packaging  Technology  Scaling  

–  Smaller  test  contact  geometries  and  finer  pitches  –  New  materials  and  handling  systems  –  Packaging  evoluEon,    Example:  CSP  and  WLP      

•  New  Test  Inser8ons  and  More  Test  Par88oning  –  New  wafer,  die,  and  SOC  configuraEons  (C2C,  C2W,  W2W)  –  Development  of  new  test  methods  and  test  strategies  –  In  process  product  funcEonal  test  with  increasing  pin  counts  –  Invent  /  redefine  silicon  debug  and  fault  localizaEon    (yield  learning)    

•  Chip  to  Probe  Centric  Design  For  Test  (New  on-­‐off  chip  DFT)  –  Extend  performance  tesEng  off  chip  (chip  to  chip  interfaces)  –  ISIO  buffering  for  ATE  pin  electronics  –  Need  for  fast,  very  high,  stack  data  volume  collecEon  and  chip  repair  –  Dynamic  power  /  thermal  monitoring  and  control    

•  Future  Requirements  –  New  requirements  for  Protocol  Aware  and  ApplicaEon  Specific  test  –  Start  planning  for  future  on  chip  OpEcal  Transceivers  

 

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Ac8ve  MEMS  Probe  Card  Benefits  •  Mi8gate  Rising  Cost  of  Test  (COT)  

•  Extend  ATE  and  Bench  Instrumenta8on  –  Enable  wafer  /  die  manufacturing  test  for  scaled  systems  integraEon  into  silicon  –  Expand  design  verificaEon,  characterizaEon  capability  –  Enhance  /  enable  future  silicon  debug  and  fault  localizaEon    (yield  learning)    

•  Interstrata  In-­‐Out    (ISIO)  Buffering  /  Performance  Tes8ng  –  ATE  pin  electronics  and  tradiEonal  probe  loads  too  large    

•  Chip  to  Probe  Centric  Design  for  Test  (DFT)  –  Extended  Performance  tesEng  off  chip  and  chip  to  chip    

•  Future  Ac8ve  MEMS  Probe  Features  –  No  limit  ABIST  fail  storage  w/fast  access  Eme,  rapid  fail  collecEon  and  chip  repair  –  Customer  defined  Protocol  Aware  FuncEonal  Test    (PAFT)  –  Customer  defined  ApplicaEon  Specific  Integrated  Test  (ASIT)  –  Fine  Pitch  Hybrid  Wire  and  OpEcal  Transceiver  Probes  

 

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Ac8ve  MEMS  Probe  Card  Architecture  

     

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Low  Force  MEMS  Probes  IBM  AcEve  Si  Space  Transformer  

Silicon  Space  Transformer  

Ceramic  Space  Transformer  

µC4  bonding  (50um  Pitch)  C4  bonding  

 (150um  Pitch)  Wire-­‐bonds  

Interposer  PCB  

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Ac8ve  MEMS  Probe  Cross-­‐Sec8on  

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Ac8ve  Circuitry  

µC4  Bonding  

Interconnect  µPillars  

TSVs  

MEMS  Probe  

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Ac8ve  MEMS  Probe  Card    

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•  Over  1300  IO’s  •  50µm  min  pitch  •  5k  Pwr  /  Gnd  •  4  power  planes  

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Why  Low  Force  MEMS  Probe?  •  Why  MEMS?    

–  Wafer  Scale  manufacturing  –  Lithographic  scaling  and  planarizaEon  –  No  probe  count  limitaEons  –  Short  probe  length  for  beber  electrical  

performance  

•  Why  Low  Force?    –  Minimal  damage  to  all  test  contact  surfaces    –  Thin  silicon,  thinner  test  pads,  low-­‐k  

dielectrics  –  Enable  inline  product  test    

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•  Fine Pitch MEMS Probe •  Operating OD: 15µm •  Scrub Length: 10-15µm •  Force: 0.2 gF

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Video  of  Fine  Pitch  Probe  

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Low  profile  MEMS  probe  has  shallow  scrubbing  angle    è  high  scrub  pressure      

 

How  Low  Force  MEMS  Probe  Works  

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Scrubbing  acEon  removes  naEve  surface  oxide  

•  Example:  A  14  µm  round  Ep  produces  a  0.2  to  0.4µm  scrub  depth  on  aluminum  pad.    

Un-probed µC4s

Probed µC4s

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Parametric  Test  Results  •  Contact  resistance  on  µC4  lead  free  solder    bumps  at  -­‐10C,    25C,    and  85C  

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14µm  OD  at  -­‐10C:  <1.8Ω    

Examples  of  Mean  CRes  Value  per  Die,  52  channels,  100mA    current  

14µm  OD  at  25C:  <0.6Ω     14µm  OD  at  85C:  <1.5Ω    

CRes  each  channel  =  Resistance  on  bumps  (Path  +  CRes)  –  Resistance  on  Gold  (Path  +  CRes)  

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Func8onal  Test  Results  •  Wafer  Test  Flow  

–  External  IO  and  Interstrata  IO  (  ISIO  )  DC  Pin  TesEng  –  Power  Supply  Shorts  and  Standby  Current  –  Structural  ATPG  Scan  and  Logic  Test  –  Array  Built  In  Self  Test    (  ABIST  )  –  Performance  Interstrata  Input  /  Output  (  ISIO    )  Test  

•  3D  Wafer  Level  eDRAM  and  ISIO  AC  Characteriza8on    –  Fmax,  Vmin  /  Vmax  –  Stack  Power  /  Thermal  –  Logic  ,  eDRAM,  and  ISIO  Performance  Measurements    

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Func8onal  Test  Results    

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•  Superior  AC  coverage  at  wafer  test  enabled  by  Ac8ve  MEMS  card  •  Enhanced  Known  Good  Stack  (KGS)  via  KGD  sor8ng  

•  Same  results    on  three  µPillar  surface  metallizaEons  (gold,  copper,  pb-­‐free    solder)  

Wafer Chuck

Active Probe

3D Wafer

93k PCB

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eDRAM  and  ISIO  Performance  Test  @  Wafer  Level    

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1.3V 1.2V 1.1V 1.0V 0.8V

600ps

400ps

500ps

PASS

FAIL

VDD

Glo

bal C

lock

Per

iod

0.9V

Good  TSV  Die  for  Stack  Fmax  =  2.2  GHz  ,    Vrange  =  .7v  to  1.4v  

Glo

bal C

lock

Per

iod

AcEve  Chip  

eDRAM, logic, etc. is 100 % tested through TSV, ISIO, C2C interconnects Pre-stack for KGS

Logic eDram eDram

Probe Card

DUT

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DTS1 DTS2 DTS3 DTS4 DTS5 DTS6

DTS1 DTS2 DTS3 DTS4 DTS5 DTS6

DTS1 DTS2 DTS3 DTS4 DTS5 DTS6

DTS1 DTS2 DTS3 DTS4 DTS5 DTS6

DTS1 DTS2 DTS3 DTS4 DTS5 DTS6

DTS1 DTS2 DTS3 DTS4 DTS5 DTS6

DTS1 DTS2 DTS3 DTS4 DTS5 DTS6

DTS1 DTS2 DTS3 DTS4 DTS5 DTS6

Dynamic  Power  and  Thermal  Monitoring  •  Ac8ve  MEMS  Probe  enables  Very  Fast  Response  Time              for  Power  Switching,  Voltage  Regula8on,  and  Clock  Controls  

•  Flexible  for  Adap8ve  Test,    Sequen8al  Tes8ng,    and  Chip  Test  Par88oning    

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Active Probe Card dynamically monitors die Thermal and Power Sensors    

Temperature Rise due to high switching activity

Instant Temperature Control by Active Probe Card reducing switching activity

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Performance  Varia8on  Localiza8on  

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Circ

uit D

elay

Cha

nge

(%)

Due

to P

ower

Dis

sipa

tion

1

2

3

Position of Tested Die Performance Sensors

Chip eDRAM Chip eDRAM Chip eDRAM

•  Performance  varia8on  can  be  quickly  measured  and  isolated  with  Ac8ve  MEMS  probe  measurement  systems  for  AC  yield  learning  at  wafer  test  

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Ac8ve  Probe  Instrumenta8on  •  Tested  die  and  probe  have  pairs  of  performance  measurement  circuits  •  dx0-­‐1  and  dx1-­‐0  are  measured  for  Clock  Skew  •  Clock  Skew  through  MEMS  and  Tested  Die  measured  <  15ps    @  .8  -­‐  1.3V  

nclk0

nclk1

in0

ck0 skitter0

dx0-1 dx1-0

in1

ck1 skitter1

x0

x1

Active Chip with MEMS Probe

Wafer Die

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Summary  • MEMS  Probes  successfully  bonded  to  a  thinned  Ac8ve  Device  with  TSV,  agached  to  a  complex  space  transformer  stack  in  a  fully  func8onal  probe  card  

•  Demonstrated  full  DC  and  AC  func8onal  tes8ng  on  3D  chips  with  50µm  pitch  µPillars  using  Ac8ve  MEMS  probe  card  with  low  force  probes  

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Acknowledgements  •  Gary  Maier  /  IBM  SRDC  project  lead,  test  development  •  Mag  Wordeman  /  IBM  Research  3D  Circuit  Design  ,  

Architect  •  Joel  Silberman  /  IBM  Research  3D  Floor  Planning,  Physical  

Design,  Simula8on  •  Van  Thanh  Truong  /  IBM  Bromont  Packaging,  probe  BA  •  Luc  Guerin  /  IBM  Bromont  Packaging,  probe  BA  •  Thuy  Tran  Quinn  /  IBM  3D  wafer  finishing  (  probe  ,  test  

wafer  )  •  Eric  Perfecto  /  IBM  Chip  Interconnect  development  •  Katsuyuki  Sakuma  /  IBM  Packaging,  Probe  BA    R  &  D  •  Michael  Gaynes  /  IBM  Under  Fill  Research  •  Steve  Wright  /  IBM  Probe  ,  SOC,  3D  Integra8on  Research  •  Hsiang  Liu  /  IBM  Construc8on  Analysis  •  Norman  Robson  •  Dan  Berger  •  Subu  Iyer  

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•  Robert  Smith  /  AAI    Technical  Lead  •  Florent  Cros  /  AAI    Sr.  Manager  Process  Integra8on  •  Lakshmikanth  Namburi  /  AAI  Sr.  Director  of  R&D  •  Yong  Hong  /  AAI  Probe  Applica8ons  Engineering  Manager  •  Ting  Hu  /  AAI  Sr.  Design  Engineer  •  Feng  Lo  /  Lithography  Manager  •  Michael  Chang  /  R&D  Engineer  •  Shahram  Mehdizadeh  /  Sr.  Pla8ng  Engineer  •  Jane  Tran  /  Packaging  Engineer    •  AAI    Manufacturing  &  Quality  Teams  •  Greg  Medrick  /  AAI  General  Manager  ,  Advanced  Probe  Cards