S. FUKUDA LCPAC 0603251 RF-Systems for STF S. Fukuda Accelerator Laboratory Content Introduction...

S. FUKUDA LCPAC 060325 1

RF-Systems for STF

S. Fukuda

Accelerator Laboratory

Content

IntroductionStatus of STF and Plan

forFY2006LLRFSummary



Cryogenics

For 5MW

5MW

For 10MW

10MW

CM(35MV/m)


Plan to Phase-1 (for 2 years)• For #1-Modulator: Reinforce the modulator with bouncer circuit using the PNC modulators and

1:6 pulse-transformer making use of JHP pulse-transformer. Old IGBT is reused. PLC Control system is newly equipped. Almost done

• For #2 modulator: New modulator which is capable to drive 10 MW MBK klystron is designed and

manufactured. This is based on the TESLA Design. New device IEGT is promising.

Waiting the tender

• Two 5-MW Klystrons will be prepared.– Thomson TH2104A (1.296GHz in KEK used in JHP) is tested at 1.3GHz.

Under testing– Procurement of Thales TH2104C is under going as the replaceable klystron.

Purchased – If competitive budget or equivalent is approved, a multi-beam klystron will be

introduced. Planning in FY2006

• Two kinds of power distribution is tested to compare the performance and cost. under progressing• LLRF system is prepared for the beam acceleration test. under progressing



Specification of STF-RFKlystron Two 5-MW klystrons (one for RF gun),

1.3 GHz,

125kV, 1.5ms(RF pulse width),5 Hz Repetition

Modulator-1 Reinforcement of PNC modulatorIGBT SW, Pulse width of 1.7ms(voltage) 1:6 Pulse Trans. With Bouncer, flat top 1%

Modulator-2 New modulator / IGBT SW, Pulse width of 1.7ms 1:15 Pulse Trans. With Bouncer, flat top 1%

Power Distribution System (PDS)

5MW power is fed into 8 cavities. Linear PDS / 3dB tournament PDS

LLRF Digital feedback system using 10 x 16bit ADCs. IF=10MHz, Lo=1310MHz, Sampling 40 MHz.Amplitude stability ±0.1％Phase stability ±0.1deg.

Accelerator Laboratory, KEK


Concept of test facility for quick and inexpensive start utilizing existing properties

Making use of power supply and waveguide component moved from PNC (Power Reactor and Nuclear Fuel Corp).

Power supply has 3 modes; (1)Short pulse (100ms), (2)long pulse (4ms) and (3)CW for the modulating anode type klystron.

For mode(2), possible klystron is modulating anode type TH2115 (Thales). About 2MW output is possible for this case.

Reform to (PT+Bouncer) allows to use TH2104A(C).

Photo of Modulator in PNC

Block diagram of PNC modulator５－１０MW　



Modulator Development

VCB

AC6.6kV

CrowbarIgnitron

Rectifier

Chock

StorageCapacitor

IGBT

Bouncer

PulseTransformer

KlystronTH2104

HeaterTransformer

1:6

23kV 140kV

135

F

215

F

50F

Shunt Snubber

Install of Pulse transformer

Waveform of modulator without bouncer

•Modulator reformation was almost done and started operation for coupler test.•Reformation was performed as half the price as the newly built modulator.•Bouncer circuit will be added in middle of April in 2006.



Candidate Klystrons(1.3GHz、 Long　 Pulse)

10 MW　 Peak 10 MW　 Peak 5-10 MW　



Klystron test status (1) Performance of the klystron, which was bought 15 years ago, was checked in

short pulse operation(3micro sec pulse width)

0

1

2

3

4

5

6

60 70 80 90 100 110 120 130

印加電圧（ｋＶ）

Pf

(MW

)ｏｕ

ｔ

1300MHz1296MHz

0

1

2

3

4

5

6

0 100 200 300 400 500

Pin(W)

Pout

(MW

)

1300MHz1296MHz

Waveform: voltage (top),Current (bottom)

Applied voltage (kV)



Klystron Test-Photo of test station and long pulse test

IGBT Sw Cabinet

Pulse Transformer TankKlystron High Power Circulator

High power Water Load

Variable Shorted WG

Coupler Insertion PointsRF waveform measured in 060301

RF Window



Modulator and klystron plan in FY2006

Modulator New modulator (#2) based on the ILC-BCD type will be manufactured.

Preparation of the tender is under going. Full completion depends on budget.

Klystron Second TH2104C (5MW tube) will be conditioned for the waveguide

components’ evaluation or RF gun test. Collaboration of the 10MW-MBK, especially of the horizontally mounted MBK ,

with Toshiba Corp. is considered. It is also depends on the budget. Design work of the 10 MW-MBK with the 36 beam-lets which is operated in 50

kV are planed. Collaboration between KEK and Russian engineers is under going.



Coupler test configuration

Usual test terminated by a high power load

Durability test under the large reflection power.

High-power circulator is required to protect the klystron


Waveguide Layout and coupler test

5MW

Coupler

High PowerDummy

Arc SensorModulatorfor 5MWKly DC

DC

Variable ShortCoupler

Circulator

Modulatorfor 5MWKly

5MWArc Sensor

DC

Circulator

DC

Coupler developed by Kako etc.


Phase-1 Cavity Test WG ConfigurationAccelerator Laboratory

Modulatorfor 5MWKly

5MW

Arc Sensor

3dB

Penetration(10m)

3-dBHybrid-PDS

3 Stub Tuner

Monitor DC

Φ Φ Φ

Power DistributionDC

Monitor DC

Another type of PDS, which is possible to change the phase and Qext of the cavities independently, should be also studied.

At first, 8 circulators will be used to have an initial test.


J-PARC based LLRF system

Digital FB system using a FPGA board

LLRF PLC system control digital FB system

400 W Amp.400 W Amp.Digital FBDigital FBcPCI systemcPCI system

will be installed will be installed in Aug.2006in Aug.2006

LLRF system @STF Phase1

Arc sensorFast Interlock

Klystron linerlizer

Power meter



Digital LLRF FB control @STF Phase1

J-PARC STF Phase-1

Cavity Normal Super

Frequency 324 MHｚ 1300 MHｚ

Q-value 2e4 2e6

Rise time 100 us 500 us

Pulse width 650 us 1.5ms

Phase difference

～ 30deg. ～ 60deg.

Pulse voltage Lorentz detuning

others Microphonics

Amp. Stability ±1％ ±0.1％

Phase stability ±1deg. ±0.1deg.

FB loop ＜ 1us ＜ 3us

JPARC linac LLRF

4x14bit ADCs324 MHz

Max. 2 cav.IF=12 MHz

LO=312 MHzSampling=48 MHz

STF phase-1

10x16bit ADCs1300 MHz

Max. 8 cav.(rocketIO)IF=10 MHz


STF phase-2

1300 MHzMax. 36 cav.IF=10 MHz


Digital cavity simulator

Achieved stability of~+-0.1%, ~+-0.05deg. @J-PARC

Amplitude:6000, phase:0deg.



FPGA & DSP boards @STF Phase1

10 16bit-ADCs10 16bit-ADCs

FPGAFPGA2DACs2DACs

Quench etc.Quench etc.

Output maxOutput max

RF offRF off(by diagnostics in DSP)(by diagnostics in DSP)

Real time intelligent diagnostics by DSP boardReal time intelligent diagnostics by DSP board

Custom FPGA board: Mezzanine card of the commercial DSP board10 16bit-ADCs and 2DACs + 2Rocket IO40 MHz clock

Commercial DSP board (Barcelona) (same to J-PARC system):4x TI C6701 DSPsCan access to FPGA like an external memory of DSP



Cavity Simulator: by commercial FPGA board

(Finished)

FB program developmentFB program development（（ ~2006.Dec~2006.Dec ））

FB operationFB operation（（ 2006 Dec.2006 Dec. ））

Software development plan for STF-Phase1

FB algorism(software development)

Real Cavities



Now, the number of ADCs in a FPGA board is limited due to the substrate. (maybe ~15 with 16 layers in substrate)The idea is based on the ‘digital radio’ and obtaining cavity signals with a ADC.

Mixture of two signals decrease the resolution of analog signals but averaging increases the resolution.

IF1(8 MHz)

IF2(12 MHz)

Triger(48 MHz)

Mixed signal(IF1+IF2)

averaging(IF2 1)-> IF1 signal

averaging(IF1 1)-> IF2 signal

Proposal of IF mixture

Over-sampling: IF 8 MHz & 12 MHz with 48 MHz sampling Over-sampling: IF 8 MHz & 12 MHz with 48 MHz sampling -> include averaging effect ->increase resolution-> include averaging effect ->increase resolution

Cavity signals do not change during averaging (due to high Q values)→　 Enough IF separation



LLRF schedule(analog llrf and MPS)• Analog llrf (amplifier, etc.): finished• MPS: almost finished (except modification for 8 cavities)• PLC program improvement (MPS, for 8 cavities): ~ Aug.,2006(digital FB system)• FPGA/DSP/Host program development: ~June 2006• Brash-up of feedback algorithm by cavity simulator: July,2006-Aug.,2006 • Installation of digital FB system to STF: Aug.,2006 • Test operation at STF with cavity simulator: ~Dec. 2006 • Host/Data acquisition software development: ~Dec. 2006



Summary In FY2005, RF system for STF has been developed as planed in the

beginning. Reformation of the PNC modulator has almost done and performed the

klystron test. Bouncer circuit will be installed in middle of April. First coupler test will be scheduled in April. Klystron bought 15 years ago was evaluated and operated normally. Plan of the FY2006 for modulator and klystron are shown. New modulator is

now under the preparation of tender. Development of MBK is also seriously considered.

LLRF is under manufactured based on the technology developed in J-PARC.

Analogue system of LLRF has installed and already operated. Digital LLRF system are developed. Digital FB hardware for STF Phase-1

was completed and installed. Cavity simulator and software development are scheduled in this spring to

autumn.


S. FUKUDA LCPAC 0603251 RF-Systems for STF S. Fukuda Accelerator Laboratory Content Introduction...

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