S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

CHAPTER 5THE LC-3

Topics

Memory organization Registers Instruction set

Opcodes Data types Addressing modes Instructions Condition codes

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

LC-3: Memory

Memory• Address size: 16 bits• Address space: 216 = 65,536 locations• #bits per location (addressability): 16 bits

LC-3 operates on 16 bits of data.

We refer to 16 bits as the word size in LC-3.

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

LC-3: Registers

Registers• Temporary storage units • Eight general-purpose registers: R0 - R7• Each register is 16 bits wide• Other registers

• PC (Program Counter – 16 bits) • IR (Instruction Register – 16 bits)• Condition Codes

How many bits are needed to uniquely identifya general-purpose register?

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

LC-3: Instruction Set

Instruction usually contains two items:• Opcode & Operands

OpcodesSpecifies the operation the instruction requests the processor to execute.• Specified by 4 bits• Bits [15:12] of the instruction or IR [15:12]• 15 opcodes

OperandsSpecifies data needed for the operation

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

LC-3: Instruction Set (Continued)

Data Types• 16-bit 2’s complement integer

Addressing Modes Specifies how an operand can be accessed 5 addressing modes in LC-3

• Immediate• Register• PC-relative• Indirect• Base+offset

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Immediate & Register Addressing Mode

Immediate addressing:

Operand is included as part of the instruction

Operand = SEXT (IR[4:0])

(SEXT means Sign extended to 16 bits)

Register addressing:

Operand is contained in a register

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

PC-Relative Addressing Mode

PC-relative addressing:

Instruction contains an offset value in IR[8:0]

Memory address = PC* + SEXT (IR[8:0])

Operand = mem [ PC + SEXT(IR[8:0]) ]

* This is the incremented PC value because PC is incremented as part of the FETCH phase

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Indirect Addressing Mode

Indirect addressing:

Instruction contains an offset value in IR[8:0]

Indirect address = PC* + SEXT (IR[8:0])

Memory address = mem [ PC + SEXT(IR[8:0]) ]

Operand = mem [ mem [ PC + SEXT(IR[8:0]) ] ]

* This is the incremented PC value because PC is incremented as part of the FETCH phase

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Base+Offset Addressing Mode

Base+offset addressing:

Instruction contains a base register and an offset value in IR[5:0]

Memory address = BaseR+ SEXT(IR[5:0])

Operand = mem [ BaseR+ SEXT(IR[5:0]) ]

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

LC-3: Instruction Set (Continued)

Data Types• 16-bit 2’s complement integer

Condition CodesLC-3 has 3 condition codes

Some opcodes set/clear condition codes, based on result• N (Negative) = 1 if the result is negative • Z (Zero) = 1 if the result is zero • P (Positive) = 1 if the result is positive (> 0)

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

LC-3: Instruction Set (Continued)

3 different types of instructions in LC-3• Operate instructions

ADD, AND, NOT• Data movement instructions

LD, LDI, LDR, LEA, ST, STR, STI• Control instructions

BR, JSR/JSRR, JMP, RTI, TRAP

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Operate Instructions

Only three operations: ADD, AND, NOT

• Source and destination operands are registers• These instructions do not reference memory• ADD and AND can use “immediate” addressing

mode

Immediate addressing: Operand is included as part of the instruction

Register addressing: Operand is contained in a register

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Data Movement Instructions

Load -- Read data from memory to register

Store -- Write data from register to memory

• LD & ST – use PC-relative addressing mode

• LDR & STR – use base+offset addressing mode

• LDI & STI – use indirect addressing mode

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Data Movement Instructions (Continued)

Load Effective Address (LEA)

Instruction contains an offset value in IR[8:0]

Computes address using PC-relative addressing ( PC + SEXT (IR[8:0]) ) and stores the result into a register.

Note: The address is stored in the register,not the contents of the memory

location.

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Control Instructions

Control instructions alter the sequence of

execution by changing the PC value.

3 types of control instructions in LC-3:• Conditional branch• Unconditional branch (jump)• TRAP

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Control Instructions

Conditional Branch

Branch specifies one or more condition codes.

If a specified condition is true PC ← PC + SEXT (IR [8:0]) ; branch to the new

locationelse

PC is not changed ; branch is not taken and the next

sequential instruction is executed

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Control Instructions (Continued)

Unconditional Branch (or Jump)Always changes the PC

TRAPChanges PC to the address of an OS “service routine”

Routine will return control to the next instruction (after TRAP)

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

LC-3 Instruction Set

The complete instruction set of LC-3 is explained in

Appendix A (pages 521 – 545) of the CPSC 240

textbook.

A few example instructions will be discussed in the

class.

Students are responsible for reviewing and

understanding the complete instruction set of LC-3.

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

LC-3 Instruction Set - Example

ADD R2, R3, R4 ;R2 ← R3 + R4Where

R2: Dst (destination register) IR[5] = 0 for Register

R3: src1 (source register 1) addressing mode

R4: src2 (source register 2)

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

LC-3 Instruction Set - Example

ADD R2, R3, #7 ;R2 ← R3 + SEXT (00111)Where

R2: Dst (destination register) IR[5] = 1 for Immediate

R3: src1 (operand 1) addressing mode

#7: Imm5 (imm. value as operand 2)

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

LC-3 Instruction Set - Example

The condition codes specified by IR[11:9] are tested. For example, ifIR[11] is set, then “n” is tested and if IR[11] is clear, “n” is not tested.

BRz Loop ; branch to Loop if the last result was zero. If z = 1, PC ← PC + SEXT (IR [8:0])

This instruction employs PC-relative addressing mode.

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

LC-3 Instruction Set - Example

This instruction employs Indirect addressing.

STI R5, ADR ; mem [ mem [ PC + SEXT (IR [8:0]) ] ] ← R5

where R5: Src (Source register)

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

LC-3 Instruction Set - Example

This instruction employs (Base + Offset) addressing.

LDR R3, R6, #8 ; R3 ← mem [ R6 + SEXT (001000) ]

where R3: Dst (Destination register)R6: Base (Base register)

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

LC-3 Instruction – Example Problems

Convert the following LC-3 instruction into the

corresponding machine codes:

1. AND R5, R1, R6

2. AND R5, R6, #14

3. BRp #9

4. LD R7, #8

5. JSR #12

6. LDR R4, R3, #12

7. LDI R4, #7

S. Barua – CPSC 240 sbarua@fullerton.edu http://sbarua.ecs.fullerton.edu

Example Program on LC-3

Consider the following program that is loaded into

memory starting at location x30FF.

x30FF 1110 0010 0000 0001

x3100 0110 0100 0100 0010

x3101 1111 0000 0010 0101

x3102 0001 0100 0100 0001

x3103 0001 0100 1000 0010

(a) Give the equivalent assembly language code.

(b) If the program is executed what is the value in R2 at the end of the execution?