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ECE 3125: Analog Electronics Design Lab 9: Power Amplifiers – Classes A & AB

Caitlin Carroll | David Rubenstein OBJECTIVE The primary objective of this experiment are (1) to develop a three-stage amplifier with an overall gain of 16000V/V, (2) calculate the resistor components to meet the specifications, and (3) simulate and build the system to verify all calculations. It is suggested to improve the model so that it gives more gain, lower DC power consumption, greater bandwidth or allows a larger AC signal as input. DESIGN SPECIFICATIONS Overall System Gain: 16000V/V Stage 1 Gain: 100V/V Stage 2 Gain: 160V/V Stage 3 Gain: 1V/V ISTAGE1 = ISTAGE3: 1mA ISTAGE2: 10mA C: 47µF PART LIST Equipment

1. Oscilloscope 2. Function Generator 3. Multimeter 4. Power Supply 5. Cables

Components 1. (3) MPSA18 2. (various) Resistors 3. (1) Load resistor 4. (4) 47µF capacitors

DESIGN APPROACH The overall approach to the design was to achieve the 16000 of gain in two stages. The first stage is a common base amplifier with a gain of 100, and the second stage is a common emitter amplifier with a gain of 160. Those two stages may cause an unwanted voltage offset in the final signal so a voltage shifter will be used as the third and final stage of the amplifier circuit.

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CIRCUIT SCHEMATICS

Circuit Schematic of 3-Stage Amplifier

Circuit Schematic with Node Voltages Shown

Circuit Schematic with Currents Shown

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CALCULATIONS (1) Common Base Amplifier

!! = !!!! − !!!

!! != !15− 5!!10!!" = 1!Ω

Assume VBB = -11 V VE = VBB – VBE = -11.7 RE = !!!!!!!!!

= 333 Ω

RB1 = !!!!!!!!!

= 50k

RB2 = !!!!!!!!!

= 8.2k

(2) Common Emitter Amplifier

Assume VC = 0.5VCC ! VC = 7.5V

!! = !!!! − !!!

!! != !15− 7.5!!10!!" = 750!Ω

Assume RE = 0.1RC ! RE = 75 Ω VE = IERE = 10mA x 75 Ω = 0.750 V VB = VE + VBE = 0.75 + 0.7 = 1.45V AV = !!!||!!!!

!!!!!!||!!! = 160

! RE1 = 5!Ω (part of small signal analysis)

RIB = (B + 1)(re + RE) = 501 x (2.5 Ω + 75 Ω) = 94k!Ω

RB = !!"!!"!!"!!!!" = 4.2k!Ω

RB = R1 || R2 Assume R2 = 50k

R1 = !"!!!!!!" = 4.8k

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PSPICE TRANSIENT WAVEFORM

(Right) Output waveform before level shift (Left) Output waveform after level shift

PSPICE FREQUENCY RESPONSE

Frequency Response of System

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3dB FREQUENCY RESPONSE AND BANDWIDTH CALCULATION

VOUT = 7.85 V 3dB point = VOUT × ! !! = 7.85 V × ! !! = 5.55 V

fc1 ≈ 700Hz fc2 ≈ 3kHz B = fc2 – fc1 ≈ 3000 – 700 = 2.3kHz

RESULTS (1) Results based on calculations

(Left) Amplified signal with 200mV input at 200kHz frequency. Gain from the system

is 130V/V (Right) Amplified signal with 200mV input at 5MHz frequency.

Input!voltage!and!input!frequency! Image!of!amplifier!circuit!built!on!a!breadboard!

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The circuit was only able to amplify the 200kHz input signal when it was at least about 200mV peak to peak. Without this minimum threshold, the output was a ~5MHz waveform which was likely just noise. The output’s amplitude was completely clipped when 200mV was provided however (indicating that the circuit did have significant gain). Individually, the stages produced gain that should have been about 1000. The same 200mV peak to peak, 200kHz signal was put into each stage and the results were taken. (2) Results with tangible gain

Output of Common Base Base amplifier (Av = 17)

Output of Common Emitter amplifier (Av = 64)

Output of Level shifter (shifted down ~1.5V)

Blue signal indicates the input to Level Shifter. Yellow

signal indicates output of Level Shifter

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Common Base Transistor

Common Emitter Transistor

Voltage Shifter (Common Collector)

Voltage Shifter (Current Source)

VC (V) 2.6 -2.0 15.5 -4.0 VB (V) -10.2 -13.1 -2.1 -14.3 VE (V) -10.8 -13.8 3.1 -15.1 VBE (V) 0.62 0.65 0.69 0.73 VCE (V) 13.3 13 14.3 8.8 IC (mA) 11.3 21.5 14.2 14.2 IB (µA) 10.8 65 13.4 52 IE (mA) 11.3 21.0 14.2 13.9

Table of measured values from each stage of the amplifier CONCLUSION A possible cause of error in the circuit is the loading of the first and second stages. When a smaller resistance is used as the load of an amplifier, the gain goes down. The input of the second stages acts as a load to the first stage. This same principle applies to the third and second stage. The input impedance of either the second or third stages may have been too small. The output of each individual stage was taken to determine where the problem was. With the first stage’s gain of 17 and the second of 64, an overall gain of 1088 should have been achieved. It is good that each stage independently achieved significant gain and that the full circuit worked in PSPICE.