RS232: Serial Communication

Introduction

The purpose of this lab is to understand the serial data communication protocol, specifically

RS232 and to implement a labview FPGA to send/receive data over RS232 to the host pc.

Serial vs. Parallel Communication

Generally, data communication can be divided into serial and parallel communication. Although

parallel communication can provide higher rate of data transmission, it is limited by its

maximum distance between two data communication devices. On the other hand, serial data

communication can overcome the distance limitation as it can be used to transmit data for longer

distance; however, data can be transmitted serially through the communication channel [3].

Parallel/Serial Conversion

Normally, when multiple bytes of data are to transmit over the serial communication channel, the

bytes of data will need to be converted from parallel to serial with shift registers.

Figure 1: Parallel/Serial Converter

Synchronous vs. Asynchronous Serial Transmission

Serial Data Communication can be further divided into synchronous and asynchronous

transmission. Synchronous transmission uses the clock signal to synchronize the data

transmission so that data can be transferred continuously [3]. However, asynchronous

transmission uses start bit and stop bit to identify the frames of data, so data cannot be

transferred continuously.

RS232 Protocol

Traditionally, RS232 has been used for serial communication between computer terminals (data

terminal equipments) and modems (data communication equipments). The protocol of RS232

can be generally divided into:

1) Physical – voltage levels, signaling rate (baud rate)

2) Data Link – data frame, parity check, and flow control

Serial IO

Parallel IO

MSB LSB

At the physical level, RS232 uses NRZ-I (Non Return to Zero- Inverted) digital code [3] to

represent digital data. Therefore, +5V to + 20V is used to represent Zero bit, and -5V to -20V is

used to represent One bit.

Figure 2: NRZ-I Encoding

Also depending on the communication devices, the baud rate can vary from 75 bit per second to

25500 bit per second.

At data link level, digital bits are group into data frame which is identified by start bit (0) and

stop bit (1). Inside the frame is the data bit, usually 8 bits data (ASCII Character). Since RS232

employs the asynchronous data transmission, the flow control is required to make sure the data is

not overflow at the receiver end. In RS232, flow control can be achieved by hardware, which

utilizes the extra signal lines, such as RTS (Request to send) and CTS (Clear to send), or

software, which uses extra bit pattern to identify the overflow state of the buffer.

Procedures for Labview FPGA Implementation of RS232

Our labview FPGA implementation can be divided into 2 parts: the transmitter and receiver. For

transmitter part, we utilized the VISA (Virtual Instrument Software Architecture) interface to

send data through RS232 serial communication channel. The female 9 pin connector is

configured with loop-back configuration by connecting TDR and RDR pins. Then the TDR is

connected to FPGA digital input in SCB-68, and the ground is connected to the digital ground.

In order to read the data from RS232 communication channel, the FPGA labview interface was

implemented. To read the data correctly, the labview program has to follow the RS232 protocol:

both physical and data link.

The physical part of the FPGA program will deal with the baud rate and digital signals. Since

RS232 uses +5V to represent digital 0 and -5V to represent digital 1, logic inverter is used to

invert the signal. Also, the FPGA uses 40MHz sampling rate [2] and we had to adjust the

sampling rate to match with the baud rate of RS232, by putting time delay [1][3].

For the data-link part, labview program has to detect the data frame, and re-build the ASCII

characters from the data frames. Therefore, the algorithm is divided into 3 parts:

1) To detect the start bit and to start the counter to count the number bits in the data frame

Figure 3: FPGA Labview Program for part 1

2) To extract the data bit and transform into 8 bits ASCII characters

Figure 4: FPGA Labview Program for part 2

3) To detect the stop bit.

Figure 5: FPGA Labview Program for part 3

Results and Discussion

Figure 6: RS232 Data Frame

Figure 7: VISA Program to send data

Figure 8: FPGA Labview to receive data

In order to send the data, the transmitter and receiver has to agree on the baud rate. Due to the

FPGA internal clock rate (40 MHz), the baud rates, which can be used, are 300, 600, 1200. 9600

baud rate causes some time-out problems, because it cannot result in integer division. For

example, 40MHz divided 9600 will result in 4166.667. Although there are some limitations due

to baud rate calculation, the program was able to transmit and receive data without much

difficulty.

References

[1] Bishop H. Robert., “Labview” 2nd

Edtion Prentice Hall Inc., 2007.

[2] Lathi ., Signal Processing and Linear Systems, Oxford University Press, 2000 (ISBN

0195219171).

[3] National Instruments., Developing Digital Communication Interfaces with Labview FPGA,

http://zone.ni.com/devzone/cda/tut/p/id/5411

Appendix: Flow Chart for FPGA Labview

Digital InputDelay 500ms

Invertor

Counter = 0 & Input Bit = Zero

Set Start Bit =True

Extract Build

Put it in the Array

Extract 8 Bits

Convert to ASCII

Convert to Char

Increment Counter

Counter >= 7Reset Counter

Set Start Bit = False

Start Bit = True

Start Bit = False

No

Yes

YesNo

Yes