Ross J REU Poster [Read-Only]reu-mse.mme.wsu.edu/past/2005/JohnsonRoss2005.pdfMaterials Research REU...
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Microstructural Characterization of Copper Thin Films Ross Johnson University of New Mexico WSU REU Program Acknowledgments: Dr. David Field, WSU Dr. No-Jin Park, Kumoh National Institute of Technology Paul Besser, Advanced Micro Devices C Motivation for Study Cu is a highly conductive material, more so than any Al/Cu alloy. For integrated circuits, a switch to Cu means higher current density which translates to faster processing speeds. However, stress voiding during processing and electromigration during performance are two problems which have proven to limit the performance of the Cu circuit. Understanding the development of thin film Cu microstructure could potentially lead to further insight on the performance and manufacturability of Cu interconnects. This study looks specifically at thin electroplated Cu films that are of varying sizes and heat treatments. The hope is to understand the factors that govern the development of the microstructure; understanding these factors will aid in producing a more consistent reliable product. Introduction Previously, before the turn of the century, Al/Cu alloys had been used as the conductive material in integrated circuits for computers. Now that industry has switched to Cu as the preferred material for interconnects, there are many new problems introduced in the manufacturability and performance of integrated circuits. Images obtained from Intel website Experimental Details Six electroplated Cu on Si samples from Advanced Micro Devices (AMD) were examined. Three samples had a 450 nm Cu layer, and the other three had an 850 nm Cu layer. One sample from each thickness underwent a heat treatment of 300 o C, 400 o C, or 500 o C. Each sample’s microstructure was characterized using FESEM EBSD analysis. . Conclusions For the 850 nm sample, grain size reduces as temperature increases. There is also a significant amount of twin boundaries developed as temperature increases. The strength of the <111> out of plane texture increases as temperature increases. For the 480 nm sample, grain size also reduces as temperature increases. Some twins are developed as temperature increases. However there is a decreasing trend in the strength of the <111> out of plane texture. When examining the microstructure of each sample, it is clear that both samples are heterogeneous. A heterogeneous microstructure is undesirable to manufacturers because the behavior of the material will be different from place to place. Factors Controlling Thin Film Microstructures There are numerous manufacturing parameters controlling the development of thin film microstructures. Some of these factors include thermal cycling, coating procedure, heat treatment, contact surface energies, and film thickness. In this study only heat treatment and film thickness will be explored. Data Key 300C 400C 500C 480nm Texture Scans 480nm Grain Scans 300C 400C 500C 850nm Texture Scans 300C 400C 500C 850nm Grain Scans 300C 400C 500C a. The pictures above show the texture of the 480 nm sample at various temperatures. The colors tell which direction is the out of plane direction according to the key. b. Information about the 480 nm sample grain sizes can be extracted from the pictures above. c. The pictures above show the texture of the 850 nm sample at various temperatures. d. Information about the 850 nm sample grain sizes can be extracted from the pictures above. Results Grain Size (Twin Boundaries Included) 0 50 100 150 200 250 300 350 400 300C 400C 500C Temperature Grain Size (nm) 480 nm 850 nm Grain Size (Twins Boundaries Excluded) 0 100 200 300 400 500 600 300C 400C 500C Temperature Grain size (nm) 480 nm 850 nm Fraction (111) Grains 0 0.2 0.4 0.6 0.8 1 300C 400C 500C Temperature Fraction (111) Grains 480 nm 850 nm Sigma 3 CSL Boundaries 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 300C 400C 500C Temperature Fraction of Sigma 3 480 nm 850 nm a. The graphs above show average grain size of each sample at various temperatures. Also these graphs give information about the number of twin boundaries in each sample. b. The graph above provides information about the texture of each sample. It plots the fraction of <111> out of plane grain orientations against heat treatment. c. The graph above depicts the effects of heat treatment on twin development. Sigma 3 CSL boundaries are the most common occurring twin boundary for Cu (or any FCC metal). This work was supported through the National Science Foundation: Division of Materials Research REU site program under grant number NSF Contract Number: 12V-3825-5133
Transcript of Ross J REU Poster [Read-Only]reu-mse.mme.wsu.edu/past/2005/JohnsonRoss2005.pdfMaterials Research REU...
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Microstructural Characterization of Copper Thin FilmsRoss Johnson
University of New MexicoWSU REU ProgramAcknowledgments:
Dr. David Field, WSUDr. No-Jin Park, Kumoh National Institute of Technology
Paul Besser, Advanced Micro Devices
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Motivation for Study
Cu is a highly conductive material, more so than any Al/Cu alloy. For integrated circuits, a switch to Cu means higher current density which translates to faster processing speeds. However, stress voiding during processing and electromigration during performance are two problems which have proven to limit the performance of the Cu circuit. Understanding the development of thin film Cu microstructure could potentially lead to further insight on the performance and manufacturability of Cu interconnects. This study looks specifically at thin electroplated Cu films that are of varying sizes and heat treatments. The hope is to understand the factors that govern the development of the microstructure; understanding these factors will aid in producing a more consistent reliable product.
Introduction
Previously, before the turn of the century, Al/Cu alloys had been used as the conductive material in integrated circuits for computers. Now that industry has switched to Cu as the preferred material for interconnects, there are many new problems introduced in the manufacturability and performance of integrated circuits.
Images obtained from Intel website
Experimental Details
Six electroplated Cu on Si samples from Advanced Micro Devices (AMD) were examined. Three samples had a 450 nm Cu layer, and the other three had an 850 nm Cu layer. One sample from each thickness underwent a heat treatment of 300oC, 400oC, or 500oC. Each sample’s microstructure was characterized using FESEM EBSD analysis.
.
Conclusions
For the 850 nm sample, grain size reduces as temperature increases. There is also a significant amount of twin boundaries developed as temperature increases. The strength of the <111> out of plane texture increases as temperature increases.
For the 480 nm sample, grain size also reduces as temperature increases. Some twins are developed as temperature increases. However there is a decreasing trend in the strength of the <111> out of plane texture.
When examining the microstructure of each sample, it is clear that both samples are heterogeneous. A heterogeneous microstructure is undesirable to manufacturers because the behavior of the material will be different from place to place.
Factors Controlling Thin Film Microstructures
There are numerous manufacturing parameters controlling the development of thin film microstructures. Some of these factors include thermal cycling, coating procedure, heat treatment, contact surface energies, and film thickness. In this study only heat treatment and film thickness will be explored.
DataKey
300C 400C 500C
480nm Texture Scans
480nm Grain Scans300C 400C 500C
850nm Texture Scans300C 400C 500C
850nm Grain Scans300C 400C 500C
a. The pictures above show the texture of the 480 nm sample at various temperatures. The colors tell which direction is the out of plane direction according to the key.
b. Information about the 480 nm sample grain sizes can be extracted from the pictures above.
c. The pictures above show the texture of the 850 nm sample at various temperatures.
d. Information about the 850 nm sample grain sizes can be extracted from the pictures above.
Results
Grain Size (Twin Boundaries Included)
050
100150200250300350400
300C 400C 500C
Temperature
Gra
in S
ize
(nm
)
480 nm
850 nm
Grain Size (Twins Boundaries Excluded)
0
100
200
300
400
500
600
300C 400C 500C
Temperature
Gra
in s
ize
(nm
)
480 nm
850 nm
Fraction (111) Grains
0
0.2
0.4
0.6
0.8
1
300C 400C 500C
Temperature
Frac
tion
(111
) Gra
ins
480 nm
850 nm
Sigma 3 CSL Boundaries
0
0.10.2
0.3
0.4
0.50.6
0.7
300C 400C 500C
Temperature
Frac
tion
of Sig
ma
3
480 nm
850 nm
a. The graphs above show average grain size of each sample at various temperatures. Also these graphs give information about the number of twin boundaries in each sample.
b. The graph above provides information about the texture of each sample. It plots the fraction of <111> out of plane grain orientations against heat treatment.
c. The graph above depicts the effects of heat treatment on twin development. Sigma 3 CSL boundaries are the most common occurring twin boundary for Cu (or any FCC metal).
This work was supported through the National Science Foundation: Division of Materials Research REU site program under grant number NSF Contract Number:
12V-3825-5133
