Robust Low Power VLSI ECE 7502 S2015 Delay Test ECE 7502 Class Discussion He Qi March 19, 2015.

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ECE7502S2015

Delay Test

ECE 7502 Class Discussion

He Qi

March 19, 2015

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Requirements

Specification

Architecture

Logic / Circuits

Physical Design

Fabrication

Manufacturing Test

Packaging Test

PCB Test

System Test

PCB Architecture

PCB Circuits

PCB Physical Design

PCB Fabrication

Design and Test Development

Customer Validate

Verify

Verify

Test

Test

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Intro to Delay Test Approach

At-speed Functional Pattern Scan Based Structural Test (Cost Effective)

Tool Automatic Test Pattern Generator (ATPG)

Timing Aware ATPG (Expensive and Time Consuming) Timing Unaware ATPG (Cheap and Fast)

Fault Model Transition Fault

Slow-to-Rise Slow-to-Fall

Path Delay Fault

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Problem of Current ATPG Approach Timing aware ATPG is too time consuming and expensive. Timing unaware ATPG can only detect timing violation on short

path. However, long paths are more likely to fail due to small delay defects.

http://www.edn.com/design/test-and-measurement/4381761/Small-delay-defect-testing-4381761

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Goal of This Work Develop a new approach/automation flow to use timing

unaware ATPG to detect most of the timing violation of device under test including small delay defects.

Ahmed, Nisar, Mohammad Tehranipoor, and Vinay Jayaram. "Timing-based delay test for screening small delay defects." In Proceedings of the 43rd annual Design Automation Conference, pp. 320-325. ACM, 2006.

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Path Length Analysis Long Path (LP): A long path in a design is defined as a path, if affected

by a small delay defect can cause a timing failure. Short Path (SP): A short path requires a significant delay defect size

that will create a very large timing variability to cause a failure. Intermediate Path (IP): A path with a delay in the range other than

long paths


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Path Length Analysis

For small delay defects in short paths, high frequency is needed to detect the defects.

This work only consider delay defects in long paths and use nominal frequency of the device under test.


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The authors move the figure “right” by caring only about the endpoints that the longest path connect to them fall into the LP category.

An observation point at the end of a path (primary output or scan flip-flop) is referred to as an endpoint.


Proposed ATPG Methodology

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Proposed ATPG Methodology We need to let ATPG tool only generate patterns for those

endpoints. Timing unaware ATPG tools have the feature of being set to only care about specific endpoints and screen others. The authors use static timing analysis tools to get the path information and use custom script to translate this information to ATPG-readable format.

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Proposed ATPG MethodologyCare only about “LP endpoints” cannot guarantee more coverage on long paths, since these endpoints also has short paths connect to them and ATPG tool tend to pick these short paths to test. Timing unaware ATPG tools can be set to use multiple path

to detect one transition delay fault site (multiple-detect), increasing the chance of involving long paths.

http://www.edn.com/design/test-and-measurement/4381761/Small-delay-defect-testing-4381761

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After using multi-detect, still a lot short paths involved.


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Proposed ATPG Methodology The authors use a custom script to check which paths

involved in the multi-detect process. They 3 path types. An endpoint which observes a transition

is referred to as an active endpoint. An endpoint which does not observe a transition, referred to as non-active. non-active endpoints active endpoints with path length less than a threshold limit active endpoints with affected paths length greater than the

threshold limit

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Results


The proposed approach generates more patterns

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Results


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Questions

What is the overhead of using their ATPG technique?

What challenges we probably will have if using their approach?

The authors mentioned their approach also applies to short paths. Is it worth to apply this to short paths after defects on long paths are already found?

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Papers [1] Ahmed, Nisar, Mohammad Tehranipoor, and Vinay Jayaram. "Timing-based delay test for screening

small delay defects." In Proceedings of the 43rd annual Design Automation Conference, pp. 320-325. ACM, 2006.

[2] K. Cheng, “Transition Fault Testing for Sequential Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 12, pp. 1971-1983, Dec. 1993.

[3] T. M. Mak, A. Krstic, K. Cheng and L. Wang, “New challenges in delay testing of nanometer, multigigahertz designs,” IEEE Design & Test of Computers, pp. 241-248, May-Jun 2004.

[4] B. Benware, C. Schuermyer, N. Tamarapalli, Kun-Han Tsai,S. Ranganathan, R. Madge, J. Rajski and P. Krishnamurthy,“Impact of multiple-detect test patterns on product quality,” in Proc. Int. Test Conf. (ITC’03), pp. 1031-1040, 2003.

[5] B. Kruseman, A. K. Majhi, G. Gronthoud and S. Eichenberger, “On hazard-free patterns for fine-delay fault testing,” in Proc. Int. Test Conf. (ITC’04), pp. 213-222, 2004.

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Paper Map

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[1] Small Delay Defects Detection for Long Path

[2] Transition Fault Testing

[4] Multiple-Detect Concept

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[3] General Delay Testing in Nano-Scale

[5] Small Delay Detect for Short Paths

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Robust Low Power VLSI ECE 7502 S2015 Delay Test ECE 7502 Class Discussion He Qi March 19, 2015.

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