RISC PROCESSOR IMPLEMENTATION USING BLUESPEC

PART 1 - FINAL PRESENTATION

Performed By: Yahel Ben-Avraham and Yaron Rimmer

Instructor: Mony Orbach

Bi-semesterial, 2012 - 2013

17/10/2013

Project goals

Goal: Implementing and analyzing RISC Processor using Bluespec

Part A:Studying the working environment, BSV

language and the basic processor implementation.

Implementing a simple RISC processor.Run a simple test bench on the FPGA system.

Pipeline Datapath 5-stage pipeline

Pipe stages: Fetch, Decode, Execute, Memory, WriteBack

Each stage implemented as a “black box” within a separate rule.

For now, not including Data forwarding, Hazard detection.

?

The Pipeline

WB

Instruction memory

Register file

Memory

MEMEXEDECFETCH

FETCH2DEC DEC2EXE EXE2MEM MEM2WB

Passing structs through FIFOs

BSV ImplementationWrapper.bsv

Defines.bsv

Datapath.bsv

Fetch.bsv Decode.bsv Execute.bsv

Memory.bsv Writeback.bsv

Fetch

Tag the instruction’s metadata (PC, cycle) Fetch the requested instruction from the

instruction memory Update next PC

Decode

Fully parse the received instruction Pre-fetch data from registers potentially in use

Execute

According to the instruction’s opcode:ALU instruction: compute the resultMemory instruction: calculate memory address to

read / write toBranch instruction: check if branch is taken and

update branch resolution and target address

Memory

According to the instruction’s opcode:StoreLoadOtherwise, pass the incoming data

Currently implemented as Register file, to be replaced by BRAM

Writeback

Save needed data to the register fileRegister 0 – read only

The Pipeline

WB

Instruction memory

Register file

Memory

MEMEXEDECFETCH

FETCH2DEC DEC2EXE EXE2MEM MEM2WB

Jumps and Branches

The first 6 bits of the instruction are checked in the Fetch stage.If Jump – next PC is immediately updated

with the rest of the instruction bits.If Branch – insert 3 NOPs to the pipeline

and wait for branch resolution from the Execute stage.

Implemented easily with Bluespec!

Functionality tests

Memory Jump Branch (taken) Branch (not taken) (ALU functions)

Examples: Memory

Examples: Jump

Examples – Branch (taken)

Examples: Branch (not taken)

The working environment

Using a platform by Shai Shachrur and Danni Hofshi.Allowing us to focus on the processor.

The platform enables:Synthesis of design to FPGA.Cycle level control using COP.Reading and writing to memories.Performance counters.

The platform

System layers

Project progress overview

Studying the working environment, BSV language and the basic processor implementation.

Implementing the presented pipelined MIPS processor.

Run a simple test bench on the FPGA system.

Started planning part 2 implementations.

Up next…

Up Next• Branch prediction, Hazard detection and Data

forwarding

• Wider instruction set

• Implement memories as BRAM (split pipeline stages)

• Running on FPGA

• Performance counters and assessments

QUESTIONS?