RiceNIC: A Reconfigurable and Programmable Gigabit Network Interface Card
1
RiceNIC: A Reconfigurable and Programmable Gigabit Network Interface Card Jeff Shafer, Dr. Scott Rixner Rice Computer Architecture: http://www.cs.rice.edu/CS/Architecture System Architecture System Architecture Port RJ-45 Port DDR Virtex FPGA Spartan FPGA PCI Interface Ethernet PHY Networks are Essential! Networks are Essential! Networking is an integral part of computer systems The role of a network interface is evolving Significant new research is changing the hardware/software interface between the operating system and the network interface card (NIC) Researchers need a flexible NIC to study this field RiceNIC is a reconfigurable and programmable Gigabit Ethernet NIC that meets these research needs NIC design is freely available for research/education! NIC provides significant computation and storage resources and allows the user to customize NIC behavior in software and hardware. Slice Registers 9,089 / 27,392 33% 4 input LUTs 11,811 / 27,392 43% BRAMs 51 / 136 37% Occupied Slices 9,164 / 13,696 66% Global Clocks 10 / 16 62% Clock Managers 5 / 8 62% NIC Features NIC Features Software Programmability Dual 300 MHz PowerPC processors 256 MB DDR memory 2MB SRAM (accessible from host and NIC) Serial port for debugging Descriptor control system Hardware Acceleration MAC / DMA controllers TCP Checksum Offloading Hardware Event notification PCI Bus (64b / 66 MHz) DDR Memory (256 MB) Bridge PCI SRAM (2 MB) Hardware Events PowerPC 405 Embedded Processor (300 MHz) PLB Bus I-Cache (16 KB) D-Cache (16 KB) BRAM (32 KB) Virtex FPGA Spartan FPGA Gigabit Ethernet PowerPC 405 Embedded Processor (300 MHz) I-Cache (16 KB) D-Cache (16 KB) Scratchpad (2 KB) Back-End DMA SRAM Controller Bridge Front-End DMA DDR Controller UART RS-232 Serial FPGA Development Board Gigabit MAC PHY Performance Performance RiceNIC TCP stream throughp compared to commercial NIC Software Design Software Design PowerPC processor runs custom packet-handling firmware Interfaces with MAC to send/receive packets Interfaces with DDR to store bulk frame data Interfaces with DMA engine to transfer data to/from host Custom Linux and FreeBSD device drivers Virtex FPGA Placement Virtex FPGA Placement Ethernet MAC DDR Controll er PCI DMA Engine NIC Control & Data Bus PowerPC Processors
-
Upload
lara-randolph -
Category
Documents
-
view
60 -
download
0
description
Serial Port. DDR. Virtex FPGA. Spartan FPGA. RJ-45 Port. Ethernet PHY. PCI Interface. Gigabit Ethernet. FPGA Development Board. PHY. RS-232 Serial. Virtex FPGA. Front-End. DDR. Gigabit. BRAM. DDR. UART. DMA. Spartan FPGA. Memory. MAC. (32 KB). Controller. (256 MB). - PowerPoint PPT Presentation
Transcript of RiceNIC: A Reconfigurable and Programmable Gigabit Network Interface Card
RiceNIC: A Reconfigurable and Programmable Gigabit Network Interface Card
Jeff Shafer, Dr. Scott RixnerRice Computer Architecture: http://www.cs.rice.edu/CS/Architecture
System ArchitectureSystem Architecture
Development PlatformDevelopment Platform Avnet Virtex-II Pro Development Board
Serial Port
RJ-45 Port
DDR
Virtex FPGA
Spartan FPGA
PCI InterfaceEthernet PHY
Networks are Essential!Networks are Essential! Networking is an integral part of computer systems The role of a network interface is evolving
Significant new research is changing the hardware/software interface between the operating system and the network interface card (NIC)
Researchers need a flexible NIC to study this field RiceNIC is a reconfigurable and programmable Gigabit
Ethernet NIC that meets these research needs NIC design is freely available for research/education! NIC provides significant computation and storage
resources and allows the user to customize NIC behavior in software and hardware.
Device UtilizationDevice Utilization Space for future development
Component Virtex FPGASlice Registers 9,089 / 27,392 33%4 input LUTs 11,811 / 27,392 43%BRAMs 51 / 136 37%Occupied Slices 9,164 / 13,696 66%Global Clocks 10 / 16 62%Clock Managers 5 / 8 62%Gate Count: 3,944,049
NIC FeaturesNIC Features Software Programmability
Dual 300 MHz PowerPC processors
256 MB DDR memory 2MB SRAM (accessible
from host and NIC) Serial port for debugging Descriptor control system
Hardware Acceleration MAC / DMA controllers TCP Checksum Offloading Hardware Event notification
PCI Bus (64b / 66 MHz)
DDRMemory(256 MB)
Bridge
PCI
SRAM(2 MB)
HardwareEvents
PowerPC 405Embedded Processor
(300 MHz)
PLB Bus
I-Cache(16 KB)
D-Cache(16 KB)
BRAM(32 KB)
Virtex FPGA
Spartan FPGA
GigabitEthernet
PowerPC 405Embedded Processor
(300 MHz)
I-Cache(16 KB)
D-Cache(16 KB)
Scratchpad(2 KB)
Back-EndDMA
SRAMController
Bridge
Front-EndDMA
DDRControllerUART
RS-232Serial
FPGA Development Board
GigabitMAC
PHY
PerformancePerformance RiceNIC TCP stream throughput
compared to commercial NIC
Software DesignSoftware Design PowerPC processor runs custom
packet-handling firmware Interfaces with MAC to
send/receive packets Interfaces with DDR to store
bulk frame data Interfaces with DMA engine
to transfer data to/from host Custom Linux and FreeBSD
device drivers
Virtex FPGA PlacementVirtex FPGA Placement
Ethernet MAC
DDR Controller
PCI DMAEngine
NIC Control & Data Bus
PowerPCProcessors
