RFCMOS





Footprints of CMOS Technology Innovation [1]
’97
0.13um
90nm
0.18um
0.25um
0.35um
65nm
40nm
28nm
’99
’01
’02
’04
’08
’10
1995
Logic Based eDRAM
00 Prologue
Memory Area Memory Area
Row Decorder
– Bi state switching device

CMOSSPICE
C
Rsub3
01

→
Semi-Auto Prober
Network Analyzer
Probe Station
→
800um
→
R+jL
→
Cox, Csub and Rsub represent equivalent circuit of Si substrate
in most cases.
PITee
Y3
PI
-Y12=-Y21
Y3
• Generation of “pi-equivalent” circuit using Y-parameters.
© 2021 KIOXIA Corporation. All Rights Reserved. 17
Step 1 Low frequency
• CSUB node can be treated as “OPEN” at low frequency.
© 2021 KIOXIA Corporation. All Rights Reserved. 18
Step 2 High frequency
• Define “ZSUB” by subtracting Cox impedance from 1/Y1 .
• “RSUB” and “CSUB” defined by real and imaginary part of “ZSUB” respectively.
© 2021 KIOXIA Corporation. All Rights Reserved. 19
Complete formula
→
02 5GCMOS


MOSFET
[F/cm-2]
[F/cm-2]
Cd Depletion Capacitance
Cox Oxide Capacitance
MOSFET
CMOS
1
10
100
1000
Years
EKV
BSIM4v4
MM9 (MosModel9) →Philips
TUC
Gate
Gate leak current is not ignorable due to the higher tunneling probability
of thinner gate oxide
In latest CMOS compact model, several current sources as Igb, Igs, Igd,
Igc(Igcs, Igcd) having Vg dependency, which gives bias dependence, and
mathematical smoothing transforming function from accumulation to
inversion mode, via depletion.
Ioff/Tr is ~100nA


This was focused as a big-problem to degrade Transistor performance from 130nm
generation.
SBSA
SB difference from reference
STI stress effect –VTH shit of 130nm CMOS-
5 10 15 20 25 30 35 40 45 50 550 60
0.17
0.19
0.21
0.23
0.25
0.27
0.29
0.31
0.33
0.15
0.35
Finger_Num
s]
Finger_model
5 10 15 20 25 30 35 40 45 50 550 60
0.28
0.29
0.30
0.31
0.32
0.33
0.34
0.35
0.27
0.36

MOSFET with adjacent well boundary tends have higher Vth. This is due to the highly doped area
generated by back-scattering of impurity atoms against photo resists. Which occur in the Well Ion
Implantation process.
eff = efforg (1+KU0WE(SCA+WEBSCB+WECSCC))
SCi (i=A,B,C..), is effective distance determined by the use of SC1~SC4 (between outer edge of MOSFET and Well boundary)
Higher
Recent Compact Model formulates
Vth and Mobility shift as a linear form of SCi (i=1~4) .
© 2021 KIOXIA Corporation. All Rights Reserved. 30
CMOS
High-volume meas.
Accurate AC stat model Physical stat model
Wafer level
Fab-Link model
BigData
Fixed use of Typical model. Over spec was set in Corner and MC model.
Test structure design. GSG-TEG GSG-type SL-monitor
120 GHz Semi-Auto
Tr

03 High Volume measurement
Issues of high volume millimeter-wave measurement.
– Precise Probe skating
– Precise Wafer alignment
Design of scribe-type GSG test structure.
Compatibility kept upto 35GHz. Needs improvement.
34
embedding with simulated data of SHORT,OPEN and
DUT patterns.
S11 S12 S21 S22
04 Test structure design for
high volume measurement.
Test structure for ONE GENERATION
Inductors
MOSFETs
Resistors
Capacitors
Varactors
Metals
DC/s-parameter evaluation for MOSFETs Equivalent circuits model Spice parameter extraction Noise model (Flicker and RF noise)
s-parameter evaluation for resistors Equivalent circuits model
s-parameter evaluation for capacitors Equivalent circuits model
CV/s-parameter evaluation for varactors Equivalent circuits model Spice parameter extraction
Metal-Line Evaluation
GSG-Test Structure for Device Modeling
Target In between reference plane
Symmetrical
Complete Set for Precise Device Modeling
Adjust Left and Right pattern to configure THRU line.
Reference Plane
OPEN and SHORT De-embedding
STEP1
STEP2
De-embedding (STEP1)
Y-matrix operation is useful to operate Π configured circuit
© 2021 KIOXIA Corporation. All Rights Reserved. 41
De-embedding (STEP2)
Substrate loss Resistive and Capacitive
Y-matrix operation is useful to operate Π configured circuit
© 2021 KIOXIA Corporation. All Rights Reserved. 42
De-embedding (STEP3)
Y(DUT)-Y(OPEN) PAD
De-embedding (STEP4)
After STEP3 operation, transistor and series L and R of unwanted wiring are left.
Z{Y(DUT)-Y(OPEN)}
De-embedding (STEP5)
Unwanted series L and R can be obtained by Z{ Y(SHORT)-Y(OPEN) }
Z{ Y(SHORT)-Y(OPEN)}
Y(SHORT)-Y(OPEN)

De-embedding (STEP6)
STEP4 STEP5
Z{Y(DUT)-Y(OPEN)} Z{ Y(SHORT)-Y(OPEN)}
Z matrix of TRANSISTOR
03 Fab-linked scalable compact model.
- How is the typical model specs ?
- Linking MC model and In-line data.
- How to corporate with factory for high yield.
© 2021 KIOXIA Corporation. All Rights Reserved. 47
What is needed for RF-CMOS compact model ?
Scalable and compact
Lg (Gate Length) and Wf (Finger Length)
NF (Finger Numbers)
Linear: S-parameters > 100GHz
De-embedding: SOLT ? TRL ?
Flicker noise close to the carrier.
ACPR, EVM
Power amplifier
Self Heating
Physical configuration of RF MOSFET
Diffusion resistance Source/Drain
Overlap capacitance : CFGD, CFGS, CBD
Substrate resistance : RBPD/S, RBD/SB
Cold measurement helps to extract layout parasitic. [1]
Good indicator of transistor monitoring.
= −
= +
= −

= −
Source and Back-gate grounded VG=VDD, VD=low, VS=VB=0
Source and Back-gate grounded VG=VD=VS=VB=0
© 2021 KIOXIA Corporation. All Rights Reserved. 50
Scalable parasitic model vs. measurement data [1]
Gate Resistance
Parasitic Capacitances
Two components
Simple relation
Layout dependency works well with many CMOS generations (130nm to 40nm.)
© 2021 KIOXIA Corporation. All Rights Reserved. 51
Q1 Does RG scaling follows classical ohmic-law ?
NfLg
© 2021 KIOXIA Corporation. All Rights Reserved. 52
NO : Gate resistance behaves complex behavior
0
1
2
3
4
5
LV NMOSFET
Scaling dependence of Rg on Wf/Nf
0
1
2
3
4
5
NO : It is NOT unique behavior.


N o
rm al
iz ed
C ap
ac it
an ce
Observation of the RB scaling
0
2
4
6
8
10
12
Wf*NF
N o
rm al
iz ed
R B
NF-1*Wf-1
NFWf Rsh
RF-CMOS modeling summary
NfLgKCGB CGB
NFWf Rsh
110GHz S-parameter model vs measurement.
Existing modeling technology is applicable up to 110GHz
S11 S22
S22 MAG
S22 PHASE
S11 MAG
S11 PHASE
S21 MAG
S21 PHASE
S22 MAG
S22 PHASE
fMAX optimization of RF-NMOSFETs
40nm 2nd GenReduction of overlap capacitance (CGD) can make 40nm
CMOS widely available for IoT applications.
G
167GHz
Dietmar Kissinger “Millimeter- Wave Receiver Concepts for 77GHz Automotive Radar in
Silicon-Germanium Technology”
04 Synchronization of compact model
with latest FAB output.
Ramp-up
High Volume measurement
Fab-link model parameters vs In-line data.
S/D
sheet
resistance
Thickness
Epsilon
directly or via process function completes fab-link model.
Channel
Doping
NDEP
RDSW
Typical,σ
Process
Function
F(Ndep)
How Process function looks like ?
Establish direct link of li-line data with compact model.
Channel
Doping
10
100
1000
10000
1.0E+14 1.0E+15 1.0E+16 1.0E+17 1.0E+18 1.0E+19
Impurity Concentration [cm-3]


statistics {
process {
percent=yes
fMAX fT
Rg Cgd
Cds gm
Fab-link model vs. measurement at 60GHz correlation. [1]
64
Future MOSFET Modeling Challenges
Actual
-35 -30 -25 -20 -15 -10-40 -5
12
14
16
18
20
22
10
24
Thermal Network.
References
2 Franz Sischka, “ICCAP Modeling Handbook”, Keysight Technologies
3 Gennady Gildenblat, “Compact Modeling” Springer (2010)
4 Willy M.C. Sansen , “ ANQLOG DESIGN ESSENTIALS”, Springer
5 C.Enz, “Charge-Based MOS Transistor Modeling: The EKV Model for Low-Power and RF IC Design” Wiley
6 Wladyslaw Grabinski,”Transistor Level Modeling for Analog/RF IC Design”, Springer
7 Yogesh Chauhan,” FinFET Modeling for IC Simulation and Design, 1st Edition using the BSIM-CMG
Standard” Academic Press 2015.
Scientific, 2010.
9 M. Jamal Deen, Tor A. Fjeldly ,” CMOS RF Modeling, Characterization and Applications”World Scientific (2002)
10 Chemning Hu,” Modern Semiconductor Devices for Integrated Circuits 1st Edition”, Prentice Hall; 1 edition (April 1,
2009)
(Latest MOS-AK http://www.mos-ak.org/