Retention Based Low Power DV Challenges in DDR … · Retention Based Low Power DV Challenges in...
Transcript of Retention Based Low Power DV Challenges in DDR … · Retention Based Low Power DV Challenges in...
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Retention Based Low Power DV Challenges in DDR Systems
Subhash Joshi, Sangaiyah Pandithurai , Halavarthi Math Revana Siddesh
Qualcomm, Bangalore, India
© Accellera Systems Initiative 1
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Agenda • DDR System Overview • Low Power Techniques & Verification scope • DV Challenges for DDR Systems • DV Strategies for DDR Systems • Return on Investment [ROI] • Conclusions • Q & A
© Accellera Systems Initiative 2
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DDR System structure • Multiple clients requesting DDR Band-Width • Frequency Bump, Increasing complexity, Phy & MC • Performance requirements and power budget • Shrinking technologies & LP techniques • Multiple PD, MC & DDR-PHY on-off combinations
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DD
DDR A DDR B DDR C DDR D
Client-0
Client-1
Client-2
Client-N
Arbiter/ Scheduler MC DDR
PHY
Multiple Masters Requesting DDR BW
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Low Power Techniques Power Saving:- Active->LP->Partial ON Switches
• Slow wake-up time • Latency proportional to design config. Space • Important regs in config space.
Software based SAVE-RESTORE
• Retention flops/Special low leakage flops • Fast wake-up time • Regs in Config space and Non config space.
Flop retention based SAVE-RESTORE
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LP Verification Scope • Power Architecture
– Power domains - Power modes - Multi-voltage -Isolation strategies & LP Techniques.
• Power-Intent spec(UPF) correctness • Power-Domain interactions • Isolation strategies. • LP Techniques & Design Integrity (PVM)
– Power verification Matrix
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Matrix System Scenarios
Functional Performance Security Clock- Gating Multiple-PD
Power √ √ √ √ √
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DV Challenges for DDR System • Brand-New Design & Retention Space
• DDR-System or timing/Control Intensive Designs • Retention Miss/State-space elements • Incorrect flop in Retention • Coverage Convergence & Sign-off • Ensure Retention list completeness
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Config Space
Non- Config Space
Retention Space
END LESS CHALLENGES
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DV Strategies for DDR System
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PVM Compliant Test-Plan
Feedback DV Vectors
Func, Perf, Security, Power.
Scenario Gen. & Checks
Injection Timestamp
Assert Checks & Capping Bins
Methodology Excellence
Exploring CAD Tools
Regress Opt & Cov. Extraction
Functional & Power in Parallel
Complex & Huge debug
space
Timelines alignment
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DV Strategies Cont.…....
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Phased Approach
Phase I [BRING-UP] • UPF Clean-up, Behavioral power-models and CAD Tool environments. • Config space retention, isolation-values & Data-path scenario.
Phase II [ FEATURE- DIRECTED ] • Design Feature focused. • Assertion checks and Functional Coverage model updates.
Phase III [RANDOM] • All features enabled and disabled randomly • Multiple PC , Frequencies Sweep & DDR Aware traffic
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Config Space
Non- Config Space
Retention Space
DV Strategies Cont.…..
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• Example approach to target Retention space
Power on Reset Write Config Reg
IsolationENInitiate_PC
Check Iso Values
Power Restore
Check Reg Content & Iso values
Simplified power collapse sequence and configuration space retention verification scheme
Functional TP
Performance TP
Power TP Multiple-PD
Firewall-Security TP
Non- configuration space retention verification scheme
I S O
Always-ON Domain
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ROI
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Functional
Performance
Power
Security
Strategic Processes
Better Returns
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ROI Cont.……
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Scenario Injected post –collapse X
Inject scenario -> PC -> Verify/Check √
Functional
State space to save FSM states or
Device state
DDR Device Type change post
collapse.
Information exchange across
multiple Hierarchy.
DRAM De-rating feature
Scenario time-stamp is
important
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ROI Cont.……
Security
Crypto or Firewall
Performance ( Un-noticeable or Silent bugs)
Long-Lived Performance
Impact
Momentary Performance
Impact
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Power-up Event (E_A) PERF
SETTINGS (PERF_A)
Power Collapse &
Restore
PERF Degradation
Event (E_A) REGAIN PERF_A
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ROI Cont.……
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Clock-Gating/ Dynamic Pwr • Un-gated Clocks
to DDR – No functional but power issue.
Lock/MC to Phy interface • Dual handshake
and power down with active handshake
Identifying SW workarounds upfront • Late in the show • Difficult fix &
Product life cycle dependency
MISC • Power intent
checks, • Multiple PD’s • Isolation
miss/Level shifters: Static checks
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Sign-off & Re-use
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Coverage Convergence & Sign-off
• Leverage Functional verification Infrastructure • Readily available assertion & coverage checks • Automatic. Coverage model for Retention list • N flops , Analyzing each flop - state retention of 1 or 0
LP techniques interchangeable usage
• Config vs Retention
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Conclusion
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Complex Control Intensive designs are dreadful to crack
Swing around PVM compliant test-plan
Focus on Test-planning & Perfect execution rather PA bring-up
Key to Success:- Planning functional & Power Aware in ||
ENDLESS CHALLENGES mandate SMART STRATEGIES to witness high ROI
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Q & A
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