resume_SwagataDuttaupload
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EDUCATION GEORGIA INSTITUTE OF TECHNOLOGY GPA 4.0/4.0 Aug ‘16-Dec ‘17 (Expected) Masters in Electrical and Computer Engineering (specializing in VLSI and Digital Systems) Coursework: Adv. VLSI, Phy. Design Automation, Adv. Computer Architecture, Principles of Management Ongoing: Adv. Digital Design with Verilog, Digital Design in Nanometer Nodes, IC fabrication, Adv. Prog. Techniques R.V. COLLEGE OF ENGINEERING, INDIA GPA 9.0/10 Sep‘11-Aug ‘15 Bachelors in Electrical and Electronics Engineering SKILLS Languages and Tools: C, VHDL, Verilog(basic), Java, C++(basic), Python, Cadence Virtuoso, Cadence Encounter, Pspice, Eagle, MATLAB, Minitab. Digital Design Concepts: Timing Analysis, RTL synthesis, Physical Design Algorithms, Layout and Parasitic Extraction, SRAM, DRAM Computer Architecture Concepts: Pipelining, Multicore, Branch Prediction, Virtual Memory, Cache Coherence, Synchronization PROJECTS Design and implementation of an 8 bit SRAM using Cadence Virtuoso Implemented a pipelined system comprising of a 64 byte 6-T SRAM array with peripherals (Sense Amplifier, WL generation, row and column decoder and pre-charge), a capacitive interconnect and a ripple carry adder. Performed analysis of 6T SRAM cell sizing (Access, Pull up and Pull down) to achieve minimal cell area while meeting specifications of read-write margins and cell access time. Created layout for the SRAM array and carried out parasitic extraction. Design and implementation of an 8 bit microcontroller using VHDL The designed 8 bit microcontroller was capable of performing memory operations (LOAD, STORE), Arithmetic operations (ADD, SUB), Logic operations (AND, OR, XOR) and Shift for a predefined ISA (Instruction Set Architecture). Implemented the ALU, Control Logic, Memory and Registers and then unified them into a single high level system. Design of VHDL based home alarm system Designed and Implemented an FSM (Moore Model) based home alarm system with a lock code and indicators. Test bench was designed for verification before implementation on an FPGA board (Basys 2). Implementation of fully associative Caches and classification of cache misses Implemented a fully associative cache and implemented code for classification of cache misses as coherence, compulsory, capacity and conflict misses. Performed a comparative study to understand the behaviour of various cache organizations - Direct Mapped, fully associative and N-way set associative for different cache sizes. Implemented a replacement policy NXLRU (Next to least recently used) and compared the performance of replacement policies.S Designed and implementation of a re-configurable buck converter A software controlled buck converter was designed and implemented using an 8 bit microcontroller. The output voltage and frequency of the converter could be varied within a certain range as per user specifications. Branch Prediction miss rate Implemented code for understanding the dependence of accuracy of hybrid and Not Taken predictors on frequency of occurrence of the branch instructions. PROFESSIONAL EXPERIENCE ITC ILTD Executive (Process Excellence and Data Analytics) Aug ‘15 - May ‘16 Developed a VBA based tool for filtering and analysis of port data for new customer discovery and setting of competitive price points. Provided analytical support to multiple lean six sigma projects aimed at increasing efficiency of various functions at ITC ILTD. PUBLICATIONS Authored an IEEE paper titled "Design and Implementation of Flexible and Re configurable Buck Converters" presented in AICERA-2014. CAMPUS INVOLVEMENT Regular Volunteer for Asha for Education, Georgia Tech Chapter, Atlanta. Best Outgoing Student for RVCE, EEE 2015 batch. [email protected] | Atlanta, Georgia | 404-649-7515 https://www.linkedin.com/in/swagatadutta SWAGATA DUTTA Graduate student seeking internship position or Co-op opportunities
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Transcript of resume_SwagataDuttaupload
EDUCATION GEORGIA INSTITUTE OF TECHNOLOGY GPA 4.0/4.0 Aug ‘16-Dec ‘17 (Expected)
Masters in Electrical and Computer Engineering (specializing in VLSI and Digital Systems)
Coursework: Adv. VLSI, Phy. Design Automation, Adv. Computer Architecture, Principles of Management Ongoing: Adv. Digital Design with Verilog, Digital Design in Nanometer Nodes, IC fabrication, Adv. Prog. Techniques
R.V. COLLEGE OF ENGINEERING, INDIA GPA 9.0/10 Sep‘11-Aug ‘15
Bachelors in Electrical and Electronics Engineering
SKILLS Languages and Tools: C, VHDL, Verilog(basic), Java, C++(basic), Python, Cadence Virtuoso, Cadence Encounter, Pspice, Eagle, MATLAB, Minitab. Digital Design Concepts: Timing Analysis, RTL synthesis, Physical Design Algorithms, Layout and Parasitic Extraction, SRAM, DRAM Computer Architecture Concepts: Pipelining, Multicore, Branch Prediction, Virtual Memory, Cache Coherence, Synchronization
PROJECTS
Design and implementation of an 8 bit SRAM using Cadence Virtuoso
Implemented a pipelined system comprising of a 64 byte 6-T SRAM array with peripherals (Sense Amplifier, WL generation, row and column decoder and pre-charge), a capacitive interconnect and a ripple carry adder.
Performed analysis of 6T SRAM cell sizing (Access, Pull up and Pull down) to achieve minimal cell area while meeting specifications of read-write margins and cell access time.
Created layout for the SRAM array and carried out parasitic extraction.
Design and implementation of an 8 bit microcontroller using VHDL
The designed 8 bit microcontroller was capable of performing memory operations (LOAD, STORE), Arithmetic operations (ADD, SUB), Logic operations (AND, OR, XOR) and Shift for a predefined ISA (Instruction Set Architecture).
Implemented the ALU, Control Logic, Memory and Registers and then unified them into a single high level system.
Design of VHDL based home alarm system
Designed and Implemented an FSM (Moore Model) based home alarm system with a lock code and indicators.
Test bench was designed for verification before implementation on an FPGA board (Basys 2).
Implementation of fully associative Caches and classification of cache misses
Implemented a fully associative cache and implemented code for classification of cache misses as coherence, compulsory, capacity and conflict misses.
Performed a comparative study to understand the behaviour of various cache organizations - Direct Mapped, fully associative and N-way set associative for different cache sizes.
Implemented a replacement policy NXLRU (Next to least recently used) and compared the performance of replacement policies.S
Designed and implementation of a re-configurable buck converter
A software controlled buck converter was designed and implemented using an 8 bit microcontroller.
The output voltage and frequency of the converter could be varied within a certain range as per user specifications.
Branch Prediction miss rate
Implemented code for understanding the dependence of accuracy of hybrid and Not Taken predictors on frequency of occurrence of the branch instructions.
PROFESSIONAL EXPERIENCE ITC ILTD Executive (Process Excellence and Data Analytics) Aug ‘15 - May ‘16 Developed a VBA based tool for filtering and analysis of port data for new customer discovery and setting of competitive price
points.
Provided analytical support to multiple lean six sigma projects aimed at increasing efficiency of various functions at ITC ILTD.
PUBLICATIONS Authored an IEEE paper titled "Design and Implementation of Flexible and Re configurable Buck Converters" presented in
AICERA-2014.
CAMPUS INVOLVEMENT Regular Volunteer for Asha for Education, Georgia Tech Chapter, Atlanta.
Best Outgoing Student for RVCE, EEE 2015 batch.
[email protected] | Atlanta, Georgia | 404-649-7515 |https://www.linkedin.com/in/swagatadutta https://www.linkedin.com/in/swagatadutta
SWAGATA DUTTA
Graduate student seeking internship position or Co-op opportunities
