Supratim Das D-17, Acharya Niketan Market, Mayur Vihar Phase-1, Delhi - 110091

Email: supratimofficio@gmail.com | Mobile: +91-8750435228 | Linkedin profile: http://in.linkedin.com/pub/supratim-das/48/756/669

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Core Competencies

Func Modelling

RTL design

Verification

Firmware Design

Programming Languages

C

C++

Verilog

Shell scripting

Python

Matlab

Operating System & Tools

Linux

GDB

Xilinx Vivado

Incisive suite

DC

Catapult HLS

[1] Srivastava, S; Hashmi, M; Das. S;

Barua, D, “Real-Time blind spectrum sensing using USRP”, Circuits and Systems (ISCAS), 2015 IEEE International Symposium on Circuits and Systems.

[2] Das, S; Singh A; Singh S P; Kumar A, “A low overhead dynamic memory management system for constrained memory embedded systems”, (INDIACom) 2015.

[1] Dr. Kaushik Saha, Director (Advanced R&D group), Samsung R&D Institute India – Delhi [kasha_2000@yahoo.com]

[2] Mr. Surinder Pal Singh, Principle Engineer (Advanced Systems Technology Group), STMicroelectronics – G. Noida [surinder-pal.singh@st.com]

TECHNICAL PROFICIENCY

PUBLICATIONS

An IC Design professional with over two years of experience in complex IP development, with

good hands on experience in activities ranging from functional modeling, RTL design and

verification. Keen to learn new tools, technologies and methodologies. Proven track record to

prioritize mission critical tasks and deliver quality results within the specified timelines.

Qualification University/Board Year Performance

M.Tech ECE with specialization

in VLSI and Embedded Systems

Indraprastha Institute of Information

Technology – Delhi (IIITD)

2014 9.65 CGPA

B.Tech CSE West Bengal University of Technology 2012 8.7 CGPA

AISSCE (class XII) C.B.S.E 2007 83.4%

ICSE (class X) C.I.S.S.C.E 2005 80.6%

Samsung R&D Institute India – Delhi (Noida) Engineer, October 2014 – Present Working as a RTL design engineer with the SoC team, primarily involved in IP design and

integration activities of Samsung smart TV SoCs. I was a key player in the following: o Designed re-usable fixed point math library in C and verilog which was used

extensively as a key component in multiple channel IP development activities. o Single handedly designed and verified DVB-T2 demapper IP in a very strict timeframe. o Actively involved in training sessions of C, Linux, GDB for hardware designers. o Recognized as a reliable design engineer with sound knowledge in modeling as well as

RTL design, with ability to meet critical project deadlines and delivering quality work.

STMicroelectronics India Pvt. Ltd (Greater Noida) Intern, July 2013 – June 2014 Worked with the Advanced Systems Technologies (AST) group on various research based

problems. Made significant contribution towards extending Zigbee IP support in Contiki by implementing a major portion of the security stack, and a new embedded memory management system, for STM32W series MCU from ST.

SUMMARY OF EXPERIENCE AND EXPERTISE

PROFFESSIONAL EXPERIENCE

Soft Demapper for DVB-T2 and DVB-C2 standard using Square-Root M algorithm [SRI-Delhi] – High level modeling, performance estimation, RTL development and verification of soft decision demapper for DVB-T2 and DVB-C2 standard, supporting till 4096QAM.

Analysis and implementation of Zigbee IP on Contiki OS [STMicroelectronics] – Implemented PANA, EAP and EAP-TLS protocols as a part of the Zigbee IP stack for STM32W platform running Contiki.

High Speed and Low Area implementation of AES-128 on Spartan 6 FPGA [IIITD] – As a course project in the advanced FPGA design course designed a low area, high speed AES-128 core in Verilog, and interfaced it with microblaze softcore processor, facilitating realtime encryption/decryption.

Implementation of Column Associative cache in SimpleScalar [IIITD] – As a course project implemented the column associative cache scheme in the Simple Scalar simulator.

PROJECTS

Dynamic Memory Management for Resource Constrained Next Generation Wireless Sensor Nodes: Explored dynamic memory management mechanisms for severely resource constrained embedded devices and proposed two new designs particularly targeted towards such platforms. [https://repository.iiitd.edu.in/jspui/handle/123456789/144]

M.TECH THESIS

Awarded Employee of Quarter Award – Q2 [2015] by MD, Samsung R&D Institute – Delhi

Science Week Champion – 2006, Birla Public School, Pilani

HONORS & AWARDS

REFERENCES