Gaurav Saxena techgaurav157@gmail.com, 9680513442

Bangalore-560041, Karnataka

Career Objective

A challenging and innovative career in Analog Layout Design, which will allow me to contribute for the advancement of technology for the next generation.

Core Competency

Good understanding of full custom IC design flow.

Good understanding of MOS theory.

Thorough knowledge of IC fabrication process/semiconductor manufacturing.

Experienced the different types of errors occurred during DRC.

Experienced the different types of errors occurred during LVS verification with some tricks of fixing LVS.

Knowledge of DFM rules.

Hands on experience in doing analog layout including device matching techniques.

Layout drawing according to the constraints and experienced custom layout design.

Hands-on experience of layout in 180nm, 90nm, and 28nm technology process.

Familiar with EDA tools from Mentor Graphics Pyxis- schematic and layout editor, Calibre

tools(LVS, DRC and PEX).

Education DetailsAdvanced Diploma in ASIC Design - Full Custom 2017

RV-VLSI Design CenterBachelor Degree in Electronics and Communication 2016

Career Point University, with 8.1 CGPAPUC / 12th 2011

Central academy school, with 56 %SSLC 2009

Central academy school, with 60 %

Domain Specific ProjectRV-VLSI Design centreGraduate Trainee Engineer Oct-2016 to Nov-2016Standard CellsDescription

Standard cells were made on 90 nm, 28 nm technologies. For the different drive strengths same

cells made on the same technology.

Tools

IC studio, Mentor Calibre

Challenges

To make the optimized layout, the floor planning was the challenge. Placing the metal pins on the grids for the connection. For 28nm technology, a center of poly must be on vertical grid and center of contact should be on

horizontal or vertical grid. So with all these, minimizing the area was challenge.

RV-VLSI Design centreGraduate Trainee Engineer Nov-2016 to Nov-2016Op-Amp layout

Description

The operational amplifier layout was made to understand about the centroid matching and

device matching techniques in analog layout.

Tools

IC studio, Mentor Calibre

Challenges

Centroid matching of the transistors was the challenge. Floor planning of all the transistors with the minimum area was challenge.

The metal routing between the transistors to and from ports was challenging.

RV-VLSI Design centreGraduate Trainee Engineer Nov-2016 to Jan-2017Layout design of memory cells

Description

The layout of different blocks of SRAM on 28 nm technology, The different blocks are pre-charge, pre-decoders, control unit, sense amplifier, Dout, Din, scan block, final decoder. This project is in process and will be completed in January, 2017.

Tools

IC studio, Mentor Calibre

Challenges

The floor plan was the extremely good challenge that I faced in most of the blocks of SRAM and at last I come with a good floor plan with minimum area.

Pin placement of input and output pins according to the communication of pins to and from the transistors was the challenge according to the given constraints.

Metal routing of all the transistors from or to the input and output pins and also in between all the

transistors.

B.E / B.Tech Academic ProjectCareer Point University16-bit ALUDescription

It can perform logical as well as arithmetic operations over 16-bit operands.

Tools

Language - Verilog HDL. Software - Questasim

Challenges

It was challenging to build the logic of the design.