Research Article Design Multipurpose Circuits with Minimum ...reversible gate, namely, IG gate, is...

Research ArticleDesign Multipurpose Circuits with Minimum GarbageOutputs Using CMVMIN Gate

Bahram Dehghan

Young Researchers and Elite Club Sarvestan Branch Islamic Azad University Sarvestan Iran

Correspondence should be addressed to Bahram Dehghan bahramdehghan1gmailcom

Received 26 November 2013 Accepted 16 January 2014 Published 26 February 2014

Academic Editors Z Liu and H Tan

Copyright copy 2014 Bahram Dehghan This is an open access article distributed under the Creative Commons Attribution Licensewhich permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited

Quantum-dot cellular automata (QCA) suggest an emerging computing paradigm for nanotechnology The QCA offers novelapproach in electronics for information processing and communication QCAhave recently become the focus of interest in the fieldof low power nanocomputing and nanotechnologyThe fundamental logic elements of this technology are the majority voter (MV)and the inverter (INV)This paper presents a novel designwith less garbage output andminimumquantum cost in nanotechnologyIn the paperwe showhow to createmultipurpose reversible gates By development of suitable gates in logic circuits as an example wecan combineMFAandHS in one design usingCMVMINgateWe offerCMVMINgate implementations to be used inmultipurposecircuit We can produce concurrent half addersubtractor and one bit comparator in one design using reversible logic gates andCMVMIN gates Also a 2 times 4 decoder from recent architecture has been shown independently We investigate the result of theproposed design using truth table A significant improvement in quality of the calculated parameters and variety of required outputshas been achieved

1 Introduction

This heat dissipation extremely reduces the performance andlifetime of the circuits The solution is to use revolutionarytechnology which enables extremely low power consumptionand heat waste in computing [1] Reversible logic gates areextensively known to be compatible with future computingtechnologies which approximately dissipate zero heat [2]Reversible are the circuits or the gates that have the samenumber of inputs and outputs and have one-to-onemappingsbetween vectors of inputs and outputs thus the vector of theinput states can be uniquely reconstructed from the vector ofthe output states [3]

The QCA (Quantum-dot cellular automata) are consid-ered to be the promising technology for future generationICs that overcome the limitations of CMOSThe fundamentalunit of QCA based design is the 3-inputmajority gate (major-ity voter MV) and the inverter The wide acceptance of QCAin logic design attracts researchers to explore new universalgate structures targeting cost effective realization [4] Existingsynthesis tools do notmake efficient use ofMV in technologymapping for synthesis of logic designs Even for arithmetic

circuits in which there should be perfect matches for theMVthe synthesis tools rarely find any matches [5]

This satisfies the requirement of optimum logic gates aswell as minimum number of garbage outputs in an energyefficient design [6] We illustrate CMVMIN gate with the tar-get to reduce the number of logic gates and garbage outputsIn this work we propose the use of CMVMIN gate as a basicofmultipurpose circuitWe can construct othermultipurposecircuits similarly

2 Fundamental Reversible Gates

Because of their easiness and quantum realization cost thereare design approaches and tools that incorporate themseparately or in combination with each other The quantumcost of a reversible circuit is the number of primary quantumgates required to implement a circuit [7] Any reversiblegate performs the permutation of its input patterns only andrealizes the functions that are reversible If a reversible gatehas 119896 inputs and therefore 119896 outputs then we call it a 119896 lowast 119896reversible gate [8] We demonstrate the application of thereversible gate to designmultipurpose circuit Firstly in order

Hindawi Publishing CorporationChinese Journal of EngineeringVolume 2014 Article ID 532121 7 pageshttpdxdoiorg1011552014532121

2 Chinese Journal of Engineering

FG

A

B

P = A

Q = A oplus B

Figure 1 Feynman gate (FG)

PG

A

B

C

P = A

Q = A oplus B

R = AB oplus C

Figure 2 Peres gate (PG)

to derive the results we review the characterization of FG andPG gates In Feynman gate one of the input bits act as controlsignal (119860) That is if 119860 = 0 then the output 119876 follows theinput 119861 If 119860 = 1 then the input 119861 is flipped at the output119876 Because of this it is called controlled NOT (1-NOT) andalso called quantumXORbecause of its popularity in the fieldof quantum computing [9] Feynman gate (CNOT gate) isshown in Figure 1

A 3lowast 3 one through reversible gate called Peres gate (PG)is introduced Figure 2 shows the Peres gate as the reversiblegate

Also the block diagram of RUG is shown in Figure 3Since use of this universal function helps the realization ofXNORXOR easily the RUG can enable low cost realizationof many other complex Boolean functions [6] Anotherreversible gate namely IG gate is presented in Figure 4 [8]The application of these gates is described in the followingsections

3 The QCA Basics

The QCA (Quantum-dot cellular automata) are consideredto be a promising technology to meet such a design target[6] QCA have significant advantages in terms of powerdissipation as they do not have to dissipate all their signalenergy hence considered one of the promising technologiesto achieve the thermodynamic limit of computation [10] AQCA cell consists of two electrons positioned at oppositecorners owing to coulombic repulsion so the polarizationstates of 119875 = minus1 and 119875 = +1 can be represented by twostable configurations of a pair of electrons the correspondinglogic values of ldquo0rdquo and ldquo1rdquo also are represented in Figure 5

RUG

A

B

C

P = AB + BC + CA

Q = AB + A998400C998400

R = BC998400+ B

998400C

Figure 3 The reversible universal gate (RUG)

IG

A

B

C

D

P = A

Q = A oplus B

R = AB oplus C

S = BD oplus B998400(A oplus D)

Figure 4 4 lowast 4 reversible gate (IG)

Binary ldquo0rdquo Binary ldquo1rdquo

Figure 5 Quantum cellular automata [9]

A

B

C

F

Figure 6 QCA majority gate [12]

Chinese Journal of Engineering 3

A

B

C

F1

F2

(a) Gate structure 1

A

B

C

F1

F2

(b) Gate structure 2

A

B

C

F1

F2

(c) Symbol

Figure 7 Gate structures and symbol of CMVMIN gate [12]

RUG

0

B

C

Carry = BC

Sum = B oplus C

C998400

Figure 8 RUG as half adder

1RUG FG

FG

0

BC998400

C

Carry = BC

Borrow = B998400C

(BC)998400

Diff = Sum = B oplus C

Figure 9 Concurrent half addersubtractor circuit using RUG andFG

Table 1 Truth table of CMVMIN gate

119860 119861 119862 1198651

1198652

0 0 0 1 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 0 1

A majority gate with the logic function of MV (119860 119861 119862) =119860119861 + 119860119862 + 119861119862 is composed of five cells By setting oneof the inputs of this gate permanently to 0 or 1 AND andOR functions will be formed in QCA [11] We review NNIgate as the basic logic element for QCA based designs This3-input gate realizes the function 119865 = NNI(119860 119861 119862) =maj(1198601015840 119861 1198621015840) = 1198601015840119861 + 1198611198621015840 + 11986210158401198601015840

AQCA circuit can be efficiently built usingmajority gatesand inverters QCA majority gate is shown in Figure 6

4 Coupled Majority-Minority Gate

In QCA coplanar wire crossings are one of the very ele-gant features of this new low power computing paradigm


0

0

IGA

B B

Carry = AB

Borrow = A998400B

Diff = Sum = A oplus B

Figure 10 Concurrent half addersubtractor circuit using IG

1

A

B

AB + A998400B998400

1

0

(AB)998400

AB

A + B

(A + B)998400

A998400B + AB

998400

Figure 11 Generating 6 symmetric functions using CMVMIN gate

However these need two types of cells and are known to beneither easy to fabricate nor very robust In QCA based logicdesign the utmost necessity is to ensure least number of wirecrossings due to its single layer restriction [11]

The coupled majority-minority (CMVMIN) QCA gatestructure simultaneously realizes 3-input minority logic(MIN) and majority voter (MV) in its 2 outputs 119865

1and 119865

2

(Figure 7) The 1198651= 11986010158401198611015840+ 11986110158401198621015840+ 11986210158401198601015840 is the complement

of 1198652= 119860119861 + 119861119862 + 119862119860 This gate is also realizable with a

3times3 tile structureThe truth table of CMVMIN gate is shownin Table 1 This gate can function as an AND-NAND gate(1198652= 119860119861 and 119865

1= (119860119861)

1015840) when input 119862 is set to logic 0Similarly it can simultaneously realize OR (119865

2= 119860 + 119861) and

NOR (1198651= (119860 + 119861)

1015840) functions when 119862 is set to 1

Two structures are shown in Figures 7(a) and 7(b) Thesymbol of this gate is illustrated in Figure 7(c) [12]

5 Design Multipurpose Circuit

The major consideration in implementing the proposedmultipurpose circuit is to enhance its speed as much aspossible [13] We could achieve some other various statesconfigurations of logic circuits in quantum information andquantum computation [14]

Firstly the design capability of RUG will be evaluatedin implementing multipurpose circuits If 119860 = 0 then theoutputs will be achieved according to Figure 8 One andthree outputs represent the carry and sum of a half adderrespectively Results of RUG are shown in Figure 8

Now we propose half addersubtractor architecture inone design using RUG and two Feynman gates The design

1

1

0

FGFG

A

B

AB + A998400B998400

(AB)998400

AB

A + B

(A + B)998400

A998400B + AB

998400

Figure 12 Generating 6 symmetric functions using CMVMIN andFeynman gate

1

1

0

FGFG

A

B

AB + A998400B998400

(AB)998400

AB

A + B

(A + B)998400

A998400B + AB

998400


Ai BiPi

Ci

Si

G998400i

Figure 14 MFA (modified full adder) [15]

Table 2 Evaluation of the proposed circuit

No of gates Garbage outputsProposed circuit 3 1

of a mentioned circuit is presented which is implementedwith minimum gates and garbage outputs Results are shownin Figure 9 Table 2 shows the evaluation of the mentionedcircuit


1

1

0

0

FG

FG

PG

1

A

A

B

B

C

AB + A998400B998400

AB

A + B

(A + B)998400

A998400B + AB

998400

G998400= (AB)

998400

P

S

Diff = A oplus B

Borr = A998400B

Figure 15 Multipurpose circuit (MFA and HS)

1 1

0

0

0

PG

A

B

B

AB + A998400B998400 (A = B)

(AB)998400

A + B

(A + B)998400

A998400B + AB

998400

Borr = A998400B (A lt B)

AB998400 (A gt B)

A998400+ B

Carry = AB


Figure 16 Multipurpose circuit using CMVMIN gate and Peres gate (HS HA and OBC)

A B

= A998400B998400

= A998400B

= AB998400

= AB

F1

F2

F3

F4

Figure 17 2 times 4 decoder



On the other hand we can demonstrate our goal withIG gate that its obtained result has better performance thanprevious structure If inputs 119862 and 119863 are equal to zero thenthe circuit will be depicted as follows Hence the mentionedcircuit requires one reversible gate (IG gate) and produces onegarbage output The architecture of this gate is demonstratedin Figure 10 Table 3 shows the evaluation of the mentionedcircuit

Now let us consider a function of conventional gatesinvestigated by truth table We realized the EXOR andEXNORgates with the following equations Table 4 shows theoperation of the logic circuit topics We have

1198651oplus 1198653= 1198652oplus 1198654= EXOR

1198651oplus 1198652= 1198653oplus 1198654= EXNOR

(1)


0

1 1

0

0

0

PG

FGA

B

= A998400B998400

= A998400B

= AB998400

= AB

F1

F2

F3

F4

Figure 18 Comprehensive multipurpose circuit using CMVMIN gate and Peres gate (HS HA OBC and 2 times 4 decoder)

Table 4 Truth table of conventional gate

119860 119861 1198651= AND 119865

2= NOR 119865

3= OR 119865

4= NAND

0 0 0 1 0 10 1 0 0 1 11 0 0 0 1 11 1 1 0 1 0



A symmetric function means a Boolean function invariantto the permutation of any of its input variables [3] Figure 11points to the fact that only three CMVMIN gates are neededto realize all such 6 symmetric functions

According to Table 4 by combining CMVMIN gate andFeynman gate we can generate EXOR and EXNOR gatesFigures 12 and 13 show a combination of CMVMIN gates andFG gates

Adder is profoundly used in the generic computerbecause it is very noticeable for adding data in the processorTheMCLA [15] uses the modified full adder (MFA) as shownin Figure 14 The major consideration in implementing theproposed multipurpose circuit is to enhance its speed asmuch as possible On the other hand the equations of borrowand difference for half subtractor are as follows

Borr = 1198601015840119861 Diff = 119860 oplus 119861 (2)

Figure 15 is obtained by combining the two mentioned cir-cuits Table 5 shows the evaluation of the proposed design

We can produce half subtractor half adder and one bitcomparator in one design using Peres gate and CMVMINgates The proposed circuit of Figure 16 is evaluated in termsof number of reversible gates used and garbage outputsproduced

Table 6 shows the evaluation of the proposed designThe following circuit has another application that is as

a 2 times 4 decoder Decoder is significant component and it isutilized in many logical and functional circuits A decoder isa multiple-input multiple-output logic circuit that convertscoded inputs into coded outputs where the input and output



Table 7 Evaluation of the comprehensive multipurpose circuit


codes are different Figure 17 shows a 2 times 4 decoder Thebehaviour of mentioned conventional circuit is defined asfollows

1198651= 11986010158401198611015840 119865

2= 1198601015840119861

1198653= 1198601198611015840 119865

4= 119860119861

(3)

Hence another proposed circuit implementation usingadditional Feynman gate is presented in Figure 18

Figure 18 has been utilized to implement new aspect fromavailable circuit Table 7 shows the evaluation of the proposeddesign

We see that the mentioned circuit performs significantlyappropriate in terms of the number of gates and the numberof garbage outputs As we have seen this multipurposecircuit produces only one garbage output Therefore we caninfer that the proposed structure will successfully implementmentioned multipurpose circuit

6 Conclusion

Reversible logic has had promising interest in the recent pastdue to its less heat dissipating characteristics An importantpurpose in our designs was to ensure that the designs arepractical and usableWepresent a novel design for concurrenthalf addersubtractor scheme using RUG and two Feynmangates However these fundamental results motivate realiza-tions of the same circuit using IG gate with better perfor-mance One aim of this paper is to evaluate the CMVMINgate in the available logic circuits with capable versatilityand minimum garbage outputs susceptibility Also resultsare verified by the truth table In addition the last design isproposed for the multipurpose circuits in terms of garbage


output and gate count that was not ever seen It clearlyshows the capabilities and characteristics of CMVMIN gatefor designing circuits Also we can generalize this concept tothe other families of reversible gatesThe experimental resultsillustrate that reversible logic is less likely to exhibit redundantlogic than irreversible logic

Conflict of Interests

The author declares that there is no conflict of interestsregarding the publication of this paper

References

[1] B Dehghan ldquoDesign of asynchronous sequential circuits usingreversible logic gatesrdquo International Journal of Engineering andTechnology vol 4 no 4 pp 213ndash219 2012

[2] B Dehghan ldquoSurvey the inverse property of quantum gatesfor concurrent error detectionrdquo Journal of Basic and AppliedScientific Research vol 3 no 2 pp 603ndash608 2013

[3] P K Bhattacharjee ldquoUse of symmetric functions designed byQCA gates for next generation ICrdquo International Journal ofComputerTheory and Engineering vol 2 no 2 pp 211ndash217 2010

[4] M Dalui B Sen and B K Sikdar ldquoFault tolerant QCAlogic designwith coupledmajority-minority gaterdquo InternationalJournal of Computer Applications vol 1 no 29 pp 81ndash87 2010

[5] M Momenzadeh J Huang M B Tahoori and F LombardildquoCharacterization test and logic synthesis of and-or-inverter(AOI) gate design forQCA implementationrdquo IEEE Transactionson Computer-Aided Design of Integrated Circuits and Systemsvol 24 no 12 pp 1881ndash1892 2005

[6] B Sen T Adak A S Anand and B K Sikdar ldquoSynthesisof reversible universal QCA gate structure for energy efficientdigital designrdquo in Proceedings of the IEEE Region 10 ConferenceTrends and Development in Converging Technology Towards2020 pp 806ndash810 November 2011

[7] B Dehghan ldquoGenerating new reversible logic gates with ladderblock structure for emerging nanocircuitsrdquo Journal of Basic andApplied Scientific Research vol 3 no 1 pp 610ndash615 2013

[8] M S Islam M M Rahman Z Begum M Z Hafiz and A AlMahmud ldquoSynthesis of fault tolerant reversible logic circuitsrdquo inProceedings of the IEEE International Conference on Circuits andSystems April 2009 httparxivorgftparxivpapers100810083340pdf

[9] X S Christina and M S Justine ldquoRealization of BCD adderusing reversible logicrdquo International Journal of ComputerTheoryand Engineering vol 2 no 3 pp 333ndash337 2010

[10] H Thapliyal and N Ranganathan ldquoConservative QCA gate(CQCA) for designing concurrently testable molecular QCAcircuitsrdquo in Proceedings of the 22nd International Conference onVLSI Design pp 511ndash516 January 2009

[11] R Zhou X Xia F Wang Y Shi and H Liaoa ldquoLogiccircuit design of 2-4 decoder using quantum cellular automatardquoJournal of Computational Information Systems vol 8 no 8 pp3463ndash3469 2012

[12] S Ditti KMahata PMitra and B K Sikdar ldquoDefect character-ization in coupled majority-minority QCA gaterdquo in Proceedingsof the 4th International Conference on Design amp Technology ofIntegrated Systems in Nanoscal Era pp 293ndash298 IEEE April2009

[13] B Dehghan ldquoCharacterization and logic synthesis of URGgate for designing multipurpose circuitsrdquo European Journal ofScientific Research vol 105 no 1 pp 117ndash125 2013

[14] B Dehghan and A A Baziar ldquoOptimized methodology forrealization of logic circuits using QCA gatesrdquo InternationalJournal of Advanced Research in Computer Science and SoftwareEngineering vol 3 no 3 pp 58ndash61 2013

[15] Y-T Pai and Y-K Chen ldquoThe fastest carry lookahead adderrdquoin Proceedings of the 2nd IEEE International Workshop onElectronic Design Test and Applications pp 434ndash436 January2004

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Active and Passive Electronic Components

Control Scienceand Engineering

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Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design



Shock and Vibration


Civil EngineeringAdvances in

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Journal of

Advances inOptoElectronics


Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of


Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014


Chemical EngineeringInternational Journal of Antennas and

Propagation




Navigation and Observation



DistributedSensor Networks



FG

A

B

P = A

Q = A oplus B

Figure 1 Feynman gate (FG)

PG

A

B

C

P = A

Q = A oplus B

R = AB oplus C

Figure 2 Peres gate (PG)

to derive the results we review the characterization of FG andPG gates In Feynman gate one of the input bits act as controlsignal (119860) That is if 119860 = 0 then the output 119876 follows theinput 119861 If 119860 = 1 then the input 119861 is flipped at the output119876 Because of this it is called controlled NOT (1-NOT) andalso called quantumXORbecause of its popularity in the fieldof quantum computing [9] Feynman gate (CNOT gate) isshown in Figure 1

A 3lowast 3 one through reversible gate called Peres gate (PG)is introduced Figure 2 shows the Peres gate as the reversiblegate

Also the block diagram of RUG is shown in Figure 3Since use of this universal function helps the realization ofXNORXOR easily the RUG can enable low cost realizationof many other complex Boolean functions [6] Anotherreversible gate namely IG gate is presented in Figure 4 [8]The application of these gates is described in the followingsections

3 The QCA Basics

The QCA (Quantum-dot cellular automata) are consideredto be a promising technology to meet such a design target[6] QCA have significant advantages in terms of powerdissipation as they do not have to dissipate all their signalenergy hence considered one of the promising technologiesto achieve the thermodynamic limit of computation [10] AQCA cell consists of two electrons positioned at oppositecorners owing to coulombic repulsion so the polarizationstates of 119875 = minus1 and 119875 = +1 can be represented by twostable configurations of a pair of electrons the correspondinglogic values of ldquo0rdquo and ldquo1rdquo also are represented in Figure 5

RUG

A

B

C

P = AB + BC + CA

Q = AB + A998400C998400

R = BC998400+ B

998400C

Figure 3 The reversible universal gate (RUG)

IG

A

B

C

D

P = A

Q = A oplus B

R = AB oplus C

S = BD oplus B998400(A oplus D)

Figure 4 4 lowast 4 reversible gate (IG)

Binary ldquo0rdquo Binary ldquo1rdquo

Figure 5 Quantum cellular automata [9]

A

B

C

F

Figure 6 QCA majority gate [12]


A

B

C

F1

F2


A

B

C

F1

F2


A

B

C

F1

F2

(c) Symbol


RUG

0

B

C

Carry = BC

Sum = B oplus C

C998400


1RUG FG

FG

0

BC998400

C

Carry = BC

Borrow = B998400C

(BC)998400




119860 119861 119862 1198651

1198652

0 0 0 1 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 0 1






0

0

IGA

B B

Carry = AB

Borrow = A998400B



1

A

B

AB + A998400B998400

1

0

(AB)998400

AB

A + B

(A + B)998400

A998400B + AB

998400




1and 119865

2




1= (119860119861)


2= 119860 + 119861) and

NOR (1198651= (119860 + 119861)







1

1

0

FGFG

A

B

AB + A998400B998400

(AB)998400

AB

A + B

(A + B)998400

A998400B + AB

998400


1

1

0

FGFG

A

B

AB + A998400B998400

(AB)998400

AB

A + B

(A + B)998400

A998400B + AB

998400


Ai BiPi

Ci

Si

G998400i






1

1

0

0

FG

FG

PG

1

A

A

B

B

C

AB + A998400B998400

AB

A + B

(A + B)998400

A998400B + AB

998400

G998400= (AB)

998400

P

S

Diff = A oplus B

Borr = A998400B


1 1

0

0

0

PG

A

B

B

AB + A998400B998400 (A = B)

(AB)998400

A + B

(A + B)998400

A998400B + AB

998400


AB998400 (A gt B)

A998400+ B

Carry = AB



A B

= A998400B998400

= A998400B

= AB998400

= AB

F1

F2

F3

F4






1198651oplus 1198653= 1198652oplus 1198654= EXOR


(1)


0

1 1

0

0

0

PG

FGA

B

= A998400B998400

= A998400B

= AB998400

= AB

F1

F2

F3

F4



119860 119861 1198651= AND 119865

2= NOR 119865

3= OR 119865

4= NAND

0 0 0 1 0 10 1 0 0 1 11 0 0 0 1 11 1 1 0 1 0






Borr = 1198601015840119861 Diff = 119860 oplus 119861 (2)










1198651= 11986010158401198611015840 119865

2= 1198601015840119861

1198653= 1198601198611015840 119865

4= 119860119861

(3)




6 Conclusion






References


















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










A

B

C

F1

F2


A

B

C

F1

F2


A

B

C

F1

F2

(c) Symbol


RUG

0

B

C

Carry = BC

Sum = B oplus C

C998400


1RUG FG

FG

0

BC998400

C

Carry = BC

Borrow = B998400C

(BC)998400




119860 119861 119862 1198651

1198652

0 0 0 1 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 0 1






0

0

IGA

B B

Carry = AB

Borrow = A998400B



1

A

B

AB + A998400B998400

1

0

(AB)998400

AB

A + B

(A + B)998400

A998400B + AB

998400




1and 119865

2




1= (119860119861)


2= 119860 + 119861) and

NOR (1198651= (119860 + 119861)







1

1

0

FGFG

A

B

AB + A998400B998400

(AB)998400

AB

A + B

(A + B)998400

A998400B + AB

998400


1

1

0

FGFG

A

B

AB + A998400B998400

(AB)998400

AB

A + B

(A + B)998400

A998400B + AB

998400


Ai BiPi

Ci

Si

G998400i






1

1

0

0

FG

FG

PG

1

A

A

B

B

C

AB + A998400B998400

AB

A + B

(A + B)998400

A998400B + AB

998400

G998400= (AB)

998400

P

S

Diff = A oplus B

Borr = A998400B


1 1

0

0

0

PG

A

B

B

AB + A998400B998400 (A = B)

(AB)998400

A + B

(A + B)998400

A998400B + AB

998400


AB998400 (A gt B)

A998400+ B

Carry = AB



A B

= A998400B998400

= A998400B

= AB998400

= AB

F1

F2

F3

F4






1198651oplus 1198653= 1198652oplus 1198654= EXOR


(1)


0

1 1

0

0

0

PG

FGA

B

= A998400B998400

= A998400B

= AB998400

= AB

F1

F2

F3

F4



119860 119861 1198651= AND 119865

2= NOR 119865

3= OR 119865

4= NAND

0 0 0 1 0 10 1 0 0 1 11 0 0 0 1 11 1 1 0 1 0






Borr = 1198601015840119861 Diff = 119860 oplus 119861 (2)










1198651= 11986010158401198611015840 119865

2= 1198601015840119861

1198653= 1198601198611015840 119865

4= 119860119861

(3)




6 Conclusion






References


















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










0

0

IGA

B B

Carry = AB

Borrow = A998400B



1

A

B

AB + A998400B998400

1

0

(AB)998400

AB

A + B

(A + B)998400

A998400B + AB

998400




1and 119865

2




1= (119860119861)


2= 119860 + 119861) and

NOR (1198651= (119860 + 119861)







1

1

0

FGFG

A

B

AB + A998400B998400

(AB)998400

AB

A + B

(A + B)998400

A998400B + AB

998400


1

1

0

FGFG

A

B

AB + A998400B998400

(AB)998400

AB

A + B

(A + B)998400

A998400B + AB

998400


Ai BiPi

Ci

Si

G998400i






1

1

0

0

FG

FG

PG

1

A

A

B

B

C

AB + A998400B998400

AB

A + B

(A + B)998400

A998400B + AB

998400

G998400= (AB)

998400

P

S

Diff = A oplus B

Borr = A998400B


1 1

0

0

0

PG

A

B

B

AB + A998400B998400 (A = B)

(AB)998400

A + B

(A + B)998400

A998400B + AB

998400


AB998400 (A gt B)

A998400+ B

Carry = AB



A B

= A998400B998400

= A998400B

= AB998400

= AB

F1

F2

F3

F4






1198651oplus 1198653= 1198652oplus 1198654= EXOR


(1)


0

1 1

0

0

0

PG

FGA

B

= A998400B998400

= A998400B

= AB998400

= AB

F1

F2

F3

F4



119860 119861 1198651= AND 119865

2= NOR 119865

3= OR 119865

4= NAND

0 0 0 1 0 10 1 0 0 1 11 0 0 0 1 11 1 1 0 1 0






Borr = 1198601015840119861 Diff = 119860 oplus 119861 (2)










1198651= 11986010158401198611015840 119865

2= 1198601015840119861

1198653= 1198601198611015840 119865

4= 119860119861

(3)




6 Conclusion






References


















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










1

1

0

0

FG

FG

PG

1

A

A

B

B

C

AB + A998400B998400

AB

A + B

(A + B)998400

A998400B + AB

998400

G998400= (AB)

998400

P

S

Diff = A oplus B

Borr = A998400B


1 1

0

0

0

PG

A

B

B

AB + A998400B998400 (A = B)

(AB)998400

A + B

(A + B)998400

A998400B + AB

998400


AB998400 (A gt B)

A998400+ B

Carry = AB



A B

= A998400B998400

= A998400B

= AB998400

= AB

F1

F2

F3

F4






1198651oplus 1198653= 1198652oplus 1198654= EXOR


(1)


0

1 1

0

0

0

PG

FGA

B

= A998400B998400

= A998400B

= AB998400

= AB

F1

F2

F3

F4



119860 119861 1198651= AND 119865

2= NOR 119865

3= OR 119865

4= NAND

0 0 0 1 0 10 1 0 0 1 11 0 0 0 1 11 1 1 0 1 0






Borr = 1198601015840119861 Diff = 119860 oplus 119861 (2)










1198651= 11986010158401198611015840 119865

2= 1198601015840119861

1198653= 1198601198611015840 119865

4= 119860119861

(3)




6 Conclusion






References


















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation










0

1 1

0

0

0

PG

FGA

B

= A998400B998400

= A998400B

= AB998400

= AB

F1

F2

F3

F4



119860 119861 1198651= AND 119865

2= NOR 119865

3= OR 119865

4= NAND

0 0 0 1 0 10 1 0 0 1 11 0 0 0 1 11 1 1 0 1 0






Borr = 1198601015840119861 Diff = 119860 oplus 119861 (2)










1198651= 11986010158401198611015840 119865

2= 1198601015840119861

1198653= 1198601198611015840 119865

4= 119860119861

(3)




6 Conclusion






References


















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation













References


















RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation











RoboticsJournal of





Journal of



RotatingMachinery





VLSI Design



Shock and Vibration







Journal of



Volume 2014


SensorsJournal of





Propagation









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