Hindawi Publishing CorporationVLSI DesignVolume 2013 Article ID 967370 9 pageshttpdxdoiorg1011552013967370

Research ArticleArchitecture and Implementation of Fading Compensation forDynamic Spectrum Access Wireless Communication Systems

Masahide Hatanaka Toru Homemoto and Takao Onoye

Department of Information Systems Engineering Osaka University 1-5 Yamada-oka Suita Osaka 565-0871 Japan

Correspondence should be addressed to Masahide Hatanaka masahideistosaka-uacjp

Received 2 November 2012 Revised 16 May 2013 Accepted 17 May 2013

Academic Editor Chien-In Henry Chen

Copyright copy 2013 Masahide Hatanaka et al This is an open access article distributed under the Creative Commons AttributionLicense which permits unrestricted use distribution and reproduction in any medium provided the original work is properlycited

This paper proposes an efficient architecture and implementation of fading compensation dedicated to dynamic spectrum access(DSA) wireless communication Since pilot subcarrier arrangements are adaptively determined in wireless communication systemswith DSA the proposed architecture employs piecewise linear interpolation to the channel response estimation for data subcarriersin order to increase the channel estimation accuracy The fading compensation for an orthogonal frequency-division multiplexing(OFDM) symbol is performedwithin the time for oneOFDMsymbol tomake increase of latency smallerThe proposed architectureguarantees real-time processing with 76MHz or higher clock frequency The FPGA implementation of the proposed architectureoccupies 1577 slices and works up to 121MHz

1 Introduction

In ambient information society the ICT infrastructure inter-acts with each person in order to make the onersquos surroundingspace more comfortable In this kind of interaction varioustypes of information are exchanged ranging from small sizesuch as the control data of air conditioners and room lightsto large size of data like video streaming

Here wireless mesh networks that use unlicensed radiofrequency bands have been the focus of attention as one of theambient networks Among various wireless mesh networksIEEE 80211 WLAN series and ZigBee using carrier sensemultiple access with collision avoidance (CSMACA) areexpected to achieve popularity due to their capabilities tointerconnect However the following problem arises by usingthe technique of CSMACA Let us assume that there are twonodes 119860 and 119861 that use IEEE 80211g [1] for the former andZigBee [2] for the latter and the radio resource that 119860 hasrequested partially overlaps with that of 119861 In this situationeven if the node 119861 uses far fewer radio resources than node119860 requests the node 119860 judges that the band are not availablein case the node 119861 performs transmission and does not startto transmit data despite the presence of many unused radio

resources This causes the degradation of total transmissionperformance of the heterogeneous wireless infrastructure

In order to solve this problem the so-called cognitiveradio systems have been proposed [3 4] which introducevarious techniques with dynamic spectrum access (DSA)These techniques are based on the concept of exploitingspatial and temporal spectrumwhite space Among them [4]proposed dynamic subcarrier selection technique based onCSMACA with orthogonal frequency division multiplexing(OFDM) In this technique wireless nodes select the radioresources being used in the units of subcarriers by referringto the result of subcarrier level carrier sensing as shown inFigure 1This adaptive subcarrier selection technique enablestransmission by utilizing unused subcarriers even if there areoccupied spectrum components for other transmissions

Generally inwireless communication received signals aredistorted by fading and noise Therefore receivers need tocompensate the distortion in order to decode data correctlyIf the wireless communication is based on OFDM knowntraining signals called pilots are utilized in order to estimatethe channel response and compensate the distortion [5] Inthe IEEE 80211g four of the fixed subcarriers are utilized forpilot signals and the channel responses of data subcarriers

2 VLSI Design

Original spectrum

Spectrumafter mapping

Occupied spectrum

Frequency

Frequency

Figure 1 Mapping

are estimated by interpolating the channel responses of pilotsubcarriers [6]

However it is decided adaptively which subcarriers areutilized as data subcarriers or pilot subcarriers in targetwireless communication with DSA [7] Figure 2 outlines thearrangements of pilot subcarriers for IEEE 80211g and DSA[7] Although increasing the number of pilot subcarriersenables channel responses to be accurately estimated it alsodegrades the data rate Therefore it is necessary to estimatethe channel responses for data subcarriers by interpolationwith the estimated channel responses for pilot subcarriersin order to accurately estimate the channel responses withlimited pilot subcarriers Since the interpolation functionfor communication differs from the functions for othercommunications a dedicated channel compensation circuitfor DSA is necessary to accomplish high-speed operationto determine both decisions of interpolation function andfading compensation

Motivated by these tendencies this paper describes anefficient architecture and implementation of fading com-pensator for an OFDM baseband transceiver with DSAPiecewise linear interpolation is utilized in order to estimatethe channel responses for data subcarriers by using thechannel responses for pilot subcarriers

2 OFDM Wireless Communication withDynamic Spectrum Access

This paper assumes that DSA wireless communication withsubcarrier selection-type CSMACA [4] is employed Table 1summarizes the system parameters for the target DSA wire-less communication systemThis system is designed by takinginto account its compatibility with OFDM in IEEE 80211a[8] and IEEE 80211g [8] In this condition FFT size andthe maximum bandwidth are twice as large as those of IEEE80211g However the number of subcarriers used for datatransmission is the same as that for IEEE 80211g in order toavoid exclusive use of radio resources

Figure 3 shows the OFDM frame structure The OFDMframe consists of a physical layer convergence protocol(PLCP) preamble which is used for synchronization detec-tion header symbols that is coded communication param-eters and data symbols including transmission data ThePLCP preamble is made up of a short preamble for timingdetection and a long preamble for phase compensation The

Table 1 System parameters

No of efficient subcarriers 48No of pilot subcarriers 4FFT size 128Max bandwidth 40MHzSymbol length 4 120583sCycle prefix length 32 samplesCarrier modulation BPSK QPSK 16QAM 64QAMCoding rate 12 23 34

short preamble is a ten times iteration of the referencepattern and one reference pattern is 32 samples In thereceiver side symbol timing detection is performed by usingcorrelation between the reference pattern and the receivedshort preamble signalThe long preamble signals are for phasecompensation whose amplitude and phase are known Theheader symbol indicates the used modulation mode and thelength of data symbols

Figure 4 shows a block diagram of the target ODFMbaseband transceiver with DSA [7] In the transmitter thefirst process is forward error correction (FEC) which addsredundant data to input data so that the amount of data isset according to the coding rate Interleaving is the secondprocess and it reorders data to avoid burst error Modulateddata are assigned to subcarriers in mapping process basedon information on subcarrier assignment obtained fromsubcarrier level sensing The mapping function is given by

119894119889119909 = 119872(119901) (1)

where 119901 and 119894119889119909 are subcarrier indices before and aftermapping respectively While 119894119889119909 ranges from 0 to 127 119901ranges from 0 to 51 119872 is a transform function based onsubcarrier information obtained from subcarrier level carriersensing After mapping IFFT transforms the frequencydomain data to the time domain data Here the number ofdata from mapping to IFFT is 52 and the size of IFFT is 128Mapping should pass dummy data (ie 0rsquos) to IFFT for 76(= 128 minus 52) unused subcarriers The increased number ofinput data to IFFT increases the computational cost to bemore than that for conventional IEEE 80211g A cycle prefix(CP) whose length is greater than the channel delay spreadis added prior to transmission by copying part of the IFFToutput to mitigate the effects of intersymbol interferenceFinally through digital-analog converter (DAC) the samplesare passed to a radio frequency (RF) unit that amplifies thesignals and upconverts them to the required center frequency

The receiver operates in reverse to the transmitter Inthe receiver the first process is timing synchronization Thetiming synchronization process detects the beginning of aframe by calculating the correlation between the sequentialdata from the analog-digital converter (ADC) and the shortpreamble sequence which is the known pattern signal Aftersymbol timing is synchronized the added CP is removedand FFT transforms the time domain data to the frequencydomain data Next the demapping process which is thereverse operation of mapping selects 52 outputs of FFT

VLSI Design 3

Frequency

Fixed arrangement

Pilot

Data

(a) IEEE 80211g

Frequency

Pilot

Data

Adaptive arrangement

(b) DSA

Figure 2 Pilot subcarrier arrangement

Headersymbol

Datasymbol

Datasymbol

4 120583s4 120583s4 120583s8 120583s

Shortpreamble

Longpreamble

8 120583s

PLCP preamble

Figure 3 The OFDM frame structure

based on subcarrier information from 128 subcarriers Inother words the demapping process discards many datasignals The equalization process eliminates the effect of thetransmission channel by using the channel transfer functionestimated from long training sequences Finally Viterbidecoding process after demodulation and deinterleavingoutputs the reconstructed version of the original data

3 Fading Compensation

The received signals through the wireless channel are dis-torted by fading or noise as shown in Figure 5Therefore fad-ing compensationwhich estimates and compensates receivedsignal distortion is necessary in order to accurately decodethe received data

This section describes the fading compensation for DSAwe propose after explaining an example of preamble-basedfading compensation [6] for OFDM transmission

31 Preamble-Based Fading Compensation Figure 6 showsan overview of preamble-based fading compensation AfterFFT received preamble signals 119877pr

119898

are expressed as

119877pr119898

= 119886pr119898

119867119898+ 119885119898

(0 le 119898 le 119872 minus 1) (2)

where 119898 is the index of used subcarriers 119886pr119898

is theknown preamble signal and 119867

119898and 119885

119898represent ideal

channel response and noise channel response respectively[9] Received preamble signal 119877pr

119898

is compared to known

signal 119886pr119898

and estimated channel response 119898is calculated

as

119898

=

119877pr119898

119886pr119898

= 119867119898+

119885119898

119886pr119898

(0 le 119898 le 119872 minus 1) (3)

The primary compensated signal 119886119898is calculated by using

119898

119886119898

=119877119898

119898

(0 le 119898 le 119872 minus 1) (4)

where 119877119898is the received signal

Next secondary compensation with pilot subcarriers iscarried out to copewithmicrovariations in channel responsesin one OFDM symbol time The estimated microvariation inchannel response

119889119898

is expressed as

119889119898

= 119865 (119898 119897 (119899) 119886119901119894119897(119899)

) (5)

where 119898 is the index of data subcarriers 119897(119899) is the indexof pilot subcarriers and 119886

119901119894119897(119899)is that of the estimated

microvariation for pilot signals and 119865 is their interpolationfunction The secondary compensated signals 119886

119889119898

are givenby

119886119889119898

=

119886119889119898

119889119898

(0 le 119896 le 119872 minus 119871 minus 1) (6)

where 119871 is the number of pilot subcarriers

32 Fading Compensation for DSA In the IEEE 80211g fourof the subcarriers are dedicated to pilot signals in order tomake coherent detection robust against frequency offsets andphase noise These pilot signals are placed in ideal locations[10] Therefore the arithmetic mean can be utilized as thefunction to estimate channel microvariations However thearithmetic mean is not always efficient for OFDM with DSAsince DSA utilizes different distributions of pilot subcarriersin different communications This paper adopts piecewiselinear interpolation as the interpolation function to estimatethe channel responses for microvariations and evaluates theefficiency by comparingwith the arithmeticmeanThedetailsare described in the next subsection

4 VLSI Design

FEC Interleave Modulation

MappingDemapping

FFTIFFT

CPinsert

CPdelete

Viterbidecode Deinterleave Demodulation Channel

equalization

Spectrum intensity

Timingsynchronization

DA

AD

Figure 4 Block diagram of ODFM baseband transceiver with DSA

Transmittedsignal

Receivedsignal

I

Q

Distorted

Figure 5 Example of received signal distortion

321 Microvariation Estimation with Piecewise Linear Inter-polation The estimated microvariation for the target sub-carrier is calculated by linear interpolation between theestimated microvariation values for the left and right pilotsubcarriers shown in Figure 7 The proposed interpolationfunction is given by

119865 (119898 119894119889119909 left 119894119889119909 right)

=

(119894119889119909 right minus 119898) 119894119889119909 left + (119898 minus 119894119889119909 left)

119894119889119909 right

119894119889119909 right minus 119894119889119909 left

(7)

where 119898 is the index of the target subcarrier 119894119889119909 left and119894119889119909 right correspond to the index of the left and right pilotsubcarriers and

119894119889119909 left and 119894119889119909 right are the estimated varia-

tion values for the left and right pilot subcarriers respectively119894119889119909 left and

119894119889119909 right are expressed as

119894119889119909 left =

119886119894119889119909 left

119886119894119889119909 left

119894119889119909 right =

119886119894119889119909 right

119886119894119889119909 right

(8)

Table 2 Parameters for Rayleigh fading model

No of multipath 32Delay spread 50 nsDelay attenuation model Exponential decayMaximum Doppler frequency 20HzVariation period of multipath 0025 s (40Hz)Frequency offset 003Hzsymbol

Table 3 Conditions for preliminary experiment

No of efficient subcarriers 52128 (including 4 for pilot)Modulation BPSK QPSKNo of processed OFDM symbol Two millionPhysical layer frame size 1500 byteSNR 0sim25 dB 5 dB stepChannel model Rayleigh fading (Table 2)

322 Preliminary Experiment The preliminary experimentwas carried out through software simulation to confirm thatpiecewise linear interpolation had an advantage over thearithmetic mean in respect to the Bit Error Rate (BER)Software with floating points emulates the behavior of thetransceiver but symbol timing error is not taken into con-sideration

The Rayleigh fading model was used in the softwaresimulation whose parameters are summarized in Table 2 andsimulation conditions are listed in Table 3 Figure 8 plots theexperiment results for BER which is generally used as anindicator of the channel estimation accuracy This indicatesthat piecewise linear interpolation is more efficient than thearithmetic mean which is generally utilized in the 80211agPHYTherefore we adopted piecewise linear interpolation toestimate microvariations

4 Proposed Architecture of FadingCompensator for DSA

Figure 9 is a block diagram of the proposed fading com-pensator architecture The proposed architecture consists ofchannel estimator linear interpolator coefficient calculatorlinear projector and five memories

First the coefficient calculator stores 119894119889119909 left and119894119889119909 right obtained frommapping information in the 119894119889119909 left

VLSI Design 5

Coarsechannel

estimation

Receivedpreamble

signals

Estimatedchannelresponse

Primarycompensation

(exclude preamble)

Primarycompensated

signals

Secondarychannel estimationand interpolation

SecondarycompensationPrimary

compensateddata

signals

Primarycompensated

pilotsignals

Estimatedmicrovariation

Secondarycompensated

datasignals

Hm

am

Rm

Received signals

apil(n)

Rpr119898

ad119898

pd119898

ad119898

Figure 6 Preamble-based fading compensation

Interpolation line

Estimated value

Mapping condition

Data subcarriersPilot subcarriers

Unused subcarriers

Interpolation

0f

PfMicrovariationestimated value

Figure 7 Microvariation estimation with piecewise linear interpo-lation

0001

001

01

1

0 5 10 15 20 25

BER

SNR (dB)

BPSK (arithmetic)BPSK (piecewise)

QPSK (arithmetic)QPSK (piecewise)

Figure 8 Preliminary experiment results

memory and 119894119889119909 right memory respectively while receivingPLCP preamble signals Next the primary compensatedsignals are input and stored in the data buffer After all signalscorresponding to one OFDM symbol have been stored onedata at a time is read from the data buffer If the data is

Linearinterpolator

Channelestimator

Channelresponsememory

Coefficientcalculator

Linearprojector

Leftcoefficientmemory

Rightcoefficientmemory

Primarycompensated

data

Compensateddata

Databuffer

Leftmicrovariation

memory

Figure 9 Block diagram of proposed fading compensator

for the pilot the channel estimator calculates the estimatedmicrovariation value for the pilot and the value is written toboth left and right coefficient memories After all estimatedmicrovariation values for the pilots have been obtained theLinear interpolator calculates each estimated microvariationvalue for data by piecewise linear interpolation with thedistance between the target data subcarrier and two adjacentpilot subcarriers Finally the secondary compensated signalsfor data 119886

119889119898

are calculated from the primary compensatedsignals and estimated microvariation values for data in theLinear projector

41 Channel Estimator The block diagram of the channelestimator is shown in Figure 10

This block treats 119901119894119897(119899)

as amplitude variation 120572 andphase shift Δ120579 in a polar coordinate system in order toenable microvariations to be easily calculated Thereforereceived signals (119868 119876) in a rectangular coordinate system aretransformed to (119877 120579) in a polar coordinate system in thisblock The transformation from a rectangular coordinate toa polar coordinate is given by

119877 = radic1198682 + 1198762

120579 =

tanminus1119876119868

(119876 le 119868)

1

2120587 minus tanminus1 119868

119876(119876 gt 119868)

(9)

6 VLSI Design

12120579

Term

24Squareadd

14

14

120572

Δ120579

Phase shift

Amplitudevariation

Polar coordinate transformation circuitKnown signals

Primarycompensated

signalsQ

I

rP

120579P

11

12

12

12

12R

abs init tanminus1

table

Squareroot

(7 cycle)

Dividor(7 cycle)

Dividor(6 cycle)

Figure 10 Channel estimation block

The input size of the tanminus1 function is restricted to 11-bit by comparing 119868 with 119876 so that the tanminus1 function canbe constructed with a lookup table (LUT) All modules inthis block adopt a pipelined architecture and the square rootand divider both take seven cycles each Performing abs andsquare add take 1 cycle As a result the latency of this block is15 cycles

42 Coefficient Calculator The two data 119894119889119909 right and119894119889119909 left can be calculated with mapping information onlyTherefore the coefficient calculator obtains 119894119889119909 right and119894119889119909 left and stores them in memories while receiving longpreamble signals since the mapping information cannot bechanged in a physical layer (PHY) frame

The mapping information has two 128-bit data whereeach bit corresponds to each subcarrier The first data arecalled a utilization mask and indicate which subcarriers areused (1)unused (0) The second are called a pilot mask andindicate which subcarriers are pilot subcarriers (1) or not (0)Figure 11 is the block diagram of the coefficient calculatorThis block consists of subcarrier index generator subcarriertype checking block and coefficient generatorThe subcarrierindex generator and the coefficient generator are created by7-bit counter and the subcarrier type checking block is basedon a barrel shifter The two memories that have write accessfrom this block are dual port RAMs since thesememories alsohave read access from the linear interpolator How 119894119889119909 rightand 119894119889119909 left are determined by using these data is describedhereinafter

(1) First the 128-entry memory called the Right coeffi-cient memory is initialized to 1rsquos Next the utilizationand pilot masks are forward scanned with the sub-carrier index generator and subcarrier type checkingblock The contents of the Right coefficient memoryremain unchanged until the first detection of a pilotsubcarrier When a pilot subcarrier is detected thecorresponding entry in the right coefficient memoryis changed to 0 and then incremented values arewritten to the memory until the next pilot subcarrieris detected Figure 12 shows the contents of memoryafter this step has finished

(2) Since only 119894119889119909 right is utilized for the data subcarriers

that are at the right of the last pilot subcarrier corre-sponding entries for the Right coefficient memory tothe data subcarriers are overwritten by zero after step

Utilization mask Pilot mask

Subcarrier typechecking

128128

Coefficientgenerator

2

7

Coefficientcalculator

Rightcoefficientmemory

Leftcoefficientmemory

7

7

Subcarrierindex

generator

Figure 11 Block diagram of coefficient calculator

Right coefficient memoryLeft coefficient memory

1 1 mdash 1 2 3 4 mdash 1 1

f = 0Subcarrier index 1 2 3 4 Frequency

Pilotsubcarrier

Datasubcarrier

Figure 12 Contents of memory after step 1

1 has finished Figure 13 shows the contents ofmemoryafter this step has finished

(3) The left coefficients are determined in the same wayas those in step 1 with backward scanning and theyare stored in the left coefficient memory

(4) The entries corresponding to the subcarriers at the leftof the first pilot subcarrier are overwritten by zero inthe same way as that in step 2

Figure 14 shows the contents of memories after all stepsare executed

This step includes forward and backward scanning ofmapping information and each scan takes 128 cycles sinceutilization of the subcarrier index119891 asmemory read addressenables one cycle reading of pair coefficients from the Leftand Right coefficient memoriesThe execution cycles of steps2 and 4 are determined according to the pilot subcarrierarrangement The maximum execution cycle is 129 cycleswhen only one of 128 subcarriers is dedicated to the pilot

VLSI Design 7

Right coefficient memoryLeft coefficient memory

1 1 mdash 1 2 3 4 mdash 0 0

f = 0Subcarrier index 1 2 3 4 Frequency

Figure 13 Contents of memory after step 2

Right coefficient memory

Left coefficient memory1 1 mdash 1 2 3 4 mdash 0 00 0 mdash 4 3 2 1 mdash 1 1

f = 0Subcarrier index 1 2 3 4 Frequency

Right 2 left 3 (f = 4)

Figure 14 Contents of memory after coefficient calculation

signal The total execution cycles is at most 387 cycles sinceone cycle initialization and one cycle termination process areincluded

43 Linear Interpolator Figure 15 shows the block diagramof the linear interpolator This block has four multipliersand three adders and all of them have registered outputsTherefore the linear interpolator has ten pipeline stages sincethis block has a dividor that has seven pipeline stages

The linear interpolator performs two functions Oneis preparing the left and right estimated microvariationvalues

119894119889119909 left = (119886119894119889119909 left 120579119894119889119909 left) and

119894119889119909 right =

(119886119894119889119909 right 120579119894119889119909 right) The other is calculation of the estimated

microvariation value for data subcarriers 119889119898

= (119886119889119898

120579119889119898

)First the estimated microvariation values for pilot sub-

carriers are written in the left estimated microvariationmemory which is the output of the channel estimator Theentries corresponding to the subcarriers on the left of thefirst pilot subcarrier are written as zeroes The entries for theother subcarriers are written as the estimated microvariationvalues for the nearest pilot subcarrier on the left After allof the 128 entries have been written to the right estimatedmicrovariation values are obtained in the same way as theleft estimated microvariation values by backward-scanningthe left estimated microvariation memory and pilot maskEach of the estimated microvariation values for the datasubcarriers is calculated by linear interpolation (7) with theleft and right coefficients and the left and right estimatedmicrovariation values

These operations are executed at 285 cycles including128 cycles for writing 128 cycles for scanning 10 cycles formicrovariation calculations and 19 cycles for the initializingand terminating processes

Figure 16 shows how to utilize the left and right estimatedvalue

44 Linear Projection Block The secondary compensation iscarried out by linear projection operation with the estimatedmicrovariation value in the rectangular coordinate systemThe linear projection operation is given by

(119868

119876) =

1

119886(sin (minusΔ120579) minus cos (minusΔ120579)cos (minusΔ120579) sin (minusΔ120579)

)(1198681015840

1198761015840) (10)

Table 4 Maximum execution cycles

Blocks Maximum execution cyclesChannel estimation 15Coefficient calculator 387Linear interpolation 285Linear projection 4

Table 5 Implementation result

Occupied slice 157714336 (11)Used SRAM 234 kbitsMax frequency 112MHz

The block diagram of linear projection block is shownin Figure 17 This block can input data every cycle and tableaccess and multiplication and addition take 1 cycle As aresult the latency of this block is 4 cycles

45 Execution Cycles and Operation Frequency Table 4 sum-marizes the maximum execution cycles for each block in afading compensation circuit

When a block needs to terminate its process within 119873

OFDM symbol time (one ODFM symbol time is 4 120583s) duringreal-time operation theminimumoperation frequency119865minfor real-time operation is given by

119865min =119899

119873 sdot (40 times 10minus6) (11)

where 119899 is the number of execution cyclesSince it is necessary for the coefficient calculator to termi-

nate its process within two OFDM symbol times to receive alllong preamble signals the minimum operation frequency forreal-time operation is 483MHz (= 2(387times(40times10

minus6

)))Theexecution time for the channel estimator linear interpolatorand linear projector is 304 cycles for an OFDM symbolsince they need to perform their operations for the sameOFDM symbolTherefore theminimumoperation frequencyis 760MHz for these blocks

As a result the minimum operation frequency for theproposed fading compensator is 760MHz since the min-imum operation frequency of blocks excluding the coeffi-cient calculator is 760MHz and the minimum operationfrequency of the coefficient calculator is 483MHz

5 FPGA Design of Fading Compensator

51 Implementation Result The proposed architecture of thefading compensation circuit has been implemented in anFPGA (Xilinx Virtex-II xc2v3000) and Table 5 summarizesimplementation results This result surpasses the 760MHzdemanded for real-time operation

52 Performance Evaluation We simulated the performanceof this fading compensator without Viterbi decoding underthe conditions listed in Table 6 to confirm the behavior

8 VLSI Design

Rightcoefficientmemory

Leftmicrovariation

memory

Leftcoefficientmemory

Rightmicrovariation

register

7 Subcarrierindex

generator

7

7

1412

1214

19

21

2119

Dividor(6 cycles)

Dividor(7 cycles)

14

12

Linearinterpolator

14

12

2220

8

idx left idx left

idx left

idx left idx right

idx right

120572 dm

120579 dm

Figure 15 Block diagram of linear interpolator

Left estimated valueRight estimated value

f = 0 1 2 3 4 Subcarrier index Frequency

mdash mdashmdash mdash

1205911

120591112059111205911

1205911 1205911 1205911 1205911 1205912 1205912 1205912

12059121205912120591212059121205912

Pright = 1205911 Pright = 1205912

120591f = ( 120572fΔ120579f

)

Figure 16 Left and right estimated values

Amplitude variation120572 14Phase shift Δ120579 12

Input data I 12Q 12

Floating pointSignificant 11-bitExponent 4-bit

CompensateddataI12Q12

table tablecos(120579) sin(120579)

Figure 17 Linear projection block

Table 6 Simulation conditions

No of efficient subcarriers 52128 (including 4 for pilot)Modulation BPSK QPSKNo of Processed OFDM symbol Two millionPhysical layer frame size 1500 byteSNR 0sim25 dB 5 dB stepChannel model Rayleigh fading (Table 2)

of the proposed architecture Figure 18 shows the mappingcondition in this simulation

Figure 19 plots the simulation results for BER with hard-ware implementation These results show that the hard-ware implementation achieves comparable performance tothe 80211a-based system without the diversity reported in[11] even though our architecture utilizes a discontinuous

86 (pilot)

Frequency

64

67 92 (data)

73

11

5217

675823

Figure 18 Mapping condition

0001

001

01

1

0 5 10 15 20

BPSKQPSK

BPSK (11)QPSK (11)

BER

SNR (dB)

Figure 19 SNR versus BER

spectrum and its performance is almost the same as thetheoretical performance

6 Conclusion

In this paper a hardware architecture of fading compensationcircuit for DSA was proposed The proposed architectureadopted piecewise linear interpolation in order to accuratelyestimate channel responses for data subcarriers Fadingcompensation for an OFDM symbol was executed in oneOFDM symbol time in order to make increase of latency

VLSI Design 9

smaller The results of FPGA implementation indicated thatthe proposed circuit occupied 1577 slices and achieved112MHz operation frequency which overcame the 760MHzdemand for real-time operation on a single chip

Future work is the performance evaluation of the OFDMtransceiver with DSA combined with the proposed fadingcompensator

Acknowledgment

This research has been supported by the Global COE pro-gram of the Ministry of Education Culture Sports Scienceand Technology Japan under the title ldquoFounding AmbientInformation Society Infrastructurerdquo

References

[1] IEEE Std 80211g-2003 ldquoPart 11 Wireless LAN Medium AccessControl (MAC) and Physical Layer (PHY) SpecificationsAmendment 4 Further Higher Data Rate Extension in the 24GHz Bandrdquo June 2003

[2] Zigbee Alliance ldquoZigbee Specification Release 17rdquo ZigBee Doc-ument 053474r17 January 2008

[3] J D Poston and W D Horne ldquoDiscontiguous OFDM consid-erations for dynamic spectrum access in idle TV channelsrdquo inProceedings of the 1st IEEE International Symposium on NewFrontiers in Dynamic Spectrum Access Networks (DySPAN rsquo05)pp 607ndash610 November 2005

[4] S Miyamoto Y Goda and S Sampei ldquoDynamic subcarrierselection technique for cognitive wireless mesh networks usingcsmacardquo in Proceedings of International Workshop on SmartInfo-Media Systems in Bangkok (SISB rsquo08) pp 81ndash86 December2008

[5] L Tong B M Sadler and M Dong ldquoPilot-assisted wirelesstransmissionsrdquo IEEE Signal Processing Magazine vol 21 no 6pp 12ndash25 2004

[6] M Morikura and S Kubota ldquo80211 HIGH-SPEEDWIRELESSLAN TEXTBOOKrdquo Impress R amp D 2008

[7] M Hatanaka R Hashimoto T Tatsuka et al ldquoVLSI design ofOFDM baseband transceiver with dynamic spectrum accessrdquoin Proceedings of the 18th International Symposium on IntelligentSignal Processing and Communication Systems (ISPACS rsquo10) pp329ndash332 December 2010

[8] IEEE Std 80211a-1999 ldquoPart 11 Wireless LAN Medium AccessControl (MAC) and Physical Layer (PHY) Specifications High-Speed Physical Layer in the 5 GHz Bandrdquo June 2003

[9] HKobayashi ldquoFoundation andApplication ofOFDMCommu-nication Systemsrdquo triceps 2004

[10] S Adireddy L Tong and H Viswanathan ldquoOptimal placementof training for frequency-selective block-fading channelsrdquo IEEETransactions on Information Theory vol 48 no 8 pp 2338ndash2353 2002

[11] H K Jung W G Jeon K H Seo and Y S Cho ldquoA subcarrierselection combining technique for OFDM systemsrdquo IEICETransactions on Communications vol E86-B no 7 pp 2119ndash2124 2003

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Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

2 VLSI Design

Original spectrum

Spectrumafter mapping

Occupied spectrum

Frequency

Frequency

Figure 1 Mapping

are estimated by interpolating the channel responses of pilotsubcarriers [6]

However it is decided adaptively which subcarriers areutilized as data subcarriers or pilot subcarriers in targetwireless communication with DSA [7] Figure 2 outlines thearrangements of pilot subcarriers for IEEE 80211g and DSA[7] Although increasing the number of pilot subcarriersenables channel responses to be accurately estimated it alsodegrades the data rate Therefore it is necessary to estimatethe channel responses for data subcarriers by interpolationwith the estimated channel responses for pilot subcarriersin order to accurately estimate the channel responses withlimited pilot subcarriers Since the interpolation functionfor communication differs from the functions for othercommunications a dedicated channel compensation circuitfor DSA is necessary to accomplish high-speed operationto determine both decisions of interpolation function andfading compensation

Motivated by these tendencies this paper describes anefficient architecture and implementation of fading com-pensator for an OFDM baseband transceiver with DSAPiecewise linear interpolation is utilized in order to estimatethe channel responses for data subcarriers by using thechannel responses for pilot subcarriers

2 OFDM Wireless Communication withDynamic Spectrum Access

This paper assumes that DSA wireless communication withsubcarrier selection-type CSMACA [4] is employed Table 1summarizes the system parameters for the target DSA wire-less communication systemThis system is designed by takinginto account its compatibility with OFDM in IEEE 80211a[8] and IEEE 80211g [8] In this condition FFT size andthe maximum bandwidth are twice as large as those of IEEE80211g However the number of subcarriers used for datatransmission is the same as that for IEEE 80211g in order toavoid exclusive use of radio resources

Figure 3 shows the OFDM frame structure The OFDMframe consists of a physical layer convergence protocol(PLCP) preamble which is used for synchronization detec-tion header symbols that is coded communication param-eters and data symbols including transmission data ThePLCP preamble is made up of a short preamble for timingdetection and a long preamble for phase compensation The

Table 1 System parameters

No of efficient subcarriers 48No of pilot subcarriers 4FFT size 128Max bandwidth 40MHzSymbol length 4 120583sCycle prefix length 32 samplesCarrier modulation BPSK QPSK 16QAM 64QAMCoding rate 12 23 34

short preamble is a ten times iteration of the referencepattern and one reference pattern is 32 samples In thereceiver side symbol timing detection is performed by usingcorrelation between the reference pattern and the receivedshort preamble signalThe long preamble signals are for phasecompensation whose amplitude and phase are known Theheader symbol indicates the used modulation mode and thelength of data symbols

Figure 4 shows a block diagram of the target ODFMbaseband transceiver with DSA [7] In the transmitter thefirst process is forward error correction (FEC) which addsredundant data to input data so that the amount of data isset according to the coding rate Interleaving is the secondprocess and it reorders data to avoid burst error Modulateddata are assigned to subcarriers in mapping process basedon information on subcarrier assignment obtained fromsubcarrier level sensing The mapping function is given by

119894119889119909 = 119872(119901) (1)

where 119901 and 119894119889119909 are subcarrier indices before and aftermapping respectively While 119894119889119909 ranges from 0 to 127 119901ranges from 0 to 51 119872 is a transform function based onsubcarrier information obtained from subcarrier level carriersensing After mapping IFFT transforms the frequencydomain data to the time domain data Here the number ofdata from mapping to IFFT is 52 and the size of IFFT is 128Mapping should pass dummy data (ie 0rsquos) to IFFT for 76(= 128 minus 52) unused subcarriers The increased number ofinput data to IFFT increases the computational cost to bemore than that for conventional IEEE 80211g A cycle prefix(CP) whose length is greater than the channel delay spreadis added prior to transmission by copying part of the IFFToutput to mitigate the effects of intersymbol interferenceFinally through digital-analog converter (DAC) the samplesare passed to a radio frequency (RF) unit that amplifies thesignals and upconverts them to the required center frequency

The receiver operates in reverse to the transmitter Inthe receiver the first process is timing synchronization Thetiming synchronization process detects the beginning of aframe by calculating the correlation between the sequentialdata from the analog-digital converter (ADC) and the shortpreamble sequence which is the known pattern signal Aftersymbol timing is synchronized the added CP is removedand FFT transforms the time domain data to the frequencydomain data Next the demapping process which is thereverse operation of mapping selects 52 outputs of FFT

VLSI Design 3

Frequency

Fixed arrangement

Pilot

Data

(a) IEEE 80211g

Frequency

Pilot

Data

Adaptive arrangement

(b) DSA

Figure 2 Pilot subcarrier arrangement

Headersymbol

Datasymbol

Datasymbol

4 120583s4 120583s4 120583s8 120583s

Shortpreamble

Longpreamble

8 120583s

PLCP preamble

Figure 3 The OFDM frame structure

based on subcarrier information from 128 subcarriers Inother words the demapping process discards many datasignals The equalization process eliminates the effect of thetransmission channel by using the channel transfer functionestimated from long training sequences Finally Viterbidecoding process after demodulation and deinterleavingoutputs the reconstructed version of the original data

3 Fading Compensation

The received signals through the wireless channel are dis-torted by fading or noise as shown in Figure 5Therefore fad-ing compensationwhich estimates and compensates receivedsignal distortion is necessary in order to accurately decodethe received data

This section describes the fading compensation for DSAwe propose after explaining an example of preamble-basedfading compensation [6] for OFDM transmission

31 Preamble-Based Fading Compensation Figure 6 showsan overview of preamble-based fading compensation AfterFFT received preamble signals 119877pr

119898

are expressed as

119877pr119898

= 119886pr119898

119867119898+ 119885119898

(0 le 119898 le 119872 minus 1) (2)

where 119898 is the index of used subcarriers 119886pr119898

is theknown preamble signal and 119867

119898and 119885

119898represent ideal

channel response and noise channel response respectively[9] Received preamble signal 119877pr

119898

is compared to known

signal 119886pr119898

and estimated channel response 119898is calculated

as

119898

=

119877pr119898

119886pr119898

= 119867119898+

119885119898

119886pr119898

(0 le 119898 le 119872 minus 1) (3)

The primary compensated signal 119886119898is calculated by using

119898

119886119898

=119877119898

119898

(0 le 119898 le 119872 minus 1) (4)

where 119877119898is the received signal

Next secondary compensation with pilot subcarriers iscarried out to copewithmicrovariations in channel responsesin one OFDM symbol time The estimated microvariation inchannel response

119889119898

is expressed as

119889119898

= 119865 (119898 119897 (119899) 119886119901119894119897(119899)

) (5)

where 119898 is the index of data subcarriers 119897(119899) is the indexof pilot subcarriers and 119886

119901119894119897(119899)is that of the estimated

microvariation for pilot signals and 119865 is their interpolationfunction The secondary compensated signals 119886

119889119898

are givenby

119886119889119898

=

119886119889119898

119889119898

(0 le 119896 le 119872 minus 119871 minus 1) (6)

where 119871 is the number of pilot subcarriers

32 Fading Compensation for DSA In the IEEE 80211g fourof the subcarriers are dedicated to pilot signals in order tomake coherent detection robust against frequency offsets andphase noise These pilot signals are placed in ideal locations[10] Therefore the arithmetic mean can be utilized as thefunction to estimate channel microvariations However thearithmetic mean is not always efficient for OFDM with DSAsince DSA utilizes different distributions of pilot subcarriersin different communications This paper adopts piecewiselinear interpolation as the interpolation function to estimatethe channel responses for microvariations and evaluates theefficiency by comparingwith the arithmeticmeanThedetailsare described in the next subsection

4 VLSI Design

FEC Interleave Modulation

MappingDemapping

FFTIFFT

CPinsert

CPdelete

Viterbidecode Deinterleave Demodulation Channel

equalization

Spectrum intensity

Timingsynchronization

DA

AD

Figure 4 Block diagram of ODFM baseband transceiver with DSA

Transmittedsignal

Receivedsignal

I

Q

Distorted

Figure 5 Example of received signal distortion

321 Microvariation Estimation with Piecewise Linear Inter-polation The estimated microvariation for the target sub-carrier is calculated by linear interpolation between theestimated microvariation values for the left and right pilotsubcarriers shown in Figure 7 The proposed interpolationfunction is given by

119865 (119898 119894119889119909 left 119894119889119909 right)

=

(119894119889119909 right minus 119898) 119894119889119909 left + (119898 minus 119894119889119909 left)

119894119889119909 right

119894119889119909 right minus 119894119889119909 left

(7)

where 119898 is the index of the target subcarrier 119894119889119909 left and119894119889119909 right correspond to the index of the left and right pilotsubcarriers and

119894119889119909 left and 119894119889119909 right are the estimated varia-

tion values for the left and right pilot subcarriers respectively119894119889119909 left and

119894119889119909 right are expressed as

119894119889119909 left =

119886119894119889119909 left

119886119894119889119909 left

119894119889119909 right =

119886119894119889119909 right

119886119894119889119909 right

(8)

Table 2 Parameters for Rayleigh fading model

No of multipath 32Delay spread 50 nsDelay attenuation model Exponential decayMaximum Doppler frequency 20HzVariation period of multipath 0025 s (40Hz)Frequency offset 003Hzsymbol

Table 3 Conditions for preliminary experiment

No of efficient subcarriers 52128 (including 4 for pilot)Modulation BPSK QPSKNo of processed OFDM symbol Two millionPhysical layer frame size 1500 byteSNR 0sim25 dB 5 dB stepChannel model Rayleigh fading (Table 2)

322 Preliminary Experiment The preliminary experimentwas carried out through software simulation to confirm thatpiecewise linear interpolation had an advantage over thearithmetic mean in respect to the Bit Error Rate (BER)Software with floating points emulates the behavior of thetransceiver but symbol timing error is not taken into con-sideration

The Rayleigh fading model was used in the softwaresimulation whose parameters are summarized in Table 2 andsimulation conditions are listed in Table 3 Figure 8 plots theexperiment results for BER which is generally used as anindicator of the channel estimation accuracy This indicatesthat piecewise linear interpolation is more efficient than thearithmetic mean which is generally utilized in the 80211agPHYTherefore we adopted piecewise linear interpolation toestimate microvariations

4 Proposed Architecture of FadingCompensator for DSA

Figure 9 is a block diagram of the proposed fading com-pensator architecture The proposed architecture consists ofchannel estimator linear interpolator coefficient calculatorlinear projector and five memories

First the coefficient calculator stores 119894119889119909 left and119894119889119909 right obtained frommapping information in the 119894119889119909 left

VLSI Design 5

Coarsechannel

estimation

Receivedpreamble

signals

Estimatedchannelresponse

Primarycompensation

(exclude preamble)

Primarycompensated

signals

Secondarychannel estimationand interpolation

SecondarycompensationPrimary

compensateddata

signals

Primarycompensated

pilotsignals

Estimatedmicrovariation

Secondarycompensated

datasignals

Hm

am

Rm

Received signals

apil(n)

Rpr119898

ad119898

pd119898

ad119898

Figure 6 Preamble-based fading compensation

Interpolation line

Estimated value

Mapping condition

Data subcarriersPilot subcarriers

Unused subcarriers

Interpolation

0f

PfMicrovariationestimated value

Figure 7 Microvariation estimation with piecewise linear interpo-lation

0001

001

01

1

0 5 10 15 20 25

BER

SNR (dB)

BPSK (arithmetic)BPSK (piecewise)

QPSK (arithmetic)QPSK (piecewise)

Figure 8 Preliminary experiment results

memory and 119894119889119909 right memory respectively while receivingPLCP preamble signals Next the primary compensatedsignals are input and stored in the data buffer After all signalscorresponding to one OFDM symbol have been stored onedata at a time is read from the data buffer If the data is

Linearinterpolator

Channelestimator

Channelresponsememory

Coefficientcalculator

Linearprojector

Leftcoefficientmemory

Rightcoefficientmemory

Primarycompensated

data

Compensateddata

Databuffer

Leftmicrovariation

memory

Figure 9 Block diagram of proposed fading compensator

for the pilot the channel estimator calculates the estimatedmicrovariation value for the pilot and the value is written toboth left and right coefficient memories After all estimatedmicrovariation values for the pilots have been obtained theLinear interpolator calculates each estimated microvariationvalue for data by piecewise linear interpolation with thedistance between the target data subcarrier and two adjacentpilot subcarriers Finally the secondary compensated signalsfor data 119886

119889119898

are calculated from the primary compensatedsignals and estimated microvariation values for data in theLinear projector

41 Channel Estimator The block diagram of the channelestimator is shown in Figure 10

This block treats 119901119894119897(119899)

as amplitude variation 120572 andphase shift Δ120579 in a polar coordinate system in order toenable microvariations to be easily calculated Thereforereceived signals (119868 119876) in a rectangular coordinate system aretransformed to (119877 120579) in a polar coordinate system in thisblock The transformation from a rectangular coordinate toa polar coordinate is given by

119877 = radic1198682 + 1198762

120579 =

tanminus1119876119868

(119876 le 119868)

1

2120587 minus tanminus1 119868

119876(119876 gt 119868)

(9)

6 VLSI Design

12120579

Term

24Squareadd

14

14

120572

Δ120579

Phase shift

Amplitudevariation

Polar coordinate transformation circuitKnown signals

Primarycompensated

signalsQ

I

rP

120579P

11

12

12

12

12R

abs init tanminus1

table

Squareroot

(7 cycle)

Dividor(7 cycle)

Dividor(6 cycle)

Figure 10 Channel estimation block

The input size of the tanminus1 function is restricted to 11-bit by comparing 119868 with 119876 so that the tanminus1 function canbe constructed with a lookup table (LUT) All modules inthis block adopt a pipelined architecture and the square rootand divider both take seven cycles each Performing abs andsquare add take 1 cycle As a result the latency of this block is15 cycles

42 Coefficient Calculator The two data 119894119889119909 right and119894119889119909 left can be calculated with mapping information onlyTherefore the coefficient calculator obtains 119894119889119909 right and119894119889119909 left and stores them in memories while receiving longpreamble signals since the mapping information cannot bechanged in a physical layer (PHY) frame

The mapping information has two 128-bit data whereeach bit corresponds to each subcarrier The first data arecalled a utilization mask and indicate which subcarriers areused (1)unused (0) The second are called a pilot mask andindicate which subcarriers are pilot subcarriers (1) or not (0)Figure 11 is the block diagram of the coefficient calculatorThis block consists of subcarrier index generator subcarriertype checking block and coefficient generatorThe subcarrierindex generator and the coefficient generator are created by7-bit counter and the subcarrier type checking block is basedon a barrel shifter The two memories that have write accessfrom this block are dual port RAMs since thesememories alsohave read access from the linear interpolator How 119894119889119909 rightand 119894119889119909 left are determined by using these data is describedhereinafter

(1) First the 128-entry memory called the Right coeffi-cient memory is initialized to 1rsquos Next the utilizationand pilot masks are forward scanned with the sub-carrier index generator and subcarrier type checkingblock The contents of the Right coefficient memoryremain unchanged until the first detection of a pilotsubcarrier When a pilot subcarrier is detected thecorresponding entry in the right coefficient memoryis changed to 0 and then incremented values arewritten to the memory until the next pilot subcarrieris detected Figure 12 shows the contents of memoryafter this step has finished

(2) Since only 119894119889119909 right is utilized for the data subcarriers

that are at the right of the last pilot subcarrier corre-sponding entries for the Right coefficient memory tothe data subcarriers are overwritten by zero after step

Utilization mask Pilot mask

Subcarrier typechecking

128128

Coefficientgenerator

2

7

Coefficientcalculator

Rightcoefficientmemory

Leftcoefficientmemory

7

7

Subcarrierindex

generator

Figure 11 Block diagram of coefficient calculator

Right coefficient memoryLeft coefficient memory

1 1 mdash 1 2 3 4 mdash 1 1

f = 0Subcarrier index 1 2 3 4 Frequency

Pilotsubcarrier

Datasubcarrier

Figure 12 Contents of memory after step 1

1 has finished Figure 13 shows the contents ofmemoryafter this step has finished

(3) The left coefficients are determined in the same wayas those in step 1 with backward scanning and theyare stored in the left coefficient memory

(4) The entries corresponding to the subcarriers at the leftof the first pilot subcarrier are overwritten by zero inthe same way as that in step 2

Figure 14 shows the contents of memories after all stepsare executed

This step includes forward and backward scanning ofmapping information and each scan takes 128 cycles sinceutilization of the subcarrier index119891 asmemory read addressenables one cycle reading of pair coefficients from the Leftand Right coefficient memoriesThe execution cycles of steps2 and 4 are determined according to the pilot subcarrierarrangement The maximum execution cycle is 129 cycleswhen only one of 128 subcarriers is dedicated to the pilot

VLSI Design 7

Right coefficient memoryLeft coefficient memory

1 1 mdash 1 2 3 4 mdash 0 0

f = 0Subcarrier index 1 2 3 4 Frequency

Figure 13 Contents of memory after step 2

Right coefficient memory

Left coefficient memory1 1 mdash 1 2 3 4 mdash 0 00 0 mdash 4 3 2 1 mdash 1 1

f = 0Subcarrier index 1 2 3 4 Frequency

Right 2 left 3 (f = 4)

Figure 14 Contents of memory after coefficient calculation

signal The total execution cycles is at most 387 cycles sinceone cycle initialization and one cycle termination process areincluded

43 Linear Interpolator Figure 15 shows the block diagramof the linear interpolator This block has four multipliersand three adders and all of them have registered outputsTherefore the linear interpolator has ten pipeline stages sincethis block has a dividor that has seven pipeline stages

The linear interpolator performs two functions Oneis preparing the left and right estimated microvariationvalues

119894119889119909 left = (119886119894119889119909 left 120579119894119889119909 left) and

119894119889119909 right =

(119886119894119889119909 right 120579119894119889119909 right) The other is calculation of the estimated

microvariation value for data subcarriers 119889119898

= (119886119889119898

120579119889119898

)First the estimated microvariation values for pilot sub-

carriers are written in the left estimated microvariationmemory which is the output of the channel estimator Theentries corresponding to the subcarriers on the left of thefirst pilot subcarrier are written as zeroes The entries for theother subcarriers are written as the estimated microvariationvalues for the nearest pilot subcarrier on the left After allof the 128 entries have been written to the right estimatedmicrovariation values are obtained in the same way as theleft estimated microvariation values by backward-scanningthe left estimated microvariation memory and pilot maskEach of the estimated microvariation values for the datasubcarriers is calculated by linear interpolation (7) with theleft and right coefficients and the left and right estimatedmicrovariation values

These operations are executed at 285 cycles including128 cycles for writing 128 cycles for scanning 10 cycles formicrovariation calculations and 19 cycles for the initializingand terminating processes

Figure 16 shows how to utilize the left and right estimatedvalue

44 Linear Projection Block The secondary compensation iscarried out by linear projection operation with the estimatedmicrovariation value in the rectangular coordinate systemThe linear projection operation is given by

(119868

119876) =

1

119886(sin (minusΔ120579) minus cos (minusΔ120579)cos (minusΔ120579) sin (minusΔ120579)

)(1198681015840

1198761015840) (10)

Table 4 Maximum execution cycles

Blocks Maximum execution cyclesChannel estimation 15Coefficient calculator 387Linear interpolation 285Linear projection 4

Table 5 Implementation result

Occupied slice 157714336 (11)Used SRAM 234 kbitsMax frequency 112MHz

The block diagram of linear projection block is shownin Figure 17 This block can input data every cycle and tableaccess and multiplication and addition take 1 cycle As aresult the latency of this block is 4 cycles

45 Execution Cycles and Operation Frequency Table 4 sum-marizes the maximum execution cycles for each block in afading compensation circuit

When a block needs to terminate its process within 119873

OFDM symbol time (one ODFM symbol time is 4 120583s) duringreal-time operation theminimumoperation frequency119865minfor real-time operation is given by

119865min =119899

119873 sdot (40 times 10minus6) (11)

where 119899 is the number of execution cyclesSince it is necessary for the coefficient calculator to termi-

nate its process within two OFDM symbol times to receive alllong preamble signals the minimum operation frequency forreal-time operation is 483MHz (= 2(387times(40times10

minus6

)))Theexecution time for the channel estimator linear interpolatorand linear projector is 304 cycles for an OFDM symbolsince they need to perform their operations for the sameOFDM symbolTherefore theminimumoperation frequencyis 760MHz for these blocks

As a result the minimum operation frequency for theproposed fading compensator is 760MHz since the min-imum operation frequency of blocks excluding the coeffi-cient calculator is 760MHz and the minimum operationfrequency of the coefficient calculator is 483MHz

5 FPGA Design of Fading Compensator

51 Implementation Result The proposed architecture of thefading compensation circuit has been implemented in anFPGA (Xilinx Virtex-II xc2v3000) and Table 5 summarizesimplementation results This result surpasses the 760MHzdemanded for real-time operation

52 Performance Evaluation We simulated the performanceof this fading compensator without Viterbi decoding underthe conditions listed in Table 6 to confirm the behavior

8 VLSI Design

Rightcoefficientmemory

Leftmicrovariation

memory

Leftcoefficientmemory

Rightmicrovariation

register

7 Subcarrierindex

generator

7

7

1412

1214

19

21

2119

Dividor(6 cycles)

Dividor(7 cycles)

14

12

Linearinterpolator

14

12

2220

8

idx left idx left

idx left

idx left idx right

idx right

120572 dm

120579 dm

Figure 15 Block diagram of linear interpolator

Left estimated valueRight estimated value

f = 0 1 2 3 4 Subcarrier index Frequency

mdash mdashmdash mdash

1205911

120591112059111205911

1205911 1205911 1205911 1205911 1205912 1205912 1205912

12059121205912120591212059121205912

Pright = 1205911 Pright = 1205912

120591f = ( 120572fΔ120579f

)

Figure 16 Left and right estimated values

Amplitude variation120572 14Phase shift Δ120579 12

Input data I 12Q 12

Floating pointSignificant 11-bitExponent 4-bit

CompensateddataI12Q12

table tablecos(120579) sin(120579)

Figure 17 Linear projection block

Table 6 Simulation conditions

No of efficient subcarriers 52128 (including 4 for pilot)Modulation BPSK QPSKNo of Processed OFDM symbol Two millionPhysical layer frame size 1500 byteSNR 0sim25 dB 5 dB stepChannel model Rayleigh fading (Table 2)

of the proposed architecture Figure 18 shows the mappingcondition in this simulation

Figure 19 plots the simulation results for BER with hard-ware implementation These results show that the hard-ware implementation achieves comparable performance tothe 80211a-based system without the diversity reported in[11] even though our architecture utilizes a discontinuous

86 (pilot)

Frequency

64

67 92 (data)

73

11

5217

675823

Figure 18 Mapping condition

0001

001

01

1

0 5 10 15 20

BPSKQPSK

BPSK (11)QPSK (11)

BER

SNR (dB)

Figure 19 SNR versus BER

spectrum and its performance is almost the same as thetheoretical performance

6 Conclusion

In this paper a hardware architecture of fading compensationcircuit for DSA was proposed The proposed architectureadopted piecewise linear interpolation in order to accuratelyestimate channel responses for data subcarriers Fadingcompensation for an OFDM symbol was executed in oneOFDM symbol time in order to make increase of latency

VLSI Design 9

smaller The results of FPGA implementation indicated thatthe proposed circuit occupied 1577 slices and achieved112MHz operation frequency which overcame the 760MHzdemand for real-time operation on a single chip

Future work is the performance evaluation of the OFDMtransceiver with DSA combined with the proposed fadingcompensator

Acknowledgment

This research has been supported by the Global COE pro-gram of the Ministry of Education Culture Sports Scienceand Technology Japan under the title ldquoFounding AmbientInformation Society Infrastructurerdquo

References

[1] IEEE Std 80211g-2003 ldquoPart 11 Wireless LAN Medium AccessControl (MAC) and Physical Layer (PHY) SpecificationsAmendment 4 Further Higher Data Rate Extension in the 24GHz Bandrdquo June 2003

[2] Zigbee Alliance ldquoZigbee Specification Release 17rdquo ZigBee Doc-ument 053474r17 January 2008

[3] J D Poston and W D Horne ldquoDiscontiguous OFDM consid-erations for dynamic spectrum access in idle TV channelsrdquo inProceedings of the 1st IEEE International Symposium on NewFrontiers in Dynamic Spectrum Access Networks (DySPAN rsquo05)pp 607ndash610 November 2005

[4] S Miyamoto Y Goda and S Sampei ldquoDynamic subcarrierselection technique for cognitive wireless mesh networks usingcsmacardquo in Proceedings of International Workshop on SmartInfo-Media Systems in Bangkok (SISB rsquo08) pp 81ndash86 December2008

[5] L Tong B M Sadler and M Dong ldquoPilot-assisted wirelesstransmissionsrdquo IEEE Signal Processing Magazine vol 21 no 6pp 12ndash25 2004

[6] M Morikura and S Kubota ldquo80211 HIGH-SPEEDWIRELESSLAN TEXTBOOKrdquo Impress R amp D 2008

[7] M Hatanaka R Hashimoto T Tatsuka et al ldquoVLSI design ofOFDM baseband transceiver with dynamic spectrum accessrdquoin Proceedings of the 18th International Symposium on IntelligentSignal Processing and Communication Systems (ISPACS rsquo10) pp329ndash332 December 2010

[8] IEEE Std 80211a-1999 ldquoPart 11 Wireless LAN Medium AccessControl (MAC) and Physical Layer (PHY) Specifications High-Speed Physical Layer in the 5 GHz Bandrdquo June 2003

[9] HKobayashi ldquoFoundation andApplication ofOFDMCommu-nication Systemsrdquo triceps 2004

[10] S Adireddy L Tong and H Viswanathan ldquoOptimal placementof training for frequency-selective block-fading channelsrdquo IEEETransactions on Information Theory vol 48 no 8 pp 2338ndash2353 2002

[11] H K Jung W G Jeon K H Seo and Y S Cho ldquoA subcarrierselection combining technique for OFDM systemsrdquo IEICETransactions on Communications vol E86-B no 7 pp 2119ndash2124 2003

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VLSI Design

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Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

VLSI Design 3

Frequency

Fixed arrangement

Pilot

Data

(a) IEEE 80211g

Frequency

Pilot

Data

Adaptive arrangement

(b) DSA

Figure 2 Pilot subcarrier arrangement

Headersymbol

Datasymbol

Datasymbol

4 120583s4 120583s4 120583s8 120583s

Shortpreamble

Longpreamble

8 120583s

PLCP preamble

Figure 3 The OFDM frame structure

based on subcarrier information from 128 subcarriers Inother words the demapping process discards many datasignals The equalization process eliminates the effect of thetransmission channel by using the channel transfer functionestimated from long training sequences Finally Viterbidecoding process after demodulation and deinterleavingoutputs the reconstructed version of the original data

3 Fading Compensation

The received signals through the wireless channel are dis-torted by fading or noise as shown in Figure 5Therefore fad-ing compensationwhich estimates and compensates receivedsignal distortion is necessary in order to accurately decodethe received data

This section describes the fading compensation for DSAwe propose after explaining an example of preamble-basedfading compensation [6] for OFDM transmission

31 Preamble-Based Fading Compensation Figure 6 showsan overview of preamble-based fading compensation AfterFFT received preamble signals 119877pr

119898

are expressed as

119877pr119898

= 119886pr119898

119867119898+ 119885119898

(0 le 119898 le 119872 minus 1) (2)

where 119898 is the index of used subcarriers 119886pr119898

is theknown preamble signal and 119867

119898and 119885

119898represent ideal

channel response and noise channel response respectively[9] Received preamble signal 119877pr

119898

is compared to known

signal 119886pr119898

and estimated channel response 119898is calculated

as

119898

=

119877pr119898

119886pr119898

= 119867119898+

119885119898

119886pr119898

(0 le 119898 le 119872 minus 1) (3)

The primary compensated signal 119886119898is calculated by using

119898

119886119898

=119877119898

119898

(0 le 119898 le 119872 minus 1) (4)

where 119877119898is the received signal

Next secondary compensation with pilot subcarriers iscarried out to copewithmicrovariations in channel responsesin one OFDM symbol time The estimated microvariation inchannel response

119889119898

is expressed as

119889119898

= 119865 (119898 119897 (119899) 119886119901119894119897(119899)

) (5)

where 119898 is the index of data subcarriers 119897(119899) is the indexof pilot subcarriers and 119886

119901119894119897(119899)is that of the estimated

microvariation for pilot signals and 119865 is their interpolationfunction The secondary compensated signals 119886

119889119898

are givenby

119886119889119898

=

119886119889119898

119889119898

(0 le 119896 le 119872 minus 119871 minus 1) (6)

where 119871 is the number of pilot subcarriers

32 Fading Compensation for DSA In the IEEE 80211g fourof the subcarriers are dedicated to pilot signals in order tomake coherent detection robust against frequency offsets andphase noise These pilot signals are placed in ideal locations[10] Therefore the arithmetic mean can be utilized as thefunction to estimate channel microvariations However thearithmetic mean is not always efficient for OFDM with DSAsince DSA utilizes different distributions of pilot subcarriersin different communications This paper adopts piecewiselinear interpolation as the interpolation function to estimatethe channel responses for microvariations and evaluates theefficiency by comparingwith the arithmeticmeanThedetailsare described in the next subsection

4 VLSI Design

FEC Interleave Modulation

MappingDemapping

FFTIFFT

CPinsert

CPdelete

Viterbidecode Deinterleave Demodulation Channel

equalization

Spectrum intensity

Timingsynchronization

DA

AD

Figure 4 Block diagram of ODFM baseband transceiver with DSA

Transmittedsignal

Receivedsignal

I

Q

Distorted

Figure 5 Example of received signal distortion

321 Microvariation Estimation with Piecewise Linear Inter-polation The estimated microvariation for the target sub-carrier is calculated by linear interpolation between theestimated microvariation values for the left and right pilotsubcarriers shown in Figure 7 The proposed interpolationfunction is given by

119865 (119898 119894119889119909 left 119894119889119909 right)

=

(119894119889119909 right minus 119898) 119894119889119909 left + (119898 minus 119894119889119909 left)

119894119889119909 right

119894119889119909 right minus 119894119889119909 left

(7)

where 119898 is the index of the target subcarrier 119894119889119909 left and119894119889119909 right correspond to the index of the left and right pilotsubcarriers and

119894119889119909 left and 119894119889119909 right are the estimated varia-

tion values for the left and right pilot subcarriers respectively119894119889119909 left and

119894119889119909 right are expressed as

119894119889119909 left =

119886119894119889119909 left

119886119894119889119909 left

119894119889119909 right =

119886119894119889119909 right

119886119894119889119909 right

(8)

Table 2 Parameters for Rayleigh fading model

No of multipath 32Delay spread 50 nsDelay attenuation model Exponential decayMaximum Doppler frequency 20HzVariation period of multipath 0025 s (40Hz)Frequency offset 003Hzsymbol

Table 3 Conditions for preliminary experiment

No of efficient subcarriers 52128 (including 4 for pilot)Modulation BPSK QPSKNo of processed OFDM symbol Two millionPhysical layer frame size 1500 byteSNR 0sim25 dB 5 dB stepChannel model Rayleigh fading (Table 2)

322 Preliminary Experiment The preliminary experimentwas carried out through software simulation to confirm thatpiecewise linear interpolation had an advantage over thearithmetic mean in respect to the Bit Error Rate (BER)Software with floating points emulates the behavior of thetransceiver but symbol timing error is not taken into con-sideration

The Rayleigh fading model was used in the softwaresimulation whose parameters are summarized in Table 2 andsimulation conditions are listed in Table 3 Figure 8 plots theexperiment results for BER which is generally used as anindicator of the channel estimation accuracy This indicatesthat piecewise linear interpolation is more efficient than thearithmetic mean which is generally utilized in the 80211agPHYTherefore we adopted piecewise linear interpolation toestimate microvariations

4 Proposed Architecture of FadingCompensator for DSA

Figure 9 is a block diagram of the proposed fading com-pensator architecture The proposed architecture consists ofchannel estimator linear interpolator coefficient calculatorlinear projector and five memories

First the coefficient calculator stores 119894119889119909 left and119894119889119909 right obtained frommapping information in the 119894119889119909 left

VLSI Design 5

Coarsechannel

estimation

Receivedpreamble

signals

Estimatedchannelresponse

Primarycompensation

(exclude preamble)

Primarycompensated

signals

Secondarychannel estimationand interpolation

SecondarycompensationPrimary

compensateddata

signals

Primarycompensated

pilotsignals

Estimatedmicrovariation

Secondarycompensated

datasignals

Hm

am

Rm

Received signals

apil(n)

Rpr119898

ad119898

pd119898

ad119898

Figure 6 Preamble-based fading compensation

Interpolation line

Estimated value

Mapping condition

Data subcarriersPilot subcarriers

Unused subcarriers

Interpolation

0f

PfMicrovariationestimated value

Figure 7 Microvariation estimation with piecewise linear interpo-lation

0001

001

01

1

0 5 10 15 20 25

BER

SNR (dB)

BPSK (arithmetic)BPSK (piecewise)

QPSK (arithmetic)QPSK (piecewise)

Figure 8 Preliminary experiment results

memory and 119894119889119909 right memory respectively while receivingPLCP preamble signals Next the primary compensatedsignals are input and stored in the data buffer After all signalscorresponding to one OFDM symbol have been stored onedata at a time is read from the data buffer If the data is

Linearinterpolator

Channelestimator

Channelresponsememory

Coefficientcalculator

Linearprojector

Leftcoefficientmemory

Rightcoefficientmemory

Primarycompensated

data

Compensateddata

Databuffer

Leftmicrovariation

memory

Figure 9 Block diagram of proposed fading compensator

for the pilot the channel estimator calculates the estimatedmicrovariation value for the pilot and the value is written toboth left and right coefficient memories After all estimatedmicrovariation values for the pilots have been obtained theLinear interpolator calculates each estimated microvariationvalue for data by piecewise linear interpolation with thedistance between the target data subcarrier and two adjacentpilot subcarriers Finally the secondary compensated signalsfor data 119886

119889119898

are calculated from the primary compensatedsignals and estimated microvariation values for data in theLinear projector

41 Channel Estimator The block diagram of the channelestimator is shown in Figure 10

This block treats 119901119894119897(119899)

as amplitude variation 120572 andphase shift Δ120579 in a polar coordinate system in order toenable microvariations to be easily calculated Thereforereceived signals (119868 119876) in a rectangular coordinate system aretransformed to (119877 120579) in a polar coordinate system in thisblock The transformation from a rectangular coordinate toa polar coordinate is given by

119877 = radic1198682 + 1198762

120579 =

tanminus1119876119868

(119876 le 119868)

1

2120587 minus tanminus1 119868

119876(119876 gt 119868)

(9)

6 VLSI Design

12120579

Term

24Squareadd

14

14

120572

Δ120579

Phase shift

Amplitudevariation

Polar coordinate transformation circuitKnown signals

Primarycompensated

signalsQ

I

rP

120579P

11

12

12

12

12R

abs init tanminus1

table

Squareroot

(7 cycle)

Dividor(7 cycle)

Dividor(6 cycle)

Figure 10 Channel estimation block

The input size of the tanminus1 function is restricted to 11-bit by comparing 119868 with 119876 so that the tanminus1 function canbe constructed with a lookup table (LUT) All modules inthis block adopt a pipelined architecture and the square rootand divider both take seven cycles each Performing abs andsquare add take 1 cycle As a result the latency of this block is15 cycles

42 Coefficient Calculator The two data 119894119889119909 right and119894119889119909 left can be calculated with mapping information onlyTherefore the coefficient calculator obtains 119894119889119909 right and119894119889119909 left and stores them in memories while receiving longpreamble signals since the mapping information cannot bechanged in a physical layer (PHY) frame

The mapping information has two 128-bit data whereeach bit corresponds to each subcarrier The first data arecalled a utilization mask and indicate which subcarriers areused (1)unused (0) The second are called a pilot mask andindicate which subcarriers are pilot subcarriers (1) or not (0)Figure 11 is the block diagram of the coefficient calculatorThis block consists of subcarrier index generator subcarriertype checking block and coefficient generatorThe subcarrierindex generator and the coefficient generator are created by7-bit counter and the subcarrier type checking block is basedon a barrel shifter The two memories that have write accessfrom this block are dual port RAMs since thesememories alsohave read access from the linear interpolator How 119894119889119909 rightand 119894119889119909 left are determined by using these data is describedhereinafter

(1) First the 128-entry memory called the Right coeffi-cient memory is initialized to 1rsquos Next the utilizationand pilot masks are forward scanned with the sub-carrier index generator and subcarrier type checkingblock The contents of the Right coefficient memoryremain unchanged until the first detection of a pilotsubcarrier When a pilot subcarrier is detected thecorresponding entry in the right coefficient memoryis changed to 0 and then incremented values arewritten to the memory until the next pilot subcarrieris detected Figure 12 shows the contents of memoryafter this step has finished

(2) Since only 119894119889119909 right is utilized for the data subcarriers

that are at the right of the last pilot subcarrier corre-sponding entries for the Right coefficient memory tothe data subcarriers are overwritten by zero after step

Utilization mask Pilot mask

Subcarrier typechecking

128128

Coefficientgenerator

2

7

Coefficientcalculator

Rightcoefficientmemory

Leftcoefficientmemory

7

7

Subcarrierindex

generator

Figure 11 Block diagram of coefficient calculator

Right coefficient memoryLeft coefficient memory

1 1 mdash 1 2 3 4 mdash 1 1

f = 0Subcarrier index 1 2 3 4 Frequency

Pilotsubcarrier

Datasubcarrier

Figure 12 Contents of memory after step 1

1 has finished Figure 13 shows the contents ofmemoryafter this step has finished

(3) The left coefficients are determined in the same wayas those in step 1 with backward scanning and theyare stored in the left coefficient memory

(4) The entries corresponding to the subcarriers at the leftof the first pilot subcarrier are overwritten by zero inthe same way as that in step 2

Figure 14 shows the contents of memories after all stepsare executed

This step includes forward and backward scanning ofmapping information and each scan takes 128 cycles sinceutilization of the subcarrier index119891 asmemory read addressenables one cycle reading of pair coefficients from the Leftand Right coefficient memoriesThe execution cycles of steps2 and 4 are determined according to the pilot subcarrierarrangement The maximum execution cycle is 129 cycleswhen only one of 128 subcarriers is dedicated to the pilot

VLSI Design 7

Right coefficient memoryLeft coefficient memory

1 1 mdash 1 2 3 4 mdash 0 0

f = 0Subcarrier index 1 2 3 4 Frequency

Figure 13 Contents of memory after step 2

Right coefficient memory

Left coefficient memory1 1 mdash 1 2 3 4 mdash 0 00 0 mdash 4 3 2 1 mdash 1 1

f = 0Subcarrier index 1 2 3 4 Frequency

Right 2 left 3 (f = 4)

Figure 14 Contents of memory after coefficient calculation

signal The total execution cycles is at most 387 cycles sinceone cycle initialization and one cycle termination process areincluded

43 Linear Interpolator Figure 15 shows the block diagramof the linear interpolator This block has four multipliersand three adders and all of them have registered outputsTherefore the linear interpolator has ten pipeline stages sincethis block has a dividor that has seven pipeline stages

The linear interpolator performs two functions Oneis preparing the left and right estimated microvariationvalues

119894119889119909 left = (119886119894119889119909 left 120579119894119889119909 left) and

119894119889119909 right =

(119886119894119889119909 right 120579119894119889119909 right) The other is calculation of the estimated

microvariation value for data subcarriers 119889119898

= (119886119889119898

120579119889119898

)First the estimated microvariation values for pilot sub-

carriers are written in the left estimated microvariationmemory which is the output of the channel estimator Theentries corresponding to the subcarriers on the left of thefirst pilot subcarrier are written as zeroes The entries for theother subcarriers are written as the estimated microvariationvalues for the nearest pilot subcarrier on the left After allof the 128 entries have been written to the right estimatedmicrovariation values are obtained in the same way as theleft estimated microvariation values by backward-scanningthe left estimated microvariation memory and pilot maskEach of the estimated microvariation values for the datasubcarriers is calculated by linear interpolation (7) with theleft and right coefficients and the left and right estimatedmicrovariation values

These operations are executed at 285 cycles including128 cycles for writing 128 cycles for scanning 10 cycles formicrovariation calculations and 19 cycles for the initializingand terminating processes

Figure 16 shows how to utilize the left and right estimatedvalue

44 Linear Projection Block The secondary compensation iscarried out by linear projection operation with the estimatedmicrovariation value in the rectangular coordinate systemThe linear projection operation is given by

(119868

119876) =

1

119886(sin (minusΔ120579) minus cos (minusΔ120579)cos (minusΔ120579) sin (minusΔ120579)

)(1198681015840

1198761015840) (10)

Table 4 Maximum execution cycles

Blocks Maximum execution cyclesChannel estimation 15Coefficient calculator 387Linear interpolation 285Linear projection 4

Table 5 Implementation result

Occupied slice 157714336 (11)Used SRAM 234 kbitsMax frequency 112MHz

The block diagram of linear projection block is shownin Figure 17 This block can input data every cycle and tableaccess and multiplication and addition take 1 cycle As aresult the latency of this block is 4 cycles

45 Execution Cycles and Operation Frequency Table 4 sum-marizes the maximum execution cycles for each block in afading compensation circuit

When a block needs to terminate its process within 119873

OFDM symbol time (one ODFM symbol time is 4 120583s) duringreal-time operation theminimumoperation frequency119865minfor real-time operation is given by

119865min =119899

119873 sdot (40 times 10minus6) (11)

where 119899 is the number of execution cyclesSince it is necessary for the coefficient calculator to termi-

nate its process within two OFDM symbol times to receive alllong preamble signals the minimum operation frequency forreal-time operation is 483MHz (= 2(387times(40times10

minus6

)))Theexecution time for the channel estimator linear interpolatorand linear projector is 304 cycles for an OFDM symbolsince they need to perform their operations for the sameOFDM symbolTherefore theminimumoperation frequencyis 760MHz for these blocks

As a result the minimum operation frequency for theproposed fading compensator is 760MHz since the min-imum operation frequency of blocks excluding the coeffi-cient calculator is 760MHz and the minimum operationfrequency of the coefficient calculator is 483MHz

5 FPGA Design of Fading Compensator

51 Implementation Result The proposed architecture of thefading compensation circuit has been implemented in anFPGA (Xilinx Virtex-II xc2v3000) and Table 5 summarizesimplementation results This result surpasses the 760MHzdemanded for real-time operation

52 Performance Evaluation We simulated the performanceof this fading compensator without Viterbi decoding underthe conditions listed in Table 6 to confirm the behavior

8 VLSI Design

Rightcoefficientmemory

Leftmicrovariation

memory

Leftcoefficientmemory

Rightmicrovariation

register

7 Subcarrierindex

generator

7

7

1412

1214

19

21

2119

Dividor(6 cycles)

Dividor(7 cycles)

14

12

Linearinterpolator

14

12

2220

8

idx left idx left

idx left

idx left idx right

idx right

120572 dm

120579 dm

Figure 15 Block diagram of linear interpolator

Left estimated valueRight estimated value

f = 0 1 2 3 4 Subcarrier index Frequency

mdash mdashmdash mdash

1205911

120591112059111205911

1205911 1205911 1205911 1205911 1205912 1205912 1205912

12059121205912120591212059121205912

Pright = 1205911 Pright = 1205912

120591f = ( 120572fΔ120579f

)

Figure 16 Left and right estimated values

Amplitude variation120572 14Phase shift Δ120579 12

Input data I 12Q 12

Floating pointSignificant 11-bitExponent 4-bit

CompensateddataI12Q12

table tablecos(120579) sin(120579)

Figure 17 Linear projection block

Table 6 Simulation conditions

No of efficient subcarriers 52128 (including 4 for pilot)Modulation BPSK QPSKNo of Processed OFDM symbol Two millionPhysical layer frame size 1500 byteSNR 0sim25 dB 5 dB stepChannel model Rayleigh fading (Table 2)

of the proposed architecture Figure 18 shows the mappingcondition in this simulation

Figure 19 plots the simulation results for BER with hard-ware implementation These results show that the hard-ware implementation achieves comparable performance tothe 80211a-based system without the diversity reported in[11] even though our architecture utilizes a discontinuous

86 (pilot)

Frequency

64

67 92 (data)

73

11

5217

675823

Figure 18 Mapping condition

0001

001

01

1

0 5 10 15 20

BPSKQPSK

BPSK (11)QPSK (11)

BER

SNR (dB)

Figure 19 SNR versus BER

spectrum and its performance is almost the same as thetheoretical performance

6 Conclusion

In this paper a hardware architecture of fading compensationcircuit for DSA was proposed The proposed architectureadopted piecewise linear interpolation in order to accuratelyestimate channel responses for data subcarriers Fadingcompensation for an OFDM symbol was executed in oneOFDM symbol time in order to make increase of latency

VLSI Design 9

smaller The results of FPGA implementation indicated thatthe proposed circuit occupied 1577 slices and achieved112MHz operation frequency which overcame the 760MHzdemand for real-time operation on a single chip

Future work is the performance evaluation of the OFDMtransceiver with DSA combined with the proposed fadingcompensator

Acknowledgment

This research has been supported by the Global COE pro-gram of the Ministry of Education Culture Sports Scienceand Technology Japan under the title ldquoFounding AmbientInformation Society Infrastructurerdquo

References

[1] IEEE Std 80211g-2003 ldquoPart 11 Wireless LAN Medium AccessControl (MAC) and Physical Layer (PHY) SpecificationsAmendment 4 Further Higher Data Rate Extension in the 24GHz Bandrdquo June 2003

[2] Zigbee Alliance ldquoZigbee Specification Release 17rdquo ZigBee Doc-ument 053474r17 January 2008

[3] J D Poston and W D Horne ldquoDiscontiguous OFDM consid-erations for dynamic spectrum access in idle TV channelsrdquo inProceedings of the 1st IEEE International Symposium on NewFrontiers in Dynamic Spectrum Access Networks (DySPAN rsquo05)pp 607ndash610 November 2005

[4] S Miyamoto Y Goda and S Sampei ldquoDynamic subcarrierselection technique for cognitive wireless mesh networks usingcsmacardquo in Proceedings of International Workshop on SmartInfo-Media Systems in Bangkok (SISB rsquo08) pp 81ndash86 December2008

[5] L Tong B M Sadler and M Dong ldquoPilot-assisted wirelesstransmissionsrdquo IEEE Signal Processing Magazine vol 21 no 6pp 12ndash25 2004

[6] M Morikura and S Kubota ldquo80211 HIGH-SPEEDWIRELESSLAN TEXTBOOKrdquo Impress R amp D 2008

[7] M Hatanaka R Hashimoto T Tatsuka et al ldquoVLSI design ofOFDM baseband transceiver with dynamic spectrum accessrdquoin Proceedings of the 18th International Symposium on IntelligentSignal Processing and Communication Systems (ISPACS rsquo10) pp329ndash332 December 2010

[8] IEEE Std 80211a-1999 ldquoPart 11 Wireless LAN Medium AccessControl (MAC) and Physical Layer (PHY) Specifications High-Speed Physical Layer in the 5 GHz Bandrdquo June 2003

[9] HKobayashi ldquoFoundation andApplication ofOFDMCommu-nication Systemsrdquo triceps 2004

[10] S Adireddy L Tong and H Viswanathan ldquoOptimal placementof training for frequency-selective block-fading channelsrdquo IEEETransactions on Information Theory vol 48 no 8 pp 2338ndash2353 2002

[11] H K Jung W G Jeon K H Seo and Y S Cho ldquoA subcarrierselection combining technique for OFDM systemsrdquo IEICETransactions on Communications vol E86-B no 7 pp 2119ndash2124 2003

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International Journal of

4 VLSI Design

FEC Interleave Modulation

MappingDemapping

FFTIFFT

CPinsert

CPdelete

Viterbidecode Deinterleave Demodulation Channel

equalization

Spectrum intensity

Timingsynchronization

DA

AD

Figure 4 Block diagram of ODFM baseband transceiver with DSA

Transmittedsignal

Receivedsignal

I

Q

Distorted

Figure 5 Example of received signal distortion

321 Microvariation Estimation with Piecewise Linear Inter-polation The estimated microvariation for the target sub-carrier is calculated by linear interpolation between theestimated microvariation values for the left and right pilotsubcarriers shown in Figure 7 The proposed interpolationfunction is given by

119865 (119898 119894119889119909 left 119894119889119909 right)

=

(119894119889119909 right minus 119898) 119894119889119909 left + (119898 minus 119894119889119909 left)

119894119889119909 right

119894119889119909 right minus 119894119889119909 left

(7)

where 119898 is the index of the target subcarrier 119894119889119909 left and119894119889119909 right correspond to the index of the left and right pilotsubcarriers and

119894119889119909 left and 119894119889119909 right are the estimated varia-

tion values for the left and right pilot subcarriers respectively119894119889119909 left and

119894119889119909 right are expressed as

119894119889119909 left =

119886119894119889119909 left

119886119894119889119909 left

119894119889119909 right =

119886119894119889119909 right

119886119894119889119909 right

(8)

Table 2 Parameters for Rayleigh fading model

No of multipath 32Delay spread 50 nsDelay attenuation model Exponential decayMaximum Doppler frequency 20HzVariation period of multipath 0025 s (40Hz)Frequency offset 003Hzsymbol

Table 3 Conditions for preliminary experiment

No of efficient subcarriers 52128 (including 4 for pilot)Modulation BPSK QPSKNo of processed OFDM symbol Two millionPhysical layer frame size 1500 byteSNR 0sim25 dB 5 dB stepChannel model Rayleigh fading (Table 2)

322 Preliminary Experiment The preliminary experimentwas carried out through software simulation to confirm thatpiecewise linear interpolation had an advantage over thearithmetic mean in respect to the Bit Error Rate (BER)Software with floating points emulates the behavior of thetransceiver but symbol timing error is not taken into con-sideration

The Rayleigh fading model was used in the softwaresimulation whose parameters are summarized in Table 2 andsimulation conditions are listed in Table 3 Figure 8 plots theexperiment results for BER which is generally used as anindicator of the channel estimation accuracy This indicatesthat piecewise linear interpolation is more efficient than thearithmetic mean which is generally utilized in the 80211agPHYTherefore we adopted piecewise linear interpolation toestimate microvariations

4 Proposed Architecture of FadingCompensator for DSA

Figure 9 is a block diagram of the proposed fading com-pensator architecture The proposed architecture consists ofchannel estimator linear interpolator coefficient calculatorlinear projector and five memories

First the coefficient calculator stores 119894119889119909 left and119894119889119909 right obtained frommapping information in the 119894119889119909 left

VLSI Design 5

Coarsechannel

estimation

Receivedpreamble

signals

Estimatedchannelresponse

Primarycompensation

(exclude preamble)

Primarycompensated

signals

Secondarychannel estimationand interpolation

SecondarycompensationPrimary

compensateddata

signals

Primarycompensated

pilotsignals

Estimatedmicrovariation

Secondarycompensated

datasignals

Hm

am

Rm

Received signals

apil(n)

Rpr119898

ad119898

pd119898

ad119898

Figure 6 Preamble-based fading compensation

Interpolation line

Estimated value

Mapping condition

Data subcarriersPilot subcarriers

Unused subcarriers

Interpolation

0f

PfMicrovariationestimated value

Figure 7 Microvariation estimation with piecewise linear interpo-lation

0001

001

01

1

0 5 10 15 20 25

BER

SNR (dB)

BPSK (arithmetic)BPSK (piecewise)

QPSK (arithmetic)QPSK (piecewise)

Figure 8 Preliminary experiment results

memory and 119894119889119909 right memory respectively while receivingPLCP preamble signals Next the primary compensatedsignals are input and stored in the data buffer After all signalscorresponding to one OFDM symbol have been stored onedata at a time is read from the data buffer If the data is

Linearinterpolator

Channelestimator

Channelresponsememory

Coefficientcalculator

Linearprojector

Leftcoefficientmemory

Rightcoefficientmemory

Primarycompensated

data

Compensateddata

Databuffer

Leftmicrovariation

memory

Figure 9 Block diagram of proposed fading compensator

for the pilot the channel estimator calculates the estimatedmicrovariation value for the pilot and the value is written toboth left and right coefficient memories After all estimatedmicrovariation values for the pilots have been obtained theLinear interpolator calculates each estimated microvariationvalue for data by piecewise linear interpolation with thedistance between the target data subcarrier and two adjacentpilot subcarriers Finally the secondary compensated signalsfor data 119886

119889119898

are calculated from the primary compensatedsignals and estimated microvariation values for data in theLinear projector

41 Channel Estimator The block diagram of the channelestimator is shown in Figure 10

This block treats 119901119894119897(119899)

as amplitude variation 120572 andphase shift Δ120579 in a polar coordinate system in order toenable microvariations to be easily calculated Thereforereceived signals (119868 119876) in a rectangular coordinate system aretransformed to (119877 120579) in a polar coordinate system in thisblock The transformation from a rectangular coordinate toa polar coordinate is given by

119877 = radic1198682 + 1198762

120579 =

tanminus1119876119868

(119876 le 119868)

1

2120587 minus tanminus1 119868

119876(119876 gt 119868)

(9)

6 VLSI Design

12120579

Term

24Squareadd

14

14

120572

Δ120579

Phase shift

Amplitudevariation

Polar coordinate transformation circuitKnown signals

Primarycompensated

signalsQ

I

rP

120579P

11

12

12

12

12R

abs init tanminus1

table

Squareroot

(7 cycle)

Dividor(7 cycle)

Dividor(6 cycle)

Figure 10 Channel estimation block

The input size of the tanminus1 function is restricted to 11-bit by comparing 119868 with 119876 so that the tanminus1 function canbe constructed with a lookup table (LUT) All modules inthis block adopt a pipelined architecture and the square rootand divider both take seven cycles each Performing abs andsquare add take 1 cycle As a result the latency of this block is15 cycles

42 Coefficient Calculator The two data 119894119889119909 right and119894119889119909 left can be calculated with mapping information onlyTherefore the coefficient calculator obtains 119894119889119909 right and119894119889119909 left and stores them in memories while receiving longpreamble signals since the mapping information cannot bechanged in a physical layer (PHY) frame

The mapping information has two 128-bit data whereeach bit corresponds to each subcarrier The first data arecalled a utilization mask and indicate which subcarriers areused (1)unused (0) The second are called a pilot mask andindicate which subcarriers are pilot subcarriers (1) or not (0)Figure 11 is the block diagram of the coefficient calculatorThis block consists of subcarrier index generator subcarriertype checking block and coefficient generatorThe subcarrierindex generator and the coefficient generator are created by7-bit counter and the subcarrier type checking block is basedon a barrel shifter The two memories that have write accessfrom this block are dual port RAMs since thesememories alsohave read access from the linear interpolator How 119894119889119909 rightand 119894119889119909 left are determined by using these data is describedhereinafter

(1) First the 128-entry memory called the Right coeffi-cient memory is initialized to 1rsquos Next the utilizationand pilot masks are forward scanned with the sub-carrier index generator and subcarrier type checkingblock The contents of the Right coefficient memoryremain unchanged until the first detection of a pilotsubcarrier When a pilot subcarrier is detected thecorresponding entry in the right coefficient memoryis changed to 0 and then incremented values arewritten to the memory until the next pilot subcarrieris detected Figure 12 shows the contents of memoryafter this step has finished

(2) Since only 119894119889119909 right is utilized for the data subcarriers

that are at the right of the last pilot subcarrier corre-sponding entries for the Right coefficient memory tothe data subcarriers are overwritten by zero after step

Utilization mask Pilot mask

Subcarrier typechecking

128128

Coefficientgenerator

2

7

Coefficientcalculator

Rightcoefficientmemory

Leftcoefficientmemory

7

7

Subcarrierindex

generator

Figure 11 Block diagram of coefficient calculator

Right coefficient memoryLeft coefficient memory

1 1 mdash 1 2 3 4 mdash 1 1

f = 0Subcarrier index 1 2 3 4 Frequency

Pilotsubcarrier

Datasubcarrier

Figure 12 Contents of memory after step 1

1 has finished Figure 13 shows the contents ofmemoryafter this step has finished

(3) The left coefficients are determined in the same wayas those in step 1 with backward scanning and theyare stored in the left coefficient memory

(4) The entries corresponding to the subcarriers at the leftof the first pilot subcarrier are overwritten by zero inthe same way as that in step 2

Figure 14 shows the contents of memories after all stepsare executed

This step includes forward and backward scanning ofmapping information and each scan takes 128 cycles sinceutilization of the subcarrier index119891 asmemory read addressenables one cycle reading of pair coefficients from the Leftand Right coefficient memoriesThe execution cycles of steps2 and 4 are determined according to the pilot subcarrierarrangement The maximum execution cycle is 129 cycleswhen only one of 128 subcarriers is dedicated to the pilot

VLSI Design 7

Right coefficient memoryLeft coefficient memory

1 1 mdash 1 2 3 4 mdash 0 0

f = 0Subcarrier index 1 2 3 4 Frequency

Figure 13 Contents of memory after step 2

Right coefficient memory

Left coefficient memory1 1 mdash 1 2 3 4 mdash 0 00 0 mdash 4 3 2 1 mdash 1 1

f = 0Subcarrier index 1 2 3 4 Frequency

Right 2 left 3 (f = 4)

Figure 14 Contents of memory after coefficient calculation

signal The total execution cycles is at most 387 cycles sinceone cycle initialization and one cycle termination process areincluded

43 Linear Interpolator Figure 15 shows the block diagramof the linear interpolator This block has four multipliersand three adders and all of them have registered outputsTherefore the linear interpolator has ten pipeline stages sincethis block has a dividor that has seven pipeline stages

The linear interpolator performs two functions Oneis preparing the left and right estimated microvariationvalues

119894119889119909 left = (119886119894119889119909 left 120579119894119889119909 left) and

119894119889119909 right =

(119886119894119889119909 right 120579119894119889119909 right) The other is calculation of the estimated

microvariation value for data subcarriers 119889119898

= (119886119889119898

120579119889119898

)First the estimated microvariation values for pilot sub-

carriers are written in the left estimated microvariationmemory which is the output of the channel estimator Theentries corresponding to the subcarriers on the left of thefirst pilot subcarrier are written as zeroes The entries for theother subcarriers are written as the estimated microvariationvalues for the nearest pilot subcarrier on the left After allof the 128 entries have been written to the right estimatedmicrovariation values are obtained in the same way as theleft estimated microvariation values by backward-scanningthe left estimated microvariation memory and pilot maskEach of the estimated microvariation values for the datasubcarriers is calculated by linear interpolation (7) with theleft and right coefficients and the left and right estimatedmicrovariation values

These operations are executed at 285 cycles including128 cycles for writing 128 cycles for scanning 10 cycles formicrovariation calculations and 19 cycles for the initializingand terminating processes

Figure 16 shows how to utilize the left and right estimatedvalue

44 Linear Projection Block The secondary compensation iscarried out by linear projection operation with the estimatedmicrovariation value in the rectangular coordinate systemThe linear projection operation is given by

(119868

119876) =

1

119886(sin (minusΔ120579) minus cos (minusΔ120579)cos (minusΔ120579) sin (minusΔ120579)

)(1198681015840

1198761015840) (10)

Table 4 Maximum execution cycles

Blocks Maximum execution cyclesChannel estimation 15Coefficient calculator 387Linear interpolation 285Linear projection 4

Table 5 Implementation result

Occupied slice 157714336 (11)Used SRAM 234 kbitsMax frequency 112MHz

The block diagram of linear projection block is shownin Figure 17 This block can input data every cycle and tableaccess and multiplication and addition take 1 cycle As aresult the latency of this block is 4 cycles

45 Execution Cycles and Operation Frequency Table 4 sum-marizes the maximum execution cycles for each block in afading compensation circuit

When a block needs to terminate its process within 119873

OFDM symbol time (one ODFM symbol time is 4 120583s) duringreal-time operation theminimumoperation frequency119865minfor real-time operation is given by

119865min =119899

119873 sdot (40 times 10minus6) (11)

where 119899 is the number of execution cyclesSince it is necessary for the coefficient calculator to termi-

nate its process within two OFDM symbol times to receive alllong preamble signals the minimum operation frequency forreal-time operation is 483MHz (= 2(387times(40times10

minus6

)))Theexecution time for the channel estimator linear interpolatorand linear projector is 304 cycles for an OFDM symbolsince they need to perform their operations for the sameOFDM symbolTherefore theminimumoperation frequencyis 760MHz for these blocks

As a result the minimum operation frequency for theproposed fading compensator is 760MHz since the min-imum operation frequency of blocks excluding the coeffi-cient calculator is 760MHz and the minimum operationfrequency of the coefficient calculator is 483MHz

5 FPGA Design of Fading Compensator

51 Implementation Result The proposed architecture of thefading compensation circuit has been implemented in anFPGA (Xilinx Virtex-II xc2v3000) and Table 5 summarizesimplementation results This result surpasses the 760MHzdemanded for real-time operation

52 Performance Evaluation We simulated the performanceof this fading compensator without Viterbi decoding underthe conditions listed in Table 6 to confirm the behavior

8 VLSI Design

Rightcoefficientmemory

Leftmicrovariation

memory

Leftcoefficientmemory

Rightmicrovariation

register

7 Subcarrierindex

generator

7

7

1412

1214

19

21

2119

Dividor(6 cycles)

Dividor(7 cycles)

14

12

Linearinterpolator

14

12

2220

8

idx left idx left

idx left

idx left idx right

idx right

120572 dm

120579 dm

Figure 15 Block diagram of linear interpolator

Left estimated valueRight estimated value

f = 0 1 2 3 4 Subcarrier index Frequency

mdash mdashmdash mdash

1205911

120591112059111205911

1205911 1205911 1205911 1205911 1205912 1205912 1205912

12059121205912120591212059121205912

Pright = 1205911 Pright = 1205912

120591f = ( 120572fΔ120579f

)

Figure 16 Left and right estimated values

Amplitude variation120572 14Phase shift Δ120579 12

Input data I 12Q 12

Floating pointSignificant 11-bitExponent 4-bit

CompensateddataI12Q12

table tablecos(120579) sin(120579)

Figure 17 Linear projection block

Table 6 Simulation conditions

No of efficient subcarriers 52128 (including 4 for pilot)Modulation BPSK QPSKNo of Processed OFDM symbol Two millionPhysical layer frame size 1500 byteSNR 0sim25 dB 5 dB stepChannel model Rayleigh fading (Table 2)

of the proposed architecture Figure 18 shows the mappingcondition in this simulation

Figure 19 plots the simulation results for BER with hard-ware implementation These results show that the hard-ware implementation achieves comparable performance tothe 80211a-based system without the diversity reported in[11] even though our architecture utilizes a discontinuous

86 (pilot)

Frequency

64

67 92 (data)

73

11

5217

675823

Figure 18 Mapping condition

0001

001

01

1

0 5 10 15 20

BPSKQPSK

BPSK (11)QPSK (11)

BER

SNR (dB)

Figure 19 SNR versus BER

spectrum and its performance is almost the same as thetheoretical performance

6 Conclusion

In this paper a hardware architecture of fading compensationcircuit for DSA was proposed The proposed architectureadopted piecewise linear interpolation in order to accuratelyestimate channel responses for data subcarriers Fadingcompensation for an OFDM symbol was executed in oneOFDM symbol time in order to make increase of latency

VLSI Design 9

smaller The results of FPGA implementation indicated thatthe proposed circuit occupied 1577 slices and achieved112MHz operation frequency which overcame the 760MHzdemand for real-time operation on a single chip

Future work is the performance evaluation of the OFDMtransceiver with DSA combined with the proposed fadingcompensator

Acknowledgment

This research has been supported by the Global COE pro-gram of the Ministry of Education Culture Sports Scienceand Technology Japan under the title ldquoFounding AmbientInformation Society Infrastructurerdquo

References

[1] IEEE Std 80211g-2003 ldquoPart 11 Wireless LAN Medium AccessControl (MAC) and Physical Layer (PHY) SpecificationsAmendment 4 Further Higher Data Rate Extension in the 24GHz Bandrdquo June 2003

[2] Zigbee Alliance ldquoZigbee Specification Release 17rdquo ZigBee Doc-ument 053474r17 January 2008

[3] J D Poston and W D Horne ldquoDiscontiguous OFDM consid-erations for dynamic spectrum access in idle TV channelsrdquo inProceedings of the 1st IEEE International Symposium on NewFrontiers in Dynamic Spectrum Access Networks (DySPAN rsquo05)pp 607ndash610 November 2005

[4] S Miyamoto Y Goda and S Sampei ldquoDynamic subcarrierselection technique for cognitive wireless mesh networks usingcsmacardquo in Proceedings of International Workshop on SmartInfo-Media Systems in Bangkok (SISB rsquo08) pp 81ndash86 December2008

[5] L Tong B M Sadler and M Dong ldquoPilot-assisted wirelesstransmissionsrdquo IEEE Signal Processing Magazine vol 21 no 6pp 12ndash25 2004

[6] M Morikura and S Kubota ldquo80211 HIGH-SPEEDWIRELESSLAN TEXTBOOKrdquo Impress R amp D 2008

[7] M Hatanaka R Hashimoto T Tatsuka et al ldquoVLSI design ofOFDM baseband transceiver with dynamic spectrum accessrdquoin Proceedings of the 18th International Symposium on IntelligentSignal Processing and Communication Systems (ISPACS rsquo10) pp329ndash332 December 2010

[8] IEEE Std 80211a-1999 ldquoPart 11 Wireless LAN Medium AccessControl (MAC) and Physical Layer (PHY) Specifications High-Speed Physical Layer in the 5 GHz Bandrdquo June 2003

[9] HKobayashi ldquoFoundation andApplication ofOFDMCommu-nication Systemsrdquo triceps 2004

[10] S Adireddy L Tong and H Viswanathan ldquoOptimal placementof training for frequency-selective block-fading channelsrdquo IEEETransactions on Information Theory vol 48 no 8 pp 2338ndash2353 2002

[11] H K Jung W G Jeon K H Seo and Y S Cho ldquoA subcarrierselection combining technique for OFDM systemsrdquo IEICETransactions on Communications vol E86-B no 7 pp 2119ndash2124 2003

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

VLSI Design 5

Coarsechannel

estimation

Receivedpreamble

signals

Estimatedchannelresponse

Primarycompensation

(exclude preamble)

Primarycompensated

signals

Secondarychannel estimationand interpolation

SecondarycompensationPrimary

compensateddata

signals

Primarycompensated

pilotsignals

Estimatedmicrovariation

Secondarycompensated

datasignals

Hm

am

Rm

Received signals

apil(n)

Rpr119898

ad119898

pd119898

ad119898

Figure 6 Preamble-based fading compensation

Interpolation line

Estimated value

Mapping condition

Data subcarriersPilot subcarriers

Unused subcarriers

Interpolation

0f

PfMicrovariationestimated value

Figure 7 Microvariation estimation with piecewise linear interpo-lation

0001

001

01

1

0 5 10 15 20 25

BER

SNR (dB)

BPSK (arithmetic)BPSK (piecewise)

QPSK (arithmetic)QPSK (piecewise)

Figure 8 Preliminary experiment results

memory and 119894119889119909 right memory respectively while receivingPLCP preamble signals Next the primary compensatedsignals are input and stored in the data buffer After all signalscorresponding to one OFDM symbol have been stored onedata at a time is read from the data buffer If the data is

Linearinterpolator

Channelestimator

Channelresponsememory

Coefficientcalculator

Linearprojector

Leftcoefficientmemory

Rightcoefficientmemory

Primarycompensated

data

Compensateddata

Databuffer

Leftmicrovariation

memory

Figure 9 Block diagram of proposed fading compensator

for the pilot the channel estimator calculates the estimatedmicrovariation value for the pilot and the value is written toboth left and right coefficient memories After all estimatedmicrovariation values for the pilots have been obtained theLinear interpolator calculates each estimated microvariationvalue for data by piecewise linear interpolation with thedistance between the target data subcarrier and two adjacentpilot subcarriers Finally the secondary compensated signalsfor data 119886

119889119898

are calculated from the primary compensatedsignals and estimated microvariation values for data in theLinear projector

41 Channel Estimator The block diagram of the channelestimator is shown in Figure 10

This block treats 119901119894119897(119899)

as amplitude variation 120572 andphase shift Δ120579 in a polar coordinate system in order toenable microvariations to be easily calculated Thereforereceived signals (119868 119876) in a rectangular coordinate system aretransformed to (119877 120579) in a polar coordinate system in thisblock The transformation from a rectangular coordinate toa polar coordinate is given by

119877 = radic1198682 + 1198762

120579 =

tanminus1119876119868

(119876 le 119868)

1

2120587 minus tanminus1 119868

119876(119876 gt 119868)

(9)

6 VLSI Design

12120579

Term

24Squareadd

14

14

120572

Δ120579

Phase shift

Amplitudevariation

Polar coordinate transformation circuitKnown signals

Primarycompensated

signalsQ

I

rP

120579P

11

12

12

12

12R

abs init tanminus1

table

Squareroot

(7 cycle)

Dividor(7 cycle)

Dividor(6 cycle)

Figure 10 Channel estimation block

The input size of the tanminus1 function is restricted to 11-bit by comparing 119868 with 119876 so that the tanminus1 function canbe constructed with a lookup table (LUT) All modules inthis block adopt a pipelined architecture and the square rootand divider both take seven cycles each Performing abs andsquare add take 1 cycle As a result the latency of this block is15 cycles

42 Coefficient Calculator The two data 119894119889119909 right and119894119889119909 left can be calculated with mapping information onlyTherefore the coefficient calculator obtains 119894119889119909 right and119894119889119909 left and stores them in memories while receiving longpreamble signals since the mapping information cannot bechanged in a physical layer (PHY) frame

The mapping information has two 128-bit data whereeach bit corresponds to each subcarrier The first data arecalled a utilization mask and indicate which subcarriers areused (1)unused (0) The second are called a pilot mask andindicate which subcarriers are pilot subcarriers (1) or not (0)Figure 11 is the block diagram of the coefficient calculatorThis block consists of subcarrier index generator subcarriertype checking block and coefficient generatorThe subcarrierindex generator and the coefficient generator are created by7-bit counter and the subcarrier type checking block is basedon a barrel shifter The two memories that have write accessfrom this block are dual port RAMs since thesememories alsohave read access from the linear interpolator How 119894119889119909 rightand 119894119889119909 left are determined by using these data is describedhereinafter

(1) First the 128-entry memory called the Right coeffi-cient memory is initialized to 1rsquos Next the utilizationand pilot masks are forward scanned with the sub-carrier index generator and subcarrier type checkingblock The contents of the Right coefficient memoryremain unchanged until the first detection of a pilotsubcarrier When a pilot subcarrier is detected thecorresponding entry in the right coefficient memoryis changed to 0 and then incremented values arewritten to the memory until the next pilot subcarrieris detected Figure 12 shows the contents of memoryafter this step has finished

(2) Since only 119894119889119909 right is utilized for the data subcarriers

that are at the right of the last pilot subcarrier corre-sponding entries for the Right coefficient memory tothe data subcarriers are overwritten by zero after step

Utilization mask Pilot mask

Subcarrier typechecking

128128

Coefficientgenerator

2

7

Coefficientcalculator

Rightcoefficientmemory

Leftcoefficientmemory

7

7

Subcarrierindex

generator

Figure 11 Block diagram of coefficient calculator

Right coefficient memoryLeft coefficient memory

1 1 mdash 1 2 3 4 mdash 1 1

f = 0Subcarrier index 1 2 3 4 Frequency

Pilotsubcarrier

Datasubcarrier

Figure 12 Contents of memory after step 1

1 has finished Figure 13 shows the contents ofmemoryafter this step has finished

(3) The left coefficients are determined in the same wayas those in step 1 with backward scanning and theyare stored in the left coefficient memory

(4) The entries corresponding to the subcarriers at the leftof the first pilot subcarrier are overwritten by zero inthe same way as that in step 2

Figure 14 shows the contents of memories after all stepsare executed

This step includes forward and backward scanning ofmapping information and each scan takes 128 cycles sinceutilization of the subcarrier index119891 asmemory read addressenables one cycle reading of pair coefficients from the Leftand Right coefficient memoriesThe execution cycles of steps2 and 4 are determined according to the pilot subcarrierarrangement The maximum execution cycle is 129 cycleswhen only one of 128 subcarriers is dedicated to the pilot

VLSI Design 7

Right coefficient memoryLeft coefficient memory

1 1 mdash 1 2 3 4 mdash 0 0

f = 0Subcarrier index 1 2 3 4 Frequency

Figure 13 Contents of memory after step 2

Right coefficient memory

Left coefficient memory1 1 mdash 1 2 3 4 mdash 0 00 0 mdash 4 3 2 1 mdash 1 1

f = 0Subcarrier index 1 2 3 4 Frequency

Right 2 left 3 (f = 4)

Figure 14 Contents of memory after coefficient calculation

signal The total execution cycles is at most 387 cycles sinceone cycle initialization and one cycle termination process areincluded

43 Linear Interpolator Figure 15 shows the block diagramof the linear interpolator This block has four multipliersand three adders and all of them have registered outputsTherefore the linear interpolator has ten pipeline stages sincethis block has a dividor that has seven pipeline stages

The linear interpolator performs two functions Oneis preparing the left and right estimated microvariationvalues

119894119889119909 left = (119886119894119889119909 left 120579119894119889119909 left) and

119894119889119909 right =

(119886119894119889119909 right 120579119894119889119909 right) The other is calculation of the estimated

microvariation value for data subcarriers 119889119898

= (119886119889119898

120579119889119898

)First the estimated microvariation values for pilot sub-

carriers are written in the left estimated microvariationmemory which is the output of the channel estimator Theentries corresponding to the subcarriers on the left of thefirst pilot subcarrier are written as zeroes The entries for theother subcarriers are written as the estimated microvariationvalues for the nearest pilot subcarrier on the left After allof the 128 entries have been written to the right estimatedmicrovariation values are obtained in the same way as theleft estimated microvariation values by backward-scanningthe left estimated microvariation memory and pilot maskEach of the estimated microvariation values for the datasubcarriers is calculated by linear interpolation (7) with theleft and right coefficients and the left and right estimatedmicrovariation values

These operations are executed at 285 cycles including128 cycles for writing 128 cycles for scanning 10 cycles formicrovariation calculations and 19 cycles for the initializingand terminating processes

Figure 16 shows how to utilize the left and right estimatedvalue

44 Linear Projection Block The secondary compensation iscarried out by linear projection operation with the estimatedmicrovariation value in the rectangular coordinate systemThe linear projection operation is given by

(119868

119876) =

1

119886(sin (minusΔ120579) minus cos (minusΔ120579)cos (minusΔ120579) sin (minusΔ120579)

)(1198681015840

1198761015840) (10)

Table 4 Maximum execution cycles

Blocks Maximum execution cyclesChannel estimation 15Coefficient calculator 387Linear interpolation 285Linear projection 4

Table 5 Implementation result

Occupied slice 157714336 (11)Used SRAM 234 kbitsMax frequency 112MHz

The block diagram of linear projection block is shownin Figure 17 This block can input data every cycle and tableaccess and multiplication and addition take 1 cycle As aresult the latency of this block is 4 cycles

45 Execution Cycles and Operation Frequency Table 4 sum-marizes the maximum execution cycles for each block in afading compensation circuit

When a block needs to terminate its process within 119873

OFDM symbol time (one ODFM symbol time is 4 120583s) duringreal-time operation theminimumoperation frequency119865minfor real-time operation is given by

119865min =119899

119873 sdot (40 times 10minus6) (11)

where 119899 is the number of execution cyclesSince it is necessary for the coefficient calculator to termi-

nate its process within two OFDM symbol times to receive alllong preamble signals the minimum operation frequency forreal-time operation is 483MHz (= 2(387times(40times10

minus6

)))Theexecution time for the channel estimator linear interpolatorand linear projector is 304 cycles for an OFDM symbolsince they need to perform their operations for the sameOFDM symbolTherefore theminimumoperation frequencyis 760MHz for these blocks

As a result the minimum operation frequency for theproposed fading compensator is 760MHz since the min-imum operation frequency of blocks excluding the coeffi-cient calculator is 760MHz and the minimum operationfrequency of the coefficient calculator is 483MHz

5 FPGA Design of Fading Compensator

51 Implementation Result The proposed architecture of thefading compensation circuit has been implemented in anFPGA (Xilinx Virtex-II xc2v3000) and Table 5 summarizesimplementation results This result surpasses the 760MHzdemanded for real-time operation

52 Performance Evaluation We simulated the performanceof this fading compensator without Viterbi decoding underthe conditions listed in Table 6 to confirm the behavior

8 VLSI Design

Rightcoefficientmemory

Leftmicrovariation

memory

Leftcoefficientmemory

Rightmicrovariation

register

7 Subcarrierindex

generator

7

7

1412

1214

19

21

2119

Dividor(6 cycles)

Dividor(7 cycles)

14

12

Linearinterpolator

14

12

2220

8

idx left idx left

idx left

idx left idx right

idx right

120572 dm

120579 dm

Figure 15 Block diagram of linear interpolator

Left estimated valueRight estimated value

f = 0 1 2 3 4 Subcarrier index Frequency

mdash mdashmdash mdash

1205911

120591112059111205911

1205911 1205911 1205911 1205911 1205912 1205912 1205912

12059121205912120591212059121205912

Pright = 1205911 Pright = 1205912

120591f = ( 120572fΔ120579f

)

Figure 16 Left and right estimated values

Amplitude variation120572 14Phase shift Δ120579 12

Input data I 12Q 12

Floating pointSignificant 11-bitExponent 4-bit

CompensateddataI12Q12

table tablecos(120579) sin(120579)

Figure 17 Linear projection block

Table 6 Simulation conditions

No of efficient subcarriers 52128 (including 4 for pilot)Modulation BPSK QPSKNo of Processed OFDM symbol Two millionPhysical layer frame size 1500 byteSNR 0sim25 dB 5 dB stepChannel model Rayleigh fading (Table 2)

of the proposed architecture Figure 18 shows the mappingcondition in this simulation

Figure 19 plots the simulation results for BER with hard-ware implementation These results show that the hard-ware implementation achieves comparable performance tothe 80211a-based system without the diversity reported in[11] even though our architecture utilizes a discontinuous

86 (pilot)

Frequency

64

67 92 (data)

73

11

5217

675823

Figure 18 Mapping condition

0001

001

01

1

0 5 10 15 20

BPSKQPSK

BPSK (11)QPSK (11)

BER

SNR (dB)

Figure 19 SNR versus BER

spectrum and its performance is almost the same as thetheoretical performance

6 Conclusion

In this paper a hardware architecture of fading compensationcircuit for DSA was proposed The proposed architectureadopted piecewise linear interpolation in order to accuratelyestimate channel responses for data subcarriers Fadingcompensation for an OFDM symbol was executed in oneOFDM symbol time in order to make increase of latency

VLSI Design 9

smaller The results of FPGA implementation indicated thatthe proposed circuit occupied 1577 slices and achieved112MHz operation frequency which overcame the 760MHzdemand for real-time operation on a single chip

Future work is the performance evaluation of the OFDMtransceiver with DSA combined with the proposed fadingcompensator

Acknowledgment

This research has been supported by the Global COE pro-gram of the Ministry of Education Culture Sports Scienceand Technology Japan under the title ldquoFounding AmbientInformation Society Infrastructurerdquo

References

[1] IEEE Std 80211g-2003 ldquoPart 11 Wireless LAN Medium AccessControl (MAC) and Physical Layer (PHY) SpecificationsAmendment 4 Further Higher Data Rate Extension in the 24GHz Bandrdquo June 2003

[2] Zigbee Alliance ldquoZigbee Specification Release 17rdquo ZigBee Doc-ument 053474r17 January 2008

[3] J D Poston and W D Horne ldquoDiscontiguous OFDM consid-erations for dynamic spectrum access in idle TV channelsrdquo inProceedings of the 1st IEEE International Symposium on NewFrontiers in Dynamic Spectrum Access Networks (DySPAN rsquo05)pp 607ndash610 November 2005

[4] S Miyamoto Y Goda and S Sampei ldquoDynamic subcarrierselection technique for cognitive wireless mesh networks usingcsmacardquo in Proceedings of International Workshop on SmartInfo-Media Systems in Bangkok (SISB rsquo08) pp 81ndash86 December2008

[5] L Tong B M Sadler and M Dong ldquoPilot-assisted wirelesstransmissionsrdquo IEEE Signal Processing Magazine vol 21 no 6pp 12ndash25 2004

[6] M Morikura and S Kubota ldquo80211 HIGH-SPEEDWIRELESSLAN TEXTBOOKrdquo Impress R amp D 2008

[7] M Hatanaka R Hashimoto T Tatsuka et al ldquoVLSI design ofOFDM baseband transceiver with dynamic spectrum accessrdquoin Proceedings of the 18th International Symposium on IntelligentSignal Processing and Communication Systems (ISPACS rsquo10) pp329ndash332 December 2010

[8] IEEE Std 80211a-1999 ldquoPart 11 Wireless LAN Medium AccessControl (MAC) and Physical Layer (PHY) Specifications High-Speed Physical Layer in the 5 GHz Bandrdquo June 2003

[9] HKobayashi ldquoFoundation andApplication ofOFDMCommu-nication Systemsrdquo triceps 2004

[10] S Adireddy L Tong and H Viswanathan ldquoOptimal placementof training for frequency-selective block-fading channelsrdquo IEEETransactions on Information Theory vol 48 no 8 pp 2338ndash2353 2002

[11] H K Jung W G Jeon K H Seo and Y S Cho ldquoA subcarrierselection combining technique for OFDM systemsrdquo IEICETransactions on Communications vol E86-B no 7 pp 2119ndash2124 2003

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

6 VLSI Design

12120579

Term

24Squareadd

14

14

120572

Δ120579

Phase shift

Amplitudevariation

Polar coordinate transformation circuitKnown signals

Primarycompensated

signalsQ

I

rP

120579P

11

12

12

12

12R

abs init tanminus1

table

Squareroot

(7 cycle)

Dividor(7 cycle)

Dividor(6 cycle)

Figure 10 Channel estimation block

The input size of the tanminus1 function is restricted to 11-bit by comparing 119868 with 119876 so that the tanminus1 function canbe constructed with a lookup table (LUT) All modules inthis block adopt a pipelined architecture and the square rootand divider both take seven cycles each Performing abs andsquare add take 1 cycle As a result the latency of this block is15 cycles

42 Coefficient Calculator The two data 119894119889119909 right and119894119889119909 left can be calculated with mapping information onlyTherefore the coefficient calculator obtains 119894119889119909 right and119894119889119909 left and stores them in memories while receiving longpreamble signals since the mapping information cannot bechanged in a physical layer (PHY) frame

The mapping information has two 128-bit data whereeach bit corresponds to each subcarrier The first data arecalled a utilization mask and indicate which subcarriers areused (1)unused (0) The second are called a pilot mask andindicate which subcarriers are pilot subcarriers (1) or not (0)Figure 11 is the block diagram of the coefficient calculatorThis block consists of subcarrier index generator subcarriertype checking block and coefficient generatorThe subcarrierindex generator and the coefficient generator are created by7-bit counter and the subcarrier type checking block is basedon a barrel shifter The two memories that have write accessfrom this block are dual port RAMs since thesememories alsohave read access from the linear interpolator How 119894119889119909 rightand 119894119889119909 left are determined by using these data is describedhereinafter

(1) First the 128-entry memory called the Right coeffi-cient memory is initialized to 1rsquos Next the utilizationand pilot masks are forward scanned with the sub-carrier index generator and subcarrier type checkingblock The contents of the Right coefficient memoryremain unchanged until the first detection of a pilotsubcarrier When a pilot subcarrier is detected thecorresponding entry in the right coefficient memoryis changed to 0 and then incremented values arewritten to the memory until the next pilot subcarrieris detected Figure 12 shows the contents of memoryafter this step has finished

(2) Since only 119894119889119909 right is utilized for the data subcarriers

that are at the right of the last pilot subcarrier corre-sponding entries for the Right coefficient memory tothe data subcarriers are overwritten by zero after step

Utilization mask Pilot mask

Subcarrier typechecking

128128

Coefficientgenerator

2

7

Coefficientcalculator

Rightcoefficientmemory

Leftcoefficientmemory

7

7

Subcarrierindex

generator

Figure 11 Block diagram of coefficient calculator

Right coefficient memoryLeft coefficient memory

1 1 mdash 1 2 3 4 mdash 1 1

f = 0Subcarrier index 1 2 3 4 Frequency

Pilotsubcarrier

Datasubcarrier

Figure 12 Contents of memory after step 1

1 has finished Figure 13 shows the contents ofmemoryafter this step has finished

(3) The left coefficients are determined in the same wayas those in step 1 with backward scanning and theyare stored in the left coefficient memory

(4) The entries corresponding to the subcarriers at the leftof the first pilot subcarrier are overwritten by zero inthe same way as that in step 2

Figure 14 shows the contents of memories after all stepsare executed

This step includes forward and backward scanning ofmapping information and each scan takes 128 cycles sinceutilization of the subcarrier index119891 asmemory read addressenables one cycle reading of pair coefficients from the Leftand Right coefficient memoriesThe execution cycles of steps2 and 4 are determined according to the pilot subcarrierarrangement The maximum execution cycle is 129 cycleswhen only one of 128 subcarriers is dedicated to the pilot

VLSI Design 7

Right coefficient memoryLeft coefficient memory

1 1 mdash 1 2 3 4 mdash 0 0

f = 0Subcarrier index 1 2 3 4 Frequency

Figure 13 Contents of memory after step 2

Right coefficient memory

Left coefficient memory1 1 mdash 1 2 3 4 mdash 0 00 0 mdash 4 3 2 1 mdash 1 1

f = 0Subcarrier index 1 2 3 4 Frequency

Right 2 left 3 (f = 4)

Figure 14 Contents of memory after coefficient calculation

signal The total execution cycles is at most 387 cycles sinceone cycle initialization and one cycle termination process areincluded

43 Linear Interpolator Figure 15 shows the block diagramof the linear interpolator This block has four multipliersand three adders and all of them have registered outputsTherefore the linear interpolator has ten pipeline stages sincethis block has a dividor that has seven pipeline stages

The linear interpolator performs two functions Oneis preparing the left and right estimated microvariationvalues

119894119889119909 left = (119886119894119889119909 left 120579119894119889119909 left) and

119894119889119909 right =

(119886119894119889119909 right 120579119894119889119909 right) The other is calculation of the estimated

microvariation value for data subcarriers 119889119898

= (119886119889119898

120579119889119898

)First the estimated microvariation values for pilot sub-

carriers are written in the left estimated microvariationmemory which is the output of the channel estimator Theentries corresponding to the subcarriers on the left of thefirst pilot subcarrier are written as zeroes The entries for theother subcarriers are written as the estimated microvariationvalues for the nearest pilot subcarrier on the left After allof the 128 entries have been written to the right estimatedmicrovariation values are obtained in the same way as theleft estimated microvariation values by backward-scanningthe left estimated microvariation memory and pilot maskEach of the estimated microvariation values for the datasubcarriers is calculated by linear interpolation (7) with theleft and right coefficients and the left and right estimatedmicrovariation values

These operations are executed at 285 cycles including128 cycles for writing 128 cycles for scanning 10 cycles formicrovariation calculations and 19 cycles for the initializingand terminating processes

Figure 16 shows how to utilize the left and right estimatedvalue

44 Linear Projection Block The secondary compensation iscarried out by linear projection operation with the estimatedmicrovariation value in the rectangular coordinate systemThe linear projection operation is given by

(119868

119876) =

1

119886(sin (minusΔ120579) minus cos (minusΔ120579)cos (minusΔ120579) sin (minusΔ120579)

)(1198681015840

1198761015840) (10)

Table 4 Maximum execution cycles

Blocks Maximum execution cyclesChannel estimation 15Coefficient calculator 387Linear interpolation 285Linear projection 4

Table 5 Implementation result

Occupied slice 157714336 (11)Used SRAM 234 kbitsMax frequency 112MHz

The block diagram of linear projection block is shownin Figure 17 This block can input data every cycle and tableaccess and multiplication and addition take 1 cycle As aresult the latency of this block is 4 cycles

45 Execution Cycles and Operation Frequency Table 4 sum-marizes the maximum execution cycles for each block in afading compensation circuit

When a block needs to terminate its process within 119873

OFDM symbol time (one ODFM symbol time is 4 120583s) duringreal-time operation theminimumoperation frequency119865minfor real-time operation is given by

119865min =119899

119873 sdot (40 times 10minus6) (11)

where 119899 is the number of execution cyclesSince it is necessary for the coefficient calculator to termi-

nate its process within two OFDM symbol times to receive alllong preamble signals the minimum operation frequency forreal-time operation is 483MHz (= 2(387times(40times10

minus6

)))Theexecution time for the channel estimator linear interpolatorand linear projector is 304 cycles for an OFDM symbolsince they need to perform their operations for the sameOFDM symbolTherefore theminimumoperation frequencyis 760MHz for these blocks

As a result the minimum operation frequency for theproposed fading compensator is 760MHz since the min-imum operation frequency of blocks excluding the coeffi-cient calculator is 760MHz and the minimum operationfrequency of the coefficient calculator is 483MHz

5 FPGA Design of Fading Compensator

51 Implementation Result The proposed architecture of thefading compensation circuit has been implemented in anFPGA (Xilinx Virtex-II xc2v3000) and Table 5 summarizesimplementation results This result surpasses the 760MHzdemanded for real-time operation

52 Performance Evaluation We simulated the performanceof this fading compensator without Viterbi decoding underthe conditions listed in Table 6 to confirm the behavior

8 VLSI Design

Rightcoefficientmemory

Leftmicrovariation

memory

Leftcoefficientmemory

Rightmicrovariation

register

7 Subcarrierindex

generator

7

7

1412

1214

19

21

2119

Dividor(6 cycles)

Dividor(7 cycles)

14

12

Linearinterpolator

14

12

2220

8

idx left idx left

idx left

idx left idx right

idx right

120572 dm

120579 dm

Figure 15 Block diagram of linear interpolator

Left estimated valueRight estimated value

f = 0 1 2 3 4 Subcarrier index Frequency

mdash mdashmdash mdash

1205911

120591112059111205911

1205911 1205911 1205911 1205911 1205912 1205912 1205912

12059121205912120591212059121205912

Pright = 1205911 Pright = 1205912

120591f = ( 120572fΔ120579f

)

Figure 16 Left and right estimated values

Amplitude variation120572 14Phase shift Δ120579 12

Input data I 12Q 12

Floating pointSignificant 11-bitExponent 4-bit

CompensateddataI12Q12

table tablecos(120579) sin(120579)

Figure 17 Linear projection block

Table 6 Simulation conditions

No of efficient subcarriers 52128 (including 4 for pilot)Modulation BPSK QPSKNo of Processed OFDM symbol Two millionPhysical layer frame size 1500 byteSNR 0sim25 dB 5 dB stepChannel model Rayleigh fading (Table 2)

of the proposed architecture Figure 18 shows the mappingcondition in this simulation

Figure 19 plots the simulation results for BER with hard-ware implementation These results show that the hard-ware implementation achieves comparable performance tothe 80211a-based system without the diversity reported in[11] even though our architecture utilizes a discontinuous

86 (pilot)

Frequency

64

67 92 (data)

73

11

5217

675823

Figure 18 Mapping condition

0001

001

01

1

0 5 10 15 20

BPSKQPSK

BPSK (11)QPSK (11)

BER

SNR (dB)

Figure 19 SNR versus BER

spectrum and its performance is almost the same as thetheoretical performance

6 Conclusion

In this paper a hardware architecture of fading compensationcircuit for DSA was proposed The proposed architectureadopted piecewise linear interpolation in order to accuratelyestimate channel responses for data subcarriers Fadingcompensation for an OFDM symbol was executed in oneOFDM symbol time in order to make increase of latency

VLSI Design 9

smaller The results of FPGA implementation indicated thatthe proposed circuit occupied 1577 slices and achieved112MHz operation frequency which overcame the 760MHzdemand for real-time operation on a single chip

Future work is the performance evaluation of the OFDMtransceiver with DSA combined with the proposed fadingcompensator

Acknowledgment

This research has been supported by the Global COE pro-gram of the Ministry of Education Culture Sports Scienceand Technology Japan under the title ldquoFounding AmbientInformation Society Infrastructurerdquo

References

[1] IEEE Std 80211g-2003 ldquoPart 11 Wireless LAN Medium AccessControl (MAC) and Physical Layer (PHY) SpecificationsAmendment 4 Further Higher Data Rate Extension in the 24GHz Bandrdquo June 2003

[2] Zigbee Alliance ldquoZigbee Specification Release 17rdquo ZigBee Doc-ument 053474r17 January 2008

[3] J D Poston and W D Horne ldquoDiscontiguous OFDM consid-erations for dynamic spectrum access in idle TV channelsrdquo inProceedings of the 1st IEEE International Symposium on NewFrontiers in Dynamic Spectrum Access Networks (DySPAN rsquo05)pp 607ndash610 November 2005

[4] S Miyamoto Y Goda and S Sampei ldquoDynamic subcarrierselection technique for cognitive wireless mesh networks usingcsmacardquo in Proceedings of International Workshop on SmartInfo-Media Systems in Bangkok (SISB rsquo08) pp 81ndash86 December2008

[5] L Tong B M Sadler and M Dong ldquoPilot-assisted wirelesstransmissionsrdquo IEEE Signal Processing Magazine vol 21 no 6pp 12ndash25 2004

[6] M Morikura and S Kubota ldquo80211 HIGH-SPEEDWIRELESSLAN TEXTBOOKrdquo Impress R amp D 2008

[7] M Hatanaka R Hashimoto T Tatsuka et al ldquoVLSI design ofOFDM baseband transceiver with dynamic spectrum accessrdquoin Proceedings of the 18th International Symposium on IntelligentSignal Processing and Communication Systems (ISPACS rsquo10) pp329ndash332 December 2010

[8] IEEE Std 80211a-1999 ldquoPart 11 Wireless LAN Medium AccessControl (MAC) and Physical Layer (PHY) Specifications High-Speed Physical Layer in the 5 GHz Bandrdquo June 2003

[9] HKobayashi ldquoFoundation andApplication ofOFDMCommu-nication Systemsrdquo triceps 2004

[10] S Adireddy L Tong and H Viswanathan ldquoOptimal placementof training for frequency-selective block-fading channelsrdquo IEEETransactions on Information Theory vol 48 no 8 pp 2338ndash2353 2002

[11] H K Jung W G Jeon K H Seo and Y S Cho ldquoA subcarrierselection combining technique for OFDM systemsrdquo IEICETransactions on Communications vol E86-B no 7 pp 2119ndash2124 2003

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

VLSI Design 7

Right coefficient memoryLeft coefficient memory

1 1 mdash 1 2 3 4 mdash 0 0

f = 0Subcarrier index 1 2 3 4 Frequency

Figure 13 Contents of memory after step 2

Right coefficient memory

Left coefficient memory1 1 mdash 1 2 3 4 mdash 0 00 0 mdash 4 3 2 1 mdash 1 1

f = 0Subcarrier index 1 2 3 4 Frequency

Right 2 left 3 (f = 4)

Figure 14 Contents of memory after coefficient calculation

signal The total execution cycles is at most 387 cycles sinceone cycle initialization and one cycle termination process areincluded

43 Linear Interpolator Figure 15 shows the block diagramof the linear interpolator This block has four multipliersand three adders and all of them have registered outputsTherefore the linear interpolator has ten pipeline stages sincethis block has a dividor that has seven pipeline stages

The linear interpolator performs two functions Oneis preparing the left and right estimated microvariationvalues

119894119889119909 left = (119886119894119889119909 left 120579119894119889119909 left) and

119894119889119909 right =

(119886119894119889119909 right 120579119894119889119909 right) The other is calculation of the estimated

microvariation value for data subcarriers 119889119898

= (119886119889119898

120579119889119898

)First the estimated microvariation values for pilot sub-

carriers are written in the left estimated microvariationmemory which is the output of the channel estimator Theentries corresponding to the subcarriers on the left of thefirst pilot subcarrier are written as zeroes The entries for theother subcarriers are written as the estimated microvariationvalues for the nearest pilot subcarrier on the left After allof the 128 entries have been written to the right estimatedmicrovariation values are obtained in the same way as theleft estimated microvariation values by backward-scanningthe left estimated microvariation memory and pilot maskEach of the estimated microvariation values for the datasubcarriers is calculated by linear interpolation (7) with theleft and right coefficients and the left and right estimatedmicrovariation values

These operations are executed at 285 cycles including128 cycles for writing 128 cycles for scanning 10 cycles formicrovariation calculations and 19 cycles for the initializingand terminating processes

Figure 16 shows how to utilize the left and right estimatedvalue

44 Linear Projection Block The secondary compensation iscarried out by linear projection operation with the estimatedmicrovariation value in the rectangular coordinate systemThe linear projection operation is given by

(119868

119876) =

1

119886(sin (minusΔ120579) minus cos (minusΔ120579)cos (minusΔ120579) sin (minusΔ120579)

)(1198681015840

1198761015840) (10)

Table 4 Maximum execution cycles

Blocks Maximum execution cyclesChannel estimation 15Coefficient calculator 387Linear interpolation 285Linear projection 4

Table 5 Implementation result

Occupied slice 157714336 (11)Used SRAM 234 kbitsMax frequency 112MHz

The block diagram of linear projection block is shownin Figure 17 This block can input data every cycle and tableaccess and multiplication and addition take 1 cycle As aresult the latency of this block is 4 cycles

45 Execution Cycles and Operation Frequency Table 4 sum-marizes the maximum execution cycles for each block in afading compensation circuit

When a block needs to terminate its process within 119873

OFDM symbol time (one ODFM symbol time is 4 120583s) duringreal-time operation theminimumoperation frequency119865minfor real-time operation is given by

119865min =119899

119873 sdot (40 times 10minus6) (11)

where 119899 is the number of execution cyclesSince it is necessary for the coefficient calculator to termi-

nate its process within two OFDM symbol times to receive alllong preamble signals the minimum operation frequency forreal-time operation is 483MHz (= 2(387times(40times10

minus6

)))Theexecution time for the channel estimator linear interpolatorand linear projector is 304 cycles for an OFDM symbolsince they need to perform their operations for the sameOFDM symbolTherefore theminimumoperation frequencyis 760MHz for these blocks

As a result the minimum operation frequency for theproposed fading compensator is 760MHz since the min-imum operation frequency of blocks excluding the coeffi-cient calculator is 760MHz and the minimum operationfrequency of the coefficient calculator is 483MHz

5 FPGA Design of Fading Compensator

51 Implementation Result The proposed architecture of thefading compensation circuit has been implemented in anFPGA (Xilinx Virtex-II xc2v3000) and Table 5 summarizesimplementation results This result surpasses the 760MHzdemanded for real-time operation

52 Performance Evaluation We simulated the performanceof this fading compensator without Viterbi decoding underthe conditions listed in Table 6 to confirm the behavior

8 VLSI Design

Rightcoefficientmemory

Leftmicrovariation

memory

Leftcoefficientmemory

Rightmicrovariation

register

7 Subcarrierindex

generator

7

7

1412

1214

19

21

2119

Dividor(6 cycles)

Dividor(7 cycles)

14

12

Linearinterpolator

14

12

2220

8

idx left idx left

idx left

idx left idx right

idx right

120572 dm

120579 dm

Figure 15 Block diagram of linear interpolator

Left estimated valueRight estimated value

f = 0 1 2 3 4 Subcarrier index Frequency

mdash mdashmdash mdash

1205911

120591112059111205911

1205911 1205911 1205911 1205911 1205912 1205912 1205912

12059121205912120591212059121205912

Pright = 1205911 Pright = 1205912

120591f = ( 120572fΔ120579f

)

Figure 16 Left and right estimated values

Amplitude variation120572 14Phase shift Δ120579 12

Input data I 12Q 12

Floating pointSignificant 11-bitExponent 4-bit

CompensateddataI12Q12

table tablecos(120579) sin(120579)

Figure 17 Linear projection block

Table 6 Simulation conditions

No of efficient subcarriers 52128 (including 4 for pilot)Modulation BPSK QPSKNo of Processed OFDM symbol Two millionPhysical layer frame size 1500 byteSNR 0sim25 dB 5 dB stepChannel model Rayleigh fading (Table 2)

of the proposed architecture Figure 18 shows the mappingcondition in this simulation

Figure 19 plots the simulation results for BER with hard-ware implementation These results show that the hard-ware implementation achieves comparable performance tothe 80211a-based system without the diversity reported in[11] even though our architecture utilizes a discontinuous

86 (pilot)

Frequency

64

67 92 (data)

73

11

5217

675823

Figure 18 Mapping condition

0001

001

01

1

0 5 10 15 20

BPSKQPSK

BPSK (11)QPSK (11)

BER

SNR (dB)

Figure 19 SNR versus BER

spectrum and its performance is almost the same as thetheoretical performance

6 Conclusion

In this paper a hardware architecture of fading compensationcircuit for DSA was proposed The proposed architectureadopted piecewise linear interpolation in order to accuratelyestimate channel responses for data subcarriers Fadingcompensation for an OFDM symbol was executed in oneOFDM symbol time in order to make increase of latency

VLSI Design 9

smaller The results of FPGA implementation indicated thatthe proposed circuit occupied 1577 slices and achieved112MHz operation frequency which overcame the 760MHzdemand for real-time operation on a single chip

Future work is the performance evaluation of the OFDMtransceiver with DSA combined with the proposed fadingcompensator

Acknowledgment

This research has been supported by the Global COE pro-gram of the Ministry of Education Culture Sports Scienceand Technology Japan under the title ldquoFounding AmbientInformation Society Infrastructurerdquo

References

[1] IEEE Std 80211g-2003 ldquoPart 11 Wireless LAN Medium AccessControl (MAC) and Physical Layer (PHY) SpecificationsAmendment 4 Further Higher Data Rate Extension in the 24GHz Bandrdquo June 2003

[2] Zigbee Alliance ldquoZigbee Specification Release 17rdquo ZigBee Doc-ument 053474r17 January 2008

[3] J D Poston and W D Horne ldquoDiscontiguous OFDM consid-erations for dynamic spectrum access in idle TV channelsrdquo inProceedings of the 1st IEEE International Symposium on NewFrontiers in Dynamic Spectrum Access Networks (DySPAN rsquo05)pp 607ndash610 November 2005

[4] S Miyamoto Y Goda and S Sampei ldquoDynamic subcarrierselection technique for cognitive wireless mesh networks usingcsmacardquo in Proceedings of International Workshop on SmartInfo-Media Systems in Bangkok (SISB rsquo08) pp 81ndash86 December2008

[5] L Tong B M Sadler and M Dong ldquoPilot-assisted wirelesstransmissionsrdquo IEEE Signal Processing Magazine vol 21 no 6pp 12ndash25 2004

[6] M Morikura and S Kubota ldquo80211 HIGH-SPEEDWIRELESSLAN TEXTBOOKrdquo Impress R amp D 2008

[7] M Hatanaka R Hashimoto T Tatsuka et al ldquoVLSI design ofOFDM baseband transceiver with dynamic spectrum accessrdquoin Proceedings of the 18th International Symposium on IntelligentSignal Processing and Communication Systems (ISPACS rsquo10) pp329ndash332 December 2010

[8] IEEE Std 80211a-1999 ldquoPart 11 Wireless LAN Medium AccessControl (MAC) and Physical Layer (PHY) Specifications High-Speed Physical Layer in the 5 GHz Bandrdquo June 2003

[9] HKobayashi ldquoFoundation andApplication ofOFDMCommu-nication Systemsrdquo triceps 2004

[10] S Adireddy L Tong and H Viswanathan ldquoOptimal placementof training for frequency-selective block-fading channelsrdquo IEEETransactions on Information Theory vol 48 no 8 pp 2338ndash2353 2002

[11] H K Jung W G Jeon K H Seo and Y S Cho ldquoA subcarrierselection combining technique for OFDM systemsrdquo IEICETransactions on Communications vol E86-B no 7 pp 2119ndash2124 2003

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

8 VLSI Design

Rightcoefficientmemory

Leftmicrovariation

memory

Leftcoefficientmemory

Rightmicrovariation

register

7 Subcarrierindex

generator

7

7

1412

1214

19

21

2119

Dividor(6 cycles)

Dividor(7 cycles)

14

12

Linearinterpolator

14

12

2220

8

idx left idx left

idx left

idx left idx right

idx right

120572 dm

120579 dm

Figure 15 Block diagram of linear interpolator

Left estimated valueRight estimated value

f = 0 1 2 3 4 Subcarrier index Frequency

mdash mdashmdash mdash

1205911

120591112059111205911

1205911 1205911 1205911 1205911 1205912 1205912 1205912

12059121205912120591212059121205912

Pright = 1205911 Pright = 1205912

120591f = ( 120572fΔ120579f

)

Figure 16 Left and right estimated values

Amplitude variation120572 14Phase shift Δ120579 12

Input data I 12Q 12

Floating pointSignificant 11-bitExponent 4-bit

CompensateddataI12Q12

table tablecos(120579) sin(120579)

Figure 17 Linear projection block

Table 6 Simulation conditions

No of efficient subcarriers 52128 (including 4 for pilot)Modulation BPSK QPSKNo of Processed OFDM symbol Two millionPhysical layer frame size 1500 byteSNR 0sim25 dB 5 dB stepChannel model Rayleigh fading (Table 2)

of the proposed architecture Figure 18 shows the mappingcondition in this simulation

Figure 19 plots the simulation results for BER with hard-ware implementation These results show that the hard-ware implementation achieves comparable performance tothe 80211a-based system without the diversity reported in[11] even though our architecture utilizes a discontinuous

86 (pilot)

Frequency

64

67 92 (data)

73

11

5217

675823

Figure 18 Mapping condition

0001

001

01

1

0 5 10 15 20

BPSKQPSK

BPSK (11)QPSK (11)

BER

SNR (dB)

Figure 19 SNR versus BER

spectrum and its performance is almost the same as thetheoretical performance

6 Conclusion

In this paper a hardware architecture of fading compensationcircuit for DSA was proposed The proposed architectureadopted piecewise linear interpolation in order to accuratelyestimate channel responses for data subcarriers Fadingcompensation for an OFDM symbol was executed in oneOFDM symbol time in order to make increase of latency

VLSI Design 9

smaller The results of FPGA implementation indicated thatthe proposed circuit occupied 1577 slices and achieved112MHz operation frequency which overcame the 760MHzdemand for real-time operation on a single chip

Future work is the performance evaluation of the OFDMtransceiver with DSA combined with the proposed fadingcompensator

Acknowledgment

This research has been supported by the Global COE pro-gram of the Ministry of Education Culture Sports Scienceand Technology Japan under the title ldquoFounding AmbientInformation Society Infrastructurerdquo

References

[1] IEEE Std 80211g-2003 ldquoPart 11 Wireless LAN Medium AccessControl (MAC) and Physical Layer (PHY) SpecificationsAmendment 4 Further Higher Data Rate Extension in the 24GHz Bandrdquo June 2003

[2] Zigbee Alliance ldquoZigbee Specification Release 17rdquo ZigBee Doc-ument 053474r17 January 2008

[3] J D Poston and W D Horne ldquoDiscontiguous OFDM consid-erations for dynamic spectrum access in idle TV channelsrdquo inProceedings of the 1st IEEE International Symposium on NewFrontiers in Dynamic Spectrum Access Networks (DySPAN rsquo05)pp 607ndash610 November 2005

[4] S Miyamoto Y Goda and S Sampei ldquoDynamic subcarrierselection technique for cognitive wireless mesh networks usingcsmacardquo in Proceedings of International Workshop on SmartInfo-Media Systems in Bangkok (SISB rsquo08) pp 81ndash86 December2008

[5] L Tong B M Sadler and M Dong ldquoPilot-assisted wirelesstransmissionsrdquo IEEE Signal Processing Magazine vol 21 no 6pp 12ndash25 2004

[6] M Morikura and S Kubota ldquo80211 HIGH-SPEEDWIRELESSLAN TEXTBOOKrdquo Impress R amp D 2008

[7] M Hatanaka R Hashimoto T Tatsuka et al ldquoVLSI design ofOFDM baseband transceiver with dynamic spectrum accessrdquoin Proceedings of the 18th International Symposium on IntelligentSignal Processing and Communication Systems (ISPACS rsquo10) pp329ndash332 December 2010

[8] IEEE Std 80211a-1999 ldquoPart 11 Wireless LAN Medium AccessControl (MAC) and Physical Layer (PHY) Specifications High-Speed Physical Layer in the 5 GHz Bandrdquo June 2003

[9] HKobayashi ldquoFoundation andApplication ofOFDMCommu-nication Systemsrdquo triceps 2004

[10] S Adireddy L Tong and H Viswanathan ldquoOptimal placementof training for frequency-selective block-fading channelsrdquo IEEETransactions on Information Theory vol 48 no 8 pp 2338ndash2353 2002

[11] H K Jung W G Jeon K H Seo and Y S Cho ldquoA subcarrierselection combining technique for OFDM systemsrdquo IEICETransactions on Communications vol E86-B no 7 pp 2119ndash2124 2003

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

VLSI Design 9

smaller The results of FPGA implementation indicated thatthe proposed circuit occupied 1577 slices and achieved112MHz operation frequency which overcame the 760MHzdemand for real-time operation on a single chip

Future work is the performance evaluation of the OFDMtransceiver with DSA combined with the proposed fadingcompensator

Acknowledgment

This research has been supported by the Global COE pro-gram of the Ministry of Education Culture Sports Scienceand Technology Japan under the title ldquoFounding AmbientInformation Society Infrastructurerdquo

References

[1] IEEE Std 80211g-2003 ldquoPart 11 Wireless LAN Medium AccessControl (MAC) and Physical Layer (PHY) SpecificationsAmendment 4 Further Higher Data Rate Extension in the 24GHz Bandrdquo June 2003

[2] Zigbee Alliance ldquoZigbee Specification Release 17rdquo ZigBee Doc-ument 053474r17 January 2008

[3] J D Poston and W D Horne ldquoDiscontiguous OFDM consid-erations for dynamic spectrum access in idle TV channelsrdquo inProceedings of the 1st IEEE International Symposium on NewFrontiers in Dynamic Spectrum Access Networks (DySPAN rsquo05)pp 607ndash610 November 2005

[4] S Miyamoto Y Goda and S Sampei ldquoDynamic subcarrierselection technique for cognitive wireless mesh networks usingcsmacardquo in Proceedings of International Workshop on SmartInfo-Media Systems in Bangkok (SISB rsquo08) pp 81ndash86 December2008

[5] L Tong B M Sadler and M Dong ldquoPilot-assisted wirelesstransmissionsrdquo IEEE Signal Processing Magazine vol 21 no 6pp 12ndash25 2004

[6] M Morikura and S Kubota ldquo80211 HIGH-SPEEDWIRELESSLAN TEXTBOOKrdquo Impress R amp D 2008

[7] M Hatanaka R Hashimoto T Tatsuka et al ldquoVLSI design ofOFDM baseband transceiver with dynamic spectrum accessrdquoin Proceedings of the 18th International Symposium on IntelligentSignal Processing and Communication Systems (ISPACS rsquo10) pp329ndash332 December 2010

[8] IEEE Std 80211a-1999 ldquoPart 11 Wireless LAN Medium AccessControl (MAC) and Physical Layer (PHY) Specifications High-Speed Physical Layer in the 5 GHz Bandrdquo June 2003

[9] HKobayashi ldquoFoundation andApplication ofOFDMCommu-nication Systemsrdquo triceps 2004

[10] S Adireddy L Tong and H Viswanathan ldquoOptimal placementof training for frequency-selective block-fading channelsrdquo IEEETransactions on Information Theory vol 48 no 8 pp 2338ndash2353 2002

[11] H K Jung W G Jeon K H Seo and Y S Cho ldquoA subcarrierselection combining technique for OFDM systemsrdquo IEICETransactions on Communications vol E86-B no 7 pp 2119ndash2124 2003

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of

International Journal of

AerospaceEngineeringHindawi Publishing Corporationhttpwwwhindawicom Volume 2014

RoboticsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Active and Passive Electronic Components

Control Scienceand Engineering

Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

International Journal of

RotatingMachinery

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporation httpwwwhindawicom

Journal ofEngineeringVolume 2014

Submit your manuscripts athttpwwwhindawicom

VLSI Design

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Shock and Vibration

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawi Publishing Corporation httpwwwhindawicom

Volume 2014

The Scientific World JournalHindawi Publishing Corporation httpwwwhindawicom Volume 2014

SensorsJournal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Modelling amp Simulation in EngineeringHindawi Publishing Corporation httpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

Navigation and Observation

International Journal of

Hindawi Publishing Corporationhttpwwwhindawicom Volume 2014

DistributedSensor Networks

International Journal of