Regular circuit = tile-based circuit. REVERSIBLE LOGIC 2.

Design of Regular Design of Regular Quantum CircuitsQuantum Circuits

Regular circuit = tile-based circuit

REVERSIBLE REVERSIBLE LOGICLOGIC

2

Reversible Permutative logic Gates and Circuits

A logic gate is reversible if Each input is mapped to a unique output It permutes the set of input values

A combinational logic circuit is reversible if it satisfies the following:

Has only one Fanout, Uses only reversible gates, No feedback path, has as many input wires as output wires, and permutes the

input values.

3

Basic Reversible Gates

a a

aa

bbac

4

NOT gate

a b a c0 0 0 00 1 0 11 0 1 11 1 1 0

Controlled-NOT or Feynman gate


a

c

b

a

b

cabf

5

a b c a b f0 0 0 0 0 00 0 1 0 0 10 1 0 0 1 00 1 1 0 1 11 0 0 1 0 01 0 1 1 0 11 1 0 1 1 11 1 1 1 1 0

Toffoli gate (Controlled-Controlled NOT gate)


a

a

b

b

6

Swap gate

Implementation of Swap gate using controlled-NOT


a

b

c

baacf

abcag

a

b

c

baacf

abcag

7

a b c a f g0 0 0 0 0 00 0 1 0 0 10 1 0 0 1 00 1 1 0 1 11 0 0 1 0 01 0 1 1 1 01 1 0 1 0 11 1 1 1 1 1

Fredkin gate (Controlled SWAP gate)

ALGORITHMS FOR SYNTHESIS ALGORITHMS FOR SYNTHESIS OF REVERSIBLE LOGIC CIRCUITSOF REVERSIBLE LOGIC CIRCUITS

8

Popular Algorithms for Synthesis of Reversible Logic Circuits

MMD: Transformation based

Gupta-Agrawal-Jha: PPRM based

Mishchenko-Perkowski: Reversible wave cascade

Kerntopf: Heuristics based

Wille: BDD based synthesis

9

reed-mulLER reed-mulLER EXPANSION IN EXPANSION IN SYNTHESIS OF SYNTHESIS OF REVERSIBLE REVERSIBLE

CIRCUITSCIRCUITS10

IDEA: use reed-mulLER IDEA: use reed-mulLER EXPANSION IN SYNTHESIS OF EXPANSION IN SYNTHESIS OF

REVERSIBLE CIRCUITSREVERSIBLE CIRCUITSA New Representation is Reed-Muller Expansion

(Positive Polarity Reed-Muller).

This idea appeared for the first time in paper of Aggrawal and Jha, this paper was a competitor to MMD algorithm.

Now we design a new algorithm which takes into account multi-level expansion for reversible circuits.

11

Example of Agrawal-Jha Algorithm

12

c b a co bo ao

0 0 0 0 0 1

0 0 1 0 0 0

0 1 0 1 1 1

0 1 1 0 1 0

1 0 0 0 0 1

1 0 1 1 0 0

1 1 0 1 0 1

1 1 1 1 1 0

PPRM form for each output in terms ofInput variables are given as follows and node is created

PPRM form for each output in terms ofInput variables are given as follows and node is created

acabbc 0

accbb 0

10 aa

•Reversible function specification is given as a truth table shown here•Output c0, b0 and a0 are derived using EXORCISM-2 developed at PSU and parent node is created

Agrawal-Jha Algorithm (cont..)

Parent node is explored by examining each output variable in the PPRM expansion.

Factors are searched in the PPRM expansions that do not contain the same input variable.

For example in the expansion below appropriate terms are “c” and “ac”

The substitution is performed as In this example OR

accbb 0

factorvv ii

13

cbb acbb


acabbc 0

accbb 0

10 aa

Node0

PQ head Node0

1aa

Algorithm identifies three possible substitutions

1. 2. 3.

cbb acbb

14


1aa acbb cbb

aa 0

acbb 0

acabbc 0

10 aa

accbb 0

acabbc 0

acabbc 0

cbb 0

10 aa

abbcc 0

acbb 0

10 aa

PQ head Node 1.0 Node 1.1 Node 1.2

Node 1.0 Node 1.1 Node 1.2

15

New nodes are created based on substitution

16

1aa cbb

aa 0

acbb 0

acabbc 0

10 aa

accbb 0

acabbc 0

acabbc 0

cbb 0

10 aa

abbcc 0

acbb 0

10 aa

Node 1.0

Node 1.1 Node 1.2

acbb

acbb abcc

abcc 0

bb 0

aa 0

acabcc 0

acabbb 0

aa 0

Node 2.0 Node 2.1

PQ head Node 2.0 Node 1.1 Node 1.2 Node 2.1

Next stage of Aggrawal-Jha algorithm

17

1aa cbb

aa 0

acbb 0

acabbc 0

10 aa

accbb 0

acabbc 0

acabbc 0

cbb 0

10 aa

abbcc 0

acbb 0

10 aa

Node 1.0

Node 1.1 Node 1.2

acbb

acbb abcc

abcc 0

bb 0

aa 0

acabcc 0

acabbb 0

aa 0

Node 2.0 Node 2.1

abcc

00 cc bb 0

aa 0

Node 3.0

PQ head Node 1.1 Node 1.2 Node 2.1

Next stage of Aggrawal-Jha algorithm

18

1aa

aa 0

acbb 0

acabbc 0

10 aa

accbb 0

acabbc 0

Node 1.0

acbb

abcc 0

bb 0

aa 0

Node 2.0

abcc

00 cc bb 0

aa 0

Node 3.0

Node0

a

c

b acbb

a

b

c abcc

a

b

c

ao

bo

co

Final circuit

Solution found by the Aggrawal-Jha algorithm

Problem with Current Synthesis Approaches

Common problem with current approaches: they invariably use nxn Toffoli gates, that might imposes technological limitations.

High Quantum cost of Toffoli gates with many inputs.

Synthesize only reversible functions, not Boolean functions that is not reversible.

19

Quantum Cost of 4x4 Toffoli Gate

20

Implementation of 4x4 Toffoli gate with Quantum realizable 2x2 primitives such as controlled-V, controlled-NOT, controlled-V+.

Implementation of 4x4 Toffoli gate with Quantum realizable 2x2 primitives such as controlled-V, controlled-NOT, controlled-V+.

a

b

0

c

d

a

b

d

c

V V V+

V V V+

V V V+

a

b

0

c

d

CREATING CREATING QUANTUM QUANTUM

ARRAY FROM ARRAY FROM LATTICELATTICE

21

Expansions Rules for Lattice DIAGRAAMS

22

zbby

r sbb b b

x y z v

r sbb b b

xv

RULE (S, S)

r sb1 b

x y z v

r sb1 b

x

zbby

RULE (pD, pD)1

vzy

1

r sb1

x y z v

r sb b

x

zbby

RULE (nD, nD)1

vzy

b 11

r sb

x y z v

r sb

x

zbby

RULE (s, pD)1

vzy

1b b b b

r sb

x y z v

r sb

x

zbby

RULE (pD, s)1

vzy

1b b b b

Positive Davio Tree can be created by expanding PPRM function using positive Davio expansion.

Positive Davio Lattice is created by performing joining operation for neighboring cells at every level.

Other Lattices can be created using similar method but using expansions such as Shannon or Negative Davio expansions or combination of them.

Creating Quantum Array from Lattices

On the previous foils I showed representation of the Davio and Shannon cells as cascade of reversible gates.

Next I present unique method to create Quantum Array from Positive Davio Lattice.

The same approach can be used for other Lattices.

23

Creating Positive Davio Lattice

a

c

b

a

b

cabd

a

bc cabd

Positive Davio cell

Positive Davio cell representation with

Toffoli gate

24

bcdcdbcacabdbdad 1

abdbdad 1 bddba

abdba abb 1

ad1 a1

d

a

1 c

1 d 1 d

1 b 1 b

1 a 1 a 1 a

1 d

1

11

1

1 1

10

0

Each node represents pDv cell.

Creating Quantum Array from Positive Davio Lattice

25

+

+ +

++

+ ++

+

0

d

1

11

1

1

1

1 1

1

111

1

d

a

d

bb

1

a a

c

1

Quantum Array Representation

26

abcd

0

1

1

1

0

1

a1

ad1

bab1

d

a aabdb

adabddb1

bddab

bcdcdacbcabdaddb1

garbage

garbage

garbage

garbage

garbage

function


27

abcd

0

1

1

1

0

1

a1

ad1

bab1

d

a aabdb

adabddb1

bddab

bcdcdacbcabdaddb1

garbage

garbage

garbage

garbage

garbage

function

Creating Positive Davio Lattice

a

c

b

a

b

cabd

a

bc cabd

Positive Davio cell

Positive Davio cell representation with

Toffoli gate

28

Each node represents pDv cell.


29

Advantages of Lattice to QA

Reversible circuit synthesized with only 3x3 Toffoli gates.

Generates reversible circuit for any ESOP.

Adds ancilla bits but overall cost of the circuit will be lower due to use of low cost 3x3 Toffoli gates.

30

31

Calculating Single-Output Shannon Lattice for Calculating Single-Output Shannon Lattice for Completely Specified Boolean Function.Completely Specified Boolean Function.

32

Calculating Multi-Calculating Multi-Output Shannon Output Shannon

Lattice for Lattice for Completely Completely Specified Specified Boolean Boolean

Function.Function.

33

Calculating Multi-Output Shannon Calculating Multi-Output Shannon Lattice for Completely Specified Boolean Lattice for Completely Specified Boolean

Function.Function.

DIPAL GATES, DIPAL GATES, DIPAL GATE DIPAL GATE

FAMILIES AND FAMILIES AND THEIR ARRAYSTHEIR ARRAYS

34

Representation of pdv cell as a toffoli gate

a

c

b

a

b

cabd

a

b

c cabd

a

c

b

a

ba

b

c

cbad cbad

Positive Davio cell

Positive Davio cell representation with Toffoli

gate

Negative Davio cell

Negative Davio cell representation with Toffoli

gate

35

Development of Dipal gate

][

]1[

cbab

acabb

acba

acbaf

36

a

b

c

cabaf a

b

c

cabaf

cb

a

Shannon cell

Dipal cell representation with

reversible gates

There are 23! = 8! = 40320 3x3 Reversible logic functions, however only handful of them shown earlier are useful for synthesis purpose.

Dipal gate is a reversibleequivalent of Shannon cell Dipal gate is a reversibleequivalent of Shannon cell

•Find the reversible counterpart of well-known structures BDD, Lattices, KFDD•Show Dipal cell is between Toffoli and Fredkin

Development of Dipal gate (cont..)

37

a

b

c

bacaf

a

b

c

a

cb

bacaf

Shannon cell with negative variable

Dipal cell with negative variable represented with

reversible gates

Development of Dipal gate

][

]1[

cbab

acabb

acba

acbaf

38

a

b

c

cabaf a

b

c

cabaf

cb

a

Shannon cell

Dipal cell representation with

reversible gates

There are 23! = 8! = 40320 3x3 Reversible logic functions, however only handful of them shown earlier are useful for synthesis purpose.

Dipal gate is a reversibleequivalent of Shannon cell

Dipal gate is a reversibleequivalent of Shannon cell

Dipal gate truth table

c b a a

0 0 0 0 0 0

0 0 1 0 0 1

0 1 0 1 1 0

0 1 1 1 0 1

1 0 0 1 0 0

1 0 1 1 1 1

1 1 0 0 1 0

1 1 1 0 1 1

39

b c

b a[b c] input

output

0 0

1 1

2 6

3 5

4 4

5 7

6 2

7 3

Dipal gate unitary matrix

40

1 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0

0 0 0 0 0 0 1 0

0 0 0 0 0 1 0 0

0 0 0 0 1 0 0 0

0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0

0 0 0 1 0 0 0 0

000

001

010

011

100

101

110

111

000 001 010 011 100 101 110 111

Variants of Dipal gates

41

This is called a Dipal Gate Family

General view of Dipal Family Gate

EXPERIMENTAL EXPERIMENTAL RESULTSRESULTS

42

Results with Pdv Lattice and comparison with MMD and AJ results

43

Benchmark #Real inputs

#Garbage inputs

#Gates Lattice

Cost Lattice

CPU time Lattice

#Gates DMM

Cost DMM

#Gates AJ

Cost AJ

2to5 5 4 31 107 0.12 15 107 20 100

rd32 3 1 4 8 < 0.01 4 8 4 8

rd53 5 5 11 39 < 0.01 16 75 13 116

3_17 3 1 10 21 < 0.01 6 12 6 14

6sym 10 6 34 150 0.37 20 62 NA NA

5mod5 5 1 14 58 < 0.01 10 90 11 91

4mod5 4 1 6 18 < 0.01 5 13 5 13

ham3 3 0 3 7 < 0.01 5 7 5 9

xor5 5 0 4 4 < 0.01 4 4 4 4

Xnor5 5 1 5 5 < 0.01 -------- ---------- ---------- ----------

decod24 4 2 10 30 < 0.01 -------- ---------- 11 31

Cycle10_2 12 6 180 860 27.9 19 1198 ---------- ----------

ham7 7 5 22 58 0.10 23 81 24 68

Results with Pdv Lattice and comparison with MMD and AJ results (cont..)

44

Benchmark #Real inputs

#Garbage inputs

#Gates Lattice

Cost Lattice

CPU time Lattice

#Gates DMM

Cost DMM

#Gates AJ

Cost AJ

graycode6 6 5 5 5 < 0.01 5 5 5 5

graycode10 10 9 9 9 < 0.01 9 9 9 9

graycode20 20 19 19 19 < 0.01 19 19 19 19

nth_prime3_inc

3 4 4 6 < 0.01 4 6 ---------- ----------

nth_prime4_inc

4 5 16 48 < 0.01 12 58 ---------- ----------

nth_prime5_inc

5 5 29 91 0.22 26 78 ---------- ----------

alu 5 2 5 17 < 0.01 -------- ---------- 18 114

4_49 4 4 16 52 0.04 16 58 13 61

hwb4 4 4 12 28 < 0.01 17 63 15 35

hwb5 5 5 24 96 1.2 24 104 ---------- ----------

hwb6 6 6 32 128 2.0 42 140 ---------- ----------

pprm1 4 4 9 33 < 0.01 -------- ---------- ---------- ----------

Results with shannon Lattice

45

Benchmark #Inputs #Gates pDv Lattice

Cost pDv Lattice

#Gates Shannon Lattice

Cost Shannon Lattice

2to5 5 31 107 41 117

rd32 3 4 8 4 8

rd53 5 11 39 18 46

3_17 3 10 21 15 26

6sym 10 34 150 51 167

5mod5 5 14 58 30 81

4mod5 4 6 18 12 24

Ham3 3 3 7 6 10

xor5 5 4 4 4 4

Xnor5 5 5 5 5 5

Decod24 4 10 30 20 40

Cycle10_2 12 180 860 270 950

Ham7 7 22 58 32 68

Results with shannon Lattice (cont..)

46

Benchmark #Inputs #Gates pDv Lattice

Cost pDv Lattice

#Gates Shannon Lattice

Cost Shannon Lattice

Graycode6 6 5 5 5 5

Graycode10 10 9 9 9 9

Graycode20 20 19 19 19 19

nth_prime3_inc

3 4 6 6 8

nth_prime4_inc

4 16 48 29 61

nth_prime5_inc

5 29 91 39 101

Alu 5 5 17 10 22

4_49 4 16 52 22 58

Hwb4 4 12 28 15 31

Hwb5 5 24 96 38 110

Hwb6 6 32 128 40 134

Pprm1 4 9 33 14 38

• Fig. 2. Circuit for function FX2 created with our method for traditional cost function calculation that does not take Ion Trap technology constraints into account.

49

abcd

0

1

1

1

0

1

a1

ad1

bab1

d

a aabdb

adabddb1

bddab

bcdcdacbcabdaddb1

garbage

garbage

garbage

garbage

garbage

function

Nearest Linear Node ModelNearest Linear Node Model

• Fig. 3. Circuit from Figure 2 modified with adding SWAP gates for new cost function calculation that does take Ion Trap technology constraints into account, with XX gates added. It has 36 SWAP gates added to realize LNNM. 50

All gates are realized only on neighbors, but we have to add many SWAP gates

51

bcdcdbcacabdbdad 1

abdbdad 1 bddba

abdba abb 1

ad1 a1

d

a

1 c

1 d 1 d

1 b 1 b

1 a 1 a 1 a

1 d

1

11

1

1 1

10

0

Example of Positive Davio Lattice from [Perkowski97d]. Positive Davio Expansion is applied in each node. Variable d is repeated

52

1

2 3

45 6

7 8 9

a

b

c

f

Garbage

Garbage

Garbage

a

b

c

f

Garbage

Garbage

Garbage

(a)

(b)

Transformation of function F3(a,b,c) from classical Positive Davio Lattice to a Quantum Array with Toffoli and SWAP gates. Each SWAP gate is next replaced with 3 Feynman gates.(a) intermediate form, (b) final Quantum Array.

Intermediate Structure with Dipal Gate

1

2 3

45 6

7 8 9

a

b

c

f

Garbage

Garbage

Garbage

Garbage

Garbage

Garbage

53

Another Representation of Quantum Array with Dipal Gate

a

b

c

f

Garbage

Garbage

Garbage

Garbage

Garbage

Garbage

d1

d2

d3

d4

d5

d6

x

y

z

v

54

Layered Diagram using Dipal Gate

a

b

55

General layout of the layered diagram

Each box represents a gate from family of Dipal gate

General Pattern of Circuit with Dipal Gate

d3

d6

d2

d4

d1

a

b

cx

y

z

v

d5

56

Quantum cost based On 1d model

57

Benchmark #Gates Lattice

Cost Lattice

#Gates with SWAP insertion for Lattice

Cost with SWAP gates for Lattice

#Gates DMM

Cost DMM

#Gates with SWAP insertion for MMD

Cost with SWAP gates for MMD

2to5 31 107 61 197 15 107 31 155

rd32 4 8 8 20 4 8 6 14

rd53 11 39 44 138 16 75 72 273

3_17 10 21 14 33 6 12 8 18

6sym 34 150 56 216 20 62 78 236

5mod5 14 58 17 67 10 90 48 204

4mod5 6 18 10 30 5 13 11 31

Ham3 3 7 3 7 5 7 7 13

Xor5 4 4 4 4 4 4 4 4

Xnor5 5 5 5 5 -------- -------- -------- --------

decod24 10 30 14 42 -------- -------- -------- --------

Cycle10_2 180 860 306 1238 19 1198 199 1738

Ham7 22 58 30 112 23 81 79 249

Quantum cost based On 1d model

58

Benchmark #Gates Lattice

Cost Lattice

#Gates with SWAP insertion for Lattice

Cost with SWAP gates for Lattice

#Gates DMM

Cost DMM

#Gates with SWAP insertion for MMD

Cost with SWAP gates for MMD

Graycode6 5 5 5 5 5 5 5 5

Graycode10 9 9 9 9 9 9 9 9

Graycode20 19 19 19 19 19 19 19 19

Nth_prime3_inc

4 6 5 9 4 6 6 12

Nth_prime4_inc

16 48 20 60 12 58 18 76

Nth_prime5_inc

29 91 39 121 26 78 128 384

Alu 5 17 7 23 -------- -------- ---------- ----------

4_49 16 52 41 127 16 58 40 130

hwb4 12 28 15 40 17 63 39 129

hwb5 24 96 44 156 24 104 64 224

hwb6 32 128 72 248 42 140 144 446

pprm1 9 33 19 63 -------- -------- ---------- ----------

GENERALIZED GENERALIZED REGULARITIES FOR REGULARITIES FOR

QUANTUM AND NANO-QUANTUM AND NANO-TECHNOLOGIESTECHNOLOGIES

59

Ion-Trap Layout

60

(a) (b) (c)

(d)

Single ion

Interaction between two ions

Various regular structures are technically possible, single dimensional vector is the one that is most often discussed

61

Examples of Expansions for regular Examples of Expansions for regular structuresstructures

Non-symmetric functions require Non-symmetric functions require repeatition of input variablesrepeatition of input variables

62

• Variable b is repeated

63

Symmetry Symmetry Indices and Indices and

regular regular structures for structures for binary logicbinary logic

64

EXAMPLE: EXAMPLE:

MULTI-VALUED MULTI-VALUED REVERSIBLE LOGIC REVERSIBLE LOGIC

ADDERADDER

65

MULTI-VALUED REVERSIBLE LOGICMULTI-VALUED REVERSIBLE LOGIC

68

Three dimensional Three dimensional realization of realization of lattices for ternary lattices for ternary logic: SUMlogic: SUM

69

Three dimensional Three dimensional realization of realization of lattices for ternary lattices for ternary logic: CARRYlogic: CARRY

QUANTUM CIRCUITS QUANTUM CIRCUITS AND QUANTUM AND QUANTUM

ARRAYS FROM TRULY ARRAYS FROM TRULY QUANTUM GATESQUANTUM GATES

71

Binary Reversible Gates

Basic single qubit quantum gates

72

NOT Pauli x Pauli y Pauli z Hadamard

X Y Z H

01

10x

0

0

i

iy

10

01z

11

11

2

1H

XX YY ZZ HH

(a) (b) (c) (d)

01

10x

0

0

i

iy

10

01z

11

11

2

1H

Phase gate Pseudohadamard gate Inverse pseudohadamard gate

V S h 1h

ii

iiiV

11

1

2

1

ie

S0

01)(

11

11

2

1h

11

11

2

11h

V Gate

VV SS hh 1h 1h

ii

iiiV

11

1

2

1

ie

S0

01)(

11

11

2

1h

11

11

2

11h

(a) (b) (c) (d)

73

• The The transformations transformations

of blocks of of blocks of quantum quantum gates to the gates to the pulses level.pulses level.

• Transformation of the circuit realized in Fig. 7 using Toffoli gate. Each Toffoli and SWAP gates are replaced by quantum CNOT and CV/CV+ quantum gates and rearranged to satisfy the neighborhood requirements of Ion trap.

•

74

Lattice based Lattice based FPGA in FPGA in

CLASSICAL CLASSICAL LOGICLOGIC

75

New type of FPGA in CMOSNew type of FPGA in CMOS

In classical CMOS logic one can design a regular array, such as a form of FPGA, which realizes Shannon, positive Davio and negative Davio inside one cell.

Such array is highly testable

We can try to design something similar in quantum and reversible logic circuits.

76

Design of SRFPGA cellDesign of SRFPGA cell

77

1. Dipal completed his MS in December 2000 with thesis on “Method for Self-Repair of FPGAs”.

2. I adapted concept of Lattices which were developed Dr. Perkowski and Dr. Jeske to design FPGA like regular structure in VLSI

This cell can be mapped to Shannon, positive Davio, negative Davio and other logic gates.

General idea of SRFPGA architecture

78

•General idea of the SRFPGA architecture, each circle represents cell shown on the previous foil.•Row and column decoders are for memory addressing•The next foil shows actual physical design of the SRFPGA

79

SRFPGA layoutWith I/O pins

80

Var1

var2

var3

var4

var5

var6

var7

var8

var9

var10

var11

var12

var13

var14

var15

var16

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

1

1

1

1

1

1

1

1

1

1

1

1

0

Input test vector

Inputtestvector

Test output

Testoutput

Faults observed during column testC = 2.

Faults observed during

diagonal testD = 2

Total number ofFaults N = C * D= 2 * 2 = 4.

1. Dipal developed a unique test that identifies any number of faulty cell in the FPGA

2. Repair is based on redundancy-repair where identified faulty cells are replaced with unused good cell in the structure

3. Later Dipal adapted concept of lattice and synthesis methodology for designing reversible logic circuits.

4. His method of reversible circuit design resolves many issues that are not yet addressed by any other researchers

5. This approach can be extended to reversible and quantum logic cicuits.

CONCLUSIONS and CONCLUSIONS and possible projectspossible projects

82

Conclusions Experimental results proved that our algorithm produced better

results in terms of quantum cost compared to other contemporary algorithms for synthesis of reversible logic.

New gate family called Dipal gate

Presented new synthesis method with layered diagrams. More accurate technology specific cost model for 1D qubit

neighborhood architecture.

83

CONCLUSIONS A new method based of lattice diagram to synthesize reversible logic circuit with 3x3 Toffoli gates.A new method based of lattice diagram to synthesize reversible logic circuit with 3x3 Toffoli gates.

A new family of gates called Dipal Gates.A new family of gates called Dipal Gates.

New diagrams called layered diagram that uses family of Dipal gate for synthesis of reversible logic New diagrams called layered diagram that uses family of Dipal gate for synthesis of reversible logic

function.function.

Software for creating Lattice diagrams and software for creating quantum array from Lattice (Lattice Software for creating Lattice diagrams and software for creating quantum array from Lattice (Lattice

to QA).to QA).

Program to implement a variant of MMD algorithm.Program to implement a variant of MMD algorithm.

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Possible ProjectsPossible Projects

1.1. Generalize to ternary logicGeneralize to ternary logic

2.2. Generalize to all Dipal Gate Family gates.Generalize to all Dipal Gate Family gates.

3.3. Realization with low level pulses for NMR technology.Realization with low level pulses for NMR technology.

4.4. Development of a concept of reversible/quantum FPGA Development of a concept of reversible/quantum FPGA similar to SRFPGAsimilar to SRFPGA

5.5. Extend Agrawal-Jha method for factorized circuits.Extend Agrawal-Jha method for factorized circuits.

6.6. Extend the methods to many-output circuits.Extend the methods to many-output circuits.

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What to remember?What to remember?1. Use of PPRM in synthesis of reversible circuits.2. The main idea of Agrawal-Jha algorithm.3. How AJ algorithm can be improved?4. How this algorithm can be extended to Fredkin gates?5. Expansions Rules for Lattice Diagrams6. Creating Positive Davio Lattice7. Creating Negative Davio Lattice8. Creating Lattice for arbitrary function with a mixture of

Davio and Shannon Expansions.9. Lattices for symmetric functions.10. Transforming Positive Davio Lattice to a quantum array

(circuit) for single output functions. 86

What to remember?What to remember?1. Transforming Positive Davio Lattice to a quantum array

(circuit) for single output functions.2. Transforming Positive Davio Lattice to a quantum array

(circuit) for multi-output functions.3. Dipal gate and Dipal gate family.4. Regular structures and their use in quantum computing.5. Regularity versus LNNM model.6. Multiple-valued Lattices for ternary logic.7. FPGA based on 3*3 lattices and can they be adapted to

quantum and reversible circuits.8. Decomposition to pulses. Relation to quantum costs.

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Regular circuit = tile-based circuit. REVERSIBLE LOGIC 2.

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Transcript of Regular circuit = tile-based circuit. REVERSIBLE LOGIC 2.