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M.TECH. VLSI DESIGNSEMESTER I

SlNo

SubjectCode

Subject L T P C

Theory

1 P1MAC03 Mathematical Foundations of Electronics

Engineering

3 0 0 3

2 P1VLC01 VLSI asic ! Conce"ts 3 0 0 3

3 P1VLC02 Ad#anced $igital S%stem $esign 3 1 0 &

& P1VLC03 VLSI 'echnolog% 3 0 0 3

( P1VLC0& Verilog Programming 3 1 0 &

) P1VLC0( Analog Integrated Circuit $esign 3 1 0 &

Practical

* P1VLC0) VLSI $esign La+ 0 0 2 2

Total Credits 23

SEMESTER II

Sl

No

Subject

Code

Subject L T P C

Theory

1 P2VLC0* $igital CM,S VLSI $esign 3 1 0 &

2 P2VLC0- 'esting of VLSI Circuits. est academic elec 3 1 0 &

3 P2VLC0/ VLSI Signal Processing 3 0 0 3

& P2VLC10 ASIC $esign. #lsi cdac 3 1 0 &

( P2VLC11 VLSI for ireless communication 3 0 0 3

) Electi#e I. est cdac 3 0 0 3

Practical

* P2VLC12 Em+edded s%stem and ad#anced VLSI $esignLa+

0 0 2 2

Total Credits 23SEMESTER III

SlNo

SubjectCode

Subject L T P C

Theory

1 Electi#e II 3 0 0 3

2 Electi#e III 3 0 0 3

3 Electi#e IV 3 0 0 3

Practical

& P3VLC13 Proect Phase I 0 0 12 )

Total Credits 1(

SEMESTER IV

SlNo

SubjectCode

Subject L T P C

Practical

1 P&VLC1& Proect Phase II 0 0 2& 12

Total Credits 12

!er all Total Credits " #$ L % Lecture& T % Tutorial& P % Practical& C % Credit

LIST ' ELECTIVES 'R SEM II %ELECTIVE(I

1

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SlNo

SubjectCode

Subject L T P C

1 PEVLC1( VLSI S%stem $esign 3 0 0 3

2 PEVLC1) Solid State $e#ice Modeling andSimulation

3 0 0 3

3 PEVLC1* Em+edded S%stem $esign 3 0 0 3

& PEVLC1- $SP Processor Architecture andProgramming cdac est electi#e ii

3 0 0 3

( PEVLC1/ FP4A ased Signal Processing 3 0 0 3

LIST ' ELECTIVES 'R SEM III %ELECTIVE(II

SlNo

SubjectCode

Subject L T P C

1 PEVLC20 Com"uter Aided $esign for VLSI 3 0 0 3

2 PEVLC21 Ph%sical $esign of VLSI Circuits 3 0 0 3

3 PEVLC22 5igh S"eed Sitching Architecture 3 0 0 3

& PEVLC23 $esign of VLSI in Em+edded S%stem 3 0 0 3

( PEVLC2& Ad#anced Micro Processor andMicrocontrollers

3 0 0 3

LIST ' ELECTIVES 'R SEM III %ELECTIVE(III

SlNo

SubjectCode

Subject L T P C

1 PEVLC2( 5ardare softare co6design 3 0 0 3

2 PEVLC2) 7ano technolog% 3 0 0 3

3 PEVLC2* Introduction to MEMS S%stem $esign 3 0 0 3

& PEVLC2- 8ireless Sensor 7etor9s 3 0 0 3

( PEVLC2/ Control S%stem on Chi" 3 0 0 3

LIST ' ELECTIVES 'R SEM III %ELECTIVE(IV

SlNo

SubjectCode

Subject L T P C

1 PEVLC30 Lo Poer VLSI $esign 3 0 0 3

2 PEVLC31 Semiconductor memor% design !Processing

3 0 0 3

3 PEVLC32 Com"uter architecture and ParallelProcessing

3 0 0 3

& PEVLC33 $ata Con#erters 3 0 0 3

( PEVLC3& 7etor9 on Chi" 3 0 0 3

L % Lecture& T % Tutorial& P % Practical& C % Credit

2

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SEMESTER IP)M*C+$ M*THEM*TIC*L ',ND*TINS ' ELECTRNICS ENGINEERING L T P C

: VLSI; $ + + $*i- 'o gi#e e P5I LearningPri#ate Limited> 7e $elhi> 1//*?

2? 5? A? 'aha> H,"erations Desearch An Introduction> se#enth edition> Pearson Education> 7e

$elhi> 2002?3? 4?5? 4olu+ and C?5? Van Loan> HMatri< Com"utations> third edition> ohns 5o"9ins ni#ersit%

Press> London> 1//)?&? 7arsingh $eo> H4ra"h 'heor% 8ith A""lication to Engineering and Com"uter Science> P5I>

2003?(? D?? 8ilson> HIntroduction to 4ra"h 'heor%> Fourth Edition> Pearson Education> 2003?)? $ifferential E=uations ith oundar%6Value Pro+lems> *th ed? Jill ! Cullen> 'homson.roo9s Cole>

200/*? V? Sundara"andian> HPro+a+ilit%> Statistics and Kueuing 'heor%> P5I Learning> 7e $elhi> 200/?

3

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DLhttps://noppa.lut.fi/noppa/opintojakso/bm20a3101/.../lecture_1_2.pdfhtt"..en?i9i"edia?org.i9i.Fu@@%sethtt"..?doc?ic?ac?u9.nd.sur"rise/).ournal.#ol&.s+aa.re"ort?fu@@%sets?htmlhtt"..?dia?fi?u"m?es.mgremesal.MID.slides.LessonN202N20:Fu@@%N20Pro"ositions;?"dfitlab.ee.nsysu.edu.tw/course/97a!/part/ppt/"art0#_$%.1&'(.ppt

en?i9i"edia?org.i9i.=ueueingtheor%?cs?ute

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P)VLC+) VLSI "6ell> tin tu+ ;

5$L "rogramming methods for se=uential and com+inational circuits,NIT I VLSI VLSI $esign flo> Front end and +ac9 end VLSI design> M,S transistor> transistor as asitch >CM,S M,S logic gate design> "h%sical design of +asics logic gates >CM,S in#erters and itsCharacteristics> Poer dissi"ation Estimation of resistance> ca"acitance> inductance >CM,S logicstructures design?

,NIT II VLSI CIRC,IT CH*R*CTERI?*TIN *ND PER'RM*NCE 2

Secondar% order effects> CM,S gate transistor si@ing> si@ing routing conductors> charge sharing> $esignmargin> %ield> relia+ilit%> Scaling of M,S transistor dimensions and La%out design rules

,NIT III CMS CIRC,IT ESTIM*TIN *ND LGIC DESIGN 2Poer dissi"ation Estimation of resistance> ca"acitance> and inductance ?CM,S logic structures design>Cloc9ing strategies?

,NIT IV CMS PRCESSING TECHNLG@ 2

Cr%stal groth "rocess> CM,S technologies6 "6ell "rocess> n6ell "rocess> tin tu+ "rocess andsilicon on insulator "rocess?

,NIT V and $iffusion

5

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RE'ERENCES1? 8este> Eshraghian> HPrinci"les of CM,S VLSI design> 2ndEdition Addison 8esle%> 1//&?

2? $ouglas A Puc9nell and Bamaran Eshragian> H asic VLSI design H> 3 rdedition> P5I> 1//&?3?Samir Palnit9ar > Verilog 5$L 4uide to digital design and s%nthesis > III edition > PearsonEduaction

&? S?IMAM ! M?PE$DAM> HLogic s%nthesis for Lo Poer VLSI $esigns> Bluer Academic"u+lishers> 1//-?

,RLs1? htt"..?n"tel?iitm?ac?in.courses.10)10(03

2? htt"..?aicdesign?org.scnotes.2002notes.Cha"ter0262P:-1302;?"df

6

http://www.nptel.iitm.ac.in/courses/10610503http://www.aicdesign.org/scnotes/2002notes/Chapter02-2UP(8_13_02).pdfhttp://www.nptel.iitm.ac.in/courses/10610503http://www.aicdesign.org/scnotes/2002notes/Chapter02-2UP(8_13_02).pdf

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P)VLC+B *DV*NCED DIGIT*L S@STEM DESIGN L T P C $ ) + 9

*IM'oe Meal% ! Moore Models> Anal%sis ! S%nthesis of S%nchronous se=uentialcircuits> Introduction to V5$L> design units> data o+ects> signal dri#ers> inertial and trans"ort dela%s> deltadela%> V5$L data t%"es> concurrent and se=uential statements?

,NIT II 2$igital s%stem design 5ierach%> ASM charts> 5ardare descri"tion language> Control logic $esignDeduction of state ta+les> State Assignments> Su+"rograms Functions> Procedures> attri+utes> generio>generate> "ac9age> IEEE standard logic li+rar%> file I.,> test +ench> com"onent declaration> instantiation>

configuration

,NIT III 2Anal%sis and s%nthesis of As%nchronous se=uential circuits> critical and non6critical races> Essential5a@ard,NIT IV 2Com+inational and se=uential circuit design ith PL$s > Introduction to CPL$s ! FP4As> Com+inationallogic circuit design and V5$L im"lementation of folloing circuits first adder> Su+tractor> decoder>encoder> multi"le AL> +arrel shifter> && 9e% +oard encoder> multi"lier> di#ider> 5amming codeencoder and correction circuits

,NIT V 2'ault Modeli51Fault classes and models Stuc9 at faults> ridging faults> 'ransition and Intermittent faults? Fault$iagnosis of com+ination circuits +% con#entional methods6 Path sensiti@ation techni=ue> ooleandifferent method and Boha#i algorithm?

TT*L 9:3):Tutorial ";+ PeriodsTET 2nd Edition> 'M5?

DLs1? htt"s..?cs?ashington?edu.education.courses.()*.01au."roect.sue$ocs.tutorial2?"df

2? htt"..?i"fn?ist?utl?"t.E6Ph$.1stedition.ronFP4A/)?"dfP)VLC+$ VLSI TECHNLG@ L T P C

$ + + $

7

https://www.cs.washington.edu/education/courses/567/01au/project/sueDocs/tutorial2.pdfhttp://www.ipfn.ist.utl.pt/EU-PhD/1stedition/BrownFPGA96.pdfhttps://www.cs.washington.edu/education/courses/567/01au/project/sueDocs/tutorial2.pdfhttp://www.ipfn.ist.utl.pt/EU-PhD/1stedition/BrownFPGA96.pdf

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*IM'o ma9e the students to learn the com"lete flo of IC fa+rication> manufacturing and testing?ECTIVE'o im"art 9noledge on

Lithogra"h% techni=ues

Cr%stal groth

Com"lete flo of IC fa+rication,NIT I 2CR@ST*L GRTH/ *'ER PREP*R*TIN/ EPIT*@ *ND ID*TIN

Electronic 4rade Silicon> C@ochrals9i cr%stal groing> Silicon Sha"ing> "rocessing consideration> Va"or"hase E"ita Molecular eam E"ita Silicon on Insulators> E"ita 4roth Mechanismand 9inetics> 'hin , ,

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RE'ERENCES

1? S?M?S@e> HVLSI 'echnolog%> Mc?4ra?5ill Second Edition? 1//-?2?Amar mu9heree> HIntroduction to 7M,S and CM,S VLSI S%stem design Prentice 5all India?2000?3?ames $ Plummer> Michael $? $eal> Peter ?4riffin> HSilicon VLSI 'echnolog% fundamentals "racticeand Modeling> Prentice 5all India?2000?

&? 8ai Bai Chen>VLSI 'echnolog% CDC "ress> 2003

,RLs

1? htt"..?n"tel?iitm?ac?in.#ideo?"h"Qsu+ectIdR11*10)0/32. htt"..?authorstream?com.Presentation.7iteesh6-&)&06#lsi6technolog%6entertainment6""t6

"oer"oint.

9

http://www.nptel.iitm.ac.in/video.php?subjectId=117106093http://www.authorstream.com/Presentation/Niteesh-84640-vlsi-technology-entertainment-ppt-powerpoint/http://www.authorstream.com/Presentation/Niteesh-84640-vlsi-technology-entertainment-ppt-powerpoint/http://www.nptel.iitm.ac.in/video.php?subjectId=117106093http://www.authorstream.com/Presentation/Niteesh-84640-vlsi-technology-entertainment-ppt-powerpoint/http://www.authorstream.com/Presentation/Niteesh-84640-vlsi-technology-entertainment-ppt-powerpoint/

8/13/2019 RegC

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P)VLC+9 VERILG PRGR*MMING L T P C$ ) + 9

*IM'o ena+le the student to understand and rite the Verilog ProgramesECTIVE'o im"art 9noledge on

$ifferent data t%"es $ifferent "rogramming methods

Verilog s%nthesis,5it I Di1ital desi15 Aith !erilo1 HDL = Hierarchical -odeli51 co5ce8ts$esign Flo> 'rends in 5$L> $esign Methodologies> Modules> Instances> asic Conce"ts6 le $ata t%"es> S%stem tas9s and com"iler directi#es?

,5it B Modules a5d 8ortsModule definitions> "ort declaration> connecting "orts> hierarchical name referencing?

,5it $ Gate le!el a5d data6loA -odeli514ate le#el Modeling using +asic> #erilog gate "rimiti#es> $ifferent timings6rise> fall> min> ma t%"ical$ataflo continuos assignments> dela% s"ecification> e initial and ala%s statements> +loc9ing and non +loc9ing statements> dela%control>e#ent control> conditional statement> multia% +ranching> loo"s> se=uential and "arrelel +loc9s

,5it : Lo1ic sy5thesis Aith !erilo1 HDLS%nthesis $esign flo> #erilog s%nthesis> #erification ith gate le#el netlist> $esign "artition> se=uentialcircuit s%snthesis?

TT*L 9:3):Tutorial ";+ PERIDS Sunmicro s%stems Press> Prentics 5all2? 5dl Programming Fundamentals Vhdl And Verilog: Series 6 $a#inci Engineering ;

Hardco!er ( B++;+)+) by 7a@eih M? otros

,RLs1? htt8AAA.asic(Aorld.co-!erilo1!eritut.ht-l2? htt8AAA.ece.u-d.educoursese5ee$:2a!erilo1tutorial.8d6

10

http://www.asic-world.com/verilog/veritut.htmlhttp://www.ece.umd.edu/courses/enee359a/verilog_tutorial.pdfhttp://www.asic-world.com/verilog/veritut.htmlhttp://www.ece.umd.edu/courses/enee359a/verilog_tutorial.pdf

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P)VLC+:*N*LG INTEGR*TED CIRC,IT DESIGN L T P C$ ) + 9

*IM'oeAssociation of "oles ith nodes> fre=uenc% res"onse of common source stage> Sourcefolloers> Common gate stage> Cascode stage> $ifferential "air> Statistical characteristics of noise> >noise

in differential am"lifiers?

,NIT III PER*TIN*L *MPLI'IERS 2Conce"t of negati#e feed+ac9> Effect of loading in feed+ac9 netor9s> o"erational am"lifier "erformance"arameters> ,ne6stage ," Am"s> 'o6stage ," Am"s> In"ut range limitations> 4ain +oosting> sle rate>"oer su""l% reection> noise in ," Am"s?

,NIT IV ST* H$esign of Analog CM,S Integrated Circuits> 'ata Mc4ra 5ill> 20012? 8ille% M?C? Sansen> HAnalog design essentials> S"ringer> 200)?3? 4re+ene> Hi"olar and M,S Analog Integrated circuit design> ohn 8ile% ! sons>Inc?> 2003?&? Philli" E?Allen> $ouglasD?5ol+erg> HCM,S Analog Circuit $esign> Second edition> , 2002

,RLs1? uhae+?hartford?edu.ilumo9an.Intro()*?""t2? htt8co(lear5.i5sitesde6ault6ilescourses(8d6sEE;)J(L).8d6

P)VLC+; VLSI DESIGN L*< L T P C + + B B

11

http://co-learn.in/sites/default/files/courses-pdfs/EE618-L1.pdfhttp://co-learn.in/sites/default/files/courses-pdfs/EE618-L1.pdf

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*IM

'o gi#e hands on e

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SEMESTER IIPBVLC+#DIGIT*L CMS VLSI DESIGN L T P C

$ ) + 9*IM'oha#e the detail stud% of $igital CM,S design

ECTIVE'o im"art 9noledge on

M,S de#ice modeling

$iferente com+inational logic circuits

Cloc9ing methods for se=uential circuits

,NIT I MS TR*NSISTR PRINCIPLES 2M,S 'echnolog% and VLSI> Process "arameters and considerations for> M,S and CM,S> Electrical"ro"erties of CM,S circuits and $e#ice modeling? CM,S In#erter Scaling CM,S circuits> Scaling"rinci"les and fundamental limits?

,NIT II CM Elmores

constant> $%namic Logic 4ates> Pass 'ransistor Logic> Poer $issi"ation> Lo Poer $esign"rinci"les?

,NIT III SE4,ENTI*L LGIC CIRC,ITS 2Static and $%namic Latches and Degisters> 'iming Issues> Pi"elines> Cloc9ing strategies> Memor%

Architectures> and Memor% control circuits> S%nchronous and As%nchronous $esign?

,NIT IV DESIGNING *RITHMETIC arrel Shifters> S"eed and Area'radeoffs

,NIT V IMPLEMENT*TIN STR*TEGIES 2Full Custom and Semicustom $esign> Standard Cell design and cell li+raries> FP4A +uilding +loc9

architectures> FP4A interconnect routing "rocedures> enchmar9 Circuits> Case Studies?

TT*L 9:3):Tutorial" PERIDS Anantha Chandra9asan> 7i9olic> H $igital Integrated Circuits A $esign Pers"ecti#e?Second Edition> Fe+ 2003> Prentice 5all of India?

2? 7?8este> B? Eshraghian> H Princi"les of CM,S VLSI $esign? Second Edition> 1//3 Addision 8esle%>

3?&? M Smith> HA""lication S"ecific Integrated Circuits> Addisson 8esle%> 1//*(? Anantha Chandra9asan> 8?> ohill and F?Fo H$esign of 5igh Performance Micro"rocessor

Circuits> ohn 8ile%> 2000?,RLs1?htt"..?"d

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PBVLC+JTESTING ' VLSI CIRC,ITS L T P C$ ) + 9

*IM'o ma9e the student to understand the need for testing> difficult% in testing> and different methods oftesting

ECTIVES'o im"art 9noledge on

Various faults and fault models

'echni=ues for testing of com+inational circuits> se=uential circuits> memor% and em+eddedDAMs

,NIT I 2

Introduction to 'esting 6 Faults in digital circuits 6 Modeling of faults 6 Logical Fault Models 6 Faultdetection 6 Fault location 6 Fault dominance 6 Logic Simulation 6 '%"es of simulation 6 $ela% models 64ate le#el E#ent6dri#en simulation?

,NIT II 2

'est generation for com+inational logic circuits 6 'esta+le com+inational logic circuit design 6 'estgeneration for se=uential circuits 6 design of testa+le se=uential circuits?

,NIT III 2

$esign for 'esta+ilit% 6 Ad6hoc design 6 4eneric scan +ased design 6 Classical scan +ased design 6S%stem le#el $F' a""roaches?

,NIT IV 2

uilt6In Self 'est 6 'est "attern generation for IS' 6 Circular IS' 6 IS' Architectures 6 'esta+le Memor%$esign 6 'est algorithms 6 'est generation for Em+edded DAMs

,NIT V 2

Logic Le#el $iagnosis 6 $iagnosis +% ' reduction 6 Fault $iagnosis for Com+inational Circuits 6 Self6chec9ing design 6 S%stem Le#el $iagnosis?

TT*L 9:3):Tutorial " ;+ 8eriods $igital S%stems and 'esta+le $esign aicoPu+lishing 5ouse> 2002?

2? P?B? Lala> $igital Circuit 'esting and 'esta+ilit%> Academic Press> 2002?

3? M?L? ushnell and V?$? Agraal> Essentials of Electronic 'esting for $igital> Memor% and Mi Bluar Academic Pu+lishers> 2002?

&? A?L? Crouch> $esign for 'est for $igital ICOs and Em+edded Core S%stems> Prentice 5allInternational> 2002?

,RLs1? htt"..?ece?uc?edu.one.Com+6'4?"df2? ?ece?mcgill?ca.@@ilic.)&/.hh?""t

14

http://www.ece.uc.edu/~wjone/Comb-TG.pdfhttp://www.ece.mcgill.ca/~zzilic/649/hh.ppthttp://www.ece.uc.edu/~wjone/Comb-TG.pdfhttp://www.ece.mcgill.ca/~zzilic/649/hh.ppt

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PBVLC+2VLSI SIGN*L PRCESSING L T P C$ + + $

*IM'o stud% the signal "rocessing in VLSI "ros"ecti#eECTIVE'o im"art 9noledge on

Programming "rocessor $ifferent con#olution techni=ues

Arithmetic architectures

,NIT I INTRD,CTIN T DSP S@STEMS 2Introduction 'o $SP S%stems 6'%"ical $SP algorithmsT Iteration ound data flogra"h re"resentations> loo" +ound and iteration +ound> Longest "ath Matri "arallel"rocessing> "i"elining and "arallel "rocessing for lo "oer?

,NIT II RETIMING 2Detiming 6 definitions and "ro"ertiesT nfolding an algorithm for nfolding>"ro"erties of unfolding> sam"le "eriod reduction and "arallel "rocessing a""licationT

Algorithmic strength reduction in filters and transforms 26"arallel FID filter> 26"arallelfast FID filter> $C' algorithm architecture transformation> "arallel architectures forran96order filters> ,dd6 E#en Merge6 Sort architecture> "arallel ran96order filters?

,NIT III '*ST CNVL,TIN 2Fast con#olution Coo96'oom algorithm> modified Coo96'oo9 algorithmT Pi"elinedand "arallel recursi#e and ada"ti#e filters inefficient.efficient single channelinterlea#ing> Loo96 Ahead "i"elining in first6 order IID filters> Loo96Ahead "i"eliningith "oer6of6to decom"osition> Clustered Loo96Ahead "i"elining> "arallel"rocessing of IID filters> com+ined "i"elining and "arallel "rocessing of IID filters>"i"elined ada"ti#e digital filters> rela "i"elined LMS ada"ti#e filter?

,NIT IV scaling and roundoff noise com"utation> roundoff noise in"i"elined first6order filtersT it6Le#el Arithmetic Architectures6 "arallel multi"liers ithsign e "arallel carr%6ri""le arra% multi"liers> "arallel carr%6sa#e multi"lier> & designof L%ons +it6serial multi"liers using 5orners rule> +it6serial FID filter> CS$re"resentation> CS$ multi"lication using 5orners rule for "recision im"ro#ement?

,NIT V PRGR*MMING DIGIT*L SIGN*L PRCESSRS 2

7umerical Strength Deduction su+e to6"hase cloc9ing> a#e "i"elining>

as%nchronous "i"elining +undled data #ersus dual rail "rotocolT Programming $igitalSignal Processors general architecture ith im"ortant featuresT Lo "oer $esign needs for lo "oer VLSI chi"s> charging and discharging ca"acitance> short6circuitcurrent of an in#erter> CM,S lea9age current> +asic "rinci"les of lo "oer design?

TT*L 9: PERIDS

$igital lattice Filter Structures

15

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RE'ERENCES). Feshab F.Parhi/ VLSI Di1ital Si15al Processi51 syste-s/ Desi15 a5d

i-8le-e5tatio5 / iley/ I5ter Scie5ce/ )222.2? 4ar% Gea"> UPractical Lo Poer $igital VLSI $esign> Bluer Academic

Pu+lishers> 1//-?

3? Mohammed Ismail and 'erri Fie@> HAnalog VLSI Signal and InformationProcessing > Mc 4ra65ill> 1//&?

&? S.@. Fu51/ H.>. hite House/ T. Failath/ VLSI a5d Moder5 Si15al Processi51/ Pre5tice Hall/ )2J:?

(? ose E? France> Gannis 'si#idis> $esign of Analog 6 $igital VLSI Circuits for'elecommunication and Signal Processing > Prentice 5all> 1//&?

,RLs1? htt"..?ece?umn?edu.users."arhi.SLI$ES.cha"13?"df

2? ?ece?umn?edu.grou"s.dd".inde

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PBVLC)+*SIC DESIGN L T P C $ ) + 9*IM'o stud% the $esign of ASIC> logic cells of #arious su""liers

ECTIVES

'o im"art 9noledge on CM,S and ASIC li+rar% design>

'he t%"es of "rogramming> architecture of logic cells and I., cells>

$ifferent techni=ues of interconnection?

'o understand a+out "artitioning> floor "lanning> "lacement and routing techni=ues?

,NIT IINTRD,CTIN T *SICS/ CMS LGIC *ND *SIC LIinterfacing; 6 Altera MA (000 and *000 6Altera MA /000 6 Altera FLE Altera C%clone II:architecture > interfacing ; $esign s%stems 6 LogicS%nthesis 6 5alf gate ASIC 6Schematic entr% 6 Lo le#el design language 6 PLA tools 6E$IF6 CFI designre"resentation?,NIT IV *SIC CNSTR,CTIN/ 'LR PL*NNING/ PL*CEMENT *ND R,TING 2

S%stem "artition 6 FP4A "artitioning 6 "artitioning methods 6 floor "lanning 6 "lacement 6 "h%sical designflo glo+al routing 6 detailed routing s"ecial routing 6 circuit e gate dela%s> o"erators> timing controls> "roceduralassignments conditional statements> $ata flo and D'L> structural gate le#el sitch le#el modeling>$esign hierarchies> eha#ioral and D'L modeling> 'est +enches> Structural gate le#el descri"tion ofdecoder> e=ualit% detector> com"arator> "riorit% encoder> half adder> full adder> Di""le carr% adder> $ latchand $ fli" flo"? $ifferent counters and FSM modeling

TT*L 9:3):Tutorial " ;+ 8eriods

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RE'ERENCES

11 M??S ?Smith> A""lication S"ecific Integrated Circuits> Addison 68esle% Longman Inc?> 1//*?

11 Far@ad 7e9oogar and Farana9 7e9oogar> From ASICs to S,Cs A Practical A""roach> Prentice5all P'D> 2003?

8a%ne 8olf>'PG*( Prentice 5all P'D> 200&?11 D? Dasuman> S%stem6on6a6Chi" $esign and 'est? Santa Clara> CA Artech 5ouse Pu+lishers>2000?

11 F? 7e9oogar? 'iming Verification of A""lication6S"ecific IntegratedCircuits :ASICs;. Prentice 5allP'D> 1///?

11 ilin Altera document should +e gi#en

11 ?has9er Verilog 5$L "rimer> S "u+lication>2001

Ciletti Ad#anced $igital $esign ith the Verilog 5$L> Prentice 5all of India> 2003

DLs1? htt"..?ece?ncsu?edu.asic.tutorials.tutor1.tutor1?"df2? htt"..?asic6orld?com.

18

http://vig.prenhall.com/catalog/academic/product/0,1144,0131424610,00.htmlhttp://vig.prenhall.com/catalog/academic/product/0,1144,0131424610,00.htmlhttp://www.ece.ncsu.edu/asic/tutorials/tutor1/tutor1.pdfhttp://www.asic-world.com/http://vig.prenhall.com/catalog/academic/product/0,1144,0131424610,00.htmlhttp://www.ece.ncsu.edu/asic/tutorials/tutor1/tutor1.pdfhttp://www.asic-world.com/

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PBVLC))VLSI 'R IRELESS CMM,NIC*TINL T P C

$ + + $*IM'o stud% the ireless communication in VLSI "ers"ecti#e

ECTIVE'o im"art 9noledge on

$ata con#erters

Coding algorithms and techni=ues

,NIT I *N*LG T DIGIT*L CNVERSIN 2Performance metrics for Analog6to6digital con#erters> sam"ling> +and6"ass sam"ling> =uanti@ation> '%"esof Analog6to6digital con#erters> Sigma $elta Analog6to6digital con#erters?

,NIT II CDING THER@ *LGRITHMS *ND *RCHITECT,RE 2Con#olution codes> trellis diagram> #iter+i algorithm> soft in"ut decoding> soft out"ut decoding> 'ur+ocodes> L$PC coding> concatenated con#olution codes> eight distri+ution> S"ace6'ime codes> s"atial

channels> "erformance measure> ,rthogonal s"ace6time +loc9 codes> s"atial multi"le Su"erheterod%ne recei#er> Image reection recei#er>65artle% and 8ea#er> Jero IFrecei#er> Lo IF recei#er> 'ransmitter architecture> Su"erheterod%ne transmitter> $irect u" transmitter>'o6ste"6u" transmitter> 'ransceie#er architectures for modern ireless s%stems> Case stud%?

,NIT IV 'DM S@S@TEM 2Princi"le> "ro"agation characteristics>"rinci"le> mathematical model> ,F$M +ase+and signal"rocessing>Decei#er design> Automatic gain control and $C offset com"ensation> codesign of Automaticgain control and timing s%nchroni@ation> codesign of filtering and timing s%nchroni@ation> 'ransmit chainsetu"?,NIT V *N*LG IMP*IRMENT *ND ISS,ES 2Decei#er sensiti#it% and noise figure> $C offsets> L, lea9age> Decei#er interferers and intermodulationdistortion> Image reection> Kuadrature +alance and relation to Image reection> relation to EVM> Pea9 toa#erage "oer ratio > Local oscillator "ulling in PLL> effect of "hase noise in PLL> Effect of "hase noise on,F$M s%stems> Effect of fre=uenc% errors on ,F$M s%stems?

TT*L 9: PERIDSS"ringer> 200-?DLs1? htt"..?scri+d?com.doc./0)/)22).Coding6'heor%6Algorithms6Architectures6And6A""lications6Andre67eu+auer6Et6Al6200*2? htt"..h%"er"h%sics?"h%6astr?gsu?edu.h+ase.electronic.adc?html

19

http://www.scribd.com/doc/90696226/Coding-Theory-Algorithms-Architectures-And-Applications-Andre-Neubauer-Et-Al-2007http://www.scribd.com/doc/90696226/Coding-Theory-Algorithms-Architectures-And-Applications-Andre-Neubauer-Et-Al-2007http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/adc.htmlhttp://www.scribd.com/doc/90696226/Coding-Theory-Algorithms-Architectures-And-Applications-Andre-Neubauer-Et-Al-2007http://www.scribd.com/doc/90696226/Coding-Theory-Algorithms-Architectures-And-Applications-Andre-Neubauer-Et-Al-2007http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/adc.html

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PBVLC)B EM

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ELECTIVE % IPEVLC):VLSI S@STEM DESIGN L T P C $ + + $*IM'o introduces #arious su+s%stems of a s%stem design> their control logic> #erification and testing?ECTIVES

'o im"art 9noledge on CM,S su+s%stem deign

$ifferent t%"es of memor% structure

asic of s%stem Verilog

,NIT I CMS S, simulation time units and

"recision> s%stem Verilog data t%"es> t%"e casting?

,NIT V S@STEM VERILG *RR*@S/ STR,CT,RES *ND ,NINS 2

Assigning #alues to structures> "ac9ed and un"ac9ed structures> arra%s> structures and unions>asic "rogramming in S%stem Verilog

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*IM'o introduce a +asic 9noledge of semiconductor "h%sics> transistor modeling> o"to electronic de#icemodeling and de#ice "arameter measurement?

ECTIVES

'o im"art 9noledge onSemiconductor "h%sics> uni"olar and +i"olar de#ice modeling

,NIT I Continuit% E=uation> $iode Small Signal and Large Signal :ChangeControl Model;> 'ransistor Models E++er Molls Model and 4ummel Port Model> Me SPICEmodeling tem"erature and area effects?

,NIT III MS'ET MDELING 2

Introduction Interior La%er> M,S 'ransistor Current> 'hreshold Voltage> 'em"erature Short Channel and7arro 8idth Effect> Models for Enhancement> $e"letion '%"e M,SFE'> CM,S Models in SPICE andstud% of 'anner tool?

,NIT IV P*R*METER ME*S,REMENT 2

4eneral Methods> S"ecific i"olar Measurement> $e"letion Ca"acitance> Series Desistances> Earl%Effect> 4ummel Plots> M,SFE' Long and Short Channel Parameters> Statistical Modeling of io"olarand M,S 'ransistors?

,NIT V PTELECTRNIC DEVICE MDELING 2

Static and $%namic Models> Date E=uations> 7umerical 'echni=ue> E=ui#alent Circuits> Modeling ofLE$s> Laser $iode and Photo detectors>

TT*L 9: Periods $ouglas D?5o+erg> HCM,S Analog Circuit $esign Second Edition> , Samir S?Dofail> 8ang6Ling 4o+> HCM,S . iCM,S LSI 6 Lo Voltage> loPoer> Person education> Lo "rice edition> 2003?

3? S?M?S@e HSemiconductor $e#ices 6 Ph%sics and 'echnolog%> ohn 8ile% and sons> 1/-(?

&? 4iuse""e Masso+rio and Paolo Antogentti> HSemiconductor $e#ice Modeling ith SPICESecond Edition> Mc4ra65ill Inc> 7e Gor9> 1//3?

,RLs1? htt"..?electronics6tutorials?s.diode.diode1?html2? htt"..ecee?colorado?edu.+art.+oo9.+oo9.cha"ter&.ch&)?htmPEVLC)# EM

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'o gi#e e netor9s of em+eddeds%stems and real time characteristics of em+edded s%stems?ECTIVE'o im"art 9noledge on

Em+edded com"uters architecture

S structure organi@ation of different "rocessors

,NIT I EM Challenges in Em+eddedCom"uting s%stem design> em+edded s%stem design "rocess6 De=uirements> S"ecification> Architectural$esign> $esigning 5ardare and Softare Com"onents> S%stem Integration> Formalism for S%stem6$esign6 Structural $escri"tion> eha#ioral $escri"tion> and $esign E Flo of Control> S5ADC"rocessor6 Memor% organi@ation> $ata o"erations> Flo of Control> "arallelism ith instructions> CP usconfiguration> ADM us> S5ADC us> Memor% de#ices> In"ut.out"ut de#ices> Com"onent interfacing>

designing ith micro"rocessor de#elo"ment and de+ugging> $esign E S%stem Anal%sis and Architecture $esign>Kualit% Assurance> $esign E In9 et "rinter6 5ardare$esign and Softare $esign> Personal $igital Assistants> Set6to" o s"ecial features6 serial "rogramming "arallel sla#e "ort?

,NIT V EM addressing modes "rograms> interfacing methods"arallel i.o interface> "arallel "ort interface> memor% interfacing? 5igh s"eed i.o interfacing> interru"ts interru"t ser#ice routine6features of interru"ts interru"t #ector and "riorit%> timing generation andmeasurements> in"ut ca"ture> out"ut com"are> fre=uenc% measurement> serial i.o de#ices Ds232> Ds&-(6

Analog interfacing> a""lications?TT*L 9: 8eriods

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Deal time interfacing>

'homson learning 2001?&? Fran9 Vahid and 'on% 4i#argi> Em+edded S%stem $esign A nified 5ardare.Softare

Introduction>s> ohn 8ile% ! Sons> 2000?(? PIC microcontroller an introduction to softare and hardare interfacing % 5an68a% 5uang

DLs1? htt"..?unro+otica?com."u+lic.li+ro-?"df

24

http://www.unrobotica.com/public/libro8.pdfhttp://www.unrobotica.com/public/libro8.pdf

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PEVLC)J DSP PRCESSR *RCHITECT,RE *ND PRGR*MMING L T P C $ + + $

*IM'o learn a+out "rogramma+le $SPs and architectureECTIVES

'o im"art 9noledge on VLI8 architecture

'%"ical stud% a+out C(.C3 "rocessors>

A$SP "rocessors and some ad#anced $SPs useful for real time a""lications?

,NIT I ',ND*MENT*LS ' PRGR*MM* Con#olution of to se=uences> Filter design

,NIT IV *DSP PRCESSRS 2

Architecture of A$SP621 and A$SP6210 series of $SP "rocessors6 Addressing modes and

assem+l% language instructions A""lication "rograms Filter design> FF' calculation?

,NIT V *DV*NCED PRCESSRS 2

Architecture of 'MS320C(& Pi"e line o"eration> Code Com"oser studio 6 Architecture of 'MS320C) 6Architecture of Motorola $SP()3 Com"arison of the features of $SP famil% "rocessors?

TT*L 9: PERIDS

5armon% "rocessor>

RE'ERENCES

1? ?Ven9ataramani and M?has9ar> H$igital Signal Processors Architecture> Programming andA""lications 'ata Mc4ra 5ill Pu+lishing Com"an% Limited? 7e $elhi> 2003?

2? ser guides 'e Analog $e#ices> Motorola?DLs1? htt"..?datasheetarchi#e?com.'MS320C(

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*IM'o ena+le the students to learn the efiiceint hardare architectures for #arious signal "rocessinga""lications?ECTIVES'o im"art 9noledge on

S"eech coding and standards

Multirate signal "rocessing

,NIT I M,LTIR*TE SIGN*L PRCESSING 2$ecimation and Inter"olation> S"ectrum of decimated and inter"olated signals> Pol%"hase decom"ositionof FID filters and its a""lications to multi6rate $SP> Sam"ling rate con#erters Su+6+and encoder

,NIT II 'ILTER Com"utation of $8' using filter +an9s

,NIT III DD'S 2D,M L' a""roach> S"urious signals itter? Com"utation of s"ecial functions using C,D$IC> Vector androtation mode of C,D$IC> C,D$IC architectures

,NIT IV Incoherent demodulation 6 digital a""roach for I and K generation> s"ecial sam"ling schemes? CIC filters?Desidue num+er s%stem and high s"eed filters using D7S? $on con#ersion using discrete 5il+erttransform? nder sam"ling recei#ers> Coherent demodulation schemes

,NIT V SPEECH CDING *ND ST*ND*RDS 2Models of #ocal tract> S"eech coding using linear "rediction> CELP coder> an o#er#ie of a#eformcoding> Vocoders> Vocoder attri+utes? loc9 diagrams of encoders and decoders of 4*23?1> 4*2)> 4*2*>4*2- and 4*2/?

TT*L 9: 8eriods

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'o ma9e the students to understand the "h%sical design of a chi"ECTIVES'o im"art 9noledge on

$ifferent floor "lanning method

$ifferent routing algorithms,NIT I

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,NIT I INTRD,CTIN T VLSI TECHNLG@ 2La%out Dules6Circuit a+straction Cell generation using "rogramma+le logic arra% transistor chaining> 8einerger arra%s and gate matrices6la%out of standard cells gate arra%s and sea of gates> field"rogramma+le gate arra%:FP4A;6la%out methodologies6Pac9aging6Com"utational Com"le1//-?3? Sadi= M? Sait> 5a+i+ Goussef HVLSI Ph%sical $esign Automation> 'heor% and Practice 8orldScientific Pu+lishing Com"an%> 1stEdition>1///?

,RLs1? htt"..?ifte?de.mitar+eiter.lienig.ea+oo9?"df2? htt"..?eecs?+er9ele%?edu.neton."resentations.Ar"a10-/.tsld00-?htm

PEVLCBB HIGH SPEED SITCHING *RCHITECT,RE L T P C$ + + $

*IM'o stud% a+out different 5igh s"eed sitching circuits

ECTIVE'o im"art 9noledge on

$ifferent sitching technologies

28

http://www.ifte.de/mitarbeiter/lienig/eabook.pdfhttp://www.eecs.berkeley.edu/~newton/presentations/Arpa10_89/tsld008.htmhttp://www.ifte.de/mitarbeiter/lienig/eabook.pdfhttp://www.eecs.berkeley.edu/~newton/presentations/Arpa10_89/tsld008.htm

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$ifferent architectures

Kues architecture

,NIT I L*N SITCHING TECHNLG@ 2Sitching Conce"ts> sitch forarding techni=ues> sitch "ath control> LA7 Sitching> cut throughforarding> store and forard> #irtual LA7s?

,NIT II *TM SITCHING *RCHITECT,RE 2loc9ing netor9s 6 +asic 6 and6 enhanced +an%an netor9s> sorting netor9s 6 merge sorting> re6arranga+le netor9s 6 full6and6 "artial connection netor9s> non +loc9ing netor9s 6 Decursi#e netor9construction> com"arison of non6+loc9ing netor9> Sitching ith deflection routing 6 shuffle sitch>tandem +an%an sitch?,NIT III 4,E,ES IN *TM SITCHES 2Internal Kueueing 6In"ut> out"ut and shared =ueueing> multi"le =ueueing netor9s com+ined In"ut>out"ut and shared =ueueing 6 "erformance anal%sis of Kueued sitches?,NIT IV P*CFET SITCHING *RCHITECT,RES 2

Architectures of Internet Sitches and Douters6 ufferless and +uffered Cross+ar sitches> Multi6stagesitching> ,"tical Pac9et sitchingT Internall% +uffered Cross+ars?,NIT V IP SITCHING 2

Addressing model> IP Sitching t%"es 6 flo dri#en and to"olog% dri#en solutions> IP o#er A'M address

and ne HSitching 'heor% Architectures and "erformance in road+and A'M netor9s >ohn 8ile% ! Sons Ltd> 7e Gor9? 1//-2? Elhanan% M? 5amdi> H5igh Performance Pac9et Sitching architectures> S"ringer Pu+lications> 200*?3? Christo"her G Met@> HSitching "rotocols ! Architectures> Mc4ra 5ill Professional Pu+lishing>7eGor9?1//-?&? Dainer 5andel> Manfred 7 5u+er> Stefan Schroder> HA'M 7etor9s 6 Conce"ts Protocols>

A""lications> 3rd Edition> Addison 8esle%> 7e Gor9? 1///?

,RLs). htt"..?niceindia?com.=+an9.dc1)21highs"eedsitchingarchitecture?"df2? htt"..9612?"isd?edu.currinst.netor9.0)-0(A261S4?"df

29

http://www.niceindia.com/qbank/dc1621_high_speed_switching_architecture.pdfhttp://k-12.pisd.edu/currinst/network/06_805A_2-1_SG.pdfhttp://www.niceindia.com/qbank/dc1621_high_speed_switching_architecture.pdfhttp://k-12.pisd.edu/currinst/network/06_805A_2-1_SG.pdf

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PEVLCB$ DESIGN ' VLSI IN EM$esign challenge ,"timi@ing design metrics> Processor 'echnolog%>4eneral"ur"ose Processors> Single"ur"ose Processors> and A""lication S"ecific Processors> IC'echnolog% Full custom.VLSI> Semicustom ASIC> PL$> 'rends> $esign 'echnolog%?

,NIT II C,STM SINGLE P,RPSE PRCESSR 2

D' le#el com+inational com"onents> D' le#el se=uential com"onents > Custom Single"ur"ose Processor $esign> D' le#el Custom Single "ur"ose Processor $esign> ,"timi@ing Custom

Single "ur"ose Processors > ,"timi@ingthe original "rogram> ,"timi@ing the FSM$>,"timi@ing the data"ath> o"timi@ing the FSM?

Ge5eral8ur8ose Processorsasic architecture> $ata "ath> Control unit> Memor%> Pi"elining> Su"erscalar and VLI8 architectures>

A""lication S"ecific instruction set Processors :ASIPs;> Microcontrollers> $SP> Less4eneral ASIP en#ironments> selecting a Micro"rocessor. 4eneral "ur"ose Processor $esign?

,NIT III *DV*NCED CMM,NIC*TIN PRINCIPLES 2

Parallel> serial and ireless Communications> Serial "rotocols 'he I2C us> 'he CA7 +us> Fire ire+us> S? Parallel "rotocols PCI +us> AMA +us> ireless "rotocols Ir$A> luetooth> IEEE -02?11?

,NIT IV DIGIT*L C*MER* E*MPLE 2

sers "ers"ecti#e> $esigner "ers"ecti#e> S"ecification> Informal functional s"ecification> 7onfunctionals"ecification ?E Im"lementation 2Fi hardare and softare interaction> miheterogeneous MPS,C> Virtual architecture model> #irtual architecture in s%stemC> a""lication e 9atalin "o"o#ici>ahmed eer%a>Maril%n olf>S"ringer "u+lications>2010?3? HEm+edded S%stem $esign Ste#e 5eath>utterorth5einemann?&? HS"ecification and $esign of Em+edded s%stems> 4as9i and Vahid>Prentice 5all?

PEVLCB9*DV*NCED MICRPRCESSRS *ND MICRCNTRLLERS L T P C$ + + $

*IM

30

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'o stud% a+out the ad#anced "rocessors in the VLSI industr%

ECTIVE'o im"art 9noledge on

Pentium Processors architectures

ADM Processors architectures

Ad#anced micro controller architectures?

,NIT I MICRPRCESSR *RCHITECT,RE 2Instruction Set $ata formats Addressing modes Memor% hierarch% register file Cache Virtualmemor% and "aging Segmentation6 "i"elining the instruction "i"eline "i"eline ha@ards instructionle#el "arallelism reduced instruction set Com"uter "rinci"les DISC #ersus CISC?,NIT II HIGH PER'RM*NCE CISC *RCHITECT,RE % PENTI,M 2CP Architecture6 us ,"erations Pi"elining rach "redication floating "oint unit6 ,"erating Modes

Paging Multitas9ing E 2000?&? 4ene ?5?Miller ? Micro Com"uter Engineering > Pearson Education > 2003?(? ohn ??Peatman > H $esign ith PIC Microcontroller > Prentice hall> 1//*?)? ames L?Antona9os > An Introduction to the Intel famil% of Micro"rocessors U Pearson Education 1///?*? arr%??reg> 'he Intel Micro"rocessors Architecture > Programming andInterfacing H > P5I>2002?

,RLs). htt"..?cse?ohio6state?edu."anda.**(.slides.intel"oer"erf0)?"df2? htt"..home"ages?thm?de.hg10013.Lehre.MMS.8S030&SS0&.Ioannis.P$F.arm?"df

ELECTIVE III

PEVLCB: H*RD*RE.S'T*RE C(DESIGN L T P C$ + + $

*IM

31

http://www.cse.ohio-state.edu/~panda/775/slides/intel_power_perf_06.pdfhttp://homepages.thm.de/~hg10013/Lehre/MMS/WS0304_SS04/Ioannis/PDF/arm.pdfhttp://www.cse.ohio-state.edu/~panda/775/slides/intel_power_perf_06.pdfhttp://homepages.thm.de/~hg10013/Lehre/MMS/WS0304_SS04/Ioannis/PDF/arm.pdf

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'o ma9e the student to understand the 5ardare . Softare Co6$esign

ECTIVE'o im"art 9noledge on

Protot%"ing of S.8 !5.8

5ardare.Softare Partitioning

5ardare.Softare co s%nthesis

,NIT I S@STEM SPECI'IC*TIN *ND MDELLING 2Em+edded S%stems > 5ardare.Softare Co6$esign > Co6$esign for S%stemS"ecification and Modelling > Co6$esign for S%stem S"ecification and Modelling > Co6$esign for 5eterogeneous Im"lementation 6 Processor S%nthesis > Single6Processor

Architectures ith one ASIC > Single6Processor Architectures ith man% ASICs>Multi6Processor Architectures > Com"arison of Co6$esign A""roaches > Models ofCom"utation >De=uirements for Em+edded S%stem S"ecification ?

,NIT II H*RD*RES'T*RE P*RTITINING 2'he 5ardare.Softare Partitioning Pro+lem> 'he 5ardare.Softare PartitioningPro+lem> 5ardare.Softare Cost Estimation> 4eneration of the Partitioning 4ra"h >

Formulation of the 58.S8 Partitioning Pro+lem > ,"timi@ation > 58.S8 Partitioning+ased on 5euristic Scheduling> 58.S8 Partitioning +ased on 4enetic Algorithms ?

,NIT III H*RD*RES'T*RE C(S@NTHESIS 2'he Co6S%nthesis Pro+lem> State6'ransition 4ra"h> Definement and Controller4eneration> $istri+uted S%stem Co6S%nthesis

,NIT IV PRTT@PING *ND EM,L*TIN 2Introduction> Protot%"ing and Emulation 'echni=ues >Protot%"ing and EmulationEn#ironments >Future $e#elo"ments in Emulation and Protot%"ing >'arget

Architecture6 Architecture S"eciali@ation 'echni=ues >S%stem CommunicationInfrastructure> 'arget Architectures and A""lication S%stem Classes> Architecturesfor Control6$ominated S%stems> Architectures for $ata6$ominated S%stems >Mi Interfacing Com"onents>Verification > Languages for S%stem6Le#el S"ecification and $esign S%stem6Le#elS"ecification >$esign De"resentation for S%stem Le#el S%nthesis> S%stem Le#elS"ecification Languages> 5eterogeneous S"ecification and Multi6Language Co6simulation

TT*L 9: PERIDS

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H5ardare.Softare Co6$esign for $ata Flo $ominatedEm+edded S%stems> Bluer Academic Pu+> 1//-?2? orgen Staunstru" > 8a%ne 8olf >5ardare.Softare Co6$esign Princi"les andPractice > Bluer Academic Pu+>1//*?3? 4io#anni $e Micheli > Dolf Ernst Morgon> Deading in 5ardare.Softare Co6$esign H Baufmann Pu+lishers>2001?

DLs1? htt"..?cse?uconn?edu.@shi.course.cse(0/*.ref.olf/&codesign?"df2? htt"..210?212?20(?2).sudarshan.Main.Courses.201262013.,ddSem.5sc12.lecses.refs.lec01.demicheli/*hardaresoftare?"df?

33

http://www.cse.uconn.edu/~zshi/course/cse5097/ref/wolf94codesign.pdfhttp://210.212.205.26/sudarshan/Main/Courses/2012-2013/OddSem/Hsc_12/lecses/refs/lec01/demicheli97hardwaresoftware.pdfhttp://210.212.205.26/sudarshan/Main/Courses/2012-2013/OddSem/Hsc_12/lecses/refs/lec01/demicheli97hardwaresoftware.pdfhttp://www.cse.uconn.edu/~zshi/course/cse5097/ref/wolf94codesign.pdfhttp://210.212.205.26/sudarshan/Main/Courses/2012-2013/OddSem/Hsc_12/lecses/refs/lec01/demicheli97hardwaresoftware.pdfhttp://210.212.205.26/sudarshan/Main/Courses/2012-2013/OddSem/Hsc_12/lecses/refs/lec01/demicheli97hardwaresoftware.pdf

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PEVLCB; N*NTECHNLG@ L T P C $ + + $

*IM'o stud% a+out the nano machines and nano de#ices

ECTIVE

'o Im"art 'he Bnoledge ,n

Solid state "h%sics

$ifferent 7ano de#ices

,NIT() INTRD,CTIN T PH@SICS ' THE SLID ST*TE 2Structure6si@e de"endence of "ro"erties6cr%stal structures6face centered cu+ic nano "articles6energ%+ands6insulators> semiconductors and conductors6reci"rocal s"ace6energ% +ands and ga"s ofsemiconductors6locali@ed "articlesX donors> acce"tors and dee" tra"s6mo+ilit%,NIT(B METHDS ' ME*S,RING PRPERTIES 2Structure6atomic structures6cr%stallogra"h%6"article si@e determination surface structure6microsco"%6transmission electron microsco"%6field ion microsco"%6scanning microsco"%6s"ectrosco"%6infrared andraman s"ectrosco"%6"hotoemission and < ra% s"ectrosco"%6

,NIT ($ PRPERTIES ' INDIVID,*L N*NP*RTICLES 2Introduction6metal nanoclusters6magic num+ers6theoretical modeling of nano"articals6geometricstructure6electronic structure6reacti#it%6fluctuations6semiconducting nano"articals6o"tical "articals6"hotofragmentation rare gas and molecular clusters6inert gas clusters6su"erfluid clusters6molecularclusters6method of s%nthesis6DF "lasma6chemical methods6thermol%sis6"ulsed laser methods,NIT (9 C*R 8ile%6VC5 20033? $re 7anos%stems> 8ile% 1//2?,RLs1? htt"..snf?stanford?edu.Education.7anotechnolog%?S7F?e+?"df2? htt"..?nanotec?org?u9.finalDe"ort?htm

34

http://snf.stanford.edu/Education/Nanotechnology.SNF.web.pdfhttp://www.nanotec.org.uk/finalReport.htmhttp://snf.stanford.edu/Education/Nanotechnology.SNF.web.pdfhttp://www.nanotec.org.uk/finalReport.htm

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PEVLCB# INTRD,CTIN T MEMS S@STEM DESIGN L T P C$ + + $

*IM'o gi#e introduction to micro electro mechanical detailsECTIVE'o im"art 9noledge on

Introduction 'o MEMS Mechanism for MEMs $esign

,NIT I INTRD,CTIN T MEMS 2MEMS and Micros%stems> Miniaturi@ation> '%"ical "roducts> Micro sensors> Micro actuation> MEMSith micro actuators> Microaccelorometers and Micro fluidics> MEMS materials> Micro fa+rication

,NIT II MECH*NICS 'R MEMS DESIGN 2Elasticit%> Stress> strain and material "ro"erties> ending of thin "lates> S"ring configurations>torsional deflection> Mechanical #i+ration> Desonance> 'hermo mechanics actuators> force andres"onse time> Fracture and thin film mechanics?

,NIT III ELECTR ST*TIC DESIGN 2Electrostatics +asic theor%> electro static insta+ilit%? Surface tension> ga" and finger "ull u"> Electro

static actuators> Com+ generators> ga" closers> rotar% motors> inch orms> Electromagneticactuators? +ista+le actuators?

,NIT IV CIRC,IT *ND S@STEM ISS,ES 2Electronic Interfaces> Feed+ac9 s%stems> 7oise> Circuit and s%stem issues> Case studies Ca"aciti#e accelerometer> Pei@o electric "ressure sensor> Modeling of MEMS s%stems> CA$ forMEMS?

,NIT V INTRD,CTIN T PTIC*L *ND R' MEMS 2,"tical MEMS> 6 S%stem design +asics 4aussian o"tics> matri< o"erations> resolution?> Casestudies> MEMS scanners and retinal scanning dis"la%> $igital Micro mirror de#ices? DF Memes design +asics> case stud% Ca"aciti#e DF MEMS sitch> "erformance issues?

TT*L 9: PERIDS

CDC "ress aco Daton> 2000?&? 3? 'ai Dan 5su> MEMS ! Micro s%stems $esign and Manufacture 'ata Mc4ra 5ill> 7e $elhi>

2002?

,RLs1? htt"..?co#entor?com."roducts.mems.2? htt"..?intellisense?com.u"load.0.20120(2/0310(1?"df

35

http://www.coventor.com/products/mems/http://www.intellisense.com/upload/0/20120529031051.pdfhttp://www.coventor.com/products/mems/http://www.intellisense.com/upload/0/20120529031051.pdf

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PEVLCBJ IRELESS SENSR NETRFS L T P C$ + + $

*IM'o gi#e introduction to the ireless sensor netor9sECTIVE'o im"art 9noledge on

Architectures of sensor netor9s 7etor9ing of sensors

Infra structures

,NIT I VERVIE ' IRELESS SENSR NETRFS 2Challenges for 8ireless Sensor 7etor9s6Characteristics re=uirements6re=uired mechanisms> $ifference+eteen mo+ile ad6hoc and sensor netor9s> A""lications of sensor netor9s6 Ena+ling 'echnologies for8ireless Sensor 7etor9s?

,NIT II *RCHITECT,RES 2Single67ode Architecture 6 5ardare Com"onents> Energ% Consum"tion of Sensor 7odes > ,"eratingS%stems and E 7etor9 Architecture 6 Sensor 7etor9 Scenarios> ,"timi@ation4oals and Figures of Merit>?

,NIT III NETRFING ' SENSRS 2Ph%sical La%er and 'ranscei#er $esign Considerations> MAC Protocols for 8ireless Sensor 7etor9s>Lo $ut% C%cle Protocols And 8a9eu" Conce"ts 6 S6MAC > 'he Mediation $e#ice Protocol> 8a9eu"Dadio Conce"ts> Address and 7ame Management> Assignment of MAC Addresses> Douting Protocols

,NIT IV IN'R*STR,CT,RE EST* Locali@ation and Positioning> Sensor 'as9ing andControl?,NIT V SENSR NETRF PL*T'RMS *ND TLS 2,"erating S%stems for 8ireless Sensor 7etor9s> Sensor 7ode 5ardare er9ele% Motes>Programming Challenges> 7ode6le#el softare "latforms> 7ode6le#el Simulators> State6centric"rogramming?

Total 9: Periods H8ireless Sensor 7etor9s6'echnolog%> Protocols> And A""lications> ohn 8ile%> 200*?&? Anna 5ac> H8ireless Sensor 7etor9 $esigns> ohn 8ile%> 2003?(? has9ar Brishnamachari> 7etor9ing 8ireless Sensors> Cam+ridge Press>200(?

)? Mohammad Il%as And Imad Mahgao+>5and+oo9 ,f Sensor 7etor9s Com"act 8ireless And 8iredSensing S%stems> CDC Press>200(?*? 8a%ne 'omasi> HIntroduction 'o $ata Communication And 7etor9ing> Pearson Education> 200*,RLs). htt"..arri?uta?edu.acs.netor9s.8irelessSensor7etCha"0&?"df2? htt"..?sensor6netor9s?org.

PEVLCB2CNTRL S@STEM N CHIP L T P C

36

http://arri.uta.edu/acs/networks/WirelessSensorNetChap04.pdfhttp://www.sensor-networks.org/http://arri.uta.edu/acs/networks/WirelessSensorNetChap04.pdfhttp://www.sensor-networks.org/

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$ + + $*IM'o learn the modern IC +ased design for an% control a""licationsECTIVES'o im"art 9noledge on

control com"onents

S,C design of fu@@% logic controller

,NIT I 2

Introduction to control s%stem conce"t6o"en loo" and closed loo"6control s%stem architecture6t%"es ofcontrol methodolog%6digital control s%stem6anal%sis of digital control s%stem6remote control conce"ts anda""lications

,NIT II 2

control com"onents and detailed stud%6o" am" transmitter6 recei#ers6 standard cell arra% design64atearra% design6full custom design6structured design6IP +ase design

,NIT III 2

Stud% of CC2(33 of 'e Single chi" design of Engine control s%stemTT*L 9: 8eriods

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ELECTIVE IV

PEVLC$+ L PER VLSI DESIGN L T P C $ + + $

*IM'o learn a+out "oer dissi"ation in CM,S circuits> different "oer o"timi@ation techni=ues

ECTIVES'o Im"art Bnoledge ,n

CM,S circuits for memor% cloc9 and interconnect?

#arious techni=ues for Poer estimation in circuits

,NIT I PER DISSIP*TIN IN CMS 2

5ierarch% of limits of "oer Sources of "oer consum"tion Ph%sics of "oer dissi"ation in CM,SFE' de#ices6 asic "rinci"le of lo "oer design?

,NIT II PER PTIMI?*TIN 2

Logical le#el "oer o"timi@ation Circuit le#el lo "oer design Circuit techni=ues for reducing "oer

consum"tion in adders and multi"liers

,NIT III DESIGN ' L PER CMS CIRC,ITS 2

Com"uter Arithmetic techni=ues for lo "oer s%stems Deducing "oer consum"tion in memories Lo "oer cloc9> Interconnect and la%out design Ad#anced techni=ues S"ecial techni=ues

,NIT IV PER ESTIM*TIN 2

Poer estimation techni=ues Logic le#el "oer estimation Simulation "oer anal%sis Pro+a+ilistic"oer anal%sis?

,NIT V S@NTHESIS *ND S'T*RE DESIGN 'R L PER 2

S%nthesis for lo "oer eha#ioral le#el transforms6 Softare design for lo "oer 6TT*L 9: 8eriods

RE'ERENCES

1? B?Do% and S?C? Prasad > L,8 P,8ED CM,S VLSI circuit design> 8ile%>20002? $imitrios Soudris> Chirstian Pignet> Costas 4outis> $esigning CM,S Circuits For Lo Poer>

Bluer>20023? ?? Buo and ?5 Lou> Lo #oltage CM,S VLSI Circuits>8ile% 1///?&? A?P?Chandra9asan and D?8? roadersen> Lo "oer digital CM,S design> Bluer> 1//(?(? 4ar% Gea"> Practical lo "oer digital VLSI design> Bluer> 1//-?

)? A+dellatif ellaouar>Mohamed?I? Elmasr%> Lo "oer digital VLSI design>s Bluer> 1//(?*? ames ? Buo> Shin chia Lin> Lo #oltage S,I CM,S VLSI $e#ices and Circuits? ohn 8ile% and

sons> inc 2001DLs1? ?c"dee?ufmg?+r.fran9.lectures.Sill6LoPoer2?""t2? htt"..?cmos#lsi?com.lect1-?"df

PEVLC$) SEMICND,CTR MEMR@ DESIGN = PRCESSING L T P C $ + + $

38

http://www.cpdee.ufmg.br/~frank/lectures/Sill-LowPower2.ppthttp://www.cmosvlsi.com/lect18.pdfhttp://www.cpdee.ufmg.br/~frank/lectures/Sill-LowPower2.ppthttp://www.cmosvlsi.com/lect18.pdf

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*IM'o stud% a+out +asic semiconductor memories> their t%"es and the faults in memories?ECTIVES'esting and "ac9aging techni=ues of different memor% t%"es

,NIT I

R*NDM *CCESS MEMRIES 2SDAM Cell Structures6M,S SDAM Architecture6M,S SDAM Cell and Peri"heral Circuit ,"eration6i"olar SDAM 'echnologies6Silicon ,n Insulator :S,l; 'echnolog%6Ad#anced SDAM Architectures and'echnologies6A""lication S"ecific SDAMs?D@N*MIC R*NDM *CCESS MEMRIES DR*MS$DAM 'echnolog% $e#elo"ment6CM,S $DAMs6$DAMs Cell 'heor% and Ad#anced Cell Structures6iCM,S> $DAMs6Soft Error Failures in $DAMs6Ad#anced $DAM $esigns and Architecture6A""licationS"ecific $DAMs?

,NIT II 2

NNVL*TILE MEMRIESMas9ed Dead6,nl% Memories :D,Ms;65igh $ensit% D,Ms6Programma+le Dead6,nl% Memories:PD,Ms;6i"olar PD,Ms6CM,S PD,Ms6Erasa+le :V; 6 Programma+le Doad6,nl% Memories:EPD,Ms;6Floating64ate EPD,M Cell6,ne6'ime Programma+le :,'P; EPD,MS6Electricall% Erasa+lePD,Ms :EEPD,Ms;6EEPD,M 'echnolog% And Architecture67on#olatile SDAM6Flash Memories:EPD,Ms or EEPD,M;6Ad#anced Flash Memor% Architecture?

,NIT III 2 MEMR@ '*,LT MDELING/ TESTING/ *ND MEMR@ DESIGN 'R TEST* Pseudo Dandom 'esting6Mega+it $DAM 'esting67on#olatileMemor% Modeling and 'esting6I$$K Fault Modeling and 'esting6A""lication S"ecific Memor% 'esting

,NIT IV 2

SEMICND,CTR MEMR@ RELI* Pseudo Dandom 'esting6Mega+it$DAM 'esting67on#olatile Memor% Modeling and 'esting6I$$K Fault Modeling and 'esting6A""licationS"ecific Memor% 'esting

,NIT V 2P*CF*GING TECHNLGIESDadiation Effects6Single E#ent Phenomenon :SEP;6Dadiation 5ardening 'echni=ues6Dadiation5ardening Process and $esign Issues6Dadiation 5ardened Memor% Characteristics6Dadiation 5ardness

Assurance and 'esting 6 Dadiation $osimetr%68ater Le#el Dadiation 'esting and 'est Structures?

Ferroelectric Dandom Access Memories :FDAMs;64allium Arsenide :4aAs; FDAMs6Analog Memories6Magnetoresisti#e Dandom Access Memories :MDAMs;6ERE'ERENCES

39

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1. Asho9 B? Sharma> Semiconductor Memories 'echnolog%> 'esting> and Delia+ilit%> 8ile%6IEEE Press>2002?

2. Asho9 B? Sharma > Semiconductor Memories> 'o6Volume Set/ 8ile%6IEEEPress> 2003?

3. Asho9 B? Sharma/Semiconductor Memories 'echnolog%> 'esting> and

Delia+ilit%> Prentice 5all of India> 1//*?4. rent Beeth> D? aco+ a9er> $DAM Circuit $esign A 'utorial> 8ile%6IEEE Press> 2000?(?ett% Prince/ 5igh Performance Memories 7e Architecture $DAMs andSDAMs 6 E#olution and Function> 8ile%> 1///?

,RLs). htt"..highered?mcgra6hill?com.sites.dl.free.00*22-3)(3.10/3&2.hodgecha"t0-?"dfB. htt"..?radio6electronics?com.info.data.semicond.memor%.different6t%"es6semiconductor6memor%?"h"

40

http://highered.mcgraw-hill.com/sites/dl/free/0072283653/109342/hodge_chapt08.pdfhttp://www.radio-electronics.com/info/data/semicond/memory/different-types-semiconductor-memory.phphttp://highered.mcgraw-hill.com/sites/dl/free/0072283653/109342/hodge_chapt08.pdfhttp://www.radio-electronics.com/info/data/semicond/memory/different-types-semiconductor-memory.php

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PEVLC$B CMP,TER *RCHITET,RE *ND P*R*LLEL PRCESSING L T P C $ + + $

*IM'o Stud% the Ad#anced Com"uter Architectures

ECTIVE

'o im"art 9noledge on

7etor9 "ro"erties of com"uters

Su"erscalar techni=ues

,NIT() P*RELLEL CMP,TER PRGR*M *ND NETRF PRPERTIES 2Multi"rocessors and multicom"uters6multi#ector and SIM$ com"uters6PDAAM and VLSI M,$ELS6architectural de#elo"ment trac9s6conditions of "arallelism6data and resources de"endences6hardareand softare "arallelism6grain si@e and latenc%6grain "ac9ing and scheduling6static multi"rocessorscheduling6"rogram flo mechanisms6s%stem interconnect architecture6netor9 "ro"erties and routing

,NIT(B PRCESSRS *ND MEMR@ 2Ad#anced "rocessor technolog%6DISC scalar "rocessors6su"erscalar and #ector "rocessors6memor%

hierarchical technolog%6#irtual memor% technolog%6cache memor% organi@ations6shared memor%organi@ations

,NIT($ PIPELINING *ND S,PERSC*L*R TECHNI4,ES 2Linear "i"eline "rocessors6as%nchronous and s%nchronous models6cloc9ing and timing control s"eedu">efficienc%>and through"ut6nonlinear "i"eline "rocessors6reser#ation and latenc% anal%sis6Collison Free Scheduling6 Pi"eline Schedule ,"timi@ation6Instruction Pi"eline $esign6InstructionE Shared memor% MIM$ architectures>RE'ERENCE

1? $e@so Sima> 'erence Fountain> Peter Bacsu9> Ad#anced Com"uter architecture A $esign S"ace A""roach > Pearson education > 2003?2? Bai 5ang> HAd#anced Com"uter Architecture > Mc4ra 5ill International> 1//3?

3? ohn P?Shen> HModern "rocessor design 6 Fundamentals of su"er scalar"rocessors> 'ata Mc4ra 5ill 2003?

,RLs).htt"..?niceindia?com.=+an9.A71)(2C,MP'EDADC5I'EC'DEPADALLELPD,CESSI74?"df2? htt".."eo"le?engr?ncsu?edu.efg.(0).sum//.001.lec16intro?"df

PEVLC$$ D*T* CNVERTERS

41

http://www.niceindia.com/qbank/AN_1652_COMPUTER_ARCHITECTURE____PARALLEL_PROCESSING.pdf%20%0D2http://www.niceindia.com/qbank/AN_1652_COMPUTER_ARCHITECTURE____PARALLEL_PROCESSING.pdf%20%0D2http://www.niceindia.com/qbank/AN_1652_COMPUTER_ARCHITECTURE____PARALLEL_PROCESSING.pdf%20%0D2http://people.engr.ncsu.edu/efg/506/sum99/001/lec1-intro.pdfhttp://www.niceindia.com/qbank/AN_1652_COMPUTER_ARCHITECTURE____PARALLEL_PROCESSING.pdf%20%0D2http://www.niceindia.com/qbank/AN_1652_COMPUTER_ARCHITECTURE____PARALLEL_PROCESSING.pdf%20%0D2http://www.niceindia.com/qbank/AN_1652_COMPUTER_ARCHITECTURE____PARALLEL_PROCESSING.pdf%20%0D2http://people.engr.ncsu.edu/efg/506/sum99/001/lec1-intro.pdf

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L T P C$ + + $

*IMTo study the di66ere5t data co5!erters

ECTIVE

'o im"art the 9noledge on

Sam"le And 5old Circuits

A to $ and $ to A con#ersions

,NIT I IEEE "ress> 1//(?2? Franco Malo+erti> H$ata Con#erters> S"ringer> 200*?3? Dud% #an de Plassche> HCM,S Integrated Analog6to6$igital and $igital6to6AnalogCon#erters Bluer Acedamic Pu+lishers> oston> 2003?

,RLs1? htt"..6inst?eecs?+er9ele%?edu.ee2&*.fa0&.fa0&.lectures.L11f0&?"df2? htt"..?ee?ucla?edu.+re+.director?html

42

http://www-inst.eecs.berkeley.edu/~ee247/fa04/fa04/lectures/L11_f04.pdfhttp://www.ee.ucla.edu/~brweb/director.htmlhttp://www-inst.eecs.berkeley.edu/~ee247/fa04/fa04/lectures/L11_f04.pdfhttp://www.ee.ucla.edu/~brweb/director.html

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PEVLC$9 NETRF N CHIP L T P C$ + + $

*IM'o gi#e a +asic introduction on 7etor9 on chi"ECTIVESTo i-8art the 5oAled1e o5

Em+edded S,C A""lications 'esting strategies of 7,C

Softare for Multi"rocessor 7etor9s on Chi"

,NIT I 2Em+edded S,C A""lications ! Platform Elements 7etor9ing domain> multimedia domain> irelesscommunications> A""lication trends> First order a""lication "artitioning> Architecture> "rocessingelements> on chi" communication?

,NIT II 2S%stem Le#el $esign Princi"les Platform +ased design "aradigm> design "hases> a+straction mechanics>models of com"utation> s%stem le#el design re=uirements> tradition 58.S8 co6design> and s%stem +asedtransaction +ased modeling> current research on MPS,C design methodologies

,NIT III 2'esting strategies of 7,C ,n "ac9et sitched netor9s for on chi" communication> 'esting Strategies for7etor9s on Chi"

,NIT IV 2Cloc9ing strategies on chi"> "arallel com"uter as 7,C region

,NIT V C*SE ST,D@ 2Softare for Multi"rocessor 7etor9s on Chi" IPV& format ith K,S su""ort> Intel I2&00 reference7P> ,SCI 'LM standard>

TT*L 9: Periods

7etor9 interface architecture and design issues

RE'ERENCES

1?Integrated s%stem le#el modeling of netor9 on chi" ena+led multi "rocessor "latforms > 'im BogelVisit Ama@onOs 'im Bogel Pagesearch resultsLearn a+out Author Central

>Dainer Leu"ers>5einrich Me%r> S"ringer "u+lication?2?7etor9s on Chi">A