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LHCb RICH Electronics. University of Oxford.

LHCb RICH L-0 Interface Module.

Reference Manual

Author: John BibbyContact: Jim Libby1

University of Oxford.

May 2006.

Version 1.0

1 [email protected]

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1 Introduction...............................................................................................................42 System overview........................................................................................................53 Architecture...............................................................................................................7

3.1 LHCb RICH Architecture................................................................................73.2 Level-0 interface Module Architecture............................................................83.3 L-0 module PCB...............................................................................................113.4 PINT..................................................................................................................113.5 TTCrx...............................................................................................................133.6 GOLs.................................................................................................................143.7 QPLL/Xtal........................................................................................................143.8 VCSELs............................................................................................................163.9 CRT4T..............................................................................................................183.10 Optical fibres..................................................................................................193.11 PILOT.............................................................................................................21

4 L-0 LHCb timing....................................................................................................254.1 L-0 Calibration mode......................................................................................254.3 Fibre link test mode.........................................................................................354.4 Physics Run Mode............................................................................................364.5 LHCBPIX1 data pulse width..........................................................................36

5 JTAG........................................................................................................................385.1 Introduction......................................................................................................385.2 JTAG principles...............................................................................................385.3 JTAG Implementation in the L-0 interface module.....................................39

5.3.1 The RICH L-0 Module JTAG TDI/TDO chain.....................................395.3.2 Other JTAG hardware issues..................................................................405.3.3 Configuration Registers...........................................................................415.3.4 JTAG Device IDs......................................................................................415.3.5 JTAG conversion to I2C for TTCrx........................................................41

6 Low Voltage Power Requirements........................................................................426.1 LHCBPIX1 Low Voltage requirements.........................................................426.2 Grounds (0 V reference)..................................................................................436.3 L-0 interface Low Voltage requirements.......................................................43

7 The Oxford Test Station low voltage power supply scheme...............................458 Production testing...................................................................................................47

8.1 Introduction......................................................................................................478.2 The Oxford Test Stations................................................................................478.3 The three phases of testing..............................................................................478.4 Aims and the sequence for the First Phase Testing......................................48

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8.4.1 Visual inspection.......................................................................................498.4.2 Power-up tests...........................................................................................498.4.3 Synchronisation tests................................................................................498.4.4 JTAG test...................................................................................................518.4.5 Link tests....................................................................................................528.4.6 PILOT test and LV references................................................................53

8.5 Second phase test: nominal threshold values for L-0 interface module.....538.6 Thermal burn-in..............................................................................................548.7 The third phase of testing................................................................................54

9 L-0 module mechanical information.....................................................................589.1 Space Constraints............................................................................................589.2 Interconnects....................................................................................................59

10 Acknowledgements...............................................................................................60Appendix A: L-0 40-way low voltage and JTAG connector pins allocation........61Appendix B: HPD to L-0 connectivity.....................................................................62Glossary of terms.......................................................................................................65References...................................................................................................................67

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1 Introduction

The main aims of this document are to describe both the purpose and function of the L-0 module within the LHCb RICH electronics. The document is aimed at technical experts and users who are involved in the production, installation, commissioning and running phases. The document addresses certain troubleshooting scenarios; guidance is given in isolating and tracing the origin of the problem. Within some sections certain references are necessary to fully understand the points being made. (In such cases the references are presented within the section.)

In the design of the document a top down approach has been adopted in describing the LHCb RICH architecture then working down to the description of the main functions of the L-0 interface module blocks and components.

Section 2 gives an overview of the L-0 system. Section 3 contains general detail on each block of the L-0 module. Sections 2 and 3 can be skipped by those already familiar with the RICH L-0 electronics. However, these sections would provide a first order guide for identifying source of faults during the running phase. Sections 4, 5 and 6 describe in more detail the L-0 interface timing, JTAG controls and low voltage requirements, respectively. Section 8 relates to the power requirements for the L-0 electronics within the Oxford test setup. Section 9 relates to the L-0 production tests. (Sections 4 to 9 need to be used with reference to the L-0 schematics, the LHCb TFC (Trigger and Fast Control), fibre test, PILOT calibration and PINT documents.) Section 10 gives details on the L-0 module mechanical dimensions and board layout, but for completeness these should be used with the information available in the CERN EDMS data base [1, 2]

The methods for the timing and synchronisation within LHCb are not addressed. The information for this is available [3, 4, 5] but at the time of writing this topic is still not fully resolved within LHCb.

To aid the reader there is a Glossary of terms included at the end of the document.

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2 System overview

The LHCb RICH readout electronics and DAQ are designed to readout pixel Hybrid Photon Detectors (HPDs) [6], which are the photo-detectors for the LHCb RICH. A schematic of the LHCb RICH readout architecture and the chosen modularity is shown in Fig. 1.

The RICH L-0 interface module is located on the detector, where it processes the first stage multiplexed HPD Pixel detector data. This incoming data is first routed to the custom-ASIC PINT [7] where headers, trailers and parity information are added and formatted. This 32-bit wide data is then transferred at 40 MHz to the GOL [8] serialisers. At the GOL the data is multiplexed to a 1-bit wide packet. The data is then driven at 1.6 GHz, via a VCSEL diode [9], into a 50μm diameter multimode fibre and onward to the counting rooms some 80m away. There is one fibre per HPD. One L-0 interface board services two HPDs.

Within the L-0 interface module the synchronisation of the “binary front-end pixel chip” (LHCBPIX1) [10] data capture, readout and of the GOL/VCSEL is performed within the PINT using the TTCrx [3] derived clocks, triggers and resets. The various running modes for the LHCBPIX1 and the fibres are generated from the TTCrx Broadcast Commands. The I2C [11] control signals, required for the TTCrx configuration, is derived within the PINT using the JTAG [12] protocol. The configuration for all other front-end blocks is carried out using JTAG.

The vital low noise analogue reference and calibration voltages for the LHCBPIX1 are generated by the Analogue Pilot ASIC [13, 14]. Furthermore, these are filtered within the L-0 interface module. The external digital and analogue power supplies are also filtered on the L-0 board.

The operating temperatures of the L-0 board and the Pixel Anode HPDs [6] are monitored via the on-board L-0 Analogue Pilot ASIC interfaced to the LHCb ECS system with JTAG.

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Figure 1. A schematic of the LHCb RICH architecture. The modularity of each component is shown to the left of the vertical dashed line.

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3 Architecture

3.1 LHCb RICH Architecture

The LHCb RICH architecture (Figure 1) consists mainly of the following major blocks: The binary front-end pixel chip, LHCBPIX1

LHCBPIX1 is encapsulated inside the HPD vacuum envelope. It performs pre-amplification, shaping and discrimination of the HPD signals, implements the Level-0 latency buffer and outputs at 40 MHz multiplexed Level-0 accepted events at 32 bits wide.

The on-detector Level-0 Interface Module.The module is the interface to the LHCb timing, trigger and fast control (TFC) [4] system, the LHCb experiment control system (ECS) [15], the Level-1 electronics, the low voltage power supplies and LHCBPIX1. One interface module supports two pixel HPDs.

The interface module contains a Pixel INTerface (PINT) ASIC, which synchronises and formats the incoming LHCBPIX1 data and transports this to the GOLs. The GOLs perform a second level of multiplexing resulting in a single bit wide fibre data output rate of 1.6 Gbits/s. Furthermore, the data undergo formatting to comply with the protocol required for fibre optic transmission.

A block diagram of the Level-0 interface module is shown in Fig. 2. The optical fibre links.

The optical fibre links are used to transmit data from the on-detector electronics to the off-detector electronics, which are situated ~80m away. The CERN developed radiation-hard Gbit Optical Link serialiser chip (GOL) is used together with a Vertical Cavity Surface Emitting Lasers (VCSELs) to transmit the data. The Gigabit-Link Ethernet protocol with 8 bit by 10 bit (8B/10B) encoding is used. The Agilent Commercial devices [16] will be used for the optical fibre receiver at the L-1 modules.

The off-detector electronics (Level-1).The Level-1 electronics are located in the counting room. These consist of the Level-1 readout modules and associated support modules. The Level-1 readout board receives the 1.60 GHz multiplexed fibre data from the Level-0 interface. It implements the LHCb Level-1 architecture, buffers and processes the data, provides an L-1 interface to the TTC and ECS systems and transports the data to the DAQ system.

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LHCb RICH L-0 Interface Blocks

GOL1+

VCSEL

TTCrx

AnaloguePilot

QPLL+Xtal

PINTGOL2

+VCSEL

Power Supply filtersECS

HPD1

HPD2

HPDVoltagesand Bias.

TFC Fibre

DataFibre1To L1

Data Fibre2 To L1

Base Power Supply.

SPECsSlave.

2*CRT4T

Figure 2. A schematic of the main blocks within the L-0 Module.

3.2 Level-0 interface Module Architecture.

One Level-0 interface module serves two HPD-LHCBPIX1 silicon pixel devices. It is mounted on a column of 14 HPDs and 16 HPDs for RICH 1 and RICH-2, respectively. There are a total of 242 Level-0 modules serving 484 HPDs. There are 98 Level-0 modules for RICH-1 and 144 for RICH-2. A design layout with a top view onto the L-0 module is shown Fig. 3 and a photograph of a Level-0 module mounted on a column structure is shown in Fig 4. Also shown are two HPDs, and the Low Voltage (LV) and High Voltage (HV) service boards. The LV service board provides both power to the Level-0 module and the silicon bias voltage for the pixel chip; the silicon bias voltage is routed and filtered through the Level-0 interface module. The ECS JTAG is also routed through the LV service board to the L-0 interface module.

A schematic of the main blocks within and around the Level-0 module is shown in Fig 2. The main blocks are the PINT, the Analogue PILOT chip, the TTCrx, two GOLs and two VCSELs. Fig. 5 shows a photograph of a final pre-production Level-0 module with the location of the main blocks labelled. The general layout and PCB for the Level-0 module is described below. The functions for each of the main blocks within the L-0 interface module are also described.

A variety of test points are available to validate the correct function of the Level-0

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module. The 32-bit parallel data, which is transferred to the GOLs from the PINT, can be spied on for monitoring and test purposes, using a logic analyser connected to the Level-0 module via the MICT connectors. This facility is used to verify correct data transmission into the GOLs. These data into the GOLs can also be compared to that received by L-1 electronics to test the integrity of the fibre optic transmission. Other test points throughout the L-0 interface PCB allow verification of the TTC and JTAG control signals. Furthermore, a mechanism for applying an external Level-0-Accept into the PINT logic is available, thus by-passing the TTCrx generated Level-0 Accept.

LHCb RICH2 11/02/04I.N.F.N. Genova - S. Cuneo1

HPD COLUMN BOARDS LAYOUT - TOP VIEW

LV BOARD(GREEN)

HPD ASSEMBLY

HV BOARD(MAGENTA)

KAPTONS FROMHPD

L0 BOARD(CYAN)

Cu SCREEN(BROWN)

HV CABLES

ACTIVELY COOLEDFRAME (BLUE)

Figure 3: The RICH2 HPD and electronics layout. Dimensions are given in mm.

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RICH2 COLUMN ASSEMBLY.

HPDs.

L-0 InterfaceModule

Kaptons

Local Low VoltagePower supplies.

SupportFrame.

Figure 4. A photograph of the L-0 interface module within a column assembly.

J.H.B University of Oxford.

L-0 INTERFACE MODULE.

1 4 32

56

7 8 9PINT 5.TTCrx 1.GOLs 2,3.QPLL 4.PILOT 6.TRUELIGHT 7.VCSELs 8,9.

CRT4T ReverseSide.

Figure 5. A photograph of the L-0 board. The main components are labelled.

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3.3 L-0 module PCB

The Level-0 module circuitry is mounted on to an 18 layer PCB. The column structure requires the PCB fits within the limited space available between two HPDs and the depth along the HPD central axis, which are 16.5 cm by 10 cm, respectively. The board thickness is 3 mm.

The PCB must handle data bit rates up to 1.6 Gbits/s and integrate the radiation hard ASICS, GOLs, QPLL/Xtal, TTCrx and the fuse link PGA PINT, into one module. Many signal lines are of controlled impedance and limited in length to ensure clean rise times, signal source matching and synchronised digital timing across the board. The layout is critical for speed of operation and limiting noise and stability. Ground currents up to 6 A have to be handled that must not generate noise >200 e into the LHCBPIX1 pixel chip. Analogue and digital paths are kept separate and there is no common reference or “Star” [17] point at the L-0 interface board level.

The main package types that are mounted on the PCB are: 144 BGA (Ball Grid Array) for the GOLs and TTCrx, 896 BGA for the PINT block, LPCC64 for the PILOT, QFN-16 for the CRT4T and LPCC28 for QPLL/Xtal

The thermal stability was tested by several fully mounted PCB being successfully operated over several cycles from room temperature to 600 C. One board was successfully tested to 800 C.

The interface module has to function reliably within a radiation hard environment [18], therefore only radiation qualified active and passive components are used mainly. (The Hirose connector and the plastic housing of MICT connector are the only unqualified components.) The PCB material is mainly FR4 which will not suffer from radiation damage.

3.4 PINT

At the heart of the Level-0 module is the Pixel INTerface (PINT) BGA [7]. The PINT is a fuse link 896 BGA ACTEL 1000 chip [19]. The principle functions of the PINT are:

1. Interpret the global TTCrx Level-0 accept signals and clocks to generate the data capture commands, readout signals and clocks required by the LHCBPIX1.

2. Format the resulting LHCBPIX1 data signals and add the headers, trailers, Parity, LHCBPIX1 FIFO status, bunch ID and interface this data to the GOLs.

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3. From the TTC Broadcast Command set the mode of operation for the front-end electronics, generate LHCBPIX1 calibration test pulses and related timings and, generate the optical fibre link test patterns to be routed through the GOLs.

4. The LHCBPIX1 chip, GOLs, TTCrx and the PILOT have differing signal requirements for their ECS inputs—the PINT interfaces the ECS signals to match these needs.

5. The JTAG state machines for TTCrx, GOLs, and PILOT are not designed to use triple logic voting. The JTAG logic is not radiation hard. To decrease the possibility of SEU problems via the JTAG route the TRST (T-RESET) for each chip is activated from the PINT and held in the active state after configuration.

6. The TTCrx uses I2C protocol for configuration. This is translated and formed from the JTAG protocol within the PINT and interfaced to the TTCrx.

7. Monitor and report the status of the various L0 blocks.8. Read the hardwired switches that tag the board ID.

Fig. 6 shows a block diagram of the main functional blocks within the PINT. (These are coloured.) Their relation to TTCrx, GOLs, PILOT and PIXEL chips are also indicated.

A more detailed description of the PINT is given in Ref. [7]. Details of the Radiation Hardness Qualification of the PINT can be found in Ref. [20].

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Block diag for PINT and Ancillaries (Level-0 Board).

JTAGControl.

CMOS to GTL

AnalogueSupplies

andFilters..

TTCInterface

PILOT.

DAC andAnalogue

References.

2*GOLs+

Optical Driver

3*32+32*32=DATA+

Header andTrailer

16 deep*12FIFO=

BX Counter+

ERRORS.

Timing, TestAnd

Control

TTCrx

GTL to CMOS

JTAG PIntInterface.

JTAG

LVDS

HPD BINARY CHIPs

LinkTest

PatternIIC

*2 fo

r 2

GO

Ls

and

two

HPD

s.

Figure 6. Block diagram of the PINT’s Main Internal Blocks.

3.5 TTCrx

The TTCrx [3] receives the LHCb TFC signals from the TTC fibre optics via the on-board Truelight receiver [21]. It decodes the different clocks, triggers, broadcast commands to construct the TFC control, calibration, test and reset signals. These are distributed via the PINT to the QPLL, GOLs, PILOT, PINT and LHCBPIX1. The bunch count data, supplied by TTCrx, is added to the LHCBPIX1 header data in the PINT.

The signals, distributed within the L-0 electronics, are the L-0 trigger accepts, CLK40, CLK40DES1, CLK40DES2, the Bunch crossing 12 bit ID and the broadcast commands. The CLK40DES1 and CLK40DES2 can be skewed with respect to CLK40. The broadcast commands define and trigger various resets and modes of operation.

Other TTCrx addressing information is listed below.• The TTCrx I2C address is set to be “1” on all devices. (One TTCrx per TTC

and ECS/I2C line.) Though it can be set up to 10 bits.• Internal Timing Control registers are accessible via I2C.• Only chip ID and the boundary scan are accessible via JTAG. The boundary

scan is not used.

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• The TTCrx Reset-b is controlled from the PINT.3.6 GOLs

The LHCBPIX1 data are transferred, via the PINT, GOLs and VCSELs, to the off-detector Level-1 electronics serially at 1.6 Gbits/s rate through 50 μm multimode fibre. The 1.6 Gbits/s is made up of 1.28 Gbits/s data rate for one LHCBPIX1 and 320 Mbits/s line-coding bit rate.

The 32-bit wide parallel data from the PINT is processed and serialised in the GOLs [8]. The data is formatted to meet the fast Gigabit-link Ethernet and data transport protocol for the fibre-optic transmission using the 8 bit by 10 bit encoding. The data is interfaced directly to the VCSEL. The selected clock edge for the validation of the data into the GOLs is hardwired to be Positive. The Tx-En (Transmit enable) flag, set in the PINT, is used to define idle or data state of the GOL.

The GOLs control the VCSEL currents and bias settings. The VCSELs are driven directly with a fixed modulation current, but the laser threshold currents are set up in the GOLs.

The GOLs are configured and monitored with JTAG via the PINT. The ECS functions are listed below.

1. Reset-b is activated from the PINT. 2. GOL “Ready” or PLL state is monitored via the PINT.3. The GOL power-up sequence is controlled via CRT4T [8] radiation hard

CMOS switches. (See section 3.7.)4. Setting the lasing threshold current.

3.7 QPLL/Xtal

The TTCrx CLK40DES1 clock signal is used for synchronising the logic throughout the L-0 interface circuits. For the high-speed transmission data rate through the GOLs it is vital that the CLK40DES1 signal to the GOL should have a jitter less than 40 ps peak to peak [22, 23]. However, the direct TTCrx CLK40DES1 has a jitter in the region of 300 ps peak to peak. Therefore a radiation hard, low jitter solution for the clock source for the GOLs is required in the L-0 interface design.

A special jitter filter circuit, using a CERN radiation hard ASIC, the QPLL [24] and associated Xtal, is used to improve the CLK40DES1 jitter to a level that is required to drive the GOL serialiser with an acceptable bit error rate (BER), which is defined to be below 10-12. The QPLL is a very stable Quartz Xtal based phase locked loop.

A spur from the single ended CLK40DES1 clock output of the TTCrx is fed to

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the QPLL/Xtal circuitry. The QPLL has a very low locking range; therefore the CLK40DES1 output must have its output frequency close to the QPLL/Xtal reference frequency to lock. The PLL lock is monitored by the PINT. The output of QPLL has a very low level time jitter of less than 40 ps. This output is a differential LVDS signal, which is fed to the GOL CLKLHCP and CLKLHCN inputs.

Great care is necessary with the PCB layout around the QPLL/Xtal components. The recommendations for the Xtal circuit design to avoid excessive Xtal heating, and to keep the jitter to less than 40 ps tolerance was rigidly adhered to. The power supply to this circuit is well decoupled because noise through this rail can also induce unwanted jitter.

The LHCBPIX1 data is synchronised through the PINT with the TTCrx CLK40DES1. In the GOLs the data are clocked on the positive edge of the QPLL, CLKLHCP. The data into the GOLs requires a set-up time of ~5 ns to settle. The relative timing of this QPLL clock and the incoming data from the PINT, at the GOL inputs, is shown in Fig. 7. There is a comfortable 9.28 ns data set-up time, as measured.

Figure 7. The relationship between GOL input data and master clock timing.

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Due to the unavailability of suitable equipment we have not been able to achieve any eye diagram runs with our GOL fibre designs to check the performance and jitter but we have carried out long fibre test runs at 1.6 Gbits/s to check the transmitted and received data for BER. The results of data integrity and parity checks at the L-1 receiver are used. Our results show errors less 10-13 [25]. The run mode is set to 1, which means that the QPLL self monitors and auto calibration is performed on loss of the lock. This is achieved by hardwiring the Ext Control input to 0 and the Auto restart to 1.

3.8 VCSELs

The VCSEL [9] specifications are such that they match the output from the GOL and produce adequate light output for successful L-1 receiver operation when coupled to the RICH optical link and all its interfaces. The VCSEL packaging was chosen to achieve reliable coupling and matching to the 50m multimode fibre.

A special commercial device from ULM was chosen2. The choice and design was an LHCb driven one [22, 23]; it has also been validated specifically for the RICH system [25]. The VCSEL is mounted in a SMA package for robustness, positive location for optical coupling and for ease of mounting into a PCB. Details of the electro-optical characteristics and maximum ratings of the VCSEL are given in Tables 1 and 2, respectively. The assembly is easily soldered to the circuit PCB but great care was needed in the PCB layout to achieve the lowest impedance loss, and the shortest electrical coupling paths to the GOLs. Low and high frequency local decoupling of the VCSEL anode power bus is implemented to reduce the possibility of any noise or jitter from this source [26, 2]. (The circuit diagram is given in Fig.11 discussed in Section 3.8.)

Avoiding excessive currents into the VCSEL must be avoided at all times. Tests over the total safe current range of 5 to 12 mA DC and at various voltages across the GOL and VCSEL versus the light output were carried out in Oxford. Figure 8 shows the results of these tests. Within the working sensitivity range of the L1 receiver [16] it was demonstrated that there is a large safe working margin with no obvious negative or positive saturation effects. Furthermore, there is a very low BER when operating at values for the minimum laser threshold value of current (4-5 mA). The fixed modulation range from the GOL is 10 mA leading to a further 5 mA average current being drawn. The resulting total mean current of ~10 mA is within the tolerant limits of the VCSEL shown in Table 2. The voltage at the VCSEL anode was settled to be 3.0 V taking into account the powering requirements discussed in

2 Component number ULM850-05-TN-USMBOP.

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the Section 3.8. More BER tests have been carried out, using these values for threshold current and GOL operating volts, with the results showing that the BER is <10 -13.

Parameter and Symbol Units Min

Typ

Max

ULM Test conditions.

Emission Wavelength nm 835 850 860 T=20CFibre-Coupled mean power

mW 6 125m fibre

Threshold Current Ith mA 7 T=20CVariation Ith v Temp mA 0.7 T=(0 to 70)c Threshold Voltage V 1.5 1.8 2.0Laser Current mA 30 Popt=6mW*Laser Voltage V 1.6 2.0 2.3 Popt=6mW*Differential series resistance

R 25 Popt=6mW*

3dB modulation bandwidth

GHz 3 6 Popt=6mW*

Rise/Falltime pS 90 150 10%, 90% Poff/on=0.5/6mW

Wavelength Tuning/current

Nm/mA 0.15 0.2

* Into 125 Optical Fibre.Table 1. The VCSEL Electro-Optical characteristics

Property Maximum ratingsElectrical power dissipation 30 mWContinuous forward current 12 mAReverse voltage 8 VSoldering temperature 3330 CTable 2. The maximum ratings of various VCSEL properties.

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O p tic a l P o w e r O u t o f N e w U L M 8 5 0 -0 5 -T N-U S M B O P V C S E L

0

0 .2

0 .4

0 .6

0 .8

1

1 .2

4 5 6 7 8 9 10 1 1 1 2 13

T o ta l C u rre n t (m A )

Op

tic

al P

ow

er

(mW

)

2 .542 .753 .003 .253 .30

V C S E L A n o d e

V o ltag e (V )

Figure 8. VCSEL optical power output versus total VCSEL current for different applied anode voltages.

3.9 CRT4T

In the first version of the L-0 design it was observed, that during power start-up, the GOLs were not reliably phase locking to the incoming QPLL/Xtal clock. The GOL designer’s explanation for this was that GOL gets into a "hyper-state" when it is partially powered up and receiving power via inputs such as the clock and control lines. One solution is to ensure that the GOL is never slowly powered up when the clocks and other inputs are partially powered, then to rapidly apply the power when these lines are stable. This is achieved in the LHCb RICH design by rapidly applying the Vdd power, when the clocks and control lines are established, to the GOLs via a radiation hard ASIC chip, the CRT4T [8]. The other unused GOL inputs are pulled to a steady “0” or “1” state.

It was also pointed out, late in the design, that it was necessary to keep the GOL output, at the VCSEL cathode, above ~1 Volts. Measurements of the cathode voltage as a function of total VCSEL current are shown in Fig. 9 for 5 different VCSEL anode bias voltages. To maintain the anode voltage above ~1 V over the operational current range of 5 to 12 mA the VCSEL anode had to be kept above 3.0

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V. A sequential power-up circuitry, also using a block of the CRT4T, was designed to use and switch the available 3.3 V and limit this to 3.0 V at the VCSEL anodes. The circuit diagram showing the integration of the CRT4T with the GOL and VCSEL is shown in Fig. 10. (The block diagram of the CRT4T is shown in Fig. 11; there is additional functionality of the ASIC not used in this design.) The CRT4T devices are mounted on the back surface of the PCB and close to the region of the GOLs.

The GOL and VCSEL switch-on must occur after the Clocks and other input lines to the GOLs have been established. The CRT4T switch is externally triggered via ECS. Control of the VCSEL currents during the sequential start-up was necessary and excess current protection was included into the design.

GOL Potential Difference Against Total VCSEL Current

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

4 5 6 7 8 9 10 11 12 13

Total Current (mA)

Volta

ge a

t VC

SEL

Cat

hode

(V)

2.542.753.003.253.30

VCSEL Anode

Voltage (V)

Figure 9. Voltage dropped at GOL output as a function of VCSEL current and anode voltage. 3.10 Optical fibres

The fibre type and source of the fibres to be used in the LHCb RICHs is now a Common LHCb item, defined by the LHCb collaboration [27]. The RICH tests of the optical connection from the L-0 module to the L-1 receiver [25] used Fonetworks3

multi-mode fibres and connectors.

3 http://www.fonetworks.com

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http://www.fonetworks.com/


GOL

VCSEL(3.0V)

(2.7V)

CRT4T

Figure 10. LHCb-RICH CRT4T-GOL-VCSEL circuit.

Figure 11. CRT4T block diagram.

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3.11 PILOT

The PILOT ASIC [28, 13, 14] provides reference voltages for the LHCBPIX1 DACs. These include the analogue and digital GTL references as well as the two nominal DAC references and the test_hi and test_lo voltages. There are six 8 bit DACs available to set the reference voltages.

There are four current sources for the temperature monitoring sensors. The PILOT generates and monitors its own DAC and ADC bias voltage

references. In addition it monitors its own temperature and those of the two LHCBPIX1s and PINT, using the four available current sources for PT type temperature sensors. A 10 bit ADC with 16 multiplexed inputs is used for the temperature and voltage monitoring. The TTCrx CLK40 is used for conversion.

The PILOT is controlled and monitored using JTAG via the PINT [14]. The mode bit is set from the PINT. This enables the ALICE or LHCb mode current sources for temperature measuring. Each mode has two current sources.

A block diagram of its coupling to other blocks within the L-0 architecture is shown in Fig. 11. Not shown are the ADC paths around and through the PILOT within the L-0 interface module, related to temperature and reference voltage monitoring. A brief summary of the PILOT’s main monitoring and supply functions and nominal values is shown in Table 3.

The calibration and testing of the PILOT chip for the LHCb RICH electronics has been carried out [28]. Two on-board voltage divider references are used to calibrate the PILOT ADCs when coupled to the LHCBPIX1 pixels.

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CLK

CLK*

NEVR*

STROBE*

CE*

DATA_RST*

TEST_PULSE*

MODE

TDI0 TDI1

TMS

TCLK

TRESET*

TDO

DATA*<0:31>

CMOS-> GTL GTL-> CMOS

to HPD from HPD2* 32

DAC_REF_VDD

DAC_REF_MID

ANALOG_TEST_HI

ANALOG_TEST_LO

to HPD

ReferenceGenerator

DAC8

DAC8

ANALOG POWER

ReadoutControl

BXmemory

16*12FIFO

BXcounterStrobe

Control

Test_pulseControl

ClockControl

ResetControl

DIGITAL POWER

JTAGController

Registers

TDIc TMSc TCLKc TRST*c TDOc

from ECS interface

CLK_in L0 TRIGGER_in RESET_in TEST_PULSE_in

from TTCrx

TX[0:15]

32

TXDATAa TXCNTLa TXCLKa TX[16:31] TXDATAb TXCNTLb TXCLKbTXDIV0 TXDIV1

32

to GLink serialiser

LOCKEDa LOCKEDb

ANALOG

DIGITAL

CONTROL

GOL INTERFACE

LHCb PILOT CHIP

BCntRes_in

control

ALL

CLK

40s

L-0

ACC

EPT

RES

ETR

UN

MO

DE

BC

NT

CLK

CLK

-ST

RO

BE

NEV

R CE

TEST

PU

LSE

DA

TA R

ESET TD

ITD

OTM

STC

KTR

ESET

TDO

DA

TA 0

-31

DA

TA 3

2 63

DA

C_R

EF_M

IDD

AC

-REF

_VD

DG

TL-R

EFAN

ALO

GU

E_TE

TS_H

IAN

ALO

GU

E_TE

ST_L

O

ANAL

OG

UE

POW

ERTD

ITM

STC

LKTR

STTD

O Reg

iste

rs

DIG

ITAL

PO

WER

TX[0

:32]

TXD

AT-

TXeN

TCK

LHC

P*2

TCK

LHC

N*2

TX[0

:32]

TXD

AT-

TXeN

PLL

LOC

KED

PLL

LOC

KED

PILOT CHIP WITHINL-O BOARD

ARCHITECTURE.

PILOTASIC

CLK40

Figure 12. A schematic of the PILOT within the L-0 interface scheme.

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Label ADC input

DAC output NominalVALUE

COMMENTS

T1_ALICE 0 1.222 V 5*PT VoltsT2._ALICE 1 1.222 V 5*PT VoltsT1_LHCb 0 1.3 V PT1000 VoltsT2_LHCb 1 1.3 V PT1000 VoltsMODE 0=LHCb; 1=ALICEvo_DRHI 2 1.8 V Pixel-Dac-Biasvo_DRMID 3 920 mV Pixel-Dac-Bias-Midvo_GTLA 4 900 mV Pixel-JTAG-Refvo_GTLD 5 900 mV Pixel-Data-Refvo_TESTHI 6 1.1 V Pixel-HiCal-Voltvo_TESTLOW 7 1.05 V Pixel-LoCal-VoltVDDDPC 8 1.8 V Pixel- -Dig-VoltVDDAPC 9 1.8 V Pixel-Analogue-Volt1.5VdDig 10 1.5 V PINT Core-VoltsGTL 1.6 Vttd 11 1.6 V Pixel -Term-Volts2V5Dig 12 1.25 V Digital Supply.

Used as Pilot -ref3.3VDig 13 1.65 V Digital Supply.

Used as Pilot -ref DACPCV 14 Pixel-DAC-VoltagesDACPCI 15 Pixel-DAC-CurrentsVbias_out 1.655 V DAC BiasDAC_ref_Vdd_out

1.0 V DAC Bias

DAC_ref_Mid_out

0.56 V DAC Bias

Vref0_out 513m V ADC reference LoVref1_out 1.925 V ADC reference Hivo_DRMID. 946mV Output for DAC bias MID.vo_DRHI. 1.712V Output for DAC bias HIGHvo_TESTLOW. 946mV Output for Pixel Cal Lo volts.vo_TESTHI. 1.12V Output for Pixel Cal High

volts.vo_GTLA. 802mV Output for Analogue JTAG

GTL

Version 1.0 23


vo_GTLD. 802mV Output for Digital JTAG GTLTable 3. Typical Analogue Pilot Reference Values.

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3.12 Low Voltage Filtering

The L-0 board routes ten externally generated digital and analogue power supply voltages for on-board use and for the LHCBPIX1 pixels. Most voltages, especially those required for the TTCrx, QPLL, GOLs, LHCBPIX1, are locally filtered with respect to their local analogue or digital reference planes. The 80 V silicon bias is filtered with respect to the analogue ground plane.

It should be noted that there is a conflict with the PIXEL JTAG which uses the L-0 digital ground referred JTAG logic at the L-0 interface to drive the analogue referred JTAG at the LHCBPIX1. However, the JTAG is not switching during data taking. Furthermore, full system tests show that the board operates within the required signal to noise range when JTAG is active at 100 KHz rate during data capturing.

The bias voltage for the LHCBPIX1 chips, which is 80 V with low noise and low current requirements, is filtered to the analogue ground and routed through the L-0 module. There is very little leakage (<1 nA at 80V) due to the PCB and the various connectors.

The on-board PILOT ASIC generates the LHCBPIX1 DAC/ADC reference voltages and currents, The LHCBPIX1 Test Pulse-lo and hi calibration levels are set and sourced by the PILOT. These two items are all locally filtered to analogue ground/reference and are AC coupled together to enable tracking in transient conditions. The currents for the PT type temperature sensors and the calibration reference for the PILOT are also filtered through the analogue ground plane.

Version 1.0 25


4 L-0 LHCb timing

This section details the relative timing of control signals, clocks and data across the L-0 interface. The measurements presented in this Section should be used as a reference when fault finding during production, commissioning and maintenance.

4.1 L-0 Calibration mode

For the L-0 interface module, the calibration mode is used to check the integrity of the data from the source LHCBPIX1 through the PINT and GOL to its transmission down the optical fibres.

The test set-up is described in detail in Section 8 and the various signals are defined in Fig. 28. In the lab the calibration command signal, or broadcast command, is issued by the TTCvi module. In the final experiment this module will be replaced by the Readout Supervisor. The command is transmitted down the TTC optical fibre where it is received on the L-0 module by the TTCrx chip. The PINT then interprets the converted electrical signal and subsequently generates a test-pulse at the inputs of the LHCBPIX1 pixels. A delayed L-0_Accept signal (L-1A in Fig. 28) issued via the TTC system triggers the PINT to strobe and readout the data associated with the test-pulse. The L-0_Accept delay has to match the latency in the LHCBPIX1 delay registers plus the delay through the Amplifier/Shaper/Discriminators. The test pulse, with programmed width, is produced in the PINT using CLK40DES2. The L-0_Accept is generated by the L-1A signal and arrives at a fixed time after the Broadcast command. The strobe, data capture and readout of the LHCBPIX1, using CLK40DES1, are triggered by the L-0_Accept. CLK40DES1 and CLK40DES2 can be delayed relative to each other.

The timing is shown schematically in Fig. 13. The coarse and fine timing are given by the “Delay” and the “Variable time related to CLK40DES1”, respectively. Their precise definitions are given below:

“Delay” is the time required, from the front-end of the test pulse in 25 ns CLK40DES2 time increments, for the front-end of the strobe to latch the data, generated by the test pulse, within the LHCBPIX1.

“Variable time related to CLK40DES1” is the fine time delay of CLK40DES2 relative to CLK40DES1, in 104.17 ps time increments. This allows the signal produced by the differentiated front edge of the test pulse to fit in the centre of the delayed strobe window and to fit within the data taking latency conditions.

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The Calibration mode can be interleaved with Physics Mode. The calibration mode functions within the LHCBPIX1 and the PINT and are addressed in some detail in Refs. [7] and [10].

Test Pulse.

Strobe.

CLK40Des1-.

CLK40Des1+.

Delay

T_Hold.

Variable time related to CLK40Des1. Strobe.

Test Pulse—Strobe “Data Capture" Timing Diag.

CLK40Des2-.

Figure 13. LHCBPIX1 PIXEL Calibration “Data Capture” timing.

Scope traces showing actual Test pulse measurements are shown in Fig. 14 and 15. For these measurements the following settings and measurement were adopted:

1. “The variable Fine time related to CLK2” is set to 0.2. LHCBPIX1 latency “Delay” is generated by setting LHCBPIX1 DAC42 =11.

The resulting delay at the LHCBPIX1 PIXEL delay unit = [(11*2) +3] * 25 ns= 625 ns.

3. Test pulse configuration and set-up: Start = 123 clock ticks4

Width = 10 clock ticks Test-hi set to 1.118 V Test-lo set to 1.090 V

4. Nominal Vth (LHCBPIX1 PIXEL DAC 39) ~205.5. Test Pattern set to “diagonals”.

4 Within the Oxford test set up this depends on the test station used.

Version 1.0 27


The Fast-OR is the test-pulse output from the pixel-cell discriminator entering the start of the delay units. This signal is then ‘delayed’ by the duration of the digital pipeline (latency). This delay can be seen in Figure 15 by the timing offset of 616ns between the Fast-OR signal and the STROBE. The trace IDs and their test point at the ZIF resistor [R] is shown to the right of each trace [29].

Figure 14. Test Pulse to Strobe measured timing is 708 ns

Version 1.0 28


Figure 15 Fast-OR to Strobe measured timing is 616 ns.

With data being latched and readout correctly it was observed that the time between the front-edge of test pulse to the strobe (capture of data) is 708 ns. The front edge of the Fast_Or to the strobe is 616 ns (Set delay in LHCBPIX1 =600nS). This demonstrates that an oscilloscope can be used to set the timing of the TEST pulse relative to the Strobe using the Fast_Or output at the LHCBPIX1 ZIF. (This is for coarse timing only.)

The test pulse starting values must be entered for this first order test to work. This can be done by using the available calibration configuration menu. The following need to be configured: PINT registers, Configure test pulse, the start of test pulse and the test pulse length.

The determination of the optimum “Variable time related to CLK2” setting would require a Time Scan to be done. This is discussed in Section 8.

4.2 Data Capture and Readout timing Mode

Version 1.0 29


L-0 Generated Data Capture and Readout Timings up to GOLs.

L-0 Accept(LK35)

Strobe. (R3)

NEVR (R4)

CE (R5)

Data Into PINTFrom Pixels.(RN16/4)

Data Into GOLs.(MICT-38)

TTCrxTo PINT.

PINT.

Generated

PINT to

PIXEL.

PINT to

PIXEL.

Data Into PINT.

PINT To

GOL.

33 Clocks ( Shift on neg edge).

(35+1) Clocks(Pos edge QPLL CLK into GOLs).

T0

11 ClocksMeasured =275nS

6 ClocksMeasured=6=150nS

7 clocksMeasured=175nS

7 ClocksMeasured=175nS

13 ClocksMeasured=325nS

50nS

CLK Ticks

Figure 16. Summary of the data capture and read out timing for the LHCBPIX1 to GOLs. The “Calibration” mode described in Section 4.1 was used to obtain the above values.

The sequence of events for data capture and readout is triggered by a TTCrx L-0_Accept. The test pulse is generated from a broadcast command when in the Calibration mode and was used when recording the oscilloscope traces shown on the following pages.

Fig. 16 shows the relationship of the TTC L-0_Accept signal at the PINT input to all of the signals required for the LHCBPIX1 data capture and read out up to the GOLs. The data for the diagram was compiled from the oscilloscope screen shots shown in Figs. 17 to 24. These were taken in the test assemblies at Oxford using production versions of the PINT and L-0 PCB5. The data were probed at the HPD ZIF resistors and L-0 interface module when coupled to two LHCBPIX1 PIXEL assemblies. The point probed on the L-0 interface module PCB or the HPD ZIF in order to make a measurement is indicated [29]. Table 4 summarises the signals, logic levels, and the timings.

One important feature to note is that the data to the PINT (TEST-DATA31 RN16/4) is clocked out from the LHCBPIX1 on the positive edge of CLK+ so there is

5 PINT v2.1η and PCB v5.

Version 1.0 30


a delay of 12.5 ns to receipt of the data at the PINT inputs. This can be seen in Fig. 19. The origin of this delay is unknown.

Figure 17. TTCrx L0_Accept to Strobe timing. =150nS.

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Figure 18. Strobe to NEVR timing is 25 ns.

Figure 19. PINT input data timing relative to NEVR. is ~102nS

Figure 20. GOL input data timing relative to NEVR is 150 ns.

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Figure 21. GOL data set-up time relative to CLKLHCP is 9.2 ns.

Figure 22. Clock phase differences and GOL input data across the L-0 interface logic with 10 ns/division.

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Figure 23. Clock phase differences and GOL input data across the L-0 interface logic with 20 ns/division.

Figure 24. Data into the GOLs relative to HPD NEVR is 150nS.

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Signal Polarity Source Destination Time from T0

Probe point

Test Pulse

Neg CMOS

PINT 2*PIXEL -Variable R7-HPD ZIF

Fast-Or Pos CMOS

PIXEL ZIF ~90nS after the negative going edge of the Test pulse

R10-HPD ZIF

L-0 Accept

Pos CMOS

TTCrx PINT---- 0 LK60-L0 PCB

Strobe Neg GTL PINT 2*PIXEL 150nS R3-HPD ZIFNEVR Neg GTL PINT 2*PIXEL 175nS R4-HPD ZIFCE Neg GTL PINT 2*PIXEL 225nS R5-HPD ZIFPix Data To PINT

Neg GTL PIXEL PINT Starts at 275nS

RN16/4-LO PCB

Start Data to GOLs

Pos CMOS

PINT GOLs 325nS MICT38-LO PCB

Table 4. Tabulation of the L-0 interface “Data Capture and Readout Timing” measurements.

4.3 Fibre link test mode

The mode is used for testing the TTCrx, QPLL/Xtal, GOLs and data fibre links. It does not check for data coming into the PINT from LHCBPIX1.

The timing sequence is very similar to the calibration mode for the data capture and readout part; it is triggered on receipt of either an L-0_Accept being generated or through a relevant TTCrx broadcast command signal. The mode is flagged in the BID (Bunch ID) FIFO in the PINT. When using the broadcast command mode the test pulse is generated but the resulting data from the LHCBPIX1 is masked and the internally generated PINT tests pattern with headers and trailers is read out to the GOLs. This mode can be interleaved with LHCb physics running. In

Version 1.0 35


the link test mode, initiated by an external L-0_Accept, the LHCBPIX data is also ignored and the test pattern is routed to the GOLs. However, this mode cannot be interleaved with physics runs. The Test data is always routed to the PINT output buffers and on to the GOLs. The Mode is entered by loading the PINT Configurable register with the appropriate value [7].

4.4 Physics Run Mode

This is the physics running mode, where a TTCrx L-0_Accept is generated by the Physics Trigger Processors to trigger the LHCBPIX1 data capture and readout of the data to the off detector L-1 electronics. The coarse and fine delay settings for physics running will be determined in situ. The delay figure will mainly be governed by the LHCb L-0 sub detector’s various data delays, L-0 trigger processing6, Readout Supervisor, TTC to TTCrx and PINT delays. Propagation times through fibres, cables, and differences in Time-of-flight of the trigger data and the LHCBPIX1 data also need to be taken into account. The corresponding value of the sum of all of these will need to be entered into LHCBPIX1 DAC 42, the delay control register.

The delayed LHCBPIX1 data is either stored or rejected. L-0_Accept stores the data at the LHCBPIX using the PINT generated strobe. The data is read out through the L-0 interface module to the GOLs using the PINT generated CE and NEVR synchronous with the CLK40DES1.

The timing diagram for the data capture and readout is very similar to the calibration mode (Fig. 13) but with a corresponding LHCb “Delay” and no broadcast test pulse.

4.5 LHCBPIX1 data pulse width

Fig. 25 shows the LHCBPIX1 data arriving at the input to the PINT chip. The data are strobed into the PINT with CLK40DES1. This data pulse width is ~27.3 ns FWHM. The figure demonstrates that if the negative edge of CLK40DES1 was used to latch the LHCBPIX1 data there could be an overlap of this data to two clock edges. Data would be wrongly clocked on the second clock edge; in the first design this was the cause of many problems. Care was taken in the following PINT designs to ensure that the clocking of this data into the PINT was on a clock edge that was delayed by greater than 5 ns but less than 20ns with respect to the leading edge of the

6 The current delay from the LHCb beam crossing to an L-0 trigger decision is ~4μs (160 clock ticks)

for LHCb.

Version 1.0 36


LHCBPIX1 data. CLK40DES1 is the synchronising clock used in the loading of this data into the PINT and by using the positive edge7 to latch this data the ambiguous selection is avoided.

Figure 25. The PIXEL data Pulse Width of 27.3nS and the L-0 CLK40DES1.

7 The edge selection is configurable within the PINT.

Version 1.0 37


5 JTAG

5.1 Introduction

For LHCb running the RICH Front-end electronics JTAG is controlled/driven by the ECS, via the SPECs slave and the Milano LV module, to the RICH front-end L-0 interface modules and the LHCBPIX1. The JTAG protocol is used to configure all the devices in the RICH L-0 local chain. It is also used to monitor and report error conditions, such as out-of-lock of the phase locking devices, to the ECS. There is one ECS chain per RICH L-0 module (resulting in reliability and no ECS data bottle neck)

5.2 JTAG principles

Boundary Scan Testing8 was developed in the mid-1980s as the JTAG interface to solve physical access problems on PCBs caused by increasingly crowded assemblies, which were now possible due to novel packaging technologies. Boundary scan embeds test circuitry at chip level to form a complete board-level test protocol. With boundary scan - industry standard IEEE 1149.1 since 1990 [12] - you can access even the most complex assemblies for testing, debugging and in-system device programming.

The boundary scan principleThe IEEE 1149.1 standard defines a four-wire serial interface (a fifth wire is optional) designated the Test Access Port (TAP) to access complex integrated circuits (ICs) such as microprocessors, DSPs, ASICs, and CPLDs. In addition to the TAP, a compliant IC also contains shift registers and a state machine to execute the boundary-scan functions. Data entering the chip on the TDI (Test Data In) pin is stored in the instruction register or in one of the data registers. Serial data leaves the chip on the TDO (Test Data Out) pin. The boundary-scan logic is clocked by the signal on TCK (Test Clock). The TMS (Test Mode Select) signal drives the state of the TAP controller. The optional TRST (Test Reset) serves as a hardware-reset signal.

Multiple scan-compatible ICs may be serially interconnected on the PCB, forming one or more boundary scan chains, each chain having its own TAP. Each scan chain provides electrical access from the serial TAP interface to every pin on every IC that is part of the chain. In normal operation, the IC performs its intended function as though the boundary-scan circuits were not present. However, when the

8 Taken from JTAG Technologies information http://www.jtag.com

Version 1.0 38


device’s scan logic is activated for the purpose of testing or in-system programming, data can be sent to the IC and read from it using the serial interface. This data may be used to stimulate the device core, drive signals outward from the device pins to the PCB, sense the input pins from the PCB and sense the device outputs.

5.3 JTAG Implementation in the L-0 interface module The JTAG protocol is used to configure and carry out monitoring of the whole of the RICH L-0 front-end electronics. The majority of the JTAG interface logic complies with the IEEE 1149.1 standard. The TTCrx uses I2C signals [11], which are translated from the JTAG within the PINT. No boundary scan functions are carried out because these are unavailable in the PINT ACTEL PGA.

5.3.1 The RICH L-0 Module JTAG TDI/TDO chain

The L-0 interface module JTAG chain and state machines is composed of seven blocks. The TDI/TD0 sequence for these is as follows:

1. PINT2. LHCBPIX1.0 3. LHCBPIX1.1 4. GOL15. GOL26. PILOT7. TTCrx.

The logic level standards of the components differ: The incoming/outgoing signals, from the SPECs slave, for the L-0 interface

module are LVDS standard signals. The LHCBPIX1.0 and LHCBPIX1.1 use the GTL+ standard signals. The GOL1, GOL2, the PILOT and the TTCrx all use the CMOS standard

signals. The PINT handles LVDS, GTL and CMOS standards.

The various standards for all of the blocks are developed by the PINT. The JTAG chain and logic levels are shown in the block diag. Fig. 26.

Version 1.0 39


JTAG TDI/TDO Chain and Logic Levels (Oxford set-up).

JTA

G C

ontr

olle

r37

05

Oxf

ord

Pow

er S

uppl

y

PINTPINTConf- PINT

PINT

PIX 1 PIX

2

GOL-1GOL-2PILOTTTCrxPINTB.S.

CMOS LVDS CMOS GTL GTL GTL

PINT LVDS

CMOS

CMOSCMOSCMOSCMOS

TDO TDI/TDO TDO

TDI/TDOTDI/TDOTDI/TDO

TDITDI

TDOTDO

PINT

TDI

TDITDI/TDO

CMOS

TDI

TDO

Figure 26. The JTAG chain and logic levels on the L-0 interface module.

In the final system the Oxford power supply and JTAG controller 3705 are replaced by the Milano LV board which incorporates a SPECs slave. JTAG is a series linked TDI/TDO system so to facilitate tracing faults in the chain there are facilities within the L-0 interface to allow hardwire linking to by-pass any link/block in the chain. This is also coupled with complete isolation of the TDI -TDO lines for each block. As described in Section 8 this is utilized in the first stage of L-0 board testing where the LHCBPIX1 chips are removed from the JTAG chain.

5.3.2 Other JTAG hardware issues

The TTCrx output is tri-state and an R129 resistor is required on the output to quickly pull down the TDO line when entering the high (off) impedance state. The L-0 interface module JTAG runs successfully at 100 KHz TCK rate, concurrently with data taking.

It has not been tested at the LHCb ECS proposed 1 MHz TCK rate at the time of writing. This rate is to be used with the SPECs system.

The JTAG TCK and TMS for each JTAG state machine are common bussed items with the appropriate PINT generated signal standard for each block.

The JTAG state machines are not radiation hard so to avoid any accidental changes of state from SEU, the TRST is in the active state at all times when in the

Version 1.0 40


idle mode. It is re-activated when accessing the state machines. This is achieved by controlling the TRST lines from the PINT [7]. A consequence of the TRST being held active while the state machines are idle is that the registers cannot be monitored via JTAG during data taking.

5.3.3 Configuration Registers

The configuration settings and functions for all of the devices and their registers are covered in detail in the following references:

1. PINT. Section 7 [7] 2. LHCBPIX1. Appendices 11 and 12 [10]3. GOL. Chapter 2 [8]4. PILOT [14]5. TTCrx Chapters 3 and 7 [3]

5.3.4 JTAG Device IDs

JTAG scans and checks the ID of all the chips in the chain. For the main blocks in the L-0 interface module:

GOLs = 0x1453 5049 (HEX) TTCrx = 0x1545 408F (HEX) PILOT = 0x1201 1973 (HEX) PINT = Depends on the module ID. This code is unique for each

module and it helps to identify the module as a RICH item and its location within LHCb.

5.3.5 JTAG conversion to I2C for TTCrx

All of the configuration registers in the TTCrx can be accessed via I2C. In LHCb I2C will be used for setting these registers and the I2C protocol and signals are generated within the PINT. Within the TTCrx, JTAG is used for reading the chip ID, but it can be used for boundary scan purposes.

Version 1.0 41


6 Low Voltage Power Requirements

This Section lists the various power requirements of the components on the L-0 interface module. The total power requirements delivered through the 40-way IDC connector are also given.

6.1 LHCBPIX1 Low Voltage requirements

Firstly the power requirements of the LHCBPIX1 alone are discussed. There are two voltages that provide the pull-up level for the GTL logic signals:VTTA is for the inputs biased from the analogue supply (JTAG at LHCBPIX1 etc.). VTTD is for the digital inputs (CLK*, STROBE* etc) and for the digital outputs (DATA*<0:31>). The following list of bias voltages and currents are for an individual LHCBPIX1. The values are those for the maximum possible consumption when all LHCBPIX1 data and control lines are pulled to a GTL level “1” state. =0V.

1. VTTA (82R GTL Load) (Analogue) = 1.8V @ 80 mA2. VTTD (82R GTL Load) (Digital) = 1.6V @ 625 mA 3. GTL ref. (Digital) = 0.9V @ 0.1 mA 4. Vddd@40MHz (Digital) = 1.8V. @ 600 mA 5. Welld (Digital) = 1.8V @ 0 mA 6. Vdda (Analogue) = 1.8V. @ 400 mA 7. Wella (Analogue) = 1.8V @ 0 mA

The following list of applied voltages and currents drawn are for the whole L-0 interface module with two LHCBPIX1 chips attached. Again the largest possible values of currents drawn are quoted.

1. PIXEL chip (Analogue) = 1.8V @ 960mA2. Analogue PILOT (Analogue) = 2.6V @ 21mA3. 2*LHCBPIX1 (Digital) = 1.6V @ 1.25A (82R load)4. 2*LHCBPIX1 (Digital) = 1.8V @ 1.20A5. Truelight (Digital) = 5.0V @ 40mA6. QPLL (Digital) = 2.5V @ 40mA7. GOL (Digital) = 2.5V @ 312mA8. TTCrx (Digital) = 3.3V. @ 76mA9. ACTEL Core (Digital) = 1.5V @ ~100mA10. ACTEL Banks (Digital) = 3.3V @ ~100mA11. ACTEL Banks (Digital) = 2.5V @ ~100mA 12. ACTEL ref bias (Digital) = 0.8V @ 1mA

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The maximum digital and analogue reference currents with respect to ground are 3.22 A and 0.981 A. This assumes that all the LHCBPIX1 ADCs and DAC s have been set to their safe working values.

6.2 Grounds (0 V reference)

There are Separate “Ground” returns for Digital and Analogue at the L-0 interface module.

Any coupling of the “Zero Volt References” should be made at the HPD Ziff board and then to a known LHCb “STAR”9 point. All Supplies and Grounds from the Low Voltage module must be kept separate at the L-0 interface board level.

6.3 L-0 interface Low Voltage requirements Power requirements with fully configured, two LHCBPIX1 pixels, and up and running system are summarized in the following table.

9 STAR point has yet to be defined within LHCb.

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Block. Voltage AnalogueCurrent

DigitalCurrent

VOLTS. AMPS Av Amps.

TRUELIGHT 5.0 0.040TTCrx 3.3 0.076QPLL/XTAL 2.5 0.0402*GOLs 2.5 0.6242* CRT4T 2.5 2*VCSEL, 3.3 0.020PINT 1.5 0.100

2.5 0.100

3.3 0.100

PILOT 2.5 @ 0.021LHCBPIX1 Vdda 1.8 0.800VTTA 1.8 0.160Vddd 1.8 1.200GTL ref 0.8-0.9 0.0001VTTD 1.6 1.250Bias Supply 80 @~120nA

Total.

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7 The Oxford Test Station low voltage power supply scheme

The voltages and currents reported here are based on measurements done in the test stations at Oxford. There should not be too much difference when using the SPECs and Milano system. The generic power supply scheme for the Oxford L-0 test stations is shown in Fig. 27.

The Oxford L-0 Test Station Low Voltage Power Supply Scheme.

5VoltAnalogue

BaseSupply

JTAGControlModule

3705.

5VoltDigitalBase

Supply

+80VoltAnodeBias

Supply

Ele

ctro

met

er

0V

0V

5V

5V

FromPC

Oxf

ord

L-0

/LH

CB

PIX

1Po

wer

supp

ly a

nd J

TA

G

Inte

rfac

e.

LHCBPIX10

LHCBPIX11L

-0 In

terf

ace

Mod

ule

40Way IDC connection.

Link “T”

Note: Link “T” is used only in the bench tests.

Figure 27. Typical Power supply and JTAG routing to the L-0 Interface and the LHCBPIX1 PIXELs

The following list gives the supply voltages and currents drawn at the base supplies for various L-0 configurations.

1. BASE supply voltages:a. Analogue Voltage: = 5.1 volts.b. Digital Voltage: = 5.1 volts.

2. With the Oxford LV power supplies connected but no LHCBPIX1s and no L-0 Interface modules connected:

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a. Analogue Current: = 0.13Ab. Digital Current: = 0.043A

3. With the L-0 Interface Module connected but no LHCBPIX1s:a. Analogue Current: = 0.8Ab. Digital Current: = 0.195A

4. With the L-0 Interface Module connected and two LHCBPIX1s when powered but unconfigured10:

a. Analogue Current = 3.86Ab. Digital Current = 1.2A

5. With two LHCBPIX1s connected into the L-0 interface module and with the PIXEL DACs and the Analogue Pilot set to nominal values:

a. Analogue Current: = 1.7Ab. Digital Current: = 0.850A

6. The LHCBPIX1 anode bias:a. Bias Supply = +80 voltsb. Bias Current. ~ 120nAmps.

These measurements were taken with data and trigger rates that are sparse compare to the LHCb Running conditions. With a 1 MHz L-0 accept rate the digital currents will be higher than those above. (Results of measurements under these conditions will be added as they become available.)

10 Caution: The switch-on of the power supplies result in random settings for the PILOT and LHCBPIX1 PIXEL DACS. The supply currents into the LHCBPIX1 PIXEL can be high. This is a situation that could result in damage to the LHCBPIX1 PIXEL/HPDs. Therefore, RUN the JTAG configuration program to set nominal value immediately after power switch-on.

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8 Production testing

8.1 Introduction

This section adopts a generic approach to the testing and does not attempt to detail the production-testing software and hardware schemes as used in Oxford. There is an in-house document that already does this.

The various quality control tests must have been carried out on all the components prior to the assembly of the L-0 modules. In particular, the analogue PILOTs were tested individually [28]. Furthermore, the BGA package type devices must always be stored in a dry-nitrogen atmosphere prior to mounting on the PCB.

The boards are automatically optically inspected (AOI) at the manufacturer before shipping to Oxford. On receipt of the completed assemblies the modules require some further hardware set-up before the first phase of electrical testing:

1. The board ID, , governed by the unique laser marked number on the Analogue PILOT, needs to be set up.

2. The VCSELs emitters and TRUELIGHT receiver are mounted.3. Various links need to be in place on the L-0 module. These are for the by-

passing of the JTAG chain at the LHCBPIX1-0 and LHCBPIX1-1, the coupling of wella and welld to their respective reference rails, the connecting of the LEDs to their power rails, and for the TTCrx address and board ID to be set-up.

8.2 The Oxford Test Stations

A schematic of the L-0 test stations is shown in Fig. 28; this set up is used for all phases of the testing as described below. The L1-A and BGo are externally generated synchronised input signals to the TTCvi [30]. The BGo triggers the Broadcast command for the test pulse and the link tests. The L1-A initialises the generation of L-0 _Accept within and through the TTCvi.

The electrometer monitors the bias currents taken by the LHCBPIX1 PIXELs.Other modules used in the test set-up have been discussed in the previous Sections.

8.3 The three phases of testing

There are three phases to the electrical testing of the modules:1. Tests of the basic functionality of the boards without the LHCBPIX1 pixel

anodes attached.

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2. Setting the nominal threshold values of the L-0 interface with respect to the required noise specification.

3. Converting the threshold values to number of electrons and compare to the specification to detect single photoelectrons in the HPDs.

OXFORD L-0 MODULE PRODUCTION TEST SET-UP

DigitalBasePS.

DATA FibresTo L-1

Receivers

LHCBPIX1 PIXELsTTCvi TTCvx

BGo

L-1A

KAPTONS

L-0 INTERFACEMODULE

TTCFIBRES

OXFORD Power Supply.

LEDs

40Way.

AnalogueBasePS.

+80VBias

Electrometer

JTAGCont

3705 To/FromPC

CRT4T/GOLSwitch

Figure 28. The Oxford setup used for all phases of testing.

8.4 Aims and the sequence for the First Phase Testing.

(Warning: Tests with LHCBPIX1-0 and LHCBPIX1-1 coupled into the L-0 interface module must never be attempted until all the first phase L-0 board tests have been completed. The complete JTAG chain must be fully functional to enable the setting of the LHCBPIX1 PIXELs DACs to the safe nominal working values and the setting PILOT generated DC levels, which are used in the LHCBPIX1 PIXELs. Otherwise, at switch-on LHCBPIX1 PIXELs DAC levels and PILOT levels may be set to values, which if maintained, can damage the LHCBPIX1 PIXELs. )

There are six stages to the first phase of testing: 1. visual inspection.2. power-up tests.

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3. synchronisation tests.4. JTAG test.5. fibre link tests.6. PILOT tests.

Any board failing any of these tests is put to one side for separate detailed diagnostic tests. The results are reported to the manufacture, where appropriate.

8.4.1 Visual inspection

Boards are inspected for bad solder joints and bridges between tracks or pins. Also, a search for misaligned components is made.

8.4.2 Power-up tests

As stated above the two LHCBPIX1 PIXELs must not be connected to the L-0 interface. All other modules are coupled to the L-0 interface module at this stage. The key features of this test are:

The L-0 interface modules are coupled to the Oxford power supply via the 40- way header cable.

The Oxford power supply has LEDs which indicate the voltage status on all of the output rails.

The analogue and digital base supplies are switched on. The voltage rails are current limited. Any short circuits in the voltage rails are indicated by dimmed LEDs on the

Oxford power supply at switch on. The voltage values arriving at the L-0 interface module are measured at the 40

way connector.This is not a test for open circuits at the L-0 module. These will show up with the later tests.

The GTL reference voltages, for the PINT banks receiving/transmitting the data and controls for the LHCBPIX1 PIXELs has to be set to (800-900)mV, using RV1 and RV2 .

8.4.3 Synchronisation tests

The two LHCBPIX1 PIXELs must not be connected to the L-0 interface.

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The TTC chain within the L-0 module is tested for the synchronisation of the various modules involved. There are limits to the tests of the TTCrx, which are addressed in the third phase. The main blocks and items making up the synchronising chain, which are tested in this phase, are:

1. Truelight2. TTCrx3. QPLL4. CRT4T5. GOL 16. GOL 27. 5.0 V8. 3.3 V power rail9. 2.5 V power railThe TTCvi /TTCvx with TTC fibres coupled to the TTCrx via the Truelight

receiver should be initialised and running. The TTCvi /TTCvx supplies the clocks needed for the TTCrx to generate the CLK40, CLK40DES1 and CLK40DES2.

The Oxford power supplies are switched on, and then the CRT4T/ GOL switch needs to be activated. The GOLs require the CRT4T/GOL switch for controlled power-up. Once powered all the LEDs on the TTCrx, QPLL, GOL1 and GOL2 outputs, indicating a valid PLL status, should come up and remain in a stable on state. If this is not the case then identify the LED situation and use Table 5 as a guide for tracing a possible cause of the fault.

If the synchronisation is correct then within the L-0 interface all the clocks required around the L-0 logic should be stable, in phase and available.

LED Status Potential causeNo TTCrx, All others OK No TTC; Truelight; No 5.0 V; No 3.3 V; Faulty

TTCrx; TTCrx RESET held in on state; faulty LED No GOLs, all others OK Faulty switch to CRT4Ts; CRT4T; QPLL output; 2.5

V error; GOL Resets held in on state (PINT--)Any one GOL, all others OK

Corresponding CRT4T; faulty LED. Reset--

QPLL, all others OK QPLL LED.No QPLL, No GOLs. QPLL and/or faulty Xtal; 2.5 Volts.All off 2.5 V, 3.3 V and 5 V missing: LED jumper links set

to off; Truelight, TTCrx and QPLL at fault; Major PINT problem possible—RESETS???

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Table 5. Initial possible Synchronisation errors, translation from LED status.

8.4.4 JTAG test

The two LHCBPIX1 PIXELs must not be connected to the L-0 interface.The L-0 module configuration begins with a JTAG routine that reads the JTAG device IDs of the TTCrx, GOLs, PINT and PILOT. If the device codes read back are correct then the JTAG TDI/TDO hardware chain and control lines TCK, TMS are assumed to be fine. The JTAG Device IDs should be:

GOLs = 0x1453 5049 TTCrx = 0x1545 408F PILOT = 0x1201 1973 PINT = Depends on the board id.

The errors in the JTAG chain that can be met are: 1. Running JTAG causes the TTCrx or GOLs to lose lock intermittently. Can be

caused by one of the devices (the TTCrx or GOLs) being placed erroneously into the Boundary Scan mode, which temporarily changes the function of the device output pads. TMS, TCK faults, TDI/TDO shorts or wrong logic levels do not help this situation. The same conditions can also produce JTAG ID errors.

2. JTAG ID set to FFFFs. This can be caused by: (Similar to 1)a) TDI/TDO short circuit or other errors in any link or devices. If it is

within a device or package pins then tracing the fault will require a reasonable understanding of the JTAG boundary scan architecture and the JTAG TAP (Test Access Port) controller state diagram. (For reference see Chapter 3 of the IEEE 1149.1 standard.) Capturing single shot traces on the oscilloscope and analysing the TCK, TMS and TDI/TDO at each block in the JTAG chain can be helpful. A quick scoping to search for identical data on the TDI/TDO links can show up the location of any TDI/TDO short circuits.

b) Timing or logic level errors on the bussed TMS or TCK lines. Monitor and diagnose these bussed logic signals with an oscilloscope

c) Ensure that the LHCBPIX1-0 and LHCBPIX1-1 TDI/TDO by-pass links are in place.

To aid fault finding there are facilities built in to the L-0 Module to sequentially hardware and software isolate each block from the TDI/TDO chain. Resort to this

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only after the TCK and TMS busses have been checked out.Short circuits and other errors have been experienced on the TTCrx and GOL1

TDI/TDO lines.

8.4.5 Link tests

Always take great care to keep the fibre couplers and fibre surfaces clean, dust free and avoid sharp bends in the fibre cables.The configuration for this mode is set within the PINT. The appropriate L-0_Accept starts the readout of a fixed pattern of data from the PINT to the GOLS/VCSELs through to the L-1 receiver. The set up for link tests is described in detail in section 4.3. This mode is used for the thorough testing of the TTCrx, QPLL/Xtal, GOLs and fibre links.

Listed below are some error scenarios with possible causes and solutions.1. No data arriving at L-1 on both links.

VCSEL threshold currents are in error; check value entered from the menu.

Use power meter to check outputs of the VCSELs. Check that the VCSELs are mounted on the L-0 board

correctly, in particular check the polarity. GOLs are not achieving the correct operating or driving

values for the VCSELs. Check the circuitry around the CRT4T, using figure 10 for reference.

2. No Data arriving on one of the links. VCSEL threshold current is in error; check value entered from the

menu. GOL is not achieving the correct operating or driving values for the

VCSEL; check the circuitry around the CRT4T. Faulty VCSEL use the power meter to check the output power. Carry

out a Threshold Bias current vs. VCSEL Power output test. Dirt/dust in VCSEL opening; use Air duster to blow out dust. Faulty GOL; measure the DC voltages and AC components around the

GOL. Bad Link: Exchange Links to see if fault follows link.

3. Parity errors or data crashes at L-1 on one specific link. GOL, CRT4T, VCSEL intermittent errors; investigate as in 1 and 2. VCSEL temperature problems; check CRT4T DC values.

Version 1.0 52


Wrong current in VCSEL due to faulty/flakey GOL.4. Parity errors or data crashes at L-1 on both links.

TTCrx, QPLL, CRT4T errors. TTCrx or QPLL losing phase-lock. Faults in the 5V, 3.3V or 2.5V power rails to the TTCrx, QPLL, GOLs

and/or CRT4T.

8.4.6 PILOT test and LV references

Before proceeding with any further test it is necessary to calibrate the PILOT in order to drive the LHCBPIX1 chips. The calibration is performed in two steps. In the first step the ADC on the PILOT is calibrated using the two references voltages provided by the dividers R93-R96. These four identical resistors divide the 2.5 V and 3.3 V and these levels are connected to the PILOT test inputs. Using a multi-meter the two levels are measured and input to the testing program. The ADC is then sampled 5000 times and the average values returned for these reference inputs are used to calibrate this function of the chip.

Once the calibration constants of the ADC are known the six DACs are then calibrated. Each of them is scanned between 0 and 180 and for each point the corresponding level is sampled 100 times with the ADC. The ADC measurements are averaged and converted to volts using the calibration constants just calculated. The six volts vs. DAC count distribution are then fitted as a straight line and the coefficients so obtained are use to convert an input voltage to its corresponding DAC count.

8.5 Second phase test: nominal threshold values for L-0 interface module

This phase requires that the two LHCBPIX1 PIXELs be coupled, via the Kaptons, to the L-0 module. The TTC, all power supplies, CRT4T/GOL switch and JTAG interface all need to be included as shown in Figure 28. The following hardware configuration is required.

1. The JTAG by-pass TDI/TDO links for the LHCBPIX1 must not be in place. 2. The +80 V bias should be applied to both LHCBPIX1 and the total current

should be ~120 nA. 3. The LHCBPIX1 run mode is set ALICE. 4. The LHCBPIX1 PIXEL DACs 31 contains the nominal starting threshold

value.

Version 1.0 53


A threshold-noise scan is carried out on both PIXELs, with the noise hits/Event of <10-4 being the target for the nominal threshold value setting for that set up. This setting should be in the range of 200 to 205 to be acceptable. If it is not, the scan is repeated up to three times; if an acceptable threshold is not found the L-0 interface module is rejected.

8.6 Thermal burn-in Boards that successfully pass the first and second phase of testing are baked overnight at 500 C to stressed the board and accelerate the rate of infant mortality. Any component failures at this time will be picked up at the beginning of the third testing phase.

8.7 The third phase of testing

The set-up is identical to the second phase, but this third phase takes much more time and is generally carried out in a second test set-up. A pair of high efficiency LHCBPIX1s is required for this test; these act as a ‘standard candle’ to compare L-0 modules.

The thresholds measured during the second phase are converted from an arbitrary unit to a number of electrons during this phase. First of all the thresholds are measured again with higher statistics. Then the detection efficiency of each pixel is measured with 100 test pulses with height varying between 0 and 20 mV with 1 mV increments.

In order to avoid any effect due to time walk this procedure is repeated varying the delay of the test pulse between 0 and 75 ns in steps of 1ns. For a fixed test pulse height the pixel efficiency vs. test pulse delay distribution will in general behave like a plateau curve of width about 25 ns; a typical distribution for an individual ALICE pixel is shown in Fig. 29. However, the centre of the plateau varies from pixel-to-pixel therefore an optimum delay is found from the distribution of the number of pixels with efficiency higher than 98% vs. test pulse delay which is seen shown in Fig. 30.

Having fixed the delay, the efficiency vs. test pulse is plotted for every pixel. An example is shown in Fig. 31. The threshold value is defined as the test pulse for which the efficiency is 50%. This value is then converted into electrons using 1mV = 100 electrons11.

11 This conversion factor is derived from the capacitance of the test pulse capacitor on each ALICE

pixel cell is 16 fF. So from V=Q/C 1mV=100 electrons.

Version 1.0 54


The distribution of 8192 thresholds so obtained for each LHCBPIX1 chip is fitted with a Gaussian. An example is shown in Fig. 32. Boards with a sigma excessively large are discarded these are indicative of noise induced within the L-0 module. It has been found that the width is well measured by sampling only one in eight ALICE pixels. As this leads to a significant decrease in the amount of time taken for the third phase of testing this has now been adopted as the default.

All the data shown in the figures is taken from the tests done on board 77.(The test procedures in the third stage are still evolving so this section may be

updated.)

Figure 29: The efficiency as a function of test pulse delay for an individual ALICE pixel.

Version 1.0 55


Figure 30: Distribution of pixels with efficiency greater than 98% as a function of test pulse delay. The maximum of this distribution is chosen as the optimal setting with which to measure the thresholds.

Figure 31. The efficiency as a function of the number of electrons for an individual pixel.

Version 1.0 56


Figure 32. The distribution of pixel thresholds for one LHCBPIX1 read out with an L-0 module.

Version 1.0 57


9 L-0 module mechanical information

This Section describes the space constraints imposed upon the L-0 module. The boards interconnects are also described.

9.1 Space Constraints

The available space to house the L-0 interface electronics is very limited within the LHCb RICH Photon detector plane region [1]. The support structure and the routing of services such as the data fibres, the TTC fibres and the low voltage-high current power rails place tight constraints on the available board area and size within which the complex electronics has to be supported.

The acceptable board mechanics and layout needed to house the electronics and to cope with the above constraints was discussed in great detail. Result is shown in Figs. 33 and 34. The volume occupied by each board is (165 * 100 * 3) mm3

LHCb RICH J.H.Bibby

L-0 Interface Board Dimensions.

165

10 10

89.5

30

30

20

20

100

3.75 3.75

Diam 3.5 The grey area is availablefor components.

146.5

Area covered by 40way connector shroud

157.5

Figure 33. Schematic of the PCB mechanical details.

Version 1.0 58


3 .7 5

J 3

LH C bLe ve l 0

j0 4 /0 1 6In te rfa c e v 3

P c b N u m b e r _ _ _P a ss _ _ _ _ _ _ _ _ _

F a il _ _ _ _ _ _ _ _ _J . Bi b b yM . J o n e sN . Ro to lo

D S2

U6

U2U4

D S1

1 6 5

1 5 7 .5

U1

8 9 .5

J 1

U3

U8

U5

SK 3

DA

NG

ER

80

V

3 .7 5

2 5 .5 1

5 0 .7

3 0

3 0

2 0

1 0 0

L-0 Interface Dimensions and Layout

Figure 34 PCB Mechanical layout.

9.2 Interconnects

The L-0 module interconnects are:1. 40-way shrouded IDC connector for Power supplies and JTAG. The pin

functions are listed in Appendix A.2. ST fibre optics connector for the TTC input. It is mounted at 45 degrees to one

board edge.3. Two SMA fibre optics connectors for the VCSEL and Data Fibre outputs.

They are mounted at 45 degrees to one board edge.4. Four 0.5 mm pitch, 50-way HIROSE FH12S-50S-0.5 SH connector. These are

ribbon connectors for coupling the LHCBPIX1 PIXELs to the L-0 interface module. The pin functions are given in Appendix B.

5. Headers for coupling the PT resistors for measuring PILOT and PINT temperatures.

6. Two of 38 way MICT connectors coupling the PINT/GOL signals to a logic analyser. (These are used only on the pre-production types)

Version 1.0 59


10 AcknowledgementsThe success of this project is due to the long term commitment and dedication of the many personnel at Oxford, CERN, Imperial College and Cambridge. In particular the author would like to thank the following for all their direct help and support; the Oxford team of Marco Adinolfi, Neville Harnew, Mark Jones, Jim Libby, Andrew Powell, Nico Rotolo, Stig Topp-Jorgenson, Nigel Smale and Phil Sullivan, Jorgen Christiansen at CERN, Steve Wotton of Cambridge, and Ken Wyllie at CERN.

Version 1.0 60


Appendix A: L-0 40-way low voltage and JTAG connector pins allocation

PIN ID Functions. PIN ID Functions.

A1 JTAG TDI-N A11 1V8_DIGB1 JTAG TDI-P B11 DIG_GNDA2 JTAG TMS-P A12 DIG_GNDB2 JTAG TMS-N B12 DIG_GNDA3 JTAG TCK-N A13 DIG_GNDB3 JTAG TCK-P B13 DIG_GNDA4 JTAG TDO-P A14 DIG_GNDB4 JTAG TDO-N B14 GOL_Pwr.UpA5 3.3V_DIG A15 ANA_GNDB5 1V5_DIG B15 ANA_GNDA6 5V_DIG A16 ANA_GNDB6 2V5_DIG B16 ANA_GNDA7 2V5_DIG A17 ANA_GNDB7 2V5_DIG B17 1V8_ANAA8 1V6_VTTD A18 1V8_ANAB8 1V6_VTTD B18 1V8_ANAA9 1V6_VTTD A19 2V5_ANAB9 1V8_DIG B19 2V5_ANAA10 1V8_DIG A20 80V_DEP1B10 1V8_DIG B20 80V_DEP2

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Appendix B: HPD to L-0 connectivity

Details can be found in references [2, 29] 50 way HIROSE FH12S-50S-0.5 SH connector J1 and J2, J3 and J4 coupling of L-0 to LHCBPIX1 PIXELs

Connector J1a and J1 and J3Signal Name J1a

Pin#(HPD)

J1andJ3 Pin#(L-0 Board)

Signal Name J1aPin#(HPD)

J1and J3 Pin#(L-0 Board)

VSSD (Dig

GND)

1 50 FAST_OR* 26 25

DATA <16> 2 49 TEST_PULSE* 27 24DATA <17> 3 48 VTTIN (GTL_1.8V) 28 23DATA <18> 4 47 VTTIN (GTL_1.8V) 29 22DATA <19> 5 46 VTTIN (GTL_1.8V) 30 21DATA <20> 6 45 WELLD 31 20DATA <21> 7 44 WELLD 32 19DATA <22> 8 43 GTL_REF 33 18DATA <23> 9 42 VSSD (Dig GND) 34 17VSSD (Dig

GND)

10 41 VSSA (Ana GND) 35 16

DATA <24> 11 40 FAST_MULT 36 15DATA <25> 12 39 ANALOG_TEST_LO 37 14DATA <26> 13 38 ANALOG_TEST_HI 38 13DATA <27> 14 37 NOT CONNECTED 39 12DATA <28> 15 36 VSSA (Ana GND) 40 11DATA <29> 16 35 WELLA 41 10DATA <30> 17 34 WELLA 42 9DATA <31> 18 33 VDDA (Ana 1.8V) 43 8VSSD (Dig

GND)

19 32 VDDA (Ana 1.8V) 44 7

STROBE* 20 31 VDDA (Ana 1.8V) 45 6CE* 21 30 VDDA (Ana 1.8V) 46 5ABORT* 22 29 VDDA (Ana 1.8V) 47 4DATA_RESET* 23 28 VTTA (JTAG-GTL) 48 3SHIFT_RESET* 24 27 VTTA (JTAG-GTL) 49 2

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ALICE 25 26 VSSA (Ana GND) 50 1

Notes: VDDA Analogue 1.8V. VSSA Analogue GND. VSSD Digital GND. VDDD Digital 1.8V. VTTA GTL JTAG pull-up VTTin GTL for Synchronising Sigs.

Connector J2a and J2b

Signal Name J2a Pin#(HPD)

J2and J4 (L-0 Board)

Signal Name J2aPin#(HPD)

J2 and J4 (L-0 Board)

VSSA (Ana

GND)

1 50 VDDD (Dig

1.8V)

26 25

NOT CONNECTED

2 49 VDDD (Dig

1.8V)

27 24

IBIAS (VBIAS) 3 48 VDDD (Dig

1.8V)

28 23

IBIAS (VBIAS) 4 47 VDDD (Dig

1.8V)

29 22

NOT CONNECTED

5 46 VDDD (Dig

1.8V) 30 21

VSSA (Ana

GND)

6 45 VDDD (Dig

1.8V)

31 20

TEMPERATURE (1ST WIRE)

7 44 VSSD (Dig GND)32 19

TEMPERATURE (2ND WIRE)

8 43 DATA <0> 33 18

GTL_REFA 9 42 DATA <1> 34 17DAC_SENSE_I 10 41 DATA <2> 35 16DAC_SENSE_V 11 40 DATA <3> 36 15DAC_REF_VDD 12 39 DATA <4> 37 14DAC_REF_MID 13 38 DATA <5> 38 13TRESET* 14 37 DATA <6> 39 12

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TMS 15 36 DATA <7> 40 11TCLK 16 35 VSSD (Dig

GND) 41 10

TDO 17 34 DATA <8> 42 9TDI1 18 33 DATA <9> 43 8TDI0 19 32 DATA <10> 44 7VSSA(Ana GND) 20 31 DATA <11> 45 6VSSD (Dig

GND) 21 30 DATA <12> 46 5

NEVR* 22 29 DATA <13> 47 4CLK* 23 28 DATA <14> 48 3CLK 24 27 DATA <15> 49 2VDDD (Dig

1.8V)

25 26 VSSD (DigGND)

50 1

NOTE: The two wires for the temperature reading are connected to the SAME SIDE of the

PT1000 sensor. The other side of the sensor is connected to VSSA (analog GND).

Version 1.0 64


Glossary of termsCE. Without NEVR, reads out from the LHCBPIX1 Readout

buffers.CLK+. Positive Pixel Clock.CLK-. Negative Pixel Clock.CLK40. The TTCrx clock used only for the PILOT DAC/ADC

conversions.CLK40DES1. The TTCrx clock used for the synchronisation in the PINT

for data capture, data processing and data output to the GOLs.CLK40DES2. The TTCrx clock used for the synchronisation of the Test-

Pulse.CLKLHCN The negativeGOL LVDS clock input.CLKLHCP. The positive GOL LVDS clock input.Fast-Or. Digital output from the LHCBPIX1 Front-end electronics. GOL. Gigabit Optical Link Transmitter.GTL. Gunning Transistor logic.HIROSE. Kapton Film/Ribbon connector used on the L-0 module and

the HPD LHCBPIX1 ZIF boards for coupling L-0 module to the LHCBPI.

HPD. Hybrid Photon Detector.IIC. A simple bi-directional 2-wire Inter-IC or I2C-bus for efficient

internal -IC control.http://www.semiconductors.philips.com/acrobat_download/literature/9398/39340011.pdf

JTAG. A standard for testing the internal circuitry on a chip itself and written by the Joint Test Action Group (JTAG). The architecture is known as "JTAG boundary scan" or as "IEEE 1149 boundary scan ".http://www.ieee.org

L-0_Accept. LHCb level 0 trigger.LHCBPIX1 Front-end Pixel ASIC located in the vacuum envelope of the

HPD.LVDS. Low Voltage Differential Signalling, NEVR. With CE, Loads data to the Readout buffers.PILOT CERN radiation hard ASIC whose function is to supply

analogue Bias volts and currents to LHCBPIX1 also monitors front end Volts and Currents.

PINT. Pixel INTerface.QPLL Quartz Xtal Based Phase-Lock Loop.

Version 1.0 65

http://www.ieee.org/

http://www.semiconductors.philips.com/acrobat_download/literature/9398/39340011.pdf



SMA. Fibre connector type as used by the VCSEL data transmitter.ST. Fibre connector type as used by the TTCrx Truelight receiver.Strobe. Stores the front-end data info to the LHCBPIX1 FIFO on an

LHCb L-0 Accept.Test-pulse. Discharges capacitors into the LHCBPIX1 Front-end

electronics. TFC. The control of the TTC system in LHCb is performed by the

Timing and Fast Control system (TFC).Truelight TTC optical receiverTTC. Distributes all the required synchronization (clock and resets)

and trigger signals to the front-end systems of LHC experiments. (Fibre optics to front-ends)

TTCrx. A Timing Trigger Control Receiver ASIC.VCSEL Vertical Cavity Surface Emitting Laser.

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http://lhcb-comp.web.cern.ch/lhcb-comp/TFC/default.html


References

[1] EDMS L-0 mechanics https://edms.cern.ch/file/490700/1/dimension.pdf [2] EDMS L-0 electronicshttps://edms.cern.ch/file/490699/2/Level_0_schematic_version2.pdf[3] TTCrx Reference Manual, J. Christiansen, A. Marchioro, P. Moreira and T. Toifl. http://ttc.web.cern.ch/TTC/intro.html.[4] Synchronization of front-end electronics.http://lhcb-elec.web.cern.ch/lhcb-elec/html/synchronisation.htm[5] Use of TTC system in LHCb:http://lhcb-elec.web.cern.ch/lhcb-elec/html/ttc_use.htm[6] Technical specification for the supply of pixel Hybrid Photon Detectors for the LHCb Ring Imaging Cherenkov system.https://edms.cern.ch/file/498198/1/hpd_tech_spec_050127.doc

[7] [7] The RICH Pixel INTerface (PINT) chip, M. Adinolfi, CERN/LHCb 2004-059 (to be released).[8] GOL reference manual, J. Christiansen, A. Marchioro, P. Moreira, T. Toifl, A.Kluge and G.Cervelli, http://proj-gol.web.cern.ch/proj-gol[9] VCSEL---ULM photonics.http://www.ulm-photonics.de(Dr.-Ing. Burghard SchneiderGeneral Manager / GeschaeftsfuehrungSCHOTT AG - ULM-photonics GmbHLise-Meitner-St. 13; D-89081 Ulm / GermanyFon +49(0)731 550194-014; Cell +49 (0)177 200 2974; Fax +49 (0)[email protected])[10] LHCBPIX1 Documentation: Draft 2, Ken Wyllie,http://kwyllie.home.cern.ch/kwyllie/LHCBPIX1_doc/LHCBPIX1_manual.pdf[11] IIC-Bus specification, Philips Semiconductors document 9398 393 40011.http://www.semiconductors.philips.com/acrobat_download/literature/9398/39340011.pdf[12] Boundary Scan Architecture, IEEE Standard 1149.1.http://standards.ieee.org/reading/ieee/std_public/description/testtech/1149.1-1990_desc.html[13] CERN Analog Pilot Chip Description and pad list, G. Anelli, R. Dinapoli and A. Kluge.

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http://standards.ieee.org/reading/ieee/std_public/description/testtech/1149.1-1990_desc.html

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http://kwyllie.home.cern.ch/kwyllie/LHCBPIX1_doc/LHCBPIX1_manual.pdf

http://www.ulm-photonics.de/

http://proj-gol.web.cern.ch/proj-gol

https://edms.cern.ch/file/498198/1/hpd_tech_spec_050127.doc

http://lhcb-elec.web.cern.ch/lhcb-elec/html/ttc_use.htm

http://lhcb-elec.web.cern.ch/lhcb-elec/html/synchronisation.htm

http://ttc.web.cern.ch/TTC/intro.html

https://edms.cern.ch/file/490699/2/Level_0_schematic_version2.pdf

https://edms.cern.ch/file/490700/1/dimension.pdf


http://a.home.cern.ch/a/akluge/www/work/alice/spd/spd_frame.html[14] Specifications of the digital control part of the Analogue Pilot Chip, A.Kluge.http://a.home.cern.ch/a/akluge/www/work/alice/spd/spd_frame.html[15] The ECS interface.http://lhcb-elec.web.cern.ch/lhcb-elec/html/ecs_interface.htm[16] Agilent, HFBR-782B/BE/BH Pluggable parallel fibre optic module receiverdata sheet.http://www.avagotech.com/pc/downloadDocument.do?id=3174[17] Grounding, shielding and power distribution in LHCb, V. Bobillier, J. Christiansen and R. Frei, LHCb 2004-039.http://doc.cern.ch/archive/electronic/cern/others/LHB/public/lhcb-2004-039.pdf[18] Radiation hard reference or expected radiation levels in the LHCb RICH.http://lhcb-background.web.cern.ch/lhcb-background/Radiation/SUMtable2.htm[19] ACTEL 1000 data sheet, http://www.actel.com/products/axcelerator/index.html#features[20] Radiation qualification of the PINT, M. Adinolfi.http://indico.cern.ch/materialDisplay.py?contribId=s1t3&materialId=0&confId=a053509[21] TTC optical Receiver, Truelight device TRR-1B43-000.http://lhcb-elec.web.cern.ch/lhcb-elec/html/special_components.htm#TTC%20optical%20receiver[22] High speed ribbon optical link for the level 0 muon trigger, E. Aslanides et al., LHCb-2003-008.http://documents.cern.ch/cgi-bin/setlink?base=LHCb&categ=public&id=lhcb-2003-008[23] Private communication A. Vollhardt, IT tracker Group.[24] QPLL User Manual, Paulo Moreira, CERNhttp://ttc.web.cern.ch/TTC/intro.html[25] Overview of the RICH Optical Data Link and Evaluation of its Optical Attenuation, A. Powell, LHCb 2006-003.http://documents.cern.ch/cgi-bin/setlink?base=LHCb&categ=internal&id=lhcb-2006-003[26] The readout Electronics of the RICH Detector,https://edms.cern.ch/file/492255/1/RICH_electronics_system.pdf[27] LHCb parallel optical readout link homepage. http://www.physik.unizh.ch/~avollhar/LHCb_parallel_optical_links.html[28] The Analogue pilot testing document, A. Powell.http://indico.cern.ch/getFile.py/access?resId=1&materialId=0&confId=a053509

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https://edms.cern.ch/file/492255/1/RICH_electronics_system.pdf

http://documents.cern.ch/cgi-bin/setlink?base=LHCb&categ=internal&id=lhcb-2006-003

http://documents.cern.ch/cgi-bin/setlink?base=LHCb&categ=internal&id=lhcb-2006-003


http://documents.cern.ch/cgi-bin/setlink?base=LHCb&categ=public&id=lhcb-2003-008

http://documents.cern.ch/cgi-bin/setlink?base=LHCb&categ=public&id=lhcb-2003-008

http://lhcb-elec.web.cern.ch/lhcb-elec/html/special_components.htm#TTC%20optical%20receiver

http://lhcb-elec.web.cern.ch/lhcb-elec/html/special_components.htm#TTC%20optical%20receiver

http://indico.cern.ch/materialDisplay.py?contribId=s1t3&materialId=0&confId=a053509

http://indico.cern.ch/materialDisplay.py?contribId=s1t3&materialId=0&confId=a053509

http://www.actel.com/products/axcelerator/index.html#features

http://lhcb-background.web.cern.ch/lhcb-background/Radiation/SUMtable2.htm

http://doc.cern.ch/archive/electronic/cern/others/LHB/public/lhcb-2004-039.pdf

http://www.avagotech.com/pc/downloadDocument.do?id=3174

http://lhcb-elec.web.cern.ch/lhcb-elec/html/ecs_interface.htm

http://a.home.cern.ch/a/akluge/www/work/alice/spd/spd_frame.html

http://a.home.cern.ch/a/akluge/www/work/alice/spd/spd_frame.html


[29] HPD pin outhttp://www.ge.infn.it/~mini/[30] TTCvi/vx reference manual. http://ttc.web.cern.ch/TTC/intro.html

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