Reference 1

© 2009 Microchip Technology Inc. DS70157D

16-bit MCU and DSC Program-mer’s Reference Manual

High-Performance Microcontrollers (MCU)and Digital Signal Controllers (DSC)

Note the following details of the code protection feature on Microchip devices:• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

DS70157D-page 2

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

© 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

© 2009 Microchip Technology Inc.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

Table of Contents

PAGESECTION 1. INTRODUCTION 5

Introduction ......................................................................................................................................................... 6Manual Objective ................................................................................................................................................ 6Development Support ......................................................................................................................................... 6Style and Symbol Conventions ........................................................................................................................... 7Instruction Set Symbols ...................................................................................................................................... 8Related Documents ............................................................................................................................................. 9

SECTION 2. PROGRAMMER’S MODEL 1116-bit MCU and DSC Core Architecture Overview ............................................................................................ 12Programmer’s Model ......................................................................................................................................... 14Working Register Array ..................................................................................................................................... 17Default Working Register (WREG) .................................................................................................................... 17Software Stack Frame Pointer .......................................................................................................................... 18

SECTION 3. INSTRUCTION SET OVERVIEW 29Introduction ....................................................................................................................................................... 30Instruction Set Overview ................................................................................................................................... 30Instruction Set Summary Tables ....................................................................................................................... 32

SECTION 4. INSTRUCTION SET DETAILS 41Data Addressing Modes .................................................................................................................................... 42Program Addressing Modes .............................................................................................................................. 51Instruction Stalls ................................................................................................................................................ 52Byte Operations ................................................................................................................................................ 54Word Move Operations ..................................................................................................................................... 56Using 10-bit Literal Operands ........................................................................................................................... 59Software Stack Pointer and Frame Pointer ....................................................................................................... 60Conditional Branch Instructions ........................................................................................................................ 65Z Status Bit ........................................................................................................................................................ 66Assigned Working Register Usage .................................................................................................................... 67DSP Data Formats (dsPIC30F and dsPIC33F Devices) ................................................................................... 70Accumulator Usage (dsPIC30F and dsPIC33F Devices) .................................................................................. 72Accumulator Access (dsPIC30F and dsPIC33F Devices) ................................................................................. 73DSP MAC Instructions (dsPIC30F and dsPIC33F Devices) ............................................................................. 74DSP Accumulator Instructions (dsPIC30F and dsPIC33F Devices) ................................................................. 78Scaling Data with the FBCL Instruction (dsPIC30F and dsPIC33F Devices) .................................................... 79Normalizing the Accumulator with the FBCL Instruction (dsPIC30F and dsPIC33F Devices) .......................... 81

SECTION 5. INSTRUCTION DESCRIPTIONS 83Instruction Symbols ........................................................................................................................................... 84Instruction Encoding Field Descriptors Introduction .......................................................................................... 84Instruction Description Example ........................................................................................................................ 88Instruction Descriptions ..................................................................................................................................... 89

SECTION 6. REFERENCE 357Instruction Bit Map .......................................................................................................................................... 358Instruction Set Summary Table ....................................................................................................................... 360Revision History .............................................................................................................................................. 367

© 2009 Microchip Technology Inc. DS70157D-page 3

16-bit MCU and DSC Programmer’s Reference Manual

SECTION 7. INDEX 369

SECTION 8. WORLDWIDE SALES AND SERVICE 374

DS70157D-page 4 © 2009 Microchip Technology Inc.

Introduction

1

Section 1. Introduction

HIGHLIGHTSThis section of the manual contains the following topics:

1.1 Introduction ....................................................................................................................... 61.2 Manual Objective .............................................................................................................. 61.3 Development Support ....................................................................................................... 61.4 Style and Symbol Conventions ......................................................................................... 71.5 Instruction Set Symbols .................................................................................................... 81.6 Related Documents .......................................................................................................... 9



1.1 INTRODUCTIONMicrochip Technology’s focus is on products that meet the needs of the embedded controlmarket. We are a leading supplier of:

• 8-bit general purpose microcontrollers (PIC® MCUs)• 16-bit Digital Signal Controllers (dsPIC® DSCs)• 16-bit and 32-bit Microcontrollers (MCUs)• Speciality and standard nonvolatile memory devices• Security devices (KEELOQ® Security ICs)• Application-specific standard productsPlease request a Microchip Product Selector Guide for a listing of all the interesting products thatwe have to offer. This literature can be obtained from your local sales office or downloaded fromthe Microchip web site (www.microchip.com).

1.2 MANUAL OBJECTIVEThis manual is a software developer’s reference for the 16-bit MCU and DSC device families.This manual describes the Instruction Set in detail and also provides general information to assistthe user in developing software for the 16-bit MCU and DSC families.

This manual does not include detailed information about the core, peripherals, system integrationor device-specific information. The user should refer to the specific device family referencemanual for information about the core, peripherals and system integration. For device-specificinformation, the user should refer to the individual data sheets. The information that can be foundin the data sheets includes:

• Device memory map• Device pinout and packaging details• Device electrical specifications• List of peripherals included on the deviceCode examples are given throughout this manual. These examples are valid for any device inthe 16-bit MCU and DSC families.

1.3 DEVELOPMENT SUPPORTMicrochip offers a wide range of development tools that allow users to efficiently develop anddebug application code. Microchip’s development tools can be broken down into four categories:

• Code generation• Hardware/Software debug• Device programmer• Product evaluation boardsInformation about the latest tools, product briefs and user guides can be obtained from theMicrochip web site (www.microchip.com) or from your local Microchip Sales Office.

Microchip offers other reference tools to speed the development cycle. These include:

• Application Notes • Reference Designs • Microchip web site • Local Sales Offices with Field Application Support • Corporate Support Line The Microchip web site also lists other sites that may be useful references.


http://www.microchip.com

Section 1. IntroductionIntroduction

1
1.4 STYLE AND SYMBOL CONVENTIONS
Throughout this document, certain style and font format conventions are used. Most formatconventions imply that a distinction should be made for the emphasized text. The MCU industryhas many symbols and non-conventional word definitions/abbreviations. Table 1-1 provides adescription of the conventions used in this document.

Table 1-1: Document Conventions

Symbol or Term Description

set To force a bit/register to a value of logic ‘1’.clear To force a bit/register to a value of logic ‘0’.Reset 1. To force a register/bit to its default state.

2. A condition in which the device places itself after a device Resetoccurs. Some bits will be forced to ‘0’ (such as interrupt enable bits),while others will be forced to ‘1’ (such as the I/O data direction bits).

0xnnnn Designates the number ‘nnnn’ in the hexadecimal number system. These conventions are used in the code examples. For example, 0x013F or 0xA800.

: (colon) Used to specify a range or the concatenation of registers/bits/pins. One example is ACCAU:ACCAH:ACCAL, which is the concatenation of three registers to form the 40-bit Accumulator.Concatenation order (left-right) usually specifies a positional relationship (MSb to LSb, higher to lower).

< > Specifies bit locations in a particular register. One example is SR<7:5> (or IPL<2:0>), which specifies the register and associated bits or bit positions.

LSb, MSb Indicates the Least Significant or Most Significant bit in a field.LSB, MSB Indicates the Least/Most Significant Byte in a field of bits.lsw, msw Indicates the least/most significant word in a field of bits.Courier Font Used for code examples, binary numbers and for Instruction Mnemonics

in the text.Times New Roman Font, Italic

Used for equations and variables.

Times New Roman Font, Bold Italic

Used in explanatory text for items called out from a figure, equation or example.

Note: A Note presents information that we want to re-emphasize, either to help you avoid a common pitfall, or make you aware of operating differences between some device family members. In most instances, a Note is used in a shaded box (as illustrated below); however, when referenced in a table, a Note will appear at the bottom of the associated table (see Table 1-2).

Note: This is a Note in a shaded note box.



1.5 INSTRUCTION SET SYMBOLSThe Summary Tables in Section 3.2 “Instruction Set Overview” and Section 6.2 “InstructionSet Summary Table”, and the instruction descriptions in Section 5.4 “InstructionDescriptions” utilize the symbols shown in Table 1-2.

Table 1-2: Symbols Used in Instruction Summary Tables and Descriptions

Symbol(1) Description

{ } Optional field or operation[text] The location addressed by text(text) The contents of text#text The literal defined by texta ∈ [b, c, d] “a” must be in the set of [b, c, d]<n:m> Register bit field{label:} Optional label nameAcc Accumulator A or Accumulator BAWB Accumulator Write Backbit4 4-bit wide bit position (0:7 in Byte mode, 0:15 in Word mode)Expr Absolute address, label or expression (resolved by the linker)f File register addresslit1 1-bit literal (0:1)lit4 4-bit literal (0:15)lit5 5-bit literal (0:31)lit8 8-bit literal (0:255)lit10 10-bit literal (0:255 in Byte mode, 0:1023 in Word mode)lit14 14-bit literal (0:16383)lit16 16-bit literal (0:65535)lit23 23-bit literal (0:8388607)Slit4 Signed 4-bit literal (-8:7)Slit6 Signed 6-bit literal (-32:31) (range is limited to -16:16)Slit10 Signed 10-bit literal (-512:511)Slit16 Signed 16-bit literal (-32768:32767)TOS Top-of-StackWb Base working register Wd Destination working register (direct and indirect addressing)Wm, Wn Working register divide pair (dividend, divisor)Wm * Wm Working register multiplier pair (same source register)Wm * Wn Working register multiplier pair (different source registers)Wn Both source and destination working register (direct addressing)Wnd Destination working register (direct addressing)Wns Source working register (direct addressing)WREG Default working register (assigned to W0)Ws Source working register (direct and indirect addressing)Wx Source Addressing mode and working register for X data bus prefetchWxd Destination working register for X data bus prefetch Wy Source Addressing mode and working register for Y data bus prefetchWyd Destination working register for Y data bus prefetchNote 1: The range of each symbol is instruction dependent. Refer to Section

5. “Instruction Descriptions” for the specific instruction range.


Section 1. IntroductionIntroduction

1
1.6 RELATED DOCUMENTS
Microchip, as well as other sources, offer additional documentation which can aid in yourdevelopment with 16-bit MCUs and DSCs. These lists contain the most common documentation,but other documents may also be available. Please check the Microchip web site(www.microchip.com) for the latest published technical documentation.

1.6.1 Third-Party DocumentationThere are several documents available from third-party sources around the world. Microchipdoes not review these documents for technical accuracy. However, they may be a helpful sourcefor understanding the operation of Microchip16-bit MCU and DSC devices. Please refer to theMicrochip web site (www.microchip.com) for third-party documentation related to the 16-bit MCUand DSC families.





NOTES:


Section 2. Programmer’s Model

Programm

er’s M

odel

2
HIGHLIGHTS
This section of the manual contains the following topics:

2.1 16-bit MCU and DSC Core Architecture Overview ......................................................... 122.2 Programmer’s Model....................................................................................................... 142.3 Working Register Array................................................................................................... 172.4 Default Working Register (WREG) ................................................................................. 172.5 Software Stack Frame Pointer ........................................................................................ 18



2.1 16-BIT MCU AND DSC CORE ARCHITECTURE OVERVIEWThis section provides an overview of the 16-bit architecture features and capabilities for thefollowing families of devices:

• 16-bit Microcontrollers (MCUs):- PIC24F- PIC24H

• 16-bit Digital Signal Controllers (DSCs):- dsPIC30F- dsPIC33F

2.1.1 Features Specific to 16-bit MCU and DSC CoreThe core of the 16-bit MCU and DSC devices is a 16-bit (data) modified Harvard architecture withan enhanced instruction set. The core has a 24-bit instruction word, with an 8-bit Op code field.The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user programmemory space. An instruction prefetch mechanism is used to help maintain throughput andprovides predictable execution. The majority of instructions execute in a single cycle.

2.1.1.1 REGISTERS

The 16-bit MCU and DSC devices have sixteen, 16-bit working registers. Each of the workingregisters can act as a data, address or offset register. The 16th working register (W15) operatesas a software Stack Pointer for interrupts and calls.

2.1.1.2 INSTRUCTION SET

The instruction set is almost identical for the 16-bit MCU and DSC architectures. The instructionset includes many Addressing modes and was designed for optimum C compiler efficiency.

2.1.1.3 DATA SPACE ADDRESSING

The data space can be addressed as 32K words or 64 Kbytes. The upper 32 Kbytes of the dataspace memory map can optionally be mapped into program space at any 16K program wordboundary, a feature known as Program Space Visibility (PSV). The program to data spacemapping feature lets any instruction access program space as if it were the data space, which isuseful for storing data coefficients.

2.1.1.4 ADDRESSING MODES

The core supports Inherent (no operand), Relative, Literal, Memory Direct, Register Direct,Register Indirect and Register Offset Addressing modes. Each instruction is associated with apredefined Addressing mode group, depending upon its functional requirements. As many as 7Addressing modes are supported for each instruction.

For most instructions, the CPU is capable of executing a data (or program data) memory read, aworking register (data) read, a data memory write and a program (instruction) memory read perinstruction cycle. As a result, 3-operand instructions can be supported, allowing A + B = Coperations to be executed in a single cycle.

2.1.1.5 ARITHMETIC AND LOGIC UNIT

A high-speed, 17-bit by 17-bit multiplier is included to significantly enhance the core arithmeticcapability and throughput. The multiplier supports Signed, Unsigned, and Mixed mode, 16-bit by16-bit, or 8-bit by 8-bit integer multiplication. All multiply instructions execute in a single cycle.

The 16-bit Arithmetic Logic Unit (ALU) is enhanced with integer divide assist hardware thatsupports an iterative non-restoring divide algorithm. It operates in conjunction with the REPEATinstruction looping mechanism, and a selection of iterative divide instructions, to support 32-bit(or 16-bit) divided by 16-bit integer signed and unsigned division. All divide operations require 19cycles to complete, but are interruptible at any cycle boundary.


Section 2. Programmer’s ModelProgram

mer’s

Model

2

2.1.1.6 EXCEPTION PROCESSING

The 16-bit MCU and DSC devices have a vectored exception scheme with support for up to 8sources of non-maskable traps and up to 118 interrupt sources. In both families, each interruptsource can be assigned to one of seven priority levels.

2.1.2 dsPIC30F and dsPIC33F FeaturesIn addition to the information provided in 2.1.1 “Features Specific to 16-bit MCU and DSCCore”, this section describes the DSP enhancements that are available in the dsPIC30F anddsPIC33F families of devices.

2.1.2.1 PROGRAMMING LOOP CONSTRUCTS

Overhead free program loop constructs are supported using the DO instruction, which isinterruptible.

2.1.2.2 DSP INSTRUCTION CLASS

The DSP class of instructions are seamlessly integrated into the architecture and execute froma single execution unit.

2.1.2.3 DATA SPACE ADDRESSING

The data space is split into two blocks, referred to as X and Y data memory. Each memory blockhas its own independent Address Generation Unit (AGU). The MCU class of instructions operatesolely through the X memory AGU, which accesses the entire memory map as one linear dataspace. The DSP dual source class of instructions operates through the X and Y AGUs, whichsplits the data address space into two parts. The X and Y data space boundary is arbitrary anddevice-specific.

2.1.2.4 MODULO AND BIT-REVERSED ADDRESSING

Overhead free circular buffers (modulo addressing) are supported in both X and Y addressspaces. The modulo addressing removes the software boundary checking overhead for DSPalgorithms. Furthermore, the X AGU circular addressing can be used with any of the MCU classof instructions. The X AGU also supports bit-reverse addressing, to greatly simplify input oroutput data reordering for radix-2 FFT algorithms.

2.1.2.5 DSP ENGINE

The DSP engine features a high-speed, 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bitsaturating accumulators and a 40-bit bidirectional barrel shifter. The barrel shifter is capable ofshifting a 40-bit value, up to 16 bits right, or up to 16 bits left, in a single cycle. The DSPinstructions operate seamlessly with all other instructions and have been designed for optimalreal-time performance. The MAC instruction and other associated instructions can concurrentlyfetch two data operands from memory while multiplying two working registers. This requires thatthe data space be split for these instructions and linear for all others. This is achieved in atransparent and flexible manner through dedicating certain working registers to each addressspace.

2.1.2.6 EXCEPTION PROCESSING

The dsPIC30F devices have a vectored exception scheme with support for up to 8 sources ofnon-maskable traps and up to 54 interrupt sources. The dsPIC33F devices have a similarexception scheme, but supports up to 118 interrupt sources. In both families, each interruptsource can be assigned to one of seven priority levels.



2.2 PROGRAMMER’S MODELFigure 2-1 through Figure 2-2 show the programmer’s model diagrams for the 16-bit MCU andDSC families of devices.

Figure 2-1: PIC24F and PIC24H Programmer’s Model Diagram

TABPAG

22 0

7 0

015

Program Counter

Data Table Page Address

Status Register

Working Registers

W1

W2

W3

W4

W5

W6

W7

W8

W9

W10

W11

W12

W13

W14/Frame Pointer

W15/Stack Pointer

PSVPAG7 0

Program Space Visibility Page Address

Z— — — —

RCOUNT15 0

REPEAT Loop Counter

IPL2 IPL1

SPLIM Stack Pointer Limit Register

SRL

PUSH.S Shadow

— —

15 0 CPU Core Control Register

Legend

CORCON

— DC RA N C

TBLPAG

PSVPAG

IPL0 OV

W0/WREG

SRH

DIV and MULResult Registers



mer’s

Model

2

Figure 2-2: dsPIC30F and dsPIC33F Programmer’s Model Diagram

TABPAG

22 0

7 0

015

Program Counter

Data Table Page Address

Status Register

Working Registers

MAC OperandRegisters

W1

W2

W3

W4

W5

W6

W7

W8

W9

W10

W11

W12/MAC Offset

W13/MAC Write Back

W14/Frame Pointer

W15/Stack Pointer

MAC AddressRegisters

39 031

DSPAccumulators

ACCA

ACCB

PSVPAG7 0

Program Space Visibility Page Address

ZOA OB SA SB

RCOUNT15 0

REPEAT Loop Counter

DCOUNT15 0

DO Loop Counter

DOSTART22 0

DO Loop Start Address

IPL2 IPL1

SPLIM Stack Pointer Limit Register

15

SRL

PUSH.S Shadow

DO Shadow

OAB SAB

15 0 CPU Core Control Register

Legend

CORCON

DA DC RA N C

TBLPAG

PSVPAG

IPL0 OV

W0/WREG

SRH

DO Loop End AddressDOEND22 0

DIV and MULResult Registers



All registers in the programmer’s model are memory mapped and can be manipulated directly bythe instruction set. A description of each register is provided in Table 2-1.

Note: Unless otherwise specified, the Programmer’s Model Register Descriptions inTable 2-1 apply to all MCU and DSC device families.

Table 2-1: Programmer’s Model Register Descriptions

Register Description

CORCON CPU Core Configuration registerPC 23-bit Program CounterPSVPAG Program Space Visibility Page Address registerRCOUNT Repeat Loop Count registerSPLIM Stack Pointer Limit Value registerSR ALU and DSP Engine STATUS registerTBLPAG Table Memory Page Address registerW0-W15 Working register arrayACCA, ACCB(1) 40-bit DSP AccumulatorsDCOUNT(1) DO Loop Count registerDOEND(1) DO Loop End Address registerDOSTART(1) DO Loop Start Address registerNote 1: This register is only available on dsPIC30F and dsPIC33F devices.



mer’s

Model

2

2.3 WORKING REGISTER ARRAYThe 16 working (W) registers can function as data, address or offset registers. The function of aW register is determined by the instruction that accesses it.

Byte instructions, which target the working register array, only affect the Least Significant Byte(LSB) of the target register. Since the working registers are memory mapped, the Least and MostSignificant Bytes (MSBs) can be manipulated through byte-wide data memory space accesses.

2.4 DEFAULT WORKING REGISTER (WREG)The instruction set can be divided into two instruction types: working register instructions and fileregister instructions. The working register instructions use the working register array as data values, or as addresses that point to a memory location. In contrast, file register instructionsoperate on a specific memory address contained in the instruction opcode.

File register instructions that also utilize a working register do not specify the working register thatis to be used for the instruction. Instead, a default working register (WREG) is used for these fileregister instructions. Working register, W0, is assigned to be the WREG. The WREG assignmentis not programmable.



2.5 SOFTWARE STACK FRAME POINTERA frame is a user-defined section of memory in the stack, used by a function to allocate memoryfor local variables. W14 has been assigned for use as a Stack Frame Pointer with the link (LNK)and unlink (ULNK) instructions. However, if a Stack Frame Pointer and the LNK and ULNKinstructions are not used, W14 can be used by any instruction in the same manner as all otherW registers. See 4.7.2 “Software Stack Frame Pointer” for detailed information about theFrame Pointer.

2.5.1 Software Stack PointerW15 serves as a dedicated Software Stack Pointer, and will be automatically modified by functioncalls, exception processing and returns. However, W15 can be referenced by any instruction inthe same manner as all other W registers. This simplifies reading, writing and manipulating theStack Pointer. Refer to 4.7.1 “Software Stack Pointer” for detailed information about the StackPointer.

2.5.2 Stack Pointer Limit Register (SPLIM)The SPLIM is a 16-bit register associated with the Stack Pointer. It is used to prevent the StackPointer from overflowing and accessing memory beyond the user allocated region of stackmemory. Refer to 4.7.3 “Stack Pointer Overflow” for detailed information about the SPLIM.

2.5.3 Accumulator A, Accumulator B (dsPIC30F and dsPIC33F Devices)

Accumulator A (ACCA) and Accumulator B (ACCB) are 40-bit wide registers, utilized by DSPinstructions to perform mathematical and shifting operations. Each accumulator is composed of3 memory mapped registers:

• AccxU (bits 39-32)• AccxH (bits 31-16)• AccxL (bits 15-0)

Refer to 4.12 “Accumulator Usage (dsPIC30F and dsPIC33F Devices)” for details on usingACCA and ACCB.

2.5.4 Program CounterThe Program Counter (PC) is 23 bits wide. Instructions are addressed in the 4M x 24-bit userprogram memory space by PC<22:1>, where PC<0> is always set to ‘0’ to maintain instructionword alignment and provide compatibility with data space addressing. This means that duringnormal instruction execution, the PC increments by 2.

Program memory located at 0x800000 and above is utilized for device configuration data, Unit IDand Device ID. This region is not available for user code execution and the PC can not accessthis area. However, one may access this region of memory using table instructions. For detailson accessing the configuration data, Unit ID and Device ID, refer to the specific device familyreference manual.

2.5.5 TBLPAG RegisterThe TBLPAG register is used to hold the upper 8 bits of a program memory address during tableread and write operations. Table instructions are used to transfer data between program memoryspace and data memory space. For details on accessing program memory with the tableinstructions, refer to the specific device family reference manual.

2.5.6 PSVPAG Register (PIC24F, PIC24H, dsPIC30F and dsPIC33F)Program space visibility allows the user to map a 32 Kbyte section of the program memory spaceinto the upper 32 Kbytes of data address space. This feature allows transparent access ofconstant data through instructions that operate on data memory. The PSVPAG register selectsthe 32 Kbyte region of program memory space that is mapped to the data address space. Fordetails on program space visibility, refer to the specific device family reference manual.



mer’s

Model

2

2.5.7 RCOUNT RegisterThe 14-bit RCOUNT register contains the loop counter for the REPEAT instruction. When aREPEAT instruction is executed, RCOUNT is loaded with the repeat count of the instruction,either “lit14” for the “REPEAT #lit14” instruction, or the contents of Wn for the “REPEAT Wn”instruction. The REPEAT loop will be executed RCOUNT + 1 time.

2.5.8 DCOUNT Register (dsPIC30F and dsPIC33F Devices)The 14-bit DCOUNT register contains the loop counter for hardware DO loops. When a DOinstruction is executed, DCOUNT is loaded with the loop count of the instruction, either “lit14” forthe “DO #lit14,Expr” instruction, or the 14 Least Significant bits of Ws for the “DO Ws,Expr”instruction. The DO loop will be executed DCOUNT + 1 time.

2.5.9 DOSTART Register (dsPIC30F and dsPIC33F Devices)The DOSTART register contains the starting address for a hardware DO loop. When a DOinstruction is executed, DOSTART is loaded with the address of the instruction following the DOinstruction. This location in memory is the start of the DO loop. When looping is activated,program execution continues with the instruction stored at the DOSTART address after the lastinstruction in the DO loop is executed. This mechanism allows for zero overhead looping.

2.5.10 DOEND Register (dsPIC30F and dsPIC33F Devices)The DOEND register contains the ending address for a hardware DO loop. When a DO instructionis executed, DOEND is loaded with the address specified by the expression in the DO instruction.This location in memory specifies the last instruction in the DO loop. When looping is activatedand the instruction stored at the DOEND address is executed, program execution will continuefrom the DO loop start address (stored in the DOSTART register).

2.5.11 STATUS RegisterThe 16-bit STATUS register, maintains status information for instructions which have mostrecently been executed. Operation Status bits exist for MCU operations, loop operations andDSP operations. Additionally, the STATUS register contains the CPU Interrupt Priority Level bits,IPL<2:0>, which are used for interrupt processing.

Depending on the MCU and DSC family, the following register descriptions are provided:

• Register 2-1 for PIC24F and PIC24H devices• Register 2-2 for dsPIC30F and dsPIC33F devices

2.5.11.1 MCU ALU STATUS BITS

The MCU operation Status bits are either affected or used by the majority of instructions in theinstruction set. Most of the logic, math, rotate/shift and bit instructions modify the MCU Status bitsafter execution, and the conditional Branch instructions use the state of individual Status bits todetermine the flow of program execution. All conditional branch instructions are listed in 4.8 “Conditional Branch Instructions”.

The Carry, Zero, Overflow, Negative and Digit Carry (C, Z, OV, N and DC) bits are used to showthe immediate status of the MCU ALU. They indicate when an operation has resulted in a Carry,Zero, Overflow, Negative result and Digit Carry, respectively. When a subtract operation isperformed, the C flag is used as a Borrow flag.

Note 1: If a REPEAT loop is executing and gets interrupted, RCOUNT may be cleared bythe Interrupt Service Routine to break out of the REPEAT loop when the foregroundcode is re-entered.

2: Refer to the specific device family reference manual for complete details aboutREPEAT loops.



The Z status bit is a special zero status bit that is useful for extended precision arithmetic. The Zbit functions like a normal Z flag for all instructions except those that use a carry or borrow input(ADDC, CPB, SUBB and SUBBR). See 4.9 “Z Status Bit” for usage of the Z status bit.

2.5.11.2 LOOP STATUS BITS

The REPEAT Active (RA) bit is used to indicate when looping is active. The RA flag indicates thata REPEAT instruction is being executed, and it is only affected by the REPEAT instructions. TheRA flag is set to ‘1’ when the instruction being repeated begins execution, and it is cleared whenthe instruction being repeated completes execution for the last time.

Since the RA flag is also read-only, it may not be directly cleared. However, if a REPEAT or itstarget instruction is interrupted, the Interrupt Service Routine may clear the RA flag of the SRL,which resides on the stack. This action will disable looping once program execution returns fromthe Interrupt Service Routine, because the restored RA will be ‘0’.

2.5.11.2.1 DO Active (DA) bit (dsPIC30F and dsPIC33F Devices)The DO Active (DA) bit is used to indicate when looping is active. The DO instructions affect theDA flag, which indicates that a DO loop is active. The DA flag is set to ‘1’ when the first instructionof the DO loop is executed, and it is cleared when the last instruction of the loop completes finalexecution.

The DA flag is read-only. This means that looping may not be initiated by writing a ‘1’ to DA, norlooping may be terminated by writing a ‘0’ to DA. If a DO loop must be terminated prematurely,the EDT bit, CORCON<11>, should be used.

2.5.11.3 DSP ALU STATUS BITS (dsPIC30F AND dsPIC33F DEVICES)

The high byte of the STATUS Register (SRH) is used by the DSP class of instructions, and it ismodified when data passes through one of the adders. The SRH provides status informationabout overflow and saturation for both accumulators. The Saturate A, Saturate B, Overflow A andOverflow B (SA, SB, OA, OB) bits provide individual accumulator status, while the Saturate ABand Overflow AB (SAB, OAB) bits provide combined accumulator status. The SAB and OAB bitsprovide the software developer efficiency in checking the register for saturation or overflow.

The OA and OB bits are used to indicate when an operation has generated an overflow into theguard bits (bits 32 through 39) of the respective accumulator. This condition can only occur whenthe processor is in Super Saturation mode, or if saturation is disabled. It indicates that theoperation has generated a number which cannot be represented with the lower 31 bits of theaccumulator.

The SA and SB bits are used to indicate when an operation has generated an overflow out of theMost Significant bit of the respective accumulator. The SA and SB bits are active, regardless ofthe Saturation mode (Disabled, Normal or Super) and may be considered “sticky”. Namely, oncethe SA or SB is set to ‘1’, it can only be cleared manually by software, regardless of subsequentDSP operations. When required, it is recommended that the bits be cleared with the BCLRinstruction.

For convenience, the OA and OB bits are logically ORed together to form the OAB flag, and theSA and SB bits are logically ORed to form the SAB flag. These cumulative status bits provideefficient overflow and saturation checking when an algorithm is implemented, which utilizes bothaccumulators. Instead of interrogating the OA and the OB bits independently for arithmeticoverflows, a single check of OAB may be performed. Likewise, when checking for saturation,SAB may be examined instead of checking both the SA and SB bits. Note that clearing the SABflag will clear both the SA and SB bits.

Note 1: All MCU bits are shadowed during execution of the PUSH.S instruction and they arerestored on execution of the POP.S instruction.

2: All MCU bits, except the DC flag (which is not in the SRL), are stacked duringexception processing (see 4.7.1 “Software Stack Pointer”).



mer’s

Model

2

2.5.11.4 INTERRUPT PRIORITY LEVEL STATUS BITS

The three Interrupt Priority Level (IPL) bits of the SRL, SR<7:5>, and the IPL3 bit, CORCON<3>,set the CPU’s IPL which is used for exception processing. Exceptions consist of interrupts andhardware traps. Interrupts have a user-defined priority level between 0 and 7, while traps have afixed priority level between 8 and 15. The fourth Interrupt Priority Level bit, IPL3, is a special IPLbit that may only be read or cleared by the user. This bit is only set when a hardware trap isactivated and it is cleared after the trap is serviced.

The CPU’s IPL identifies the lowest level exception which may interrupt the processor. Theinterrupt level of a pending exception must always be greater than the CPU’s IPL for the CPU toprocess the exception. This means that if the IPL is 0, all exceptions at priority Level 1 and abovemay interrupt the processor. If the IPL is 7, only hardware traps may interrupt the processor.

When an exception is serviced, the IPL is automatically set to the priority level of the exceptionbeing serviced, which will disable all exceptions of equal and lower priority. However, since theIPL field is read/write, one may modify the lower three bits of the IPL in an Interrupt ServiceRoutine to control which exceptions may preempt the exception processing. Since the SRL isstacked during exception processing, the original IPL is always restored after the exception isserviced. If required, one may also prevent exceptions from nesting by setting the NSTDIS bit,INTCON1<15>.

2.5.12 Core Control Register For all MCU and DSC devices, the 16-bit CPU Core Control (CORCON) register, is used to setthe configuration of the CPU. This register provides the ability to map program space into dataspace.

In addition to setting CPU modes, the CORCON register contains status information about theIPL<3> status bit, which indicates if a trap exception is being processed.

Depending on the MCU and DSC family, the following CORCON register descriptions areprovided:

• Register 2-3 for PIC24F and PIC24H devices• Register 2-4 for dsPIC30F and dsPIC33F devices

2.5.12.1 dsPIC30F AND dsPIC33F SPECIFIC BITS

In addition to setting CPU modes, the following features are available through the CORCONregister:

• Set the ACCA and ACCB saturation enable• Set the Data Space Write Saturation mode• Set the Accumulator Saturation and Rounding modes• Set the Multiplier mode for DSP operations• Terminate DO loops prematurely• Provide status information about the DO loop nesting level (DL<2:0>)

Note: Refer to the specific device family reference manual for complete details onexception processing.



2.5.13 Shadow RegistersA shadow register is used as a temporary holding register and can transfer its contents to or fromthe associated host register upon some event. Some of the registers in the programmer’s modelhave a shadow register, which is utilized during the execution of a DO, POP.S, or PUSH.Sinstruction. Shadow register usage is shown in Table 2-2.

For dsPIC30F and dsPIC33F devices, since the DCOUNT, DOSTART and DOEND registers areshadowed, the ability to nest DO loops without additional overhead is provided. Since all shadowregisters are one register deep, up to one level of DO loop nesting is possible. Further nesting ofDO loops is possible in software, with support provided by the DO Loop Nesting Level Status bits(CORCON<10:8>) in the CORCON register.

Note: The DO instruction is only available in dsPIC30F and dsPIC33F devices.

Table 2-2: Automatic Shadow Register Usage

Location DO(1) POP.S/PUSH.S

DCOUNT(1) Yes —

DOSTART(1) Yes —

DOEND(1) Yes —

STATUS Register – DC, N, OV, Z and C bits — YesW0-W3 — YesNote 1: The DO shadow registers are only available in dsPIC30F and dsPIC33F devices.

Note: All shadow registers are one register deep and are not directly accessible.Additional shadowing may be performed in software using the software stack.



mer’s

Model

2

Register 2-1: SR: CPU Status Register (PIC24H and PIC24F Devices)U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0— — — — — — — DC

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0IPL<2:0>(1,2) RA N OV Z C

bit 7 bit 0

Legend: U = Unimplemented bit, read as ‘0’R = Readable bit W = Writable bit C = Clearable bit-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-9 Unimplemented: Read as ‘0’bit 8 DC: MCU ALU Half Carry/Borrow bit

1 = A carry-out from the 4th low order bit (for byte-sized data) or 8th low order bit (for word-sized dataof the result occurred

0 = No carry-out from the 4th low order bit (for byte-sized data) or 8th low order bit (for word-sized dataof the result occurred

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(1,2)

111 = CPU Interrupt Priority Level is 7 (15). User interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14)101 = CPU Interrupt Priority Level is 5 (13)100 = CPU Interrupt Priority Level is 4 (12)011 = CPU Interrupt Priority Level is 3 (11)010 = CPU Interrupt Priority Level is 2 (10)001 = CPU Interrupt Priority Level is 1 (9)000 = CPU Interrupt Priority Level is 0 (8)

bit 4 RA: REPEAT Loop Active bit1 = REPEAT loop in progress0 = REPEAT loop not in progress

bit 3 N: MCU ALU Negative bit1 = Result was negative0 = Result was non-negative (zero or positive)

bit 2 OV: MCU ALU Overflow bitThis bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude thatcauses the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation)0 = No overflow occurred

bit 1 Z: MCU ALU Zero bit1 = An operation that affects the Z bit has set it at some time in the past0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)

bit 0 C: MCU ALU Carry/Borrow bit1 = A carry-out from the Most Significant bit of the result occurred0 = No carry-out from the Most Significant bit of the result occurred

Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt PriorityLevel. The value in parentheses indicates the IPL, if IPL<3> = 1. User interrupts are disabled whenIPL<3> = 1.

2: The IPL<2:0> status bits are read only when NSTDIS = 1 (INTCON1<15>).



Register 2-2: SR: CPU STATUS Register (dsPIC30F and dsPIC33F Devices)R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R-0 R/W-0OA OB SA(1,2) SB(1,2) OAB SAB(1,2,3) DA(4) DC

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0IPL<2:0>(5) RA N OV Z(6) C

bit 7 bit 0

Legend:R = Readable bit W = Writable bit C = Clearable bit-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 OA: Accumulator A Overflow bit 1 = Accumulator A overflowed0 = Accumulator A has not overflowed

bit 14 OB: Accumulator B Overflow bit1 = Accumulator B overflowed0 = Accumulator B has not overflowed

bit 13 SA: Accumulator A Saturation bit(1,2)

1 = Accumulator A is saturated or has been saturated at some time0 = Accumulator A is not saturated

bit 12 SB: Accumulator B Saturation bit(1,2)

1 = Accumulator B is saturated or has been saturated at some time0 = Accumulator B is not saturated

bit 11 OAB: OA || OB Combined Accumulator Overflow bit1 = Accumulators A or B have overflowed0 = Neither Accumulators A or B have overflowed

bit 10 SAB: SA || SB Combined Accumulator bit(1,2,3)

1 = Accumulators A or B are saturated or have been saturated at some time in the past0 = Neither Accumulators A or B are saturated

bit 9 DA: DO Loop Active bit(4)

1 = DO loop in progress0 = DO loop not in progress

bit 8 DC: MCU ALU Half Carry bit1 = A carry-out from the Most Significant bit of the lower nibble occurred0 = No carry-out from the Most Significant bit of the lower nibble occurred

Note 1: This bit may be read or cleared, but not set.

2: Once this bit is set, it must be cleared manually by software.

3: Clearing this bit will clear SA and SB.

4: This bit is read-only.

5: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt PriorityLevel. The value in parentheses indicates the IPL, if IPL<3> = 1.

6: Refer to 4.9 “Z Status Bit” for operation with the ADDC, CPB, SUBB and SUBBR instructions.



mer’s

Model

2

bit 7-5 IPL<2:0>: Interrupt Priority Level bits(5)

111 = CPU Interrupt Priority Level is 7 (15). User interrupts disabled110 = CPU Interrupt Priority Level is 6 (14)101 = CPU Interrupt Priority Level is 5 (13)100 = CPU Interrupt Priority Level is 4 (12)011 = CPU Interrupt Priority Level is 3 (11)010 = CPU Interrupt Priority Level is 2 (10)001 = CPU Interrupt Priority Level is 1 (9)000 = CPU Interrupt Priority Level is 0 (8)

bit 4 RA: REPEAT Loop Active bit1 = REPEAT loop in progress0 = REPEAT loop not in progress

bit 3 N: MCU ALU Negative bit1 = The result of the operation was negative0 = The result of the operation was not negative

bit 2 OV: MCU ALU Overflow bit1 = Overflow occurred0 = No overflow occurred

bit 1 Z: MCU ALU Zero bit(6)

1 = The result of the operation was zero0 = The result of the operation was not zero

bit 0 C: MCU ALU Carry/Borrow bit1 = A carry-out from the Most Significant bit occurred0 = No carry-out from the Most Significant bit occurred

Register 2-2: SR: CPU STATUS Register (dsPIC30F and dsPIC33F Devices) (Continued)


2: Once this bit is set, it must be cleared manually by software.

3: Clearing this bit will clear SA and SB.

4: This bit is read-only.

5: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt PriorityLevel. The value in parentheses indicates the IPL, if IPL<3> = 1.

6: Refer to 4.9 “Z Status Bit” for operation with the ADDC, CPB, SUBB and SUBBR instructions.



Register 2-3: CORCON: Core Control Register (PIC24F and PIC24H Devices)U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0— — — — IPL3(1,2) PSV — —

bit 7 bit 0

Legend: C = Clearable bit R = Readable bit W = Writable bit-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownU = Unimplemented bit, read as ‘0’

bit 15-4 Unimplemented: Read as ‘0’bit 3 IPL3: Interrupt Priority Level 3 Status bit(1,2)

1 = CPU Interrupt Priority Level is 8 or greater (trap exception activated)0 = CPU Interrupt Priority Level is 7 or less (no trap exception activated)

bit 2 PSV: Program Space Visibility in Data Space Enable bit1 = Program space visible in data space0 = Program space not visible in data space

bit 1-0 Unimplemented: Do not use


2: This bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.



mer’s

Model

2

Register 2-4: CORCON: Core Control Register (dsPIC30F and dsPIC33F Devices)U U U R/W-0 R(0)/W-0 R-0 R-0 R/W-0— — — US EDT(1) DL<2:0>(2,3)

bit 15 bit 8

R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0SATA SATB SATDW ACCSAT IPL3(4,5) PSV RND IF

bit 7 bit 0

Legend: C = Clearable bit R = Readable bit W = Writable bit-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownU = Unimplemented bit, read as ‘0’

bit 15-13 Unimplemented: Do not usebit 12 US: Unsigned or Signed Multiplier Mode Select bit

1 = Unsigned mode enabled for DSP multiply operations0 = Signed mode enabled for DSP multiply operations

bit 11 EDT: Early DO Loop Termination Control bit(1)

1 = Terminate executing DO loop at end of current iteration0 = No effect

bit 10-8 DL<2:0>: DO Loop Nesting Level Status bits(2,3)

111 = DO looping is nested at 7 levels110 = DO looping is nested at 6 levels110 = DO looping is nested at 5 levels110 = DO looping is nested at 4 levels011 = DO looping is nested at 3 levels010 = DO looping is nested at 2 levels001 = DO looping is active, but not nested (just 1 level)000 = DO looping is not active

bit 7 SATA: ACCA Saturation Enable bit1 = Accumulator A saturation enabled0 = Accumulator A saturation disabled

bit 6 SATB: ACCB Saturation Enable bit1 = Accumulator B saturation enabled0 = Accumulator B saturation disabled

bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit1 = Data space write saturation enabled0 = Data space write saturation disabled

bit 4 ACCSAT: Accumulator Saturation Mode Select bit1 = 9.31 saturation (Super Saturation)0 = 1.31 saturation (Normal Saturation)

bit 3 IPL3: Interrupt Priority Level 3 Status bit(4,5)

1 = CPU Interrupt Priority Level is 8 or greater (trap exception activated)0 = CPU Interrupt Priority Level is 7 or less (no trap exception activated)

Note 1: This bit will always read ‘0’.

2: DL<2:1> are read-only.

3: The first two levels of DO loop nesting are handled by hardware.

4: This bit may be read or cleared, but not set.




bit 2 PSV: Program Space Visibility in Data Space Enable bit1 = Program space visible in data space0 = Program space not visible in data space

bit 1 RND: Rounding Mode Select bit1 = Biased (conventional) rounding enabled0 = Unbiased (convergent) rounding enabled

bit 0 IF: Integer or Fractional Multiplier Mode Select bit1 = Integer mode enabled for DSP multiply operations0 = Fractional mode enabled for DSP multiply operations

Register 2-4: CORCON: Core Control Register (dsPIC30F and dsPIC33F Devices) (Continued)

Note 1: This bit will always read ‘0’.

2: DL<2:1> are read-only.

3: The first two levels of DO loop nesting are handled by hardware.

4: This bit may be read or cleared, but not set.



Section 3. Instruction Set Overview

Instruction Set O

verview

3

HIGHLIGHTSThis section of the manual contains the following major topics:

3.1 Introduction ..................................................................................................................... 303.2 Instruction Set Overview ................................................................................................. 303.3 Instruction Set Summary Tables ..................................................................................... 32



3.1 INTRODUCTION The 16-bit MCU and DSC instruction set provides a broad suite of instructions, which supportstraditional microcontroller applications and a class of instructions, which supports math intensiveapplications. Since almost all of the functionality of the PIC® MCU instruction set has beenmaintained, this hybrid instruction set allows a friendly DSP migration path for users alreadyfamiliar with the PIC microcontroller.

3.2 INSTRUCTION SET OVERVIEWDepending on the device family, the 16-bit MCU and DSC instruction set contains up to 83instructions, which can be grouped into the functional categories shown in Table 3-1. Table 1-2defines the symbols used in the instruction summary tables, Table 3-2 through Table 3-11. Thesetables define the syntax, description, storage and execution requirements for each instruction.Storage requirements are represented in 24-bit instruction words and execution requirementsare represented in instruction cycles.

Table 3-1: Instruction Groups

Most instructions have several different Addressing modes and execution flows, which requiredifferent instruction variants. For instance, depending on the device family, there are up to sixunique ADD instructions and each instruction variant has its own instruction encoding. Instructionformat descriptions and specific instruction operation are provided in Section 5. “InstructionDescriptions”. Additionally, a composite alphabetized instruction set table is provided inSection 6. “Reference”.

Functional Group Summary Table Page Number

Move Instructions Table 3-2 3-32Math Instructions Table 3-3 3-32Logic Instructions Table 3-4 3-34Rotate/Shift Instructions Table 3-5 3-35Bit Instructions Table 3-6 3-36Compare/Skip Instructions Table 3-7 3-37Program Flow Instructions Table 3-8 3-38Shadow/Stack Instructions Table 3-9 3-39Control Instructions Table 3-10 3-39DSP Instructions(1) Table 3-11 3-39Note 1: DSP instructions are only available in the dsPIC30F and dsPIC33F device families.


Section 3. Instruction Set OverviewInstruction Set

Overview

3

3.2.1 Multi-Cycle InstructionsAs the instruction summary tables show, most instructions execute in a single cycle, with thefollowing exceptions:

• Instructions DO, MOV.D, POP.D, PUSH.D, TBLRDH, TBLRDL, TBLWTH and TBLWTL require 2 cycles to execute.

• Instructions DIV.S, DIV.U and DIVF are single-cycle instructions, which should be exe-cuted 18 consecutive times as the target of a REPEAT instruction.

• Instructions that change the program counter also require 2 cycles to execute, with the extra cycle executed as a NOP. SKIP instruction, which skips over a 2-word instruction, requires 3 instruction cycles to execute, with 2 cycles executed as a NOP.

• The RETFIE, RETLW and RETURN are a special case of an instruction that changes the program counter. These execute in 3 cycles, unless an exception is pending and then they execute in 2 cycles.

3.2.2 Multi-Word InstructionsAs defined by Table 3-2: “Move Instructions”, almost all instructions consume one instructionword (24 bits), with the exception of the CALL, DO and GOTO instructions, which are ProgramFlow Instructions, listed in Table 3-8. These instructions require two words of memory becausetheir opcodes embed large literal operands.

Note: The DO and DIVF instructions are only available in the dsPIC30F and dsPIC33Fdevice families.

Note: Instructions that access program memory as data, using Program Space Visibility(PSV), will incur a one or two cycle delay for all 16-bit MCU and DSC devices. Whenthe target instruction of a REPEAT loop accesses program memory as data, only thefirst execution of the target instruction is subject to the delay. See the specific devicefamily reference manual for details.



3.3 INSTRUCTION SET SUMMARY TABLES

Table 3-2: Move Instructions

Assembly Syntax Description Words Cycles Page Number

EXCH Wns,Wnd Swap Wns and Wnd 1 1 5-203

MOV f {,WREG}(1) Move f to destination 1 1 5-233

MOV WREG,f Move WREG to f 1 1 5-234MOV f,Wnd Move f to Wnd 1 1 5-235MOV Wns,f Move Wns to f 1 1 5-236MOV.B #lit8,Wnd Move 8-bit literal to Wnd 1 1 5-237MOV #lit16,Wnd Move 16-bit literal to Wnd 1 1 5-238MOV [Ws+Slit10],Wnd Move [Ws + signed 10-bit offset] to Wnd 1 1 5-239MOV Wns,[Wd+Slit10] Move Wns to [Wd + signed 10-bit offset] 1 1 5-240MOV Ws,Wd Move Ws to Wd 1 1 5-241MOV.D Ws,Wnd Move double Ws to Wnd:Wnd + 1 1 2 5-243MOV.D Wns,Wd Move double Wns:Wns + 1 to Wd 1 2 5-243SWAP Wn Wn = byte or nibble swap Wn 1 1 5-340TBLRDH Ws,Wd Read high program word to Wd 1 2 5-341TBLRDL Ws,Wd Read low program word to Wd 1 2 5-343TBLWTH Ws,Wd Write Ws to high program word 1 2 5-345TBLWTL Ws,Wd Write Ws to low program word 1 2 5-347

Note 1: When the optional {,WREG} operand is specified, the destination of the instruction is WREG. When{,WREG} is not specified, the destination of the instruction is the file register f.

Table 3-3: Math Instructions


ADD f {,WREG}(1) Destination = f + WREG 1 1 5-89

ADD #lit10,Wn Wn = lit10 + Wn 1 1 5-90ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 5-91ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 5-93ADDC f {,WREG}(1) Destination = f + WREG + (C) 1 1 5-98ADDC #lit10,Wn Wn = lit10 + Wn + (C) 1 1 5-99ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 5-100ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 5-102DAW.B Wn Wn = decimal adjust Wn 1 1 5-183DEC f {,WREG}(1) Destination = f – 1 1 1 5-184DEC Ws,Wd Wd = Ws – 1 1 1 5-185DEC2 f {,WREG}(1) Destination = f – 2 1 1 5-186DEC2 Ws,Wd Wd = Ws – 2 1 1 5-187DIV.S Wm, Wn Signed 16/16-bit integer divide 1 18(2) 5-189DIV.SD Wm, Wn Signed 32/16-bit integer divide 1 18(2) 5-189DIV.U Wm, Wn Unsigned 16/16-bit integer divide 1 18(2) 5-191


2: The divide instructions must be preceded with a “REPEAT #17” instruction, such that they are executed18 consecutive times.



Overview

3

DIV.UD Wm, Wn Unsigned 32/16-bit integer divide 1 18(2) 5-191DIVF Wm, Wn Signed 16/16-bit fractional divide 1 18(2) 5-193INC f {,WREG}(1) Destination = f + 1 1 1 5-212INC Ws,Wd Wd = Ws + 1 1 1 5-213INC2 f {,WREG}(1) Destination = f + 2 1 1 5-214INC2 Ws,Wd Wd = Ws + 2 1 1 5-215MUL f W3:W2 = f * WREG 1 1 5-255MUL.SS Wb,Ws,Wnd {Wnd + 1,Wnd} = signed(Wb) * signed(Ws) 1 1 5-256MUL.SU Wb,#lit5,Wnd {Wnd + 1,Wnd} = signed(Wb) * unsigned(lit5) 1 1 5-258MUL.SU Wb,Ws,Wnd {Wnd + 1,Wnd} = signed(Wb) * unsigned(Ws) 1 1 5-260MUL.SU Wb,#lit5,Wnd {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) 1 1 5-260MUL.US Wb,Ws,Wnd {Wnd + 1,Wnd} = unsigned(Wb) * signed(Ws) 1 1 5-262MUL.UU Wb,Ws,Wnd {Wnd + 1,Wnd} = unsigned(Wb) * unsigned(Ws) 1 1 5-265MUL.UU Wb,#lit5,Wnd {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(lit5) 1 1 5-264SE Ws,Wnd Wnd = signed-extended Ws 1 1 5-309SUB f {,WREG}(1) Destination = f – WREG 1 1 5-319SUB #lit10,Wn Wn = Wn – lit10 1 1 5-320SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 5-321SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 5-322

SUBB f {,WREG}(1) Destination = f – WREG – (C) 1 1 5-325

SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 5-326

SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 5-329

SUBBR f {,WREG}(1) Destination = WREG – f – (C) 1 1 5-331

SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 5-332

SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 5-334SUBR f {,WREG}(1) Destination = WREG – f 1 1 5-336SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 5-337SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 5-338ZE Ws,Wnd Wnd = zero-extended Ws 1 1 5-355

Table 3-3: Math Instructions (Continued)



2: The divide instructions must be preceded with a “REPEAT #17” instruction, such that they are executed18 consecutive times.



Table 3-4: Logic Instructions


AND f {,WREG}(1) Destination = f .AND. WREG 1 1 5-104AND #lit10,Wn Wn = lit10 .AND. Wn 1 1 5-105AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 5-106AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 5-107CLR f f = 0x0000 1 1 5-163CLR WREG WREG = 0x0000 1 1 5-163CLR Wd Wd = 0x0000 1 1 5-164COM f {,WREG}(1) Destination = f 1 1 5-168COM Ws,Wd Wd = Ws 1 1 5-169IOR f {,WREG}(1) Destination = f .IOR. WREG 1 1 5-216IOR #lit10,Wn Wn = lit10 .IOR. Wn 1 1 5-217IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 5-218IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 5-219NEG f {,WREG}(1) Destination = f + 1 1 1 5-267NEG Ws,Wd Wd = Ws + 1 1 1 5-268SETM f f = 0xFFFF 1 1 5-310SETM WREG WREG = 0xFFFF 1 1 5-310SETM Wd Wd = 0xFFFF 1 1 5-311XOR f {,WREG}(1) Destination = f .XOR. WREG 1 1 5-350XOR #lit10,Wn Wn = lit10 .XOR. Wn 1 1 5-351XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 5-352XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 5-353




Overview

3

Table 3-5: Rotate/Shift Instructions

Assembly Syntax Description Words Cycles Page #

ASR f {,WREG}(1) Destination = arithmetic right shift f 1 1 5-109ASR Ws,Wd Wd = arithmetic right shift Ws 1 1 5-111ASR Wb,#lit4,Wnd Wnd = arithmetic right shift Wb by lit4 1 1 5-113ASR Wb,Wns,Wnd Wnd = arithmetic right shift Wb by Wns 1 1 5-114LSR f {,WREG}(1) Destination = logical right shift f 1 1 5-224LSR Ws,Wd Wd = logical right shift Ws 1 1 5-225LSR Wb,#lit4,Wnd Wnd = logical right shift Wb by lit4 1 1 5-227LSR Wb,Wns,Wnd Wnd = logical right shift Wb by Wns 1 1 5-228RLC f {,WREG}(1) Destination = rotate left through Carry f 1 1 5-293RLC Ws,Wd Wd = rotate left through Carry Ws 1 1 5-294RLNC f {,WREG}(1) Destination = rotate left (no Carry) f 1 1 5-296RLNC Ws,Wd Wd = rotate left (no Carry) Ws 1 1 5-297RRC f {,WREG}(1) Destination = rotate right through Carry f 1 1 5-299RRC Ws,Wd Wd = rotate right through Carry Ws 1 1 5-300RRNC f {,WREG}(1) Destination = rotate right (no Carry) f 1 1 5-302RRNC Ws,Wd Wd = rotate right (no Carry) Ws 1 1 5-303SL f {,WREG}(1) Destination = left shift f 1 1 5-314SL Ws,Wd Wd = left shift Ws 1 1 5-315SL Wb,#lit4,Wnd Wnd = left shift Wb by lit4 1 1 5-317SL Wb,Wns,Wnd Wnd = left shift Wb by Wns 1 1 5-318




Table 3-6: Bit Instructions


BCLR f,#bit4 Bit clear f 1 1 5-115BCLR Ws,#bit4 Bit clear Ws 1 1 5-116BSET f,#bit4 Bit set f 1 1 5-140BSET Ws,#bit4 Bit set Ws 1 1 5-141BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 5-142BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 5-142BTG f,#bit4 Bit toggle f 1 1 5-144BTG Ws,#bit4 Bit toggle Ws 1 1 5-145BTST f,#bit4 Bit test f 1 1 5-153BTST.C Ws,#bit4 Bit test Ws to C 1 1 5-154BTST.Z Ws,#bit4 Bit test Ws to Z 1 1 5-154BTST.C Ws,Wb Bit test Ws<Wb> to C 1 1 5-155BTST.Z Ws,Wb Bit test Ws<Wb> to Z 1 1 5-155 BTSTS f,#bit4 Bit test f then set f 1 1 5-157BTSTS.C Ws,#bit4 Bit test Ws to C then set Ws 1 1 5-158BTSTS.Z Ws,#bit4 Bit test Ws to Z then set Ws 1 1 5-158FBCL Ws,Wnd Find bit change from left (MSb) side 1 1 5-204FF1L Ws,Wnd Find first one from left (MSb) side 1 1 5-206FF1R Ws,Wnd Find first one from right (LSb) side 1 1 5-208



Overview

3

Table 3-7: Compare/Skip Instructions

Assembly Syntax Description Words Cycles(1) Page Number

BTSC f,#bit4 Bit test f, skip if clear 1 1 (2 or 3) 5-146BTSC Ws,#bit4 Bit test Ws, skip if clear 1 1 (2 or 3) 5-148BTSS f,#bit4 Bit test f, skip if set 1 1 (2 or 3) 5-150BTSS Ws,#bit4 Bit test Ws, skip if set 1 1 (2 or 3) 5-151CP f Compare (f – WREG) 1 1 5-170CP Wb,#lit5 Compare (Wb – lit5) 1 1 5-171CP Wb,Ws Compare (Wb – Ws) 1 1 5-172CP0 f Compare (f – 0x0000) 1 1 5-173CP0 Ws Compare (Ws – 0x0000) 1 1 5-174

CPB f Compare with Borrow (f – WREG – C) 1 1 5-175

CPB Wb,#lit5 Compare with Borrow (Wb – lit5 – C) 1 1 5-176

CPB Wb,Ws Compare with Borrow (Wb – Ws – C) 1 1 5-177CPSEQ Wb, Wn Compare (Wb – Wn), skip if = 1 1 (2 or 3) 5-179CPSGT Wb, Wn Compare (Wb – Wn), skip if > 1 1 (2 or 3) 5-180CPSLT Wb, Wn Compare (Wb – Wn), skip if < 1 1 (2 or 3) 5-181CPSNE Wb, Wn Compare (Wb – Wn), skip if ≠ 1 1 (2 or 3) 5-182

Note 1: Conditional skip instructions execute in 1 cycle if the skip is not taken, 2 cycles if the skip is taken over aone-word instruction and 3 cycles if the skip is taken over a two-word instruction.



Table 3-8: Program Flow Instructions


BRA Expr Branch unconditionally 1 2 5-117BRA Wn Computed branch 1 2 5-118BRA C,Expr Branch if Carry (no Borrow) 1 1 (2)(1) 5-119BRA GE,Expr Branch if greater than or equal 1 1 (2)(1) 5-121BRA GEU,Expr Branch if unsigned greater than or equal 1 1 (2)(1) 5-122BRA GT,Expr Branch if greater than 1 1 (2)(1) 5-123BRA GTU,Expr Branch if unsigned greater than 1 1 (2)(1) 5-124BRA LE,Expr Branch if less than or equal 1 1 (2)(1) 5-125BRA LEU,Expr Branch if unsigned less than or equal 1 1 (2)(1) 5-126BRA LT,Expr Branch if less than 1 1 (2)(1) 5-127BRA LTU,Expr Branch if unsigned less than 1 1 (2)(1) 5-128BRA N,Expr Branch if Negative 1 1 (2)(1) 5-129BRA NC,Expr Branch if not Carry (Borrow) 1 1 (2)(1) 5-130BRA NN,Expr Branch if not Negative 1 1 (2)(1) 5-131BRA NOV,Expr Branch if not Overflow 1 1 (2)(1) 5-132BRA NZ,Expr Branch if not Zero 1 1 (2)(1) 5-133BRA OA,Expr Branch if Accumulator A Overflow 1 1 (2)(1) 5-134BRA OB,Expr Branch if Accumulator B Overflow 1 1 (2)(1) 5-135BRA OV,Expr Branch if Overflow 1 1 (2)(1) 5-136BRA SA,Expr Branch if Accumulator A Saturate 1 1 (2)(1) 5-137BRA SB,Expr Branch if Accumulator B Saturate 1 1 (2)(1) 5-138BRA Z,Expr Branch if Zero 1 1 (2)(1) 5-139CALL Expr Call subroutine 2 2 5-159CALL Wn Call indirect subroutine 1 2 5-161DO #lit14,Expr(3) Do code through PC + Expr, (lit14 + 1) times 2 2 5-195DO Wn,Expr(3) Do code through PC + Expr, (Wn + 1) times 2 2 5-197GOTO Expr Go to address 2 2 5-210GOTO Wn Go to address indirectly 1 2 5-211RCALL Expr Relative call 1 2 5-281RCALL Wn Computed call 1 2 5-283REPEAT #lit14 Repeat next instruction (lit14 + 1) times 1 1 5-285REPEAT Wn Repeat next instruction (Wn + 1) times 1 1 5-286RETFIE Return from interrupt enable 1 3 (2)(2) 5-290RETLW #lit10,Wn Return with lit10 in Wn 1 3 (2)(2) 5-291RETURN Return from subroutine 1 3 (2)(2) 5-292

Note 1: Conditional branch instructions execute in 1 cycle if the branch is not taken, or 2 cycles if the branch istaken.

2: RETURN instructions execute in 3 cycles, but if an exception is pending, they execute in 2 cycles.

3: This instruction is only available in dsPIC30F and dsPIC33F devices.



Overview

3

Table 3-9: Shadow/Stack Instructions

Table 3-10: Control Instructions

Table 3-11: DSP Instructions (dsPIC30F and dsPIC33F Devices)


LNK #lit14 Link Frame Pointer 1 1 5-223POP f POP TOS to f 1 1 5-272POP Wd POP TOS to Wd 1 1 5-273POP.D Wnd Double POP from TOS to Wnd:Wnd + 1 1 2 5-274POP.S POP shadow registers 1 1 5-275PUSH f PUSH f to TOS 1 1 5-276PUSH Ws PUSH Ws to TOS 1 1 5-277PUSH.D Wns PUSH double Wns:Wns + 1 to TOS 1 2 5-278PUSH.S PUSH shadow registers 1 1 5-279ULNK Unlink Frame Pointer 1 1 5-349


CLRWDT Clear Watchdog Timer 1 1 5-167DISI #lit14 Disable interrupts for (lit14 + 1) instruction cycles 1 1 5-188NOP No operation 1 1 5-270NOPR No operation 1 1 5-271PWRSAV #lit1 Enter Power-saving mode lit1 1 1 5-280RESET Software device Reset 1 1 5-288


ADD Acc Add accumulators 1 1 5-95ADD Ws,#Slit4,Acc 16-bit signed add to Acc 1 1 5-96CLR Acc,Wx,Wxd,Wy,Wyd,AWB Clear Acc 1 1 5-165ED Wm*Wm,Acc,Wx,Wy,Wxd Euclidean distance

(no accumulate)1 1 5-199

EDAC Wm*Wm,Acc,Wx,Wy,Wxd Euclidean distance 1 1 5-201LAC Ws,#Slit4,Acc Load Acc 1 1 5-221MAC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB Multiply and accumulate 1 1 5-229MAC Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and accumulate 1 1 5-231MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB Move Wx to Wxd and Wy to Wyd 1 1 5-245MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wn by Wm to Acc 1 1 5-247MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square to Acc 1 1 5-249MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd -(Multiply Wn by Wm) to Acc 1 1 5-251MSC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB Multiply and subtract from Acc 1 1 5-253NEG Acc Negate Acc 1 1 5-269SAC Acc,#Slit4,Wd Store Acc 1 1 5-305SAC.R Acc,#Slit4,Wd Store rounded Acc 1 1 5-307SFTAC Acc,#Slit6 Arithmetic shift Acc by Slit6 1 1 5-312SFTAC Acc,Wn Arithmetic shift Acc by (Wn) 1 1 5-313SUB Acc Subtract accumulators 1 1 5-324



NOTES:


Section 4. Instruction Set Details

Instruction Set D

etails

4


4.1 Data Addressing Modes.................................................................................................. 424.2 Program Addressing Modes ........................................................................................... 514.3 Instruction Stalls.............................................................................................................. 524.4 Byte Operations .............................................................................................................. 544.5 Word Move Operations ................................................................................................... 564.6 Using 10-bit Literal Operands ......................................................................................... 594.7 Software Stack Pointer and Frame Pointer ..................................................................... 604.8 Conditional Branch Instructions ...................................................................................... 654.9 Z Status Bit...................................................................................................................... 664.10 Assigned Working Register Usage ................................................................................. 674.11 DSP Data Formats (dsPIC30F and dsPIC33F Devices)................................................. 704.12 Accumulator Usage (dsPIC30F and dsPIC33F Devices) ............................................... 724.13 Accumulator Access (dsPIC30F and dsPIC33F Devices) .............................................. 734.14 DSP MAC Instructions (dsPIC30F and dsPIC33F Devices) ........................................... 744.15 DSP Accumulator Instructions (dsPIC30F and dsPIC33F Devices) ............................... 784.16 Scaling Data with the FBCL Instruction (dsPIC30F and dsPIC33F Devices) ................. 794.17 Normalizing the Accumulator with the FBCL Instruction (dsPIC30F and dsPIC33F

Devices) .......................................................................................................................... 81



4.1 DATA ADDRESSING MODESThe 16-bit MCU and DSC devices support three native Addressing modes for accessing datamemory, along with several forms of immediate addressing. Data accesses may be performedusing file register, register direct or register indirect addressing, and immediate addressingallows a fixed value to be used by the instruction.

File register addressing provides the ability to operate on data stored in the lower 8K of datamemory (Near RAM), and also move data between the working registers and the entire 64K dataspace. Register direct addressing is used to access the 16 memory mapped working registers,W0:W15. Register indirect addressing is used to efficiently operate on data stored in the entire64K data space, using the contents of the working registers as an effective address. Immediateaddressing does not access data memory, but provides the ability to use a constant value as aninstruction operand. The address range of each mode is summarized in Table 4-1.

Table 4-1: 16-Bit MCU and DSC Addressing Modes

4.1.1 File Register Addressing

File register addressing is used by instructions which use a predetermined data address as anoperand for the instruction. The majority of instructions that support file register addressingprovide access to the lower 8 Kbytes of data memory, which is called the Near RAM. However,the MOV instruction provides access to all 64 Kbytes of memory using file register addressing.This allows the loading of the data from any location in data memory to any working register, andstore the contents of any working register to any location in data memory. It should be noted thatfile register addressing supports both byte and word accesses of data memory, with theexception of the MOV instruction, which accesses all 64K of memory as words. Examples of fileregister addressing are shown in Example 4-1.

Most instructions, which support file register addressing, perform an operation on the specifiedfile register and the default working register WREG (see 2.4 “Default Working Register(WREG)”). If only one operand is supplied in the instruction, WREG is an implied operand andthe operation results are stored back to the file register. In these cases, the instruction iseffectively a read-modify-write instruction. However, when both the file register and WREG arespecified in the instruction, the operation results are stored in WREG and the contents of the fileregister are unchanged. Sample instructions which show the interaction between the file registerand WREG are shown in Example 4-2.

Addressing Mode Address Range

File Register 0x0000-0x1FFF (see Note)Register Direct 0x0000-0x001F (working register array W0:W15)Register Indirect 0x0000-0xFFFFImmediate N/A (constant value)Note: The address range for the File Register MOV is 0x0000-0xFFFE.

Note: Instructions which support file register addressing use ‘f’ as an operand in theinstruction summary tables of Section 3. “Instruction Set Overview”.


Section 4. Instruction Set DetailsInstruction Set

Details

4

Example 4-1: File Register Addressing

Example 4-2: File Register Addressing and WREG

4.1.2 Register Direct AddressingRegister direct addressing is used to access the contents of the 16 working registers (W0:W15).The Register Direct Addressing mode is fully orthogonal, which allows any working register to bespecified for any instruction that uses register direct addressing, and it supports both byte andword accesses. Instructions which employ register direct addressing use the contents of thespecified working register as data to execute the instruction, therefore this Addressing mode isuseful only when data already resides in the working register core. Sample instructions whichutilize register direct addressing are shown in Example 4-3.

Another feature of register direct addressing is that it provides the ability for dynamic flow control.Since variants of the DO and REPEAT instruction support register direct addressing, flexiblelooping constructs may be generated using these instructions.

DEC 0x1000 ; decrement data stored at 0x1000

Before Instruction:Data Memory 0x1000 = 0x5555

After Instruction:Data Memory 0x1000 = 0x5554

MOV 0x27FE, W0 ; move data stored at 0x27FE to W0

Before Instruction:W0 = 0x5555Data Memory 0x27FE = 0x1234

After Instruction:W0 = 0x1234Data Memory 0x27FE = 0x1234

AND 0x1000 ; AND 0x1000 with WREG, store to 0x1000

Before Instruction:W0 (WREG) = 0x332CData Memory 0x1000 = 0x5555

After Instruction:W0 (WREG) = 0x332CData Memory 0x1000 = 0x1104

AND 0x1000, WREG ; AND 0x1000 with WREG, store to WREG

Before Instruction:W0 (WREG) = 0x332CData Memory 0x1000 = 0x5555

After Instruction:W0 (WREG) = 0x1104Data Memory 0x1000 = 0x5555

Note: Instructions which must use register direct addressing, use the symbols Wb, Wn,Wns and Wnd in the summary tables of Section 3. “Instruction Set Overview”.Commonly, register direct addressing may also be used when register indirectaddressing may be used. Instructions which use register indirect addressing, usethe symbols Wd and Ws in the summary tables of Section 3. “Instruction SetOverview”.



Example 4-3: Register Direct Addressing

4.1.3 Register Indirect AddressingRegister indirect addressing is used to access any location in data memory by treating thecontents of a working register as an Effective Address (EA) to data memory. Essentially, thecontents of the working register become a pointer to the location in data memory which is to beaccessed by the instruction.

This Addressing mode is powerful, because it also allows one to modify the contents of theworking register, either before or after the data access is made, by incrementing or decrementingthe EA. By modifying the EA in the same cycle that an operation is being performed, registerindirect addressing allows for the efficient processing of data that is stored sequentially inmemory. The modes of indirect addressing supported by the 16-bit MCU and DSC devices areshown in Table 4-2.

Table 4-2: Indirect Addressing Modes

EXCH W2, W3 ; Exchange W2 and W3

Before Instruction: W2 = 0x3499 W3 = 0x003D

After Instruction: W2 = 0x003D W3 = 0x3499

IOR #0x44, W0 ; Inclusive-OR 0x44 and W0

Before Instruction: W0 = 0x9C2E

After Instruction: W0 = 0x9C6E

SL W6, W7, W8 ; Shift left W6 by W7, and store to W8

Before Instruction: W6 = 0x000C W7 = 0x0008

W8 = 0x1234

After Instruction: W6 = 0x000C W7 = 0x0008 W8 = 0x0C00

Indirect Mode Syntax Function(Byte Instruction)

Function(Word Instruction) Description

No Modification [Wn] EA = [Wn] EA = [Wn] The contents of Wn forms the EA.Pre-Increment [++Wn] EA = [Wn + = 1] EA = [Wn + = 2] Wn is pre-incremented to form the EA.Pre-Decrement [--Wn] EA = [Wn – = 1] EA = [Wn – = 2] Wn is pre-decremented to form the EA.Post-Increment [Wn++] EA = [Wn]+ = 1 EA = [Wn]+ = 2 The contents of Wn forms the EA, then

Wn is post-incremented.Post-Decrement [Wn--] EA = [Wn] – = 1 EA = [Wn] – = 2 The contents of Wn forms the EA, then

Wn is post-decremented.Register Offset [Wn+Wb] EA = [Wn + Wb] EA = [Wn + Wb] The sum of Wn and Wb forms the EA.

Wn and Wb are not modified.



Details

4

Table 4-2 shows that four Addressing modes modify the EA used in the instruction, and thisallows the following updates to be made to the working register: post-increment, post-decrement,pre-increment and pre-decrement. Since all EAs must be given as byte addresses, support isprovided for Word mode instructions by scaling the EA update by 2. Namely, in Word mode,pre/post-decrements subtract 2 from the EA stored in the working register, andpre/post-increments add 2 to the EA. This feature ensures that after an EA modification is made,the EA will point to the next adjacent word in memory. Example 4-4 shows how indirectaddressing may be used to update the EA.

Table 4-2 also shows that the Register Offset mode addresses data which is offset from a baseEA stored in a working register. This mode uses the contents of a second working register to formthe EA by adding the two specified working registers. This mode does not scale for Word modeinstructions, but offers the complete offset range of 64 Kbytes. Note that neither of the workingregisters used to form the EA are modified. Example 4-5 shows how register offset indirectaddressing may be used to access data memory.

Example 4-4: Indirect Addressing with Effective Address Update

Note: The MOV with offset instructions (see pages 5-239 and 5-240) provides a literaladdressing offset ability to be used with indirect addressing. In these instructions,the EA is formed by adding the contents of a working register to a signed 10-bitliteral. Example 4-6 shows how these instructions may be used to move data to andfrom the working register array.

MOV.B [W0++], [W13--] ; byte move [W0] to [W13]; post-inc W0, post-dec W13

Before Instruction:W0 = 0x2300W13 = 0x2708Data Memory 0x2300 = 0x7783Data Memory 0x2708 = 0x904E

After Instruction:W0 = 0x2301W13 = 0x2707 Data Memory 0x2300 = 0x7783Data Memory 0x2708 = 0x9083

ADD W1, [--W5], [++W8] ; pre-dec W5, pre-inc W8 ; add W1 to [W5], store in [W8]

Before Instruction:W1 = 0x0800W5 = 0x2200W8 = 0x2400Data Memory 0x21FE = 0x7783Data Memory 0x2402 = 0xAACC

After Instruction:W1 = 0x0800W5 = 0x21FEW8 = 0x2402Data Memory 0x21FE = 0x7783Data Memory 0x2402 = 0x7F83



Example 4-5: Indirect Addressing with Register Offset

Example 4-6: Move with Literal Offset Instructions

MOV.B [W0+W1], [W7++] ; byte move [W0+W1] to W7, post-inc W7

Before Instruction:W0 = 0x2300W1 = 0x01FEW7 = 0x1000Data Memory 0x24FE = 0x7783Data Memory 0x1000 = 0x11DC

After Instruction:W0 = 0x2300W1 = 0x01FEW7 = 0x1001Data Memory 0x24FE = 0x7783Data Memory 0x1000 = 0x1183

LAC [W0+W8], A ; load ACCA with [W0+W8]; (sign-extend and zero-backfill)

Before Instruction:W0 = 0x2344W8 = 0x0008ACCA = 0x00 7877 9321Data Memory 0x234C = 0xE290

After Instruction:W0 = 0x2344W8 = 0x0008ACCA = 0xFF E290 0000Data Memory 0x234C = 0xE290

MOV [W0+0x20], W1 ; move [W0+0x20] to W1

Before Instruction:W0 = 0x1200W1 = 0x01FEData Memory 0x1220 = 0xFD27

After Instruction:W0 = 0x1200W1 = 0xFD27Data Memory 0x1220 = 0xFD27

MOV W4, [W8-0x300] ; move W4 to [W8-0x300]

Before Instruction:W4 = 0x3411W8 = 0x2944Data Memory 0x2644 = 0xCB98

After Instruction:W4 = 0x3411W8 = 0x2944Data Memory 0x2644 = 0x3411



Details

4

4.1.3.1 REGISTER INDIRECT ADDRESSING AND THE INSTRUCTION SET

The Addressing modes presented in Table 4-2 demonstrate the Indirect Addressing modecapability of the 16-bit MCU and DSC devices. Due to operation encoding and functionalconsiderations, not every instruction which supports indirect addressing supports all modesshown in Table 4-2. The majority of instructions which use indirect addressing support the NoModify, Pre-Increment, Pre-Decrement, Post-Increment and Post-Decrement Addressingmodes. The MOV instructions, and several accumulator-based DSP instructions (dsPIC30F anddsPIC33F devices only), are also capable of using the Register Offset Addressing mode.

4.1.3.2 DSP MAC INDIRECT ADDRESSING MODES (dsPIC30F AND dsPIC33F DEVICES)

A special class of Indirect Addressing modes is utilized by the DSP MAC instructions. As isdescribed later in 4.14 “DSP MAC Instructions (dsPIC30F and dsPIC33F Devices)”, the DSPMAC class of instructions are capable of performing two fetches from memory using effectiveaddressing. Since DSP algorithms frequently demand a broader range of address updates, theAddressing modes offered by the DSP MAC instructions provide greater range in the size of theeffective address update which may be made. Table 4-3 shows that both X and Y prefetchessupport Post-Increment and Post-Decrement Addressing modes, with updates of 2, 4 and 6bytes. Since DSP instructions only execute in Word mode, no provisions are made for odd sizedEA updates.

Table 4-3: DSP MAC Indirect Addressing Modes

4.1.3.3 MODULO AND BIT-REVERSED ADDRESSING MODES (dsPIC30F AND dsPIC33F DEVICES)

The 16-bit DSC architecture provides support for two special Register Indirect Addressingmodes, which are commonly used to implement DSP algorithms. Modulo (or circular) addressingprovides an automated means to support circular data buffers in X and/or Y memory. Modulobuffers remove the need for software to perform address boundary checks, which can improvethe performance of certain algorithms. Similarly, bit-reversed addressing allows one to accessthe elements of a buffer in a nonlinear fashion. This Addressing mode simplifies data re-orderingfor radix-2 FFT algorithms and provides a significant reduction in FFT processing time.

Both of these Addressing modes are powerful features of the dsPIC30F and dsPIC33Farchitectures, which can be exploited by any instruction that uses indirect addressing. Refer tothe specific device family reference manual for details on using modulo and bit-reversedaddressing.

Note: Instructions which use register indirect addressing use the operand symbols Wdand Ws in the summary tables of Section 3. “Instruction Set Overview”.

Addressing Mode X Memory Y Memory

Indirect with no modification EA = [Wx] EA = [Wy]Indirect with Post-Increment by 2 EA = [Wx] + = 2 EA = [Wy] + = 2Indirect with Post-Increment by 4 EA = [Wx] + = 4 EA = [Wy] + = 4Indirect with Post-Increment by 6 EA = [Wx] + = 6 EA = [Wy] + = 6Indirect with Post-Decrement by 2 EA = [Wx] – = 2 EA = [Wy] – = 2Indirect with Post-Decrement by 4 EA = [Wx] – = 4 EA = [Wy] – = 4Indirect with Post-Decrement by 6 EA = [Wx] – = 6 EA = [Wy] – = 6Indirect with Register Offset EA = [W9 + W12] EA = [W11 + W12]Note: As described in 4.14 “DSP MAC Instructions (dsPIC30F and dsPIC33F

Devices)”, only W8 and W9 may be used to access X Memory, and only W10 andW11 may be used to access Y Memory.



4.1.4 Immediate AddressingIn immediate addressing, the instruction encoding contains a predefined constant operand,which is used by the instruction. This Addressing mode may be used independently, but it is morefrequently combined with the File Register, Direct and Indirect Addressing modes. The size ofthe immediate operand which may be used varies with the instruction type. Constants of size1-bit (#lit1), 4-bit (#bit4, #lit4 and #Slit4), 5-bit (#lit5), 6-bit (#Slit6), 8-bit (#lit8), 10-bit (#lit10and #Slit10), 14-bit (#lit14) and 16-bit (#lit16) may be used. Constants may be signed orunsigned and the symbols #Slit4, #Slit6 and #Slit10 designate a signed constant. All otherimmediate constants are unsigned. Table 4-4 shows the usage of each immediate operand in theinstruction set.

Table 4-4: Immediate Operands in the Instruction Set

The syntax for immediate addressing requires that the number sign (#) must immediatelyprecede the constant operand value. The “#” symbol indicates to the assembler that the quantityis a constant. If an out-of-range constant is used with an instruction, the assembler will generatean error. Several examples of immediate addressing are shown in Example 4-7.

Note: The 6-bit (#Slit6) operand is only available in dsPIC30F and dsPIC33F devices.

Operand Instruction Usage

#lit1 PWRSAV

#bit4 BCLR, BSET, BTG, BTSC, BTSS, BTST, BTST.C, BTST.Z, BTSTS, BTSTS.C, BTSTS.Z

#lit4 ASR, LSR, SL

#Slit4 ADD, LAC, SAC, SAC.R

#lit5 ADD, ADDC, AND, CP, CPB, IOR, MUL.SU, MUL.UU, SUB, SUBB, SUBBR, SUBR, XOR

#Slit6(1) SFTAC

#lit8 MOV.B, CP, CPB

#lit10 ADD, ADDC, AND, CP, CPB, IOR, RETLW, SUB, SUBB, XOR

#Slit10 MOV

#lit14 DISI, DO(1), LNK, REPEAT

#lit16 MOV

Note 1: This operand or instruction is only available in dsPIC30F and dsPIC33F devices.



Details

4

Example 4-7: Immediate Addressing

4.1.5 Data Addressing Mode TreeThe Data Addressing modes of the PIC24F and PIC24H families are summarized in Figure 4-1.

Figure 4-1: Data Addressing Mode Tree (PIC24F and PIC24H)

The Data Addressing modes of the dsPIC30F and dsPIC33F are summarized in Figure 4-2.

PWRSAV #1 ; Enter IDLE mode

ADD.B #0x10, W0 ; Add 0x10 to W0 (byte mode)

Before Instruction:W0 = 0x12A9

After Instruction:W0 = 0x12B9

XOR W0, #1, [W1++] ; Exclusive-OR W0 and 0x1; Store the result to [W1]; Post-increment W1

Before Instruction:W0 = 0xFFFFW1 = 0x0890Data Memory 0x0890 = 0x0032

After Instruction:W0 = 0xFFFFW1 = 0x0892Data Memory 0x0890 = 0xFFFE

Data Addressing Modes

Immediate

File Register

Pre-Increment

Pre-Decrement

Post-Increment

Post-Decrement

Register Offset

Literal Offset

No Modification

Direct

Indirect



Figure 4-2: Data Addressing Mode Tree (dsPIC30F and dsPIC33F)

Data Addressing Modes

Immediate

BasicFile Register

Pre-Increment

Pre-Decrement

Post-Increment

Post-Decrement

Register Offset

Literal Offset

No Modification

No Modification

Post-Decrement (2, 4 and 6)

Register Offset

Post-Increment (2, 4 and 6)

DSP MAC

Direct

Indirect

Direct

Indirect



Details

4

4.2 PROGRAM ADDRESSING MODESThe 16-bit MCU and DSC devices have a 23-bit Program Counter (PC). The PC addresses the24-bit wide program memory to fetch instructions for execution, and it may be loaded in severalways. For byte compatibility with the table read and table write instructions, each instruction wordconsumes two locations in program memory. This means that during serial execution, the PC isloaded with PC + 2.

Several methods may be used to modify the PC in a non-sequential manner, and both absoluteand relative changes may be made to the PC. The change to the PC may be from an immediatevalue encoded in the instruction, or a dynamic value contained in a working register. In dsPIC30Fand dsPIC33F devices, when DO looping is active, the PC is loaded with the address stored inthe DOSTART register, after the instruction at the DOEND address is executed. For exceptionhandling, the PC is loaded with the address of the exception handler, which is stored in theinterrupt vector table. When required, the software stack is used to return scope to the foregroundprocess from where the change in program flow occurred.

Table 4-5 summarizes the instructions which modify the PC. When performing function calls, it isrecommended that RCALL be used instead of CALL, since RCALL only consumes 1 word of program memory.

Table 4-5: Methods of Modifying Program Flow

Condition/Instruction PC Modification Software Stack Usage

Sequential Execution PC = PC + 2 NoneBRA Expr(1)

(Branch Unconditionally)PC = PC + 2*Slit16 None

BRA Condition, Expr(1)

(Branch Conditionally)PC = PC + 2 (condition false)PC = PC + 2 * Slit16 (condition true)

None

CALL Expr(1)

(Call Subroutine)PC = lit23 PC + 4 is PUSHed on the stack(2)

CALL Wn(Call Subroutine Indirect)

PC = Wn PC + 2 is PUSHed on the stack(2)

GOTO Expr(1)

(Unconditional Jump)PC = lit23 None

GOTO Wn(Unconditional Indirect Jump)

PC = Wn None

RCALL Expr(1)

(Relative Call)PC = PC + 2 * Slit16 PC + 2 is PUSHed on the stack(2)

RCALL Wn(Computed Relative Call)

PC = PC + 2 * Wn PC + 2 is PUSHed on the stack(2)

Exception Handling PC = address of the exception handler(read from vector table)

PC + 2 is PUSHed on the stack(3)

PC = Target REPEAT instruction(REPEAT Looping)

PC not modified (if REPEAT active) None

PC = DOEND address(4)

(DO Looping)PC = DOSTART (if DO active) None

Note 1: For BRA, CALL and GOTO, the Expr may be a label, absolute address or expression, which is resolved by the linker to a 16-bit or 23-bit value (Slit16 or lit23). See Section 5. “Instruction Descriptions” for details.

2: After CALL or RCALL is executed, RETURN or RETLW will POP the Top-of-Stack (TOS) back into the PC.3: After an exception is processed, RETFIE will POP the Top-of-Stack (TOS) back into the PC.4: This condition/instruction is only available in dsPIC30F and dsPIC33F devices.



4.3 INSTRUCTION STALLSIn order to maximize the data space EA calculation and operand fetch time, the X data spaceread and write accesses are partially pipelined. A consequence of this pipelining is that addressregister data dependencies may arise between successive read and write operations usingcommon registers.

‘Read After Write’ (RAW) dependencies occur across instruction boundaries and are detected bythe hardware. An example of a RAW dependency would be a write operation that modifies W5,followed by a read operation that uses W5 as an Address Pointer. The contents of W5 will not bevalid for the read operation until the earlier write completes. This problem is resolved by stallingthe instruction execution for one instruction cycle, which allows the write to complete before thenext read is started.

4.3.1 RAW Dependency DetectionDuring the instruction pre-decode, the core determines if any address register dependency isimminent across an instruction boundary. The stall detection logic compares the W register(if any) used for the destination EA of the instruction currently being executed with the W registerto be used by the source EA (if any) of the prefetched instruction. When a match between thedestination and source registers is identified, a set of rules are applied to decide whether or notto stall the instruction by one cycle. Table 4-6 lists various RAW conditions which cause aninstruction execution stall.

Table 4-6: Raw Dependency Rules (Detection by Hardware)

DestinationAddress Mode Using Wn

Source Address ModeUsing Wn

Stall Required?

Examples(2)

(Wn = W2)

Direct Direct No Stall ADD.W W0, W1, W2MOV.W W2, W3

Indirect Direct No Stall ADD.W W0, W1, [W2]MOV.W W2, W3

Indirect Indirect No Stall ADD.W W0, W1, [W2]MOV.W [W2], W3

Indirect Indirect with pre/post-modification No Stall ADD.W W0, W1, [W2]MOV.W [W2++], W3

Indirect with pre/post-modification Direct No Stall ADD.W W0, W1, [W2++]MOV.W W2, W3

Direct Indirect Stall(1) ADD.W W0, W1, W2MOV.W [W2], W3

Direct Indirect with pre/post-modification Stall(1) ADD.W W0, W1, W2MOV.W [W2++], W3

Indirect Indirect Stall(1) ADD.W W0, W1, [W2](2)MOV.W [W2], W3(2)

Indirect Indirect with pre/post-modification Stall(1) ADD.W W0, W1, [W2](2) MOV.W [W2++], W3(2)

Indirect with pre/post-modification Indirect Stall(1) ADD.W W0, W1, [W2++]MOV.W [W2], W3

Indirect with pre/post-modification Indirect with pre/post-modification Stall(1) ADD.W W0, W1, [W2++]MOV.W [W2++], W3

Note 1: When stalls are detected, one cycle is added to the instruction execution time.2: For these examples, the contents of W2 = the mapped address of W2 (0x0004).



Details

4

4.3.2 Instruction Stalls and ExceptionsIn order to maintain deterministic operation, instruction stalls are allowed to happen, even if theyoccur immediately prior to exception processing.

4.3.3 Instruction Stalls and Instructions that Change Program FlowCALL and RCALL write to the stack using W15 and may, therefore, be subject to an instructionstall if the source read of the subsequent instruction uses W15.

GOTO, RETFIE and RETURN instructions are never subject to an instruction stall because theydo not perform write operations to the working registers.

4.3.4 Instruction Stalls and DO/REPEAT LoopsInstructions operating in a DO or REPEAT loop are subject to instruction stalls, just like any otherinstruction. Stalls may occur on loop entry, loop exit and also during loop processing.

4.3.5 Instruction Stalls and PSVInstructions operating in PSV address space are subject to instruction stalls, just like any otherinstruction. Should a data dependency be detected in the instruction immediately following thePSV data access, the second cycle of the instruction will initiate a stall. Should a datadependency be detected in the instruction immediately before the PSV data access, the lastcycle of the previous instruction will initiate a stall.

Note: DO loops are only available in dsPIC30F and dsPIC33F devices.

Note: Refer to the specific device family reference manual for more detailed informationabout RAW instruction stalls.



4.4 BYTE OPERATIONSSince the data memory is byte addressable, most of the base instructions may operate in eitherByte mode or Word mode. When these instructions operate in Byte mode, the following rulesapply:

• All direct working register references use the Least Significant Byte of the 16-bit working register and leave the Most Significant Byte (MSB) unchanged

• All indirect working register references use the data byte specified by the 16-bit address stored in the working register

• All file register references use the data byte specified by the byte address• The STATUS Register is updated to reflect the result of the byte operation

It should be noted that data addresses are always represented as byte addresses. Additionally,the native data format is little-endian, which means that words are stored with the LeastSignificant Byte at the lower address, and the Most Significant Byte at the adjacent, higheraddress (as shown in Figure 4-3). Example 4-8 shows sample byte move operations andExample 4-9 shows sample byte math operations.

Example 4-8: Sample Byte Move Operations

Note: Instructions that operate in Byte mode must use the “.b” or “.B” instructionextension to specify a byte instruction. For example, the following two instructionsare valid forms of a byte clear operation:

CLR.b W0 CLR.B W0

MOV.B #0x30, W0 ; move the literal byte 0x30 to W0

Before Instruction:W0 = 0x5555

After Instruction:W0 = 0x5530

MOV.B 0x1000, W0 ; move the byte at 0x1000 to W0

Before Instruction:W0 = 0x5555Data Memory 0x1000 = 0x1234

After Instruction:W0 = 0x5534Data Memory 0x1000 = 0x1234

MOV.B W0, 0x1001 ; byte move W0 to address 0x1001



MOV.B W0, [W1++] ; byte move W0 to [W1], then post-inc W1

Before Instruction:W0 = 0x1234W1 = 0x1001Data Memory 0x1000 = 0x5555

After Instruction:W0 = 0x1234W1 = 0x1002Data Memory 0x1000 = 0x3455



Details

4

Example 4-9: Sample Byte Math OperationsCLR.B [W6--] ; byte clear [W6], then post-dec W6



SUB.B W0, #0x10, W1 ; byte subtract literal 0x10 from W0; and store to W1

Before Instruction:W0 = 0x1234W1 = 0xFFFF

After Instruction:W0 = 0x1234W1 = 0xFF24

ADD.B W0, W1, [W2++] ; byte add W0 and W1, store to [W2]; and post-inc W2

Before Instruction:W0 = 0x1234W1 = 0x5678W2 = 0x1000Data Memory 0x1000 = 0x5555

After Instruction:W0 = 0x1234W1 = 0x5678W2 = 0x1001Data Memory 0x1000 = 0x55AC



4.5 WORD MOVE OPERATIONSEven though the data space is byte addressable, all move operations made in Word mode mustbe word-aligned. This means that for all source and destination operands, the Least Significantaddress bit must be ‘0’. If a word move is made to or from an odd address, an address errorexception is generated. Likewise, all double words must be word-aligned. Figure 4-3 shows howbytes and words may be aligned in data memory. Example 4-10 contains several legal wordmove operations.

When an exception is generated due to a misaligned access, the exception is taken after theinstruction executes. If the illegal access occurs from a data read, the operation will be allowedto complete, but the Least Significant bit of the source address will be cleared to force wordalignment. If the illegal access occurs during a data write, the write will be inhibited. Example 4-11contains several illegal word move operations.

Figure 4-3: Data Alignment in Memory

0x1001 b0 0x10000x1003 b1 0x10020x1005 b3 b2 0x10040x1007 b5 b4 0x10060x1009 b7 b6 0x10080x100B b8 0x100A

Legend: b0 – byte stored at 0x1000 b1 – byte stored at 0x1003 b3:b2 – word stored at 0x1005:1004 (b2 is LSB) b7:b4 – double word stored at 0x1009:0x1006 (b4 is LSB) b8 – byte stored at 0x100A

Note: Instructions that operate in Word mode are not required to use an instructionextension. However, they may be specified with an optional “.w” or “.W” extension,if desired. For example, the following instructions are valid forms of a word clearoperation:

CLR W0 CLR.w W0 CLR.W W0



Details

4

Example 4-10: Legal Word Move OperationsMOV #0x30, W0 ; move the literal word 0x30 to W0

Before Instruction:W0 = 0x5555

After Instruction:W0 = 0x0030

MOV 0x1000, W0 ; move the word at 0x1000 to W0



MOV [W0], [W1++] ; word move [W0] to [W1],; then post-inc W1

Before Instruction:W0 = 0x1234W1 = 0x1000Data Memory 0x1000 = 0x5555Data Memory 0x1234 = 0xAAAA

After Instruction:W0 = 0x1234W1 = 0x1002Data Memory 0x1000 = 0xAAAAData Memory 0x1234 = 0xAAAA



Example 4-11: Illegal Word Move OperationsMOV 0x1001, W0 ; move the word at 0x1001 to W0

Before Instruction:W0 = 0x5555Data Memory 0x1000 = 0x1234Data Memory 0x1002 = 0x5678

After Instruction:W0 = 0x1234Data Memory 0x1000 = 0x1234Data Memory 0x1002 = 0x5678

ADDRESS ERROR TRAP GENERATED

(source address is misaligned, so MOV is performed)

MOV W0, 0x1001 ; move W0 to the word at 0x1001

Before Instruction:W0 = 0x1234Data Memory 0x1000 = 0x5555Data Memory 0x1002 = 0x6666

After Instruction:W0 = 0x1234Data Memory 0x1000 = 0x5555Data Memory 0x1002 = 0x6666


(destination address is misaligned, so MOV is not performed)

MOV [W0], [W1++] ; word move [W0] to [W1], ; then post-inc W1

Before Instruction:W0 = 0x1235W1 = 0x1000Data Memory 0x1000 = 0x1234Data Memory 0x1234 = 0xAAAAData Memory 0x1236 = 0xBBBB

After Instruction:W0 = 0x1235W1 = 0x1002Data Memory 0x1000 = 0xAAAAData Memory 0x1234 = 0xAAAAData Memory 0x1236 = 0xBBBB


(source address is misaligned, so MOV is performed)



Details

4

4.6 USING 10-BIT LITERAL OPERANDSSeveral instructions that support Byte and Word mode have 10-bit operands. For byteinstructions, a 10-bit literal is too large to use. So when 10-bit literals are used in Byte mode, therange of the operand must be reduced to 8 bits or the assembler will generate an error. Table 4-7shows that the range of a 10-bit literal is 0:1023 in Word mode and 0:255 in Byte mode.

Instructions which employ 10-bit literals in Byte and Word mode are: ADD, ADDC, AND, IOR,RETLW, SUB, SUBB and XOR. Example 4-12 shows how positive and negative literals are used inByte mode for the ADD instruction.

Table 4-7: 10-bit Literal Coding

Example 4-12: Using 10-bit Literals for Byte Operands

Literal Value Word Modekk kkkk kkkk

Byte Modekkkk kkkk

0 00 0000 0000 0000 0000

1 00 0000 0001 0000 0001

2 00 0000 0010 0000 0010

127 00 0111 1111 0111 1111

128 00 1000 0000 1000 0000

255 00 1111 1111 1111 1111

256 01 0000 0000 N/A512 10 0000 0000 N/A

1023 11 1111 1111 N/A

ADD.B #0x80, W0 ; add 128 (or -128) to W0ADD.B #0x380, W0 ; ERROR... Illegal syntax for byte mode ADD.B #0xFF, W0 ; add 255 (or -1) to W0ADD.B #0x3FF, W0 ; ERROR... Illegal syntax for byte modeADD.B #0xF, W0 ; add 15 to W0ADD.B #0x7F, W0 ; add 127 to W0ADD.B #0x100, W0 ; ERROR... Illegal syntax for byte mode

Note: Using a literal value greater than 127 in Byte mode is functionally identical to usingthe equivalent negative two’s complement value, since the Most Significant bit of thebyte is set. When operating in Byte mode, the Assembler will accept either a positiveor negative literal value (i.e., #-10).



4.7 SOFTWARE STACK POINTER AND FRAME POINTER

4.7.1 Software Stack PointerThe 16-bit MCU and DSC devices feature a software stack which facilitates function calls andexception handling. W15 is the default Stack Pointer (SP) and after any Reset, it is initialized to0x0800. This ensures that the SP will point to valid RAM and permits stack availability forexceptions, which may occur before the SP is set by the user software. The user may reprogramthe SP during initialization to any location within data space.

The SP always points to the first available free word (Top-of-Stack) and fills the software stack,working from lower addresses towards higher addresses. It pre-decrements for a stack POP(read) and post-increments for a stack PUSH (write).

The software stack is manipulated using the PUSH and POP instructions. The PUSH and POPinstructions are the equivalent of a MOV instruction, with W15 used as the destination pointer. Forexample, the contents of W0 can be PUSHed onto the Top-of-Stack (TOS) by:

PUSH W0

This syntax is equivalent to:MOV W0,[W15++]

The contents of the TOS can be returned to W0 by: POP W0

This syntax is equivalent to:MOV [--W15],W0

During any CALL instruction, the PC is PUSHed onto the stack, such that when the subroutinecompletes execution, program flow may resume from the correct location. When the PC isPUSHed onto the stack, PC<15:0> is PUSHed onto the first available stack word, thenPC<22:16> is PUSHed. When PC<22:16> is PUSHed, the Most Significant 7 bits of the PC arezero-extended before the PUSH is made, as shown in Figure 4-4. During exception processing,the Most Significant 7 bits of the PC are concatenated with the lower byte of the STATUSregister (SRL) and IPL<3>, CORCON<3>. This allows the primary STATUS register contentsand CPU Interrupt Priority Level to be automatically preserved during interrupts.

Figure 4-4: Stack Operation for CALL Instruction

Note: In order to protect against misaligned stack accesses, W15<0> is always clear.

015

W15 (before CALL)

W15 (after CALL)

Stac

k G

row

s To

war

dsH

ighe

r Add

ress

0x0000

PC<15:0> 0x0 PC<22:16>

Top-of-Stack

0xFFFE

Note: For exceptions, the upper nine bits of the second PUSHed word containsthe SRL and IPL<3>.



Details

4

4.7.1.1 STACK POINTER EXAMPLE

Figure 4-5 through Figure 4-8 show how the software stack is modified for the code snippetshown in Example 4-13. Figure 4-5 shows the software stack before the first PUSH has executed.Note that the SP has the initialized value of 0x0800. Furthermore, the example loads 0x5A5Aand 0x3636 to W0 and W1, respectively. The stack is PUSHed for the first time in Figure 4-6 andthe value contained in W0 is copied to TOS. W15 is automatically updated to point to the nextavailable stack location, and the new TOS is 0x0802. In Figure 4-7, the contents of W1 arePUSHed onto the stack, and the new TOS becomes 0x0804. In Figure 4-8, the stack is POPed,which copies the last PUSHed value (W1) to W3. The SP is decremented during the POPoperation, and at the end of the example, the final TOS is 0x0802.

Example 4-13: Stack Pointer Usage

Figure 4-5: Stack Pointer Before the First PUSH

Figure 4-6: Stack Pointer After “PUSH W0” Instruction

MOV #0x5A5A, W0 ; Load W0 with 0x5A5AMOV #0x3636, W1 ; Load W1 with 0x3636PUSH W0 ; Push W0 to TOS (see Figure 4-5)PUSH W1 ; Push W1 to TOS (see Figure 4-7)POP W3 ; Pop TOS to W3 (see Figure 4-8)

0x0000

0xFFFE

0x0800 W15 (SP)

W15 = 0x0800

W0 = 0x5A5AW1 = 0x3636

<TOS>

0x0000

0xFFFE

0x0800W15 (SP)

W15 = 0x0802

W0 = 0x5A5AW1 = 0x3636

5A5A<TOS>0x0802



Figure 4-7: Stack Pointer After “PUSH W1” Instruction

Figure 4-8: Stack Pointer After “POP W3” Instruction

4.7.2 Software Stack Frame PointerA Stack Frame is a user-defined section of memory residing in the software stack. It is used toallocate memory for temporary variables which a function uses, and one Stack Frame may becreated for each function. W14 is the default Stack Frame Pointer (FP) and it is initialized to0x0000 on any Reset. If the Stack Frame Pointer is not used, W14 may be used like any otherworking register.

The link (LNK) and unlink (ULNK) instructions provide Stack Frame functionality. The LNKinstruction is used to create a Stack Frame. It is used during a call sequence to adjust the SP,such that the stack may be used to store temporary variables utilized by the called function. Afterthe function completes execution, the ULNK instruction is used to remove the Stack Framecreated by the LNK instruction. The LNK and ULNK instructions must always be used together toavoid stack overflow.

0x0000

0xFFFE

0x0800

W15 (SP)

W15 = 0x0804

W0 = 0x5A5AW1 = 0x3636

5A5A

<TOS>0x0802 36360x0804

0x0000

0xFFFE

0x0800W15 (SP)

W15 = 0x0802

W0 = 0x5A5AW1 = 0x3636

5A5A0x0802 <TOS>0x0804

W3 = 0x3636

Note: The contents of 0x802, the new TOS, remain unchanged (0x3636).



Details

4

4.7.2.1 STACK FRAME POINTER EXAMPLE

Figure 4-9 through Figure 4-11 show how a Stack Frame is created and removed for the codesnippet shown in Example 4-14. This example demonstrates how a Stack Frame operates andis not indicative of the code generated by the compiler. Figure 4-9 shows the stack condition atthe beginning of the example, before any registers are PUSHed to the stack. Here, W15 pointsto the first free stack location (TOS) and W14 points to a portion of stack memory allocated forthe routine that is currently executing.

Before calling the function “COMPUTE”, the parameters of the function (W0, W1 and W2) arePUSHed on the stack. After the “CALL COMPUTE” instruction is executed, the PC changes to theaddress of “COMPUTE” and the return address of the function “TASKA” is placed on the stack(Figure 4-10). Function “COMPUTE” then uses the “LNK #4” instruction to PUSH the callingroutine’s Frame Pointer value onto the stack and the new Frame Pointer will be set to point to thecurrent Stack Pointer. Then, the literal 4 is added to the Stack Pointer address in W15, whichreserves memory for two words of temporary data (Figure 4-11).

Inside the function “COMPUTE”, the FP is used to access the function parameters and temporary(local) variables. [W14 + n] will access the temporary variables used by the routine and [W14 – n]is used to access the parameters. At the end of the function, the ULNK instruction is used to copythe Frame Pointer address to the Stack Pointer and then POP the calling subroutine’s FramePointer back to the W14 register. The ULNK instruction returns the stack back to the state shownin Figure 4-10.

A RETURN instruction will return to the code that called the subroutine. The calling code isresponsible for removing the parameters from the stack. The RETURN and POP instructionsrestore the stack to the state shown in Figure 4-9.

Example 4-14: Frame Pointer Usage

Figure 4-9: Stack at the Beginning of Example 4-14

TASKA: ... PUSH W0 ; Push parameter 1PUSH W1 ; Push parameter 2PUSH W2 ; Push parameter 3CALL COMPUTE ; Call COMPUTE functionPOP W2 ; Pop parameter 3POP W1 ; Pop parameter 2POP W0 ; Pop parameter 1

...

COMPUTE:LNK #4 ; Stack FP, allocate 4 bytes for local variables...ULNK ; Free allocated memory, restore original FP RETURN ; Return to TASKA

0x0000

0xFFFE

0x0800

W14 (FP)

<TOS> W15 (SP)TASKA

Frameof



Figure 4-10: Stack After “CALLCOMPUTE” Executes

Figure 4-11: Stack After “LNK #4” Executes

4.7.3 Stack Pointer Overflow There is a stack limit register (SPLIM) associated with the Stack Pointer that is reset to 0x0000.SPLIM is a 16-bit register, but SPLIM<0> is fixed to ‘0’, because all stack operations must beword-aligned.

The stack overflow check will not be enabled until a word write to SPLIM occurs, after which timeit can only be disabled by a device Reset. All effective addresses generated using W15 as asource or destination are compared against the value in SPLIM. Should the effective address begreater than the contents of SPLIM, then a stack error trap is generated.

If stack overflow checking has been enabled, a stack error trap will also occur if the W15 effectiveaddress calculation wraps over the end of data space (0xFFFF).

Refer to the specific device family reference manual for more information on the stack error trap.

4.7.4 Stack Pointer UnderflowThe stack is initialized to 0x0800 during Reset. A stack error trap will be initiated should the StackPointer address ever be less than 0x0800.

Note: Locations in data space between 0x0000 and 0x07FF are, in general, reserved forcore and peripheral Special Function Registers (SFRs).

0x0000

0xFFFE

0x0800

W14 (FP)

Parameter 1

W15 (SP)

TASKA

Frameof

Parameter 2Parameter 3PC<15:0>

0:PC<22:16><TOS>

0x0000

0xFFFE

0x0800

W14 (FP)

Parameter 1

W15 (SP)

TASKA

Frame of

Parameter 2Parameter 3PC<15:0>

0:PC<22:16>

<TOS>

FP of TASKATemp Word 1Temp Word 2



Details

4

4.8 Conditional Branch InstructionsConditional branch instructions are used to direct program flow, based on the contents of theSTATUS register. These instructions are generally used in conjunction with a Compare classinstruction, but they may be employed effectively after any operation that modifies the STATUSregister.

The compare instructions CP, CP0 and CPB, perform a subtract operation(minuend – subtrahend), but do not actually store the result of the subtraction. Instead, compareinstructions just update the flags in the STATUS register, such that an ensuing conditional branchinstruction may change program flow by testing the contents of the updated STATUS register. Ifthe result of the STATUS register test is true, the branch is taken. If the result of the STATUSregister test is false, the branch is not taken.

The conditional branch instructions supported by the dsPIC30F and dsPIC33F devices areshown in Table 4-8. This table identifies the condition in the STATUS register which must be truefor the branch to be taken. In some cases, just a single bit is tested (as in BRA C), while in othercases, a complex logic operation is performed (as in BRA GT). For dsPIC30F and dsPIC33Fdevices, it is worth noting that both signed and unsigned conditional tests are supported, and thatsupport is provided for DSP algorithms with the OA, OB, SA and SB condition mnemonics.

Table 4-8: Conditional Branch Instructions

Note 1: Instructions are of the form: BRA mnemonic, Expr.2: GEU is identical to C and will reverse assemble to BRA C, Expr.3: LTU is identical to NC and will reverse assemble to BRA NC, Expr.4: This condition is only available in dsPIC30F and dsPIC33F devices.

ConditionMnemonic(1) Description Status Test

C Carry (not Borrow) CGE Signed greater than or equal (N&&OV) || (N&&OV)GEU(2) Unsigned greater than or equal CGT Signed greater than (Z&&N&&OV) || (Z&&N&&OV)GTU Unsigned greater than C&&ZLE Signed less than or equal Z || (N&&OV) || (N&&OV)LEU Unsigned less than or equal C || ZLT Signed less than (N&&OV) || (N&&OV)LTU(3) Unsigned less than CN Negative NNC Not Carry (Borrow) CNN Not Negative NNOV Not Overflow OVNZ Not Zero ZOA(4) Accumulator A overflow OAOB(4) Accumulator B overflow OBOV Overflow OVSA(4) Accumulator A saturate SASB(4) Accumulator B saturate SBZ Zero Z

Note: The “Compare and Skip” instructions (CPBEQ, CPBGT, CPBLT, CPBNE, CPSEQ,CPSGT, CPSLT and CPSNE) do not modify the STATUS register.



4.9 Z STATUS BITThe Z Status bit is a special zero Status bit that is useful for extended precision arithmetic. TheZ bit functions like a normal Z flag for all instructions, except those that use the carry/borrow input(ADDC, CPB, SUBB and SUBBR). For the ADDC, CPB, SUBB and SUBBR instructions, the Z bit canonly be cleared and never set. If the result of one of these instructions is non-zero, the Z bit willbe cleared and will remain cleared, regardless of the result of subsequent ADDC, CPB, SUBB orSUBBR operations. This allows the Z bit to be used for performing a simple zero check on theresult of a series of extended precision operations.

A sequence of instructions working on multi-precision data (starting with an instruction with nocarry/borrow input), will automatically logically AND the successive results of the zero test. Allresults must be zero for the Z flag to remain set at the end of the sequence of operations. If theresult of the ADDC, CPB, SUBB or SUBBR instruction is non-zero, the Z bit will be cleared andremain cleared for all subsequent ADDC, CPB, SUBB or SUBBR instructions. Example 4-15 showshow the Z bit operates for a 32-bit addition. It shows how the Z bit is affected for a 32-bit additionimplemented with an ADD/ADDC instruction sequence. The first example generates a zero resultfor only the most significant word, and the second example generates a zero result for both theleast significant word and most significant word.

Example 4-15: ‘Z’ Status bit Operation for 32-Bit Addition; Add two doubles (W0:W1 and W2:W3); Store the result in W5:W4ADD W0, W2, W4 ; Add LSWord and store to W4ADDC W1, W3, W5 ; Add MSWord and store to W5

Before 32-bit Addition (zero result for the most significant word):W0 = 0x2342W1 = 0xFFF0W2 = 0x39AAW3 = 0x0010W4 = 0x0000W5 = 0x0000SR = 0x0000

After 32-bit Addition:W0 = 0x2342W1 = 0xFFF0W2 = 0x39AAW3 = 0x0010W4 = 0x5CECW5 = 0x0000SR = 0x0201 (DC,C=1)

Before 32-bit Addition (zero result for the least significant word and most significant word):W0 = 0xB76EW1 = 0xFB7BW2 = 0x4892W3 = 0x0484W4 = 0x0000W5 = 0x0000SR = 0x0000

After 32-bit Addition:W0 = 0xB76EW1 = 0xFB7BW2 = 0x4892W3 = 0x0485W4 = 0x0000W5 = 0x0000SR = 0x0103 (DC,Z,C=1)



Details

4

4.10 ASSIGNED WORKING REGISTER USAGEThe 16 working registers of the 16-bit MCU and DSC devices provide a large register set forefficient code generation and algorithm implementation. In an effort to maintain an instruction setthat provides advanced capability, a stable run-time environment and backwards compatibilitywith earlier Microchip processor cores, some working registers have a pre-assigned usage.Table 4-9 summarizes these working register assignments. For the dsPIC30F and dsPIC33F,additional details are provided in subsections 4.10.1 “Implied DSP Operands (dsPIC30F anddsPIC33F Devices)” through 4.10.3 “PIC® Microcontroller Compatibility”.

Table 4-9: Special Working Register Assignments

4.10.1 Implied DSP Operands (dsPIC30F and dsPIC33F Devices)To assist instruction encoding and maintain uniformity among the DSP class of instructions,some working registers have pre-assigned functionality. For all DSP instructions which haveprefetch ability, the following 10 register assignments must be adhered to:

• W4-W7 are used for arithmetic operands• W8-W11 are used for prefetch addresses (pointers)• W12 is used for the prefetch register offset index • W13 is used for the accumulator Write Back destination

These restrictions only apply to the DSP MAC class of instructions, which utilize workingregisters and have prefetch ability (described in 4.15 “DSP Accumulator Instructions(dsPIC30F and dsPIC33F Devices)”). The affected instructions are CLR, ED, EDAC, MAC,MOVSAC, MPY, MPY.N and MSC.

The DSP Accumulator class of instructions (described in 4.15 “DSP Accumulator Instructions(dsPIC30F and dsPIC33F Devices)”) are not required to follow the working register assignmentsin Table 4-9 and may freely use any working register when required.

Register Special Assignment

W0 Default WREG, Divide QuotientW1 Divide RemainderW2 “MUL f” Product least significant wordW3 “MUL f” Product most significant wordW4 MAC Operand(1)

W5 MAC Operand(1)

W6 MAC Operand(1)

W7 MAC Operand(1)

W8 MAC Prefetch Address (X Memory)(1)

W9 MAC Prefetch Address (X Memory)(1)

W10 MAC Prefetch Address (Y Memory)(1)

W11 MAC Prefetch Address (Y Memory)(1)

W12 MAC Prefetch Offset(1)

W13 MAC Write Back Destination(1)

W14 Frame PointerW15 Stack PointerNote 1: This assignment is only applicable in dsPIC30F and dsPIC33F devices.



4.10.2 Implied Frame and Stack PointerTo accommodate software stack usage, W14 is the implied Frame Pointer (used by the LNK andULNK instructions) and W15 is the implied Stack Pointer (used by the CALL, LNK, POP, PUSH,RCALL, RETFIE, RETLW, RETURN, TRAP and ULNK instructions). Even though W14 and W15have this implied usage, they may still be used as generic operands in any instruction, with theexceptions outlined in 4.10.1 “Implied DSP Operands (dsPIC30F and dsPIC33F Devices)”. IfW14 and W15 must be used for other purposes (it is strongly advised that they remain reservedfor the Frame and Stack Pointer), extreme care must be taken such that the run-timeenvironment is not corrupted.

4.10.3 PIC® Microcontroller Compatibility

4.10.3.1 DEFAULT WORKING REGISTER WREG

To ease the migration path for users of the Microchip 8-bit PIC MCU families, the 16-bit MCU andDSC devices have matched the functionality of the PIC MCU instruction sets as closely aspossible. One major difference between the 16-bit MCU and DSC and the 8-bit PIC MCUprocessors is the number of working registers provided. The 8-bit PIC MCU families only provideone 8-bit working register, while the 16-bit MCU and DSC families provide sixteen, 16-bit workingregisters. To accommodate for the one working register of the 8-bit PIC MCU, the 16-bit MCUand DSC device instruction set has designated one working register to be the default workingregister for all legacy file register instructions. The default working register is set to W0, and it isused by all instructions which use file register addressing.

Additionally, the syntax used by the 16-bit MCU and DSC device assembler to specify the defaultworking register is similar to that used by the 8-bit PIC MCU assembler. As shown in the detailedinstruction descriptions in Section 5. “Instruction Descriptions”, “WREG” must be used tospecify the default working register. Example 4-16 shows several instructions which use WREG.

Example 4-16: Using the Default Working Register WREG

4.10.3.2 PRODH:PRODL REGISTER PAIR

Another significant difference between the Microchip 8-bit PIC MCU and 16-bit MCU and DSCarchitectures is the multiplier. Some PIC MCU families support an 8-bit x 8-bit multiplier, whichplaces the multiply product in the PRODH:PRODL register pair. The 16-bit MCU and DSCdevices have a 17-bit x 17-bit multiplier, which may place the result into any two successiveworking registers (starting with an even register), or an accumulator.

Despite this architectural difference, the 16-bit MCU and DSC devices still support the legacy fileregister multiply instruction (MULWF) with the “MUL{.B} f” instruction (described on page 5-255).Supporting the legacy MULWF instruction has been accomplished by mapping thePRODH:PRODL registers to the working register pair W3:W2. This means that when “MUL{.B}f” is executed in Word mode, the multiply generates a 32-bit product which is stored in W3:W2,where W3 has the most significant word of the product and W2 has the least significant word ofthe product. When “MUL{.B} f” is executed in Byte mode, the 16-bit product is stored in W2,and W3 is unaffected. Examples of this instruction are shown in Example 4-17.

ADD RAM100 ; add RAM100 and WREG, store in RAM100ASR RAM100, WREG ; shift RAM100 right, store in WREGCLR.B WREG ; clear the WREG LS ByteDEC RAM100, WREG ; decrement RAM100, store in WREGMOV WREG, RAM100 ; move WREG to RAM100SETM WREG ; set all bits in the WREGXOR RAM100 ; XOR RAM100 and WREG, store in RAM100



Details

4

Example 4-17: Unsigned f and WREG Multiply (Legacy MULWF Instruction)

4.10.3.3 MOVING DATA WITH WREG

The “MOV{.B} f {,WREG}” instruction (described on page 5-145) and “MOV{.B} WREG, f”instruction (described on page 5-146) allow for byte or word data to be moved between fileregister memory and the WREG (working register W0). These instructions provide equivalentfunctionality to the legacy Microchip PIC MCU MOVF and MOVWF instructions.

The “MOV{.B} f {,WREG}” and “MOV{.B} WREG, f” instructions are the only MOV instructionswhich support moves of byte data to and from file register memory. Example 4-18 shows severalMOV instruction examples using the WREG.

Example 4-18: Moving Data with WREG

MUL.B 0x100 ; (0x100)*WREG (byte mode), store to W2

Before Instruction:W0 (WREG) = 0x7705W2 = 0x1235W3 = 0x1000Data Memory 0x0100 = 0x1255

After Instruction:W0 (WREG) = 0x7705W2 = 0x01A9W3 = 0x1000Data Memory 0x0100 = 0x1255

MUL 0x100 ; (0x100)*WREG (word mode), store to W3:W2

Before Instruction:W0 (WREG) = 0x7705W2 = 0x1235W3 = 0x1000Data Memory 0x0100 = 0x1255

After Instruction:W0 (WREG) = 0x7705W2 = 0xDEA9W3 = 0x0885Data Memory 0x0100 = 0x1255

Note: When moving word data between file register memory and the working registerarray, the “MOV Wns, f” and “MOV f, Wnd” instructions allow any working register(W0:W15) to be used as the source or destination register, not just WREG.

MOV.B 0x1001, WREG ; move the byte stored at location 0x1001 to W0MOV 0x1000, WREG ; move the word stored at location 0x1000 to W0MOV.B WREG, TBLPAG ; move the byte stored at W0 to the TBLPAG registerMOV WREG, 0x804 ; move the word stored at W0 to location 0x804



4.11 DSP DATA FORMATS (dsPIC30F AND dsPIC33F DEVICES)

4.11.1 Integer and Fractional DataThe dsPIC30F and dsPIC33F devices support both integer and fractional data types. Integerdata is inherently represented as a signed two’s complement value, where the Most Significantbit is defined as a sign bit. Generally speaking, the range of an N-bit two’s complement integeris -2N-1 to 2N-1 – 1. For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF),including ‘0’. For a 32-bit integer, the data range is -2,147,483,648 (0x8000 0000) to2,147,483,647 (0x7FFF FFFF).

Fractional data is represented as a two’s complement number, where the Most Significant bit isdefined as a sign bit, and the radix point is implied to lie just after the sign bit. This format iscommonly referred to as 1.15 (or Q15) format, where 1 is the number of bits used to representthe integer portion of the number, and 15 is the number of bits used to represent the fractionalportion. The range of an N-bit two’s complement fraction with this implied radix point is -1.0 to(1 – 21-N). For a 16-bit fraction, the 1.15 data range is -1.0 (0x8000) to 0.999969482 (0x7FFF),including 0.0 and it has a precision of 3.05176x10-5. In Normal Saturation mode, the 32-bitaccumulators use a 1.31 format, which enhances the precision to 4.6566x10-10.

Super Saturation mode expands the dynamic range of the accumulators by using the 8 bits ofthe Upper Accumulator register (ACCxU) as guard bits. Guard bits are used if the value storedin the accumulator overflows beyond the 32nd bit, and they are useful for implementing DSPalgorithms. This mode is enabled when the ACCSAT bit (CORCON<4>), is set to ‘1’ and itexpands the accumulators to 40 bits. The accumulators then support an integer range of-5.498x1011 (0x80 0000 0000) to 5.498x1011 (0x7F FFFF FFFF). In Fractional mode, the guardbits of the accumulator do not modify the location of the radix point and the 40-bit accumulatorsuse a 9.31 fractional format. Note that all fractional operation results are stored in the 40-bitAccumulator, justified with a 1.31 radix point. As in Integer mode, the guard bits merely increasethe dynamic range of the accumulator. 9.31 fractions have a range of -256.0 (0x80 0000 0000)to (256.0 – 4.65661x10-10) (0x7F FFFF FFFF). Table 4-10 identifies the range and precision ofintegers and fractions on the dsPIC30F/33F devices for 16-bit, 32-bit and 40-bit registers.

It should be noted that, with the exception of DSP multiplies, the ALU operates identically oninteger and fractional data. Namely, an addition of two integers will yield the same result (binarynumber) as the addition of two fractional numbers. The only difference is how the result isinterpreted by the user. However, multiplies performed by DSP operations are different. In theseinstructions, data format selection is made by the IF bit, CORCON<0>, and it must be setaccordingly (‘0’ for Fractional mode, ‘1’ for Integer mode). This is required because of the impliedradix point used by dsPIC30F/33F fractional numbers. In Integer mode, multiplying two 16-bitintegers produces a 32-bit integer result. However, multiplying two 1.15 values generates a 2.30result. Since the dsPIC30F and dsPIC33F devices use a 1.31 format for the accumulators, a DSPmultiply in Fractional mode also includes a left shift of one bit to keep the radix point properlyaligned. This feature reduces the resolution of the DSP multiplier to 2-30, but has no other effecton the computation (e.g., 0.5 x 0.5 = 0.25).

Table 4-10: dsPIC30F/33F Data Ranges

Register Size Integer Range Fraction Range Fraction Resolution

16-bit -32768 to 32767 -1.0 to (1.0 – 2-15) 3.052 x 10-5

32-bit -2,147,483,648 to 2,147,483,647

-1.0 to (1.0 – 2-31) 4.657 x 10-10

40-bit -549,755,813,888 to 549,755,813,887

-256.0 to (256.0 – 2-31) 4.657 x 10-10



Details

4

4.11.2 Integer and Fractional Data RepresentationHaving a working knowledge of how integer and fractional data are represented on the dsPIC30Fand dsPIC33F is fundamental to working with the device. Both integer and fractional data treatthe Most Significant bit as a sign bit, and the binary exponent decreases by one as the bit positionadvances toward the Least Significant bit. The binary exponent for an N-bit integer starts at (N-1)for the Most Significant bit, and ends at ‘0’ for the Least Significant bit. For an N-bit fraction, thebinary exponent starts at ‘0’ for the Most Significant bit, and ends at (1-N) for the Least Significantbit (as shown in Figure 4-12 for a positive value and in Figure 4-13 for a negative value).

Conversion between integer and fractional representations can be performed using simpledivision and multiplication. To go from an N-bit integer to a fraction, divide the integer value by2N-1. Likewise, to convert an N-bit fraction to an integer, multiply the fractional value by 2N-1.

Figure 4-12: Different Representations of 0x4001

Figure 4-13: Different Representations of 0xC002

Integer:

1.15 Fractional:

0x4001 = 214 + 20 = 16384 + 1 = 16385

0x4001 = 2-1 + 2-15 = 0.5 + .000030518 = 0.500030518

Implied Radix Point

0 1 0 0 0000 00 0 00 0 0 1

10 0 0 0000 00 0 00 0 0 1

-215 214 213 212 . . . . . . 20

2-15 -20 . 2-1 2-2 2-3 . . . . . .

Integer:

1.15 Fractional:

0xC002 = -215 + 214 + 21= -32768 + 16384 + 2 = -16382

0xC002 = -20 + 2-1 + 2-14 = -1.0 + 0.5 + 0.000061035 = -0.499938965

Implied Radix Point

1 1 0 0 0000 10 0 00 0 0 0

11 0 0 0000 10 0 00 0 0 0

-215 214 213 212 . . . . . . 20

2-15 -20 . 2-1 2-2 2-3 . . . . . .

1 1 0 0 0000 10 0 00 0 0 0



4.12 ACCUMULATOR USAGE (dsPIC30F AND dsPIC33F DEVICES)Accumulators A and B are utilized by DSP instructions to perform mathematical and shiftingoperations. Since the accumulators are 40 bits wide and the X and Y data paths are only 16 bits,the method to load and store the accumulators must be understood.

Item A in Figure 4-14 shows that each 40-bit Accumulator (ACCA and ACCB) consists of an 8-bitUpper register (ACCxU), a 16-bit High register (ACCxH) and a 16-bit Low register (ACCxL). Toaddress the bus alignment requirement and provide the ability for 1.31 math, ACCxH is used asa destination register for loading the accumulator (with the LAC instruction), and also as a sourceregister for storing the accumulator (with the SAC.R instruction). This is represented by Item B,Figure 4-14, where the upper and lower portions of the accumulator are shaded. In reality, duringaccumulator loads, ACCxL is zero backfilled and ACCxU is sign-extended to represent the signof the value loaded in ACCxH.

When Normal (31-bit) Saturation is enabled, DSP operations (such as ADD, MAC, MSC, etc.)utilize solely ACCxH:ACCxL (Item C in Figure 4-14) and ACCxU is only used to maintain the signof the value stored in ACCxH:ACCxL. For instance, when a MPY instruction is executed, theresult is stored in ACCxH:ACCxL, and the sign of the result is extended through ACCxU.

When Super Saturation is enabled, all registers of the accumulator may be used (Item D inFigure 4-14) and the results of DSP operations are stored in ACCxU:ACCxH:ACCxL. The benefitof ACCxU is that it increases the dynamic range of the accumulator, as described in4.11.1 “Integer and Fractional Data”. Refer to Table 4-10 to see the range of values which maybe stored in the accumulator when in Normal and Super Saturation modes.

Figure 4-14: Accumulator Alignment and Usage

A)

D)

C)

B)

ACCxU ACCxH ACCxL

A) 40-bit Accumulator consists of ACCxU:ACCxH:ACCxLB) Load and Store operationsC) Operations in Normal Saturation modeD) Operations in Super Saturation mode

31.30

Implied Radix Point (between bits 31 and 30)

015163239



Details

4

4.13 ACCUMULATOR ACCESS (dsPIC30F AND dsPIC33F DEVICES)The six registers of Accumulator A and Accumulator B are memory mapped like any otherSpecial Function Register. This feature allows them to be accessed with file register or indirectaddressing, using any instruction which supports such addressing. However, it is recommendedthat the DSP instructions LAC, SAC and SAC.R be used to load and store the accumulators,since they provide sign-extension, shifting and rounding capabilities. LAC, SAC and SAC.Rinstruction details are provided in Section 5. “Instruction Descriptions”.

Note: For convenience, ACCAU and ACCBU are sign-extended to 16 bits. This providesthe flexibility to access these registers using either Byte or Word mode (when fileregister or indirect addressing is used).



4.14 DSP MAC INSTRUCTIONS (dsPIC30F AND dsPIC33F DEVICES)The DSP Multiply and Accumulate (MAC) operations are a special suite of instructions whichprovide the most efficient use of the dsPIC30F and dsPIC33F architectures. The DSP MACinstructions, shown in Table 4-11, utilize both the X and Y data paths of the CPU core, whichenables these instructions to perform the following operations all in one cycle:

• two reads from data memory using prefetch working registers (MAC Prefetches)• two updates to prefetch working registers (MAC Prefetch Register Updates)• one mathematical operation with an accumulator (MAC Operations)

In addition, four of the ten DSP MAC instructions are also capable of performing an operation withone accumulator, while storing out the rounded contents of the alternate accumulator. Thisfeature is called accumulator Write Back (WB) and it provides flexibility for the softwaredeveloper. For instance, the accumulator WB may be used to run two algorithms concurrently, orefficiently process complex numbers, among other things.

Table 4-11: DSP MAC Instructions

4.14.1 MAC PrefetchesPrefetches (or data reads) are made using the effective address stored in the working register.The two prefetches from data memory must be specified using the working register assignmentsshown in Table 4-9. One read must occur from the X data bus using W8 or W9, and one readmust occur from the Y data bus using W10 or W11. The allowed destination registers for bothprefetches are W4-W7.

As shown in Table 4-3, one special Addressing mode exists for the MAC class of instructions. Thismode is the Register Offset Addressing mode and utilizes W12. In this mode, the prefetch ismade using the effective address of the specified working register, plus the 16-bit signed valuestored in W12. Register Offset Addressing may only be used in the X space with W9, and in theY-space with W11.

4.14.2 MAC Prefetch Register UpdatesAfter the MAC prefetches are made, the effective address stored in each prefetch working registermay be modified. This feature enables efficient single-cycle processing for data storedsequentially in X and Y memory. Since all DSP instructions execute in Word mode, only evennumbered updates may be made to the effective address stored in the working register.Allowable address modifications to each prefetch register are -6, -4, -2, 0 (no update), +2, +4 and+6. This means that effective address updates may be made up to 3 words in either direction.

When the Register Offset Addressing mode is used, no update is made to the base prefetchregister (W9 or W11), or the offset register (W12).

Instruction Description Accumulator WB?

CLR Clear accumulator YesED Euclidean distance (no accumulate) NoEDAC Euclidean distance NoMAC Multiply and accumulate YesMAC Square and accumulate NoMOVSAC Move from X and Y bus YesMPY Multiply to accumulator NoMPY Square to accumulator NoMPY.N Negative multiply to accumulator NoMSC Multiply and subtract Yes



Details

4

4.14.3 MAC OperationsThe mathematical operations performed by the MAC class of DSP instructions center aroundmultiplying the contents of two working registers and either adding or storing the result to eitherAccumulator A or Accumulator B. This is the operation of the MAC, MPY, MPY.N and MSCinstructions. Table 4-9 shows that W4-W7 must be used for data source operands in the MACclass of instructions. W4-W7 may be combined in any fashion, and when the same workingregister is specified for both operands, a square or square and accumulate operation isperformed.

For the ED and EDAC instructions, the same multiplicand operand must be specified by theinstruction, because this is the definition of the Euclidean Distance operation. Another uniquefeature about this instruction is that the values prefetched from X and Y memory are not actuallystored in W4-W7. Instead, only the difference of the prefetched data words is stored in W4-W7.

The two remaining MAC class instructions, CLR and MOVSAC, are useful for initiating or completinga series of MAC or EDAC instructions and do not use the multiplier. CLR has the ability to clearAccumulator A or B, prefetch two values from data memory and store the contents of the otheraccumulator. Similarly, MOVSAC has the ability to prefetch two values from data memory and storethe contents of either accumulator.

4.14.4 MAC Write BackThe write back ability of the MAC class of DSP instructions facilitates efficient processing ofalgorithms. This feature allows one mathematical operation to be performed with oneaccumulator, and the rounded contents of the other accumulator to be stored in the same cycle.As indicated in Table 4-9, register W13 is assigned for performing the write back, and twoAddressing modes are supported: Direct and Indirect with Post-Increment.

The CLR, MOVSAC and MSC instructions support accumulator Write Back, while the ED, EDAC,MPY and MPY.N instructions do not support accumulator Write Back. The MAC instruction, whichmultiplies two working registers which are not the same, also supports accumulator Write Back.However, the square and accumulate MAC instruction does not support accumulator Write Back(see Table 4-11).

4.14.5 MAC SyntaxThe syntax of the MAC class of instructions can have several formats, which depend on theinstruction type and the operation it is performing, with respect to prefetches and accumulatorWrite Back. With the exception of the CLR and MOVSAC instructions, all MAC class instructionsmust specify a target accumulator along with two multiplicands, as shown in Example 4-19.

Example 4-19: Base MAC Syntax

Multiply W7*W7, Accumulate to ACCB

; MAC with no prefetchMAC W4*W5, A

; MAC with no prefetchMAC W7*W7, B



If a prefetch is used in the instruction, the assembler is capable of discriminating the X or Y dataprefetch based on the register used for the effective address. [W8] or [W9] specifies the Xprefetch and [W10] or [W11] specifies the Y prefetch. Brackets around the working register arerequired in the syntax, and they designate that indirect addressing is used to perform theprefetch. When address modification is used, it must be specified using a minus-equals orplus-equals “C”-like syntax (i.e., “[W8] – = 2” or “[W8] + = 6”). When Register Offset Addressingis used for the prefetch, W12 is placed inside the brackets ([W9 + W12] for X prefetches and [W11+ W12] for Y prefetches). Each prefetch operation must also specify a prefetch destinationregister (W4-W7). In the instruction syntax, the destination register appears before the prefetch register. Legal forms of prefetch are shown in Example 4-20.

Example 4-20: MAC Prefetch Syntax

If an accumulator Write Back is used in the instruction, it is specified last. The Write Back mustuse the W13 register, and allowable forms for the Write Back are “W13” for direct addressing and“[W13] + = 2” for indirect addressing with post-increment. By definition, the accumulator not usedin the mathematical operation is stored, so the Write Back accumulator is not specified in theinstruction. Legal forms of accumulator Write Back (WB) are shown in Example 4-21.

X([W8]+=2)→ W5

ACCA=ACCA+W5*W6

; MAC with X only prefetch

MAC W5*W6, A, [W8]+=2, W5

Y([W11+W12])→ W5

ACCB=ACCB+W5*W5

; MAC with Y only prefetch

MAC W5*W5, B, [W11+W12], W5

X([W9])→ W6

ACCB=ACCB+W6*W7

Y([W10]+=4)→ W7

; MAC with X/Y prefetchMAC W6*W7, B, [W9], W6, [W10]+=4, W7



Details

4

Example 4-21: MAC Accumulator WB Syntax

Putting it all together, an MSC instruction which performs two prefetches and a write back isshown in Example 4-22.

Example 4-22: MSC Instruction with Two Prefetches and Accumulator Write Back

ACCB → W13

0 → ACCA

; CLR with direct WB of ACCB

CLR A, W13

ACCB → [W13]+=2

ACCA=ACCA+W4*W5

; MAC with indirect WB of ACCB

MAC W4*W5, A [W13]+=2

Y([W10]+=2)→ W4

ACCB=ACCB+W4*W5

ACCA → W13

; MAC with Y prefetch, direct WB of ACCA

MAC W4*W5, B, [W10]+=2, W4, W13

ACCB=ACCB-W6*W7

X([W8]+=2)→W6

Y([W10]-=6)→W7

ACCA→[W13]+=2

; MSC with X/Y prefetch, indirect WB of ACCA

MSC W6*W7, B, [W8]+=2, W6, [W10]-=6, W7 [W13]+=2



4.15 DSP ACCUMULATOR INSTRUCTIONS (dsPIC30F AND dsPIC33F DEVICES)

The DSP Accumulator instructions do not have prefetch or accumulator WB ability, but they doprovide the ability to add, negate, shift, load and store the contents of either 40-bit Accumulator.In addition, the ADD and SUB instructions allow the two accumulators to be added or subtractedfrom each other. DSP Accumulator instructions are shown in Table 4-12 and instruction detailsare provided in Section 5. “Instruction Descriptions”.

Table 4-12: DSP Accumulator Instructions

Instruction Description Accumulator WB?

ADD Add accumulators NoADD 16-bit signed accumulator add NoLAC Load accumulator NoNEG Negate accumulator NoSAC Store accumulator NoSAC.R Store rounded accumulator NoSFTAC Arithmetic shift accumulator by Literal NoSFTAC Arithmetic shift accumulator by (Wn) NoSUB Subtract accumulators No



Details

4

4.16 SCALING DATA WITH THE FBCL INSTRUCTION (dsPIC30F AND dsPIC33F DEVICES)

To minimize quantization errors that are associated with data processing using DSP instructions,it is important to utilize the complete numerical result of the operations. This may require scalingdata up to avoid underflow (i.e., when processing data from a 12-bit ADC), or scaling data downto avoid overflow (i.e., when sending data to a 10-bit DAC). The scaling, which must beperformed to minimize quantization error, depends on the dynamic range of the input data whichis operated on, and the required dynamic range of the output data. At times, these conditionsmay be known beforehand and fixed scaling may be employed. In other cases, scaling conditionsmay not be fixed or known, and then dynamic scaling must be used to process data.

The FBCL instruction (Find First Bit Change Left) can efficiently be used to perform dynamicscaling, because it determines the exponent of a value. A fixed point or integer value’s exponentrepresents the amount which the value may be shifted before overflowing. This information isvaluable, because it may be used to bring the data value to “full scale”, meaning that its numericrepresentation utilizes all the bits of the register it is stored in.

The FBCL instruction determines the exponent of a word by detecting the first bit change startingfrom the value’s sign bit and working towards the LSB. Since the dsPIC DSC device’s barrelshifter uses negative values to specify a left shift, the FBCL instruction returns the negatedexponent of a value. If the value is being scaled up, this allows the ensuing shift to be performedimmediately with the value returned by FBCL. Additionally, since the FBCL instruction onlyoperates on signed quantities, FBCL produces results in the range of -15:0. When the FBCLinstruction returns ‘0’, it indicates that the value is already at full scale. When the instructionreturns -15, it indicates that the value cannot be scaled (as is the case with 0x0 and 0xFFFF).Table 4-13 shows word data with various dynamic ranges, their exponents, and the value afterscaling each data to maximize the dynamic range. Example 4-23 shows how the FBCLinstruction may be used for block processing.

Table 4-13: Scaling Examples

As a practical example, assume that block processing is performed on a sequence of data withvery low dynamic range stored in 1.15 fractional format. To minimize quantization errors, the datamay be scaled up to prevent any quantization loss which may occur as it is processed. The FBCLinstruction can be executed on the sample with the largest magnitude to determine the optimalscaling value for processing the data. Note that scaling the data up is performed by left shiftingthe data. This is demonstrated with the code snippet below.

Word Value Exponent Full Scale Value(Word Value << Exponent)

0x0001 14 0x40000x0002 13 0x40000x0004 12 0x40000x0100 6 0x40000x01FF 6 0x7FC00x0806 3 0x40300x2007 1 0x400E0x4800 0 0x48000x7000 0 0x70000x8000 0 0x80000x900A 0 0x900A0xE001 2 0x80040xFF07 7 0x8380

Note: For the word values 0x0000 and 0xFFFF, the FBCL instruction returns -15.



Example 4-23: Scaling with FBCL; assume W0 contains the largest absolute value of the data block; assume W4 points to the beginning of the data block; assume the block of data contains BLOCK_SIZE words

; determine the exponent to use for scalingFBCL W0, W2 ; store exponent in W2

; scale the entire data block before processingDO #(BLOCK_SIZE-1), SCALELAC [W4], A ; move the next data sample to ACCASFTAC A, W2 ; shift ACCA by W2 bits

SCALE: SAC A, [W4++] ; store scaled input (overwrite original)

; now process the data; (processing block goes here)



Details

4

4.17 NORMALIZING THE ACCUMULATOR WITH THE FBCL INSTRUCTION (dsPIC30F AND dsPIC33F DEVICES)

The process of scaling a quantized value for its maximum dynamic range is known asnormalization (the data in the third column in Table 4-13 contains normalized data). Accumulatornormalization is a technique used to ensure that the accumulator is properly aligned beforestoring data from the accumulator, and the FBCL instruction facilitates this function.

The two 40-bit accumulators each have 8 guard bits from the ACCxU register, which expands thedynamic range of the accumulators from 1.31 to 9.31, when operating in Super Saturation mode(see 4.11.1 “Integer and Fractional Data”). However, even in Super Saturation mode, the StoreRounded Accumulator (SAC.R) instruction only stores 16-bit data (in 1.15 format) from ACCxH,as described in 4.12 “Accumulator Usage (dsPIC30F and dsPIC33F Devices)”. Under certainconditions, this may pose a problem.

Proper data alignment for storing the contents of the accumulator may be achieved by scalingthe accumulator down if ACCxU is in use, or scaling the accumulator up if all of the ACCxH bitsare not being used. To perform such scaling, the FBCL instruction must operate on the ACCxUbyte and it must operate on the ACCxH word. If a shift is required, the ALU’s 40-bit shifter isemployed, using the SFTAC instruction to perform the scaling. Example 4-24 contains a codesnippet for accumulator normalization.

Example 4-24: Normalizing with FBCL; assume an operation in ACCA has just completed (SR intact); assume the processor is in super saturation mode; assume ACCAH is defined to be the address of ACCAH (0x24)

MOV #ACCAH, W5 ; W5 points to ACCAHBRA OA, FBCL_GUARD ; if overflow we right shift

FBCL_HI:FBCL [W5], W0 ; extract exponent for left shiftBRA SHIFT_ACC ; branch to the shift

FBCL_GUARD:FBCL [++W5], W0 ; extract exponent for right shiftADD.B W0, #15, W0 ; adjust the sign for right shift

SHIFT_ACC:SFTAC A, W0 ; shift ACCA to normalize



NOTES:


Section 5. Instruction Descriptions

Instruction D

escriptions

5


5.1 Instruction Symbols......................................................................................................... 845.2 Instruction Encoding Field Descriptors Introduction........................................................ 845.3 Instruction Description Example ..................................................................................... 885.4 Instruction Descriptions................................................................................................... 89



5.1 Instruction SymbolsAll the symbols used in Section 5.4 “Instruction Descriptions” are listed in Table 1-2.

5.2 Instruction Encoding Field Descriptors IntroductionAll instruction encoding field descriptors used in Section 5.4 “Instruction Descriptions” areshown in Table 5-2 through Table 5-12.

Table 5-1: Instruction Encoding Field Descriptors Field Description

A(1) Accumulator selection bit: 0 = ACCA; 1 = CCB

aa(1) Accumulator Write Back mode (see Table 5-12)

B Byte mode selection bit: 0 = word operation; 1 = byte operationbbbb 4-bit bit position select: 0000 = LSB; 1111 = MSB

D Destination address bit: 0 = result stored in WREG;1 = result stored in file register

dddd Wd destination register select: 0000 = W0; 1111 = W15f ffff ffff ffff 13-bit register file address (0x0000 to 0x1FFF)

fff ffff ffff ffff 15-bit register file word address (implied 0 LSB)(0x0000 to 0xFFFE)

ffff ffff ffff ffff 16-bit register file byte address (0x0000 to 0xFFFF)ggg Register Offset Addressing mode for Ws source register

(see Table 5-4)hhh Register Offset Addressing mode for Wd destination register

(see Table 5-5)

iiii(1) Prefetch X Operation (see Table 5-6)

jjjj(1) Prefetch Y Operation (see Table 5-8)

k 1-bit literal field, constant data or expressionkkkk 4-bit literal field, constant data or expression

kk kkkk 6-bit literal field, constant data or expressionkkkk kkkk 8-bit literal field, constant data or expression

kk kkkk kkkk 10-bit literal field, constant data or expressionkk kkkk kkkk kkkk 14-bit literal field, constant data or expression

kkkk kkkk kkkk kkkk 16-bit literal field, constant data or expressionmm Multiplier source select with same working registers

(see Table 5-10)mmm Multiplier source select with different working registers

(see Table 5-11)nnnn nnnn nnnn nnn0 nnn nnnn

23-bit program address for CALL and GOTO instructions

nnnn nnnn nnnn nnnn 16-bit program offset field for relative branch/call instructionsppp Addressing mode for Ws source register (see Table 5-2)qqq Addressing mode for Wd destination register (see Table 5-3)

rrrr Barrel shift countssss Ws source register select: 0000 = W0; 1111 = W15tttt Dividend select, most significant wordvvvv Dividend select, least significant word

W Double Word mode selection bit: 0 = word operation;1 = double word operation

wwww Wb base register select: 0000 = W0; 1111 = W15xx(1) Prefetch X Destination (see Table 5-7)

xxxx xxxx xxxx xxxx 16-bit unused field (don’t care)yy(1) Prefetch Y Destination (see Table 5-9)

z Bit test destination: 0 = C flag bit; 1 = Z flag bit Note 1: This field is only available in dsPIC30F and dsPIC33F devices.


Section 5. Instruction DescriptionsInstruction

Descriptions

5

Table 5-2: Addressing Modes for Ws Source Register

Table 5-3: Addressing Modes for Wd Destination Register

Table 5-4: Offset Addressing Modes for Ws Source Register (with Register Offset)

Table 5-5: Offset Addressing Modes for Wd Destination Register(with Register Offset)

ppp Addressing Mode Source Operand000 Register Direct Ws001 Indirect [Ws]010 Indirect with Post-Decrement [Ws--]011 Indirect with Post-Increment [Ws++]100 Indirect with Pre-Decrement [--Ws]101 Indirect with Pre-Increment [++Ws]11x Unused

qqq Addressing Mode Destination Operand000 Register Direct Wd001 Indirect [Wd]010 Indirect with Post-Decrement [Wd--]011 Indirect with Post-Increment [Wd++]100 Indirect with Pre-Decrement [--Wd]101 Indirect with Pre-Increment [++Wd]11x Unused (an attempt to use this Addressing mode will force a RESET instruction)

ggg Addressing Mode Source Operand000 Register Direct Ws001 Indirect [Ws]010 Indirect with Post-Decrement [Ws--]011 Indirect with Post-Increment [Ws++]100 Indirect with Pre-Decrement [--Ws]101 Indirect with Pre-Increment [++Ws]11x Indirect with Register Offset [Ws+Wb]

hhh Addressing Mode Source Operand000 Register Direct Wd001 Indirect [Wd]010 Indirect with Post-Decrement [Wd--]011 Indirect with Post-Increment [Wd++]100 Indirect with Pre-Decrement [--Wd]101 Indirect with Pre-Increment [++Wd]11x Indirect with Register Offset [Wd+Wb]



Table 5-6: X Data Space Prefetch Operation (dsPIC30F and dsPIC33F)

Table 5-7: X Data Space Prefetch Destination (dsPIC30F and dsPIC33F)

Table 5-8: Y Data Space Prefetch Operation (dsPIC30F and dsPIC33F)

iiii Operation0000 Wxd = [W8]0001 Wxd = [W8], W8 = W8 + 20010 Wxd = [W8], W8 = W8 + 40011 Wxd = [W8], W8 = W8 + 60100 No Prefetch for X Data Space0101 Wxd = [W8], W8 = W8 – 60110 Wxd = [W8], W8 = W8 – 40111 Wxd = [W8], W8 = W8 – 21000 Wxd = [W9]1001 Wxd = [W9], W9 = W9 + 21010 Wxd = [W9], W9 = W9 + 41011 Wxd = [W9], W9 = W9 + 61100 Wxd = [W9 + W12]1101 Wxd = [W9], W9 = W9 – 61110 Wxd = [W9], W9 = W9 – 41111 Wxd = [W9], W9 = W9 – 2

xx Wxd00 W401 W510 W611 W7

jjjj Operation0000 Wyd = [W10]0001 Wyd = [W10], W10 = W10 + 20010 Wyd = [W10], W10 = W10 + 40011 Wyd = [W10], W10 = W10 + 60100 No Prefetch for Y Data Space0101 Wyd = [W10], W10 = W10 – 60110 Wyd = [W10], W10 = W10 – 40111 Wyd = [W10], W10 = W10 – 21000 Wyd = [W11]1001 Wyd = [W11], W11 = W11 + 21010 Wyd = [W11], W11 = W11 + 41011 Wyd = [W11], W11 = W11 + 61100 Wyd = [W11 + W12]1101 Wyd = [W11], W11 = W11 – 61110 Wyd = [W11], W11 = W11 – 41111 Wyd = [W11], W11 = W11 – 2



Descriptions

5

Table 5-9: Y Data Space Prefetch Destination (dsPIC30F and dsPIC33F)

Table 5-10: MAC or MPY Source Operands (Same Working Register) (dsPIC30F and dsPIC33F)

Table 5-11: MAC or MPY Source Operands (Different Working Register) (dsPIC30F and dsPIC33F)

Table 5-12: MAC Accumulator Write Back Selection (dsPIC30F and dsPIC33F)

yy Wyd00 W401 W510 W611 W7

mm Multiplicands00 W4 * W401 W5 * W510 W6 * W611 W7 * W7

mmm Multiplicands000 W4 * W5001 W4 * W6010 W4 * W7011 Invalid100 W5 * W6101 W5 * W7110 W6 * W7111 Invalid

aa Write Back Selection00 W13 = Other Accumulator (Direct Addressing)01 [W13] + = 2 = Other Accumulator (Indirect Addressing with Post-Increment)10 No Write Back11 Invalid



5.3 Instruction Description ExampleThe example description below is for the fictitious instruction FOO. The following exampleinstruction was created to demonstrate how the table fields (syntax, operands, operation, etc.)are used to describe the instructions presented in Section 5.4 “Instruction Descriptions”.

FOO The Header field summarizes what the instruction does

Implemented in: PIC24F PIC24H dsPIC30F dsPIC33F

X X

Cells marked with an ‘X’ indicate the instruction is implemented for that device family.

Syntax: The Syntax field consists of an optional label, the instruction mnemonic, any optional extensions which exist for the instruction and the operands for the instruction. Most instructions support more than one operand variant to support the various dsPIC30F/dsPIC33F Addressing modes. In these circumstances, all possible instruction operands are listed beneath each other (as in the case of op2a, op2b and op2c above). Optional operands are enclosed in braces.

Operands: The Operands field describes the set of values which each of the operands may take. Operands may be accumulator registers, file registers, literal constants (signed or unsigned), or working registers.

Operation: The Operation field summarizes the operation performed by the instruction.

Status Affected: The Status Affected field describes which bits of the STATUS Register are affected by the instruction. Status bits are listed by bit position in descending order.

Encoding: The Encoding field shows how the instruction is bit encoded. Individual bit fields are explained in the Description field, and complete encoding details are provided in Table 5.2.

Description: The Description field describes in detail the operation performed by the instruction. A key for the encoding bits is also provided.

Words: The Words field contains the number of program words that are used to store the instruction in memory.

Cycles: The Cycles field contains the number of instruction cycles that are required to execute the instruction.

Examples: The Examples field contains examples that demonstrate how the instruction operates. “Before” and “After” register snapshots are provided, which allow the user to clearly understand what operation the instruction performs.



Descriptions

5

5.4 Instruction Descriptions

ADD Add f to WREG


X X X X

Syntax: {label:} ADD{.B} f {,WREG}

Operands: f ∈ [0 ... 8191]

Operation: (f) + (WREG) → destination designated by D

Status Affected: DC, N, OV, Z, C

Encoding: 1011 0100 0BDf ffff ffff ffff

Description: Add the contents of the default working register WREG to the contents of the file register, and place the result in the destination register. The optional WREG operand determines the destination register. If WREG is specified, the result is stored in WREG. If WREG is not specified, the result is stored in the file register.

The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).The ‘f’ bits select the address of the file register.

Note 1: The extension .B in the instruction denotes a byte operationrather than a word operation. You may use a .W extension todenote a word operation, but it is not required.

2: The WREG is set to working register W0.

Words: 1

Cycles: 1

Example 1: ADD.B RAM100 ; Add WREG to RAM100 (Byte mode)

Before Instruction

AfterInstruction

WREG CC80 WREG CC80 RAM100 FFC0 RAM100 FF40

SR 0000 SR 0005 (OV, C = 1)

Example 2: ADD RAM200, WREG ; Add RAM200 to WREG (Word mode)

Before Instruction

AfterInstruction

WREG CC80 WREG CC40 RAM200 FFC0 RAM200 FFC0

SR 0000 SR 0001 (C = 1)



ADD Add Literal to Wn


X X X X

Syntax: {label:} ADD{.B} #lit10, Wn

Operands: lit10 ∈ [0 ... 255] for byte operationlit10 ∈ [0 ... 1023] for word operationWn ∈ [W0 ... W15]

Operation: lit10 + (Wn) → Wn


Encoding: 1011 0000 0Bkk kkkk kkkk dddd

Description: Add the 10-bit unsigned literal operand to the contents of the working register Wn, and place the result back into the working register Wn.

The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘k’ bits specify the literal operand.The ‘d’ bits select the address of the working register.


2: For byte operations, the literal must be specified as an unsignedvalue [0:255]. See Section 4.6 “Using 10-bit Literal Operands”for information on using 10-bit literal operands in Byte mode.

Words: 1

Cycles: 1

Example 1: ADD.B #0xFF, W7 ; Add -1 to W7 (Byte mode)

Before Instruction

AfterInstruction

W7 12C0 W7 12BFSR 0000 SR 0009 (N, C = 1)

Example 2: ADD #0xFF, W1 ; Add 255 to W1 (Word mode)

Before Instruction

AfterInstruction

W1 12C0 W1 13BFSR 0000 SR 0000



Descriptions

5

ADD Add Wb to Short Literal


X X X X

Syntax: {label:} ADD{.B} Wb, #lit5, Wd

[Wd]

[Wd++]

[Wd--]

[++Wd]

[--Wd]

Operands: Wb ∈ [W0 ... W15]lit5 ∈ [0 ... 31]Wd ∈ [W0 ... W15]

Operation: (Wb) + lit5 → Wd


Encoding: 0100 0www wBqq qddd d11k kkkk

Description: Add the contents of the base register Wb to the 5-bit unsigned short literal operand, and place the result in the destination register Wd. Register direct addressing must be used for Wb. Either register direct or indirect addressing may be used for Wd.

The ‘w’ bits select the address of the base register.The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘q’ bits select the destination Address mode.The ‘d’ bits select the destination register.The ‘k’ bits provide the literal operand, a five-bit integer number.

Note: The extension .B in the instruction denotes a byte operationrather than a word operation. You may use a .W extension todenote a word operation, but it is not required.

Words: 1

Cycles: 1

Example 1: ADD.B W0, #0x1F, W7 ; Add W0 and 31 (Byte mode); Store the result in W7

Before Instruction

AfterInstruction

W0 2290 W0 2290W7 12C0 W7 12AFSR 0000 SR 0008 (N = 1)



Example 2: ADD W3, #0x6, [--W4] ; Add W3 and 6 (Word mode); Store the result in [--W4]

Before Instruction

AfterInstruction

W3 6006 W3 6006W4 1000 W4 0FFE

Data 0FFE DDEE Data 0FFE 600CData 1000 DDEE Data 1000 DDEE

SR 0000 SR 0000



Descriptions

5

ADD Add Wb to Ws


X X X X

Syntax: {label:} ADD{.B} Wb, Ws, Wd

[Ws], [Wd]

[Ws++], [Wd++]

[Ws--], [Wd--]

[++Ws], [++Wd]

[--Ws], [--Wd]

Operands: Wb ∈ [W0 ... W15]Ws ∈ [W0 ... W15]Wd ∈ [W0 ... W15]

Operation: (Wb) + (Ws) → Wd


Encoding: 0100 0www wBqq qddd dppp ssss

Description: Add the contents of the source register Ws and the contents of the base register Wb, and place the result in the destination register Wd. Register direct addressing must be used for Wb. Either register direct or indirect addressing may be used for Ws and Wd.

The ‘w’ bits select the address of the base register.The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘q’ bits select the destination Address mode.The ‘d’ bits select the destination register.The ‘p’ bits select the source Address mode.The ‘s’ bits select the source register.


Words: 1

Cycles: 1

Example 1: ADD.B W5, W6, W7 ; Add W5 to W6, store result in W7; (Byte mode)

Before Instruction

AfterInstruction

W5 AB00 W5 AB00W6 0030 W6 0030W7 FFFF W7 FF30SR 0000 SR 0000



Example 2: ADD W5, W6, W7 ; Add W5 to W6, store result in W7; (Word mode)

Before Instruction

AfterInstruction

W5 AB00 W5 AB00W6 0030 W6 0030W7 FFFF W7 AB30SR 0000 SR 0008 (N = 1)



Descriptions

5

ADD Add Accumulators


X X

Syntax: {label:} ADD Acc

Operands: Acc ∈ [A,B]

Operation: If (Acc = A): (ACCA) + (ACCB) → ACCAElse: (ACCA) + (ACCB) → ACCB

Status Affected: OA, OB, OAB, SA, SB, SAB

Encoding: 1100 1011 A000 0000 0000 0000

Description: Add the contents of Accumulator A to the contents of Accumulator B and place the result in the selected accumulator. This instruction performs a 40-bit addition.

The ‘A’ bit specifies the destination accumulator.

Words: 1

Cycles: 1

Example 1: ADD A ; Add ACCB to ACCA

Before Instruction

After Instruction

ACCA 00 0022 3300 ACCA 00 1855 7858ACCB 00 1833 4558 ACCB 00 1833 4558

SR 0000 SR 0000

Example 2: ADD B ; Add ACCA to ACCB; Assume Super Saturation mode enabled; (ACCSAT = 1, SATA = 1, SATB = 1)

Before Instruction

AfterInstruction

ACCA 00 E111 2222 ACCA 00 E111 2222ACCB 00 7654 3210 ACCB 01 5765 5432

SR 0000 SR 4800 (OB, OAB = 1)



ADD 16-Bit Signed Add to Accumulator


X X

Syntax: {label:} ADD Ws, {#Slit4,} Acc

[Ws],

[Ws++],

[Ws--],

[--Ws],

[++Ws],

[Ws+Wb],

Operands: Ws ∈ [W0 ... W15]Wb ∈ [W0 ... W15]Slit4 ∈ [-8 ... +7]Acc ∈ [A,B]

Operation: ShiftSlit4(Extend(Ws)) + (Acc) → Acc


Encoding: 1100 1001 Awww wrrr rggg ssss

Description: Add a 16-bit value specified by the source working register to the most significant word of the selected accumulator. The source operand may specify the direct contents of a working register or an effective address. The value specified is added to the most significant word of the accumulator by sign-extending and zero backfilling the source operand prior to the operation. The value added to the accumulator may also be shifted by a 4-bit signed literal before the addition is made.

The ‘A’ bit specifies the destination accumulator.The ‘w’ bits specify the offset register Wb.The ‘r’ bits encode the optional shift.The ‘g’ bits select the source Address mode.The ‘s’ bits specify the source register Ws.

Note: Positive values of operand Slit4 represent an arithmetic shift rightand negative values of operand Slit4 represent an arithmetic shiftleft. The contents of the source register are not affected by Slit4.

Words: 1Cycles: 1

Example 1: ADD W0, #2, A ; Add W0 right-shifted by 2 to ACCA

Before Instruction

After Instruction

W0 8000 W0 8000ACCA 00 7000 0000 ACCA 00 5000 0000

SR 0000 SR 0000



Descriptions

5

Example 2: ADD [W5++], A ; Add the effective value of W5 to ACCA; Post-increment W5

Before Instruction

After Instruction

W5 2000 W5 2002ACCA 00 0067 2345 ACCA 00 5067 2345

Data 2000 5000 Data 2000 5000SR 0000 SR 0000



ADDC Add f to WREG with Carry


X X X X

Syntax: {label:} ADDC{.B} f {,WREG}

Operands: f ∈ [0 ... 8191]

Operation: (f) + (WREG) + (C) → destination designated by D



Description: Add the contents of the default working register WREG, the contents of the file register and the Carry bit and place the result in the destination register. The optional WREG operand determines the destination register. If WREG is specified, the result is stored in WREG. If WREG is not specified, the result is stored in the file register.



2: The WREG is set to working register W0. 3: The Z flag is “sticky” for ADDC, CPB, SUBB and SUBBR. These

instructions can only clear Z.

Words: 1

Cycles: 1

Example 1: ADDC.B RAM100 ; Add WREG and C bit to RAM100; (Byte mode)

Before Instruction

AfterInstruction

WREG CC60 WREG CC60 RAM100 8006 RAM100 8067

SR 0001 (C=1) SR 0000

Example 2: ADDC RAM200, WREG ; Add RAM200 and C bit to the WREG; (Word mode)

Before Instruction

AfterInstruction

WREG 5600 WREG 8A01 RAM200 3400 RAM200 3400

SR 0001 (C=1) SR 000C (N, OV = 1)



Descriptions

5

ADDC Add Literal to Wn with Carry


X X X X

Syntax: {label:} ADDC{.B} #lit10, Wn


Operation: lit10 + (Wn) + (C) → Wn



Description: Add the 10-bit unsigned literal operand, the contents of the working register Wn and the Carry bit, and place the result back into the working register Wn.



2: For byte operations, the literal must be specified as anunsigned value [0:255]. See Section 4.6 “Using 10-bit LiteralOperands” for information on using 10-bit literal operands inByte mode.

3: The Z flag is “sticky” for ADDC, CPB, SUBB and SUBBR. Theseinstructions can only clear Z.

Words: 1

Cycles: 1

Example 1: ADDC.B #0xFF, W7 ; Add -1 and C bit to W7 (Byte mode)

Before Instruction

AfterInstruction

W7 12C0 W7 12BFSR 0000 (C = 0) SR 0009 (N,C = 1)

Example 2: ADDC #0xFF, W1 ; Add 255 and C bit to W1 (Word mode)

Before Instruction

AfterInstruction

W1 12C0 W1 13C0SR 0001 (C = 1) SR 0000



ADDC Add Wb to Short Literal with Carry


X X X X

Syntax: {label:} ADDC{.B} Wb, #lit5, Wd

[Wd]

[Wd++]

[Wd--]

[++Wd]

[--Wd]


Operation: (Wb) + lit5 + (C) → Wd Status Affected: DC, N, OV, Z, C


Description: Add the contents of the base register Wb, the 5-bit unsigned short literal operand and the Carry bit, and place the result in the destination register Wd. Register direct addressing must be used for Wb. Register direct or indirect addressing may be used for Wd.




Words: 1Cycles: 1

Example 1: ADDC.B W0, #0x1F, [W7] ; Add W0, 31 and C bit (Byte mode) ; Store the result in [W7]

Before Instruction

AfterInstruction

W0 CC80 W0 CC80W7 12C0 W7 12C0

Data 12C0 B000 Data 12C0 B09FSR 0000 (C = 0) SR 0008 (N = 1)



Descriptions

5

Example 2: ADDC W3, #0x6, [--W4] ; Add W3, 6 and C bit (Word mode); Store the result in [--W4]

Before Instruction

AfterInstruction

W3 6006 W3 6006W4 1000 W4 0FFE

Data 0FFE DDEE Data 0FFE 600DData 1000 DDEE Data 1000

SRDDEE

SR 0001 (C = 1) 0000



ADDC Add Wb to Ws with Carry


X X X X

Syntax: {label:} ADDC{.B} Wb, Ws, Wd

[Ws], [Wd]

[Ws++], [Wd++]

[Ws--], [Wd--]

[++Ws], [++Wd]

[--Ws], [--Wd]


Operation: (Wb) + (Ws) + (C) → Wd



Description: Add the contents of the source register Ws, the contents of the base register Wb and the Carry bit, and place the result in the destination register Wd. Register direct addressing must be used for Wb. Either register direct or indirect addressing may be used for Ws and Wd.




Words: 1

Cycles: 1

Example 1: ADDC.B W0,[W1++],[W2++] ; Add W0, [W1] and C bit (Byte mode); Store the result in [W2]; Post-increment W1, W2

Before Instruction

AfterInstruction

W0 CC20 W0 CC20W1 0800 W1 0801W2 1000 W2 1001

Data 0800 AB25 Data 0800 AB25Data 1000 FFFF Data 1000 FF46

SR 0001 (C = 1) SR 0000



Descriptions

5

Example 2: ADDC W3,[W2++],[W1++] ; Add W3, [W2] and C bit (Word mode); Store the result in [W1]; Post-increment W1, W2

Before Instruction

AfterInstruction

W1 1000 W1 1002W2 2000 W2 2002W3 0180 W3 0180

Data 1000 8000 Data 1000 2681Data 2000 2500 Data 2000 2500

SR 0001 (C = 1) SR 0000



AND AND f and WREG


X X X X

Syntax: {label:} AND{.B} f {,WREG}

Operands: f ∈ [0 ... 8191]

Operation: (f).AND.(WREG) → destination designated by D

Status Affected: N, Z


Description: Compute the logical AND operation of the contents of the default working register WREG and the contents of the file register, and place the result in the destination register. The optional WREG operand determines the destination register. If WREG is specified, the result is stored in WREG.If WREG is not specified, the result is stored in the file register.




Words: 1

Cycles: 1

Example 1: AND.B RAM100 ; AND WREG to RAM100 (Byte mode)

Before Instruction

AfterInstruction

WREG CC80 WREG CC80 RAM100 FFC0 RAM100 FF80

SR 0000 SR 0008 (N = 1)

Example 2: AND RAM200, WREG ; AND RAM200 to WREG (Word mode)

Before Instruction

AfterInstruction

WREG CC80 WREG 0080 RAM200 12C0 RAM200 12C0

SR 0000 SR 0000



Descriptions

5

AND AND Literal and Wd


X X X X

Syntax: {label:} AND{.B} #lit10, Wn


Operation: lit10.AND.(Wn) → Wn



Description: Compute the logical AND operation of the 10-bit literal operand and the contents of the working register Wn and place the result back into the working register Wn. Register direct addressing must be used for Wn.



2: For byte operations, the literal must be specified as an unsignedvalue [0:255]. See Section 4.6 “Using 10-bit Literal Oper-ands” for information on using 10-bit literal operands in Bytemode.

Words: 1

Cycles: 1

Example 1: AND.B #0x83, W7 ; AND 0x83 to W7 (Byte mode)

Before Instruction

AfterInstruction

W7 12C0 W7 1280SR 0000 SR 0008 (N = 1)

Example 2: AND #0x333, W1 ; AND 0x333 to W1 (Word mode)

Before Instruction

AfterInstruction

W1 12D0 W1 0210SR 0000 SR 0000



AND AND Wb and Short Literal

Implemented in: PIC24F PIC24H dsPIC30F dsPIC33FX X X X

Syntax: {label:} AND{.B} Wb, #lit5, Wd[Wd][Wd++][Wd--][++Wd][--Wd]


Operation: (Wb).AND.lit5 → Wd Status Affected: N, ZEncoding: 0110 0www wBqq qddd d11k kkkk

Description: Compute the logical AND operation of the contents of the base register Wb and the 5-bit literal and place the result in the destination register Wd. Register direct addressing must be used for Wb. Either register direct or indirect addressing may be used for Wd.



Words: 1Cycles: 1

Example 1: AND.B W0,#0x3,[W1++] ; AND W0 and 0x3 (Byte mode); Store to [W1]; Post-increment W1

Before Instruction

AfterInstruction

W0 23A5 W0 23A5W1 2211 W1 2212

Data 2210 9999 Data 2210 0199SR 0000 SR 0000

Example 2: AND W0,#0x1F,W1 ; AND W0 and 0x1F (Word mode); Store to W1

Before Instruction

AfterInstruction

W0 6723 W0 6723W1 7878 W1 0003SR 0000 SR 0000



Descriptions

5

AND And Wb and Ws


X X X X

Syntax: {label:} AND{.B} Wb, Ws, Wd

[Ws], [Wd]

[Ws++], [Wd++]

[Ws--], [Wd--]

[++Ws], [++Wd]

[--Ws], [--Wd]


Operation: (Wb).AND.(Ws) → Wd Status Affected: N, Z


Description: Compute the logical AND operation of the contents of the source register Ws and the contents of the base register Wb, and place the result in the destination register Wd. Register direct addressing must be used for Wb. Either register direct or indirect addressing may be used for Ws and Wd.



Words: 1Cycles: 1

Example 1: AND.B W0, W1 [W2++] ; AND W0 and W1, and; store to [W2] (Byte mode); Post-increment W2

Before Instruction

AfterInstruction

W0 AA55 W0 AA55W1 2211 W1 2211W2 1001 W2 1002

Data 1000 FFFF Data 1000 11FFSR 0000 SR 0000



Example 2: AND W0, [W1++], W2 ; AND W0 and [W1], and; store to W2 (Word mode); Post-increment W1

Before Instruction

AfterInstruction

W0 AA55 W0 AA55W1 1000 W1 1002W2 55AA W2 2214

Data 1000 2634 Data 1000 2634SR 0000 SR 0000



Descriptions

5

ASR Arithmetic Shift Right f


X X X X

Syntax: {label:} ASR{.B} f {,WREG}

Operands: f ∈ [0 ... 8191]

Operation: For byte operation: (f<7>) → Dest<7> (f<7>) → Dest<6> (f<6:1>) → Dest<5:0> (f<0>) → CFor word operation: (f<15>) → Dest<15> (f<15>) → Dest<14> (f<14:1>) → Dest<13:0> (f<0>) → C

Status Affected: N, Z, C


Description: Shift the contents of the file register one bit to the right and place the result in the destination register. The Least Significant bit of the file register is shifted into the Carry bit of the STATUS Register. After the shift is per-formed, the result is sign-extended. The optional WREG operand deter-mines the destination register. If WREG is specified, the result is stored in WREG. If WREG is not specified, the result is stored in the file register.

The ‘B’ bit selects byte or word operation (‘0’ for word, ’1’ for byte).The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).The ‘f’ bits select the address of the file register.



Words: 1

Cycles: 1

C

Example 1: ASR.B RAM400, WREG ; ASR RAM400 and store to WREG ; (Byte mode)

Before Instruction

AfterInstruction

WREG 0600 WREG 0611RAM400 0823 RAM400 0823

SR 0000 SR 0001 (C = 1)



Example 2: ASR RAM200 ; ASR RAM200 (Word mode)

Before Instruction

AfterInstruction

RAM200 8009 RAM200 C004SR 0000 SR 0009 (N, C = 1)



Descriptions

5

ASR Arithmetic Shift Right Ws


X X X X

Syntax: {label:} ASR{.B} Ws, Wd

[Ws], [Wd]

[Ws++], [Wd++]

[Ws--], [Wd--]

[++Ws], [++Wd]

[--Ws], [--Wd]

Operands: Ws ∈ [W0 ... W15]Wd ∈ [W0 ... W15]

Operation: For byte operation: (Ws<7>) → Wd<7> (Ws<7>) → Wd<6> (Ws<6:1>) → Wd<5:0> (Ws<0>) → CFor word operation: (Ws<15>) → Wd<15> (Ws<15>) → Wd<14> (Ws<14:1>) → Wd<13:0> (Ws<0>) → C


Encoding: 1101 0001 1Bqq qddd dppp ssss

Description: Shift the contents of the source register Ws one bit to the right and place the result in the destination register Wd. The Least Significant bit of Ws is shifted into the Carry bit of the STATUS register. After the shift is performed, the result is sign-extended. Either register direct or indirect addressing may be used for Ws and Wd.

The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘q’ bits select the destination Address mode.The ‘d’ bits select the destination register.The ‘p’ bits select the source Address mode.The ‘s’ bits select the source register.


Words: 1

Cycles: 1

C



Example 1: ASR.B [W0++], [W1++] ; ASR [W0] and store to [W1] (Byte mode); Post-increment W0 and W1

BeforeInstruction

AfterInstruction

W0 0600 W0 0601W1 0801 W1 0802

Data 600 2366 Data 600 2366 Data 800 FFC0 Data 800 33C0

SR 0000 SR 0000

Example 2: ASR W12, W13 ; ASR W12 and store to W13 (Word mode)

Before Instruction

AfterInstruction

W12 AB01 W12 AB01W13 0322 W13 D580

SR 0000 SR 0009 (N, C = 1)



Descriptions

5

ASR Arithmetic Shift Right by Short Literal


X X X X

Syntax: {label:} ASR Wb, #lit4, Wnd

Operands: Wb ∈ [W0 ... W15]lit4 ∈ [0...15]Wnd ∈ [W0 ... W15]

Operation: lit4<3:0> → Shift_ValWb<15> → Wnd<15:15-Shift_Val + 1>Wb<15:Shift_Val> → Wnd<15-Shift_Val:0>


Encoding: 1101 1110 1www wddd d100 kkkk

Description: Arithmetic shift right the contents of the source register Wb by the 4-bit unsigned literal, and store the result in the destination register Wnd. After the shift is performed, the result is sign-extended. Direct addressing must be used for Wb and Wnd.

The ‘w’ bits select the address of the base register.The ‘d’ bits select the destination register.The ‘k’ bits provide the literal operand.

Note: This instruction operates in Word mode only.

Words: 1

Cycles: 1

Example 1: ASR W0, #0x4, W1 ; ASR W0 by 4 and store to W1

Before Instruction

AfterInstruction

W0 060F W0 060FW1 1234 W1 0060SR 0000 SR 0000

Example 2: ASR W0, #0x6, W1 ; ASR W0 by 6 and store to W1

Before Instruction

AfterInstruction

W0 80FF W0 80FFW1 0060 W1 FE03SR 0000 SR 0008 (N = 1)

Example 3: ASR W0, #0xF, W1 ; ASR W0 by 15 and store to W1

Before Instruction

AfterInstruction

W0 70FF W0 70FFW1 CC26 W1 0000SR 0000 SR 0002 (Z = 1)



ASR Arithmetic Shift Right by Wns


Syntax: {label:} ASR Wb, Wns, Wnd

Operands: Wb ∈ [W0 ... W15]Wns ∈ [W0 ...W15]Wnd ∈ [W0 ... W15]

Operation: Wns<3:0> → Shift_ValWb<15> → Wnd<15:15-Shift_Val + 1>Wb<15:Shift_Val> → Wnd<15-Shift_Val:0>

Status Affected: N, ZEncoding: 1101 1110 1www wddd d000 ssss

Description: Arithmetic shift right the contents of the source register Wb by the 4 Least Significant bits of Wns (up to 15 positions) and store the result in the destination register Wnd. After the shift is performed, the result is sign-extended. Direct addressing must be used for Wb, Wns and Wnd.The ‘w’ bits select the address of the base register.The ‘d’ bits select the destination register.The ‘s’ bits select the source register.

Note 1: This instruction operates in Word mode only.2: If Wns is greater than 15, Wnd = 0x0 if Wb is positive, and

Wnd = 0xFFFF if Wb is negative.Words: 1Cycles: 1

Example 1: ASR W0, W5, W6 ; ASR W0 by W5 and store to W6

Before Instruction

AfterInstruction

W0 80FF W0 80FFW5 0004 W5 0004W6 2633 W6 F80FSR 0000 SR 0000


Before Instruction

AfterInstruction

W0 6688 W0 6688W5 000A W5 000AW6 FF00 W6 0019SR 0000 SR 0000


Before Instruction

AfterInstruction

W11 8765 W11 8765W12 88E4 W12 88E4W13 A5A5 W13 F876

SR 0000 SR 0008 (N = 1)



Descriptions

5

BCLR Bit Clear f


X X X X

Syntax: {label:} BCLR{.B} f, #bit4

Operands: f ∈ [0 ... 8191] for byte operationf ∈ [0 ... 8190] (even only) for word operationbit4 ∈ [0 ... 7] for byte operationbit4 ∈ [0 ... 15] for byte operation

Operation: 0 → f<bit4>

Status Affected: None

Encoding: 1010 1001 bbbf ffff ffff fffb

Description: Clear the bit in the file register f specified by ‘bit4’. Bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 7 for byte operations, bit 15 for word operations).

The ‘b’ bits select value bit4 of the bit position to be cleared.The ‘f’ bits select the address of the file register.


2: When this instruction operates in Word mode, the file registeraddress must be word-aligned.

3: When this instruction operates in Byte mode, ‘bit4’ must bebetween 0 and 7.

Words: 1

Cycles: 1

Example 1: BCLR.B 0x800, #0x7 ; Clear bit 7 in 0x800

Before Instruction

AfterInstruction

Data 0800 66EF Data 0800 666FSR 0000 SR 0000

Example 2: BCLR 0x400, #0x9 ; Clear bit 9 in 0x400

Before Instruction

AfterInstruction

Data 0400 AA55 Data 0400 A855SR 0000 SR 0000



BCLR Bit Clear in Ws


X X X X

Syntax: {label:} BCLR{.B} Ws, #bit4

[Ws],

[Ws++],

[Ws--],

[++Ws],

[--Ws],

Operands: Ws ∈ [W0 ... W15]bit4 ∈ [0 ... 7] for byte operationbit4 ∈ [0 ... 15] for word operation

Operation: 0 → Ws<bit4>


Encoding: 1010 0001 bbbb 0B00 0ppp ssss

Description: Clear the bit in register Ws specified by ‘bit4’. Bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 7 for byte operations, bit 15 for word operations). Register direct or indi-rect addressing may be used for Ws.

The ‘b’ bits select value bit4 of the bit position to be cleared.The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘s’ bits select the source/destination register.The ‘p’ bits select the source Address mode.


2: When this instruction operates in Word mode, the sourceregister address must be word-aligned.


Words: 1

Cycles: 1

Example 1: BCLR.B W2, #0x2 ; Clear bit 3 in W2

Before Instruction

AfterInstruction

W2 F234 W2 F230SR 0000 SR 0000

Example 2: BCLR [W0++], #0x0 ; Clear bit 0 in [W0]; Post-increment W0

Before Instruction

AfterInstruction

W0 2300 W0 2302Data 2300 5607 Data 2300 5606

SR 0000 SR 0000



Descriptions

5

BRA Branch Unconditionally


Syntax: {label:} BRA Expr

Operands: Expr may be a label, absolute address or expression. Expr is resolved by the linker to a Slit16, where Slit16 ∈ [-32768 ... +32767].

Operation: (PC + 2) + 2 * Slit16 → PCNOP → Instruction Register

Status Affected: NoneEncoding: 0011 0111 nnnn nnnn nnnn nnnn

Description: The program will branch unconditionally, relative to the next PC. The offset of the branch is the two’s complement number ‘2 * Slit16’, which supports branches up to 32K instructions forward or backward. The Slit16 value is resolved by the linker from the supplied label, absolute address or expression. After the branch is taken, the new address will be (PC + 2) + 2 * Slit16, since the PC will have incremented to fetch the next instruction.The ‘n’ bits are a signed literal that specifies the number of program words offset from (PC + 2).

Words: 1Cycles: 2

Example 1: 002000 HERE: BRA THERE002002 . . .002004 . . .002006 . . .002008 . . .00200A THERE: . . .00200C . . .

; Branch to THERE

Before Instruction

After Instruction

PC 00 2000 PC 00 200ASR 0000 SR 0000

Example 2: 002000 HERE: BRA THERE+0x2002002 . . .002004 . . .002006 . . .002008 . . .00200A THERE: . . .00200C . . .

; Branch to THERE+0x2

Before Instruction

After Instruction

PC 00 2000 PC 00 200CSR 0000 SR 0000

Example 3: 002000 HERE: BRA 0x1366002002 . . .002004 . . .

; Branch to 0x1366

Before Instruction

After Instruction

PC 00 2000 PC 00 1366SR 0000 SR 0000



BRA Computed Branch


X X X X

Syntax: {label:} BRA Wn

Operands: Wn ∈ [W0 ... W15]

Operation: (PC + 2) + (2 * Wn) → PCNOP → Instruction Register


Encoding: 0000 0001 0110 0000 0000 ssss

Description: The program branches unconditionally, relative to the next PC. The offset of the branch is the sign-extended 17-bit value (2 * Wn), which supports branches up to 32K instructions forward or backward. After this instruction executes, the new PC will be (PC + 2) + 2 * Wn, since the PC will have incremented to fetch the next instruction.

The ‘s’ bits select the source register.

Words: 1

Cycles: 2

Example 1: 002000 HERE: BRA W7002002 . . . ... . . . ... . . .002108 . . .00210A TABLE7: . . .00210C . . .

; Branch forward (2+2*W7)

Before Instruction

After Instruction

PC 00 2000 PC 00 210AW7 0084 W7 0084 SR 0000 SR 0000



Descriptions

5

BRA C Branch if Carry


X X X X

Syntax: {label:} BRA C, Expr


Operation: Condition = CIf (Condition) (PC + 2) + 2 * Slit16 → PC NOP → Instruction Register


Encoding: 0011 0001 nnnn nnnn nnnn nnnn

Description: If the Carry flag bit is ‘1’, then the program will branch relative to the next PC. The offset of the branch is the two’s complement number ‘2 * Slit16’, which supports branches up to 32K instructions forward or backward. The Slit16 value is resolved by the linker from the supplied label, absolute address or expression.

If the branch is taken, the new address will be (PC + 2) + 2 * Slit16, since the PC will have incremented to fetch the next instruction. The instruction then becomes a two-cycle instruction, with a NOP executed in the second cycle.

The ‘n’ bits are a 16-bit signed literal that specify the offset from (PC + 2) in instruction words.

Words: 1

Cycles: 1 (2 if branch taken)

Example 1: 002000 HERE: BRA C, CARRY002002 NO_C: . . .002004 . . .002006 GOTO THERE002008 CARRY: . . .00200A . . .00200C THERE: . . .00200E . . .

; If C is set, branch to CARRY; Otherwise... continue

Before Instruction

After Instruction

PC 00 2000 PC 00 2008SR 0001 (C = 1) SR 0001 (C = 1)



Example 2: 002000 HERE: BRA C, CARRY002002 NO_C: ...002004 ...002006 GOTO THERE002008 CARRY: ...00200A ...00200C THERE: ...00200E ...


BeforeInstruction

AfterInstruction

PC 00 2000 PC 00 2002SR 0000 SR 0000

Example 3: 006230 HERE: BRA C, CARRY006232 NO_C: ...006234 ...006236 GOTO THERE006238 CARRY: ...00623A ...00623C THERE: ...00623E ...


Before Instruction

After Instruction

PC 00 6230 PC 00 6238SR 0001 (C = 1) SR 0001 (C = 1)

Example 4: 006230 START: ...006232 ...006234 CARRY: ...006236 ...006238 ...00623A ...00623C HERE: BRA C, CARRY00623E ...


Before Instruction

After Instruction

PC 00 623C PC 00 6234SR 0001 (C = 1) SR 0001 (C = 1)



Descriptions

5

BRA GE Branch if Signed Greater Than or Equal


Syntax: {label:} BRA GE, Expr


Operation: Condition = (N&&OV)||(!N&&!OV)If (Condition) (PC + 2) + 2 * Slit16 → PC NOP → Instruction Register


Description: If the logical expression (N&&OV)||(!N&&!OV) is true, then the program will branch relative to the next PC. The offset of the branch is the two’s complement number ‘2 * Slit16’, which supports branches up to 32K instructions forward or backward. The Slit16 value is resolved by the linker from the supplied label, absolute address or expression.



Note: The assembler will convert the specified label into the offset tobe used.

Words: 1Cycles: 1 (2 if branch taken)

Example 1: 007600 LOOP: . . .007602 . . .007604 . . .007606 . . .007608 HERE: BRA GE, LOOP00760A NO_GE: . . .

; If GE, branch to LOOP; Otherwise... continue

Before Instruction

After Instruction

PC 00 7608 PC 00 7600SR 0000 SR 0000

Example 2: 007600 LOOP: . . .007602 . . .007604 . . .007606 . . .007608 HERE: BRA GE, LOOP00760A NO_GE: . . .

; If GE, branch to LOOP; Otherwise... continue

Before Instruction

After Instruction

PC 00 7608 PC 00 760ASR 0008 (N = 1) SR 0008 (N = 1)



BRA GEU Branch if Unsigned Greater Than or Equal


X X X X

Syntax: {label:} BRA GEU, Expr

Operands: Expr may be a label, absolute address or expression. Expr is resolved by the linker to a Slit16 offset that supports an offset range of [-32768 ... +32767] program words.

Operation: Condition = CIf (Condition) (PC + 2) + 2 * Slit16 → PC NOP → Instruction Register



Description: If the Carry flag is ‘1’, then the program will branch relative to the next PC. The offset of the branch is the two’s complement number ‘2 * Slit16’, which supports branches up to 32K instructions forward or back-ward. The Slit16 value is resolved by the linker from the supplied label, absolute address or expression.



Note: This instruction is identical to the BRA C, Expr (Branch ifCarry) instruction and has the same encoding. It will reverseassemble as BRA C, Slit16.

Words: 1


Example 1: 002000 HERE: BRA GEU, BYPASS002002 NO_GEU: . . .002004 . . .002006 . . .002008 . . .00200A GOTO THERE00200C BYPASS: . . .00200E . . .

; If C is set, branch; to BYPASS; Otherwise... continue

Before Instruction

After Instruction

PC 00 2000 PC 00 200CSR 0001 (C = 1) SR 0001 (C = 1)



Descriptions

5

BRA GT Branch if Signed Greater Than


X X X X

Syntax: {label:} BRA GT, Expr


Operation: Condition = (!Z&&N&&OV)||(!Z&&!N&&!OV)If (Condition) (PC + 2) + 2 * Slit16 → PC NOP → Instruction Register



Description: If the logical expression (!Z&&N&&OV)||(!Z&&!N&&!OV) is true, then the program will branch relative to the next PC. The offset of the branch is the two’s complement number ‘2 * Slit16’, which supports branches up to 32K instructions forward or backward. The Slit16 value is resolved by the linker from the supplied label, absolute address or expression.



Words: 1


Example 1: 002000 HERE: BRA GT, BYPASS002002 NO_GT: . . .002004 . . .002006 . . .002008 . . .00200A GOTO THERE00200C BYPASS: . . .00200E . . .

; If GT, branch to BYPASS; Otherwise... continue

Before Instruction

After Instruction

PC 00 2000 PC 00 200CSR 0001 (C = 1) SR 0001 (C = 1)



BRA GTU Branch if Unsigned Greater Than


X X X X

Syntax: {label:} BRA GTU, Expr


Operation: Condition = (C&&!Z)If (Condition) (PC + 2) + 2 * Slit16 → PC NOP → Instruction Register



Description: If the logical expression (C&&!Z) is true, then the program will branch relative to the next PC. The offset of the branch is the two’s complement number ‘2 * Slit16’, which supports branches up to 32K instructions forward or backward. The Slit16 value is resolved by the linker from the supplied label, absolute address or expression.


The ‘n’ bits are a signed literal that specifies the number of instructions off-set from (PC + 2).

Words: 1


Example 1: 002000 HERE: BRA GTU, BYPASS002002 NO_GTU: . . .002004 . . .002006 . . .002008 . . .00200A GOTO THERE00200C BYPASS: . . .00200E . . .

; If GTU, branch to BYPASS; Otherwise... continue

Before Instruction

After Instruction

PC 00 2000 PC 00 200CSR 0001 (C = 1) SR 0001 (C = 1)



Descriptions

5

BRA LE Branch if Signed Less Than or Equal


X X X X

Syntax: {label:} BRA LE, Expr


Operation: Condition = Z||(N&&!OV)||(!N&&OV)If (Condition) (PC + 2) + 2 * Slit16 → PC NOP → Instruction Register



Description: If the logical expression (Z||(N&&!OV)||(!N&&OV)) is true, then the program will branch relative to the next PC. The offset of the branch is the two’s complement number ‘2 * Slit16’, which supports branches up to 32K instructions forward or backward. The Slit16 value is resolved by the linker from the supplied label, absolute address or expression.


The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC + 2).

Words: 1


Example 1: 002000 HERE: BRA LE, BYPASS002002 NO_LE: . . .002004 . . .002006 . . .002008 . . .00200A GOTO THERE00200C BYPASS: . . .00200E . . .

; If LE, branch to BYPASS; Otherwise... continue

Before Instruction

After Instruction

PC 00 2000 PC 00 2002SR 0001 (C = 1) SR 0001 (C = 1)



BRA LEU Branch if Unsigned Less Than or Equal


X X X X

Syntax: {label:} BRA LEU, Expr


Operation: Condition = !C||ZIf (Condition) (PC + 2) + 2 * Slit16 → PC NOP → Instruction Register



Description: If the logical expression (!C||Z) is true, then the program will branch relative to the next PC. The offset of the branch is the two’s complement number ‘2 * Slit16’, which supports branches up to 32K instructions for-ward or backward. The Slit16 value is resolved by the linker from the supplied label, absolute address or expression.



Words: 1


Example 1: 002000 HERE: BRA LEU, BYPASS002002 NO_LEU: . . .002004 . . .002006 . . .002008 . . .00200A GOTO THERE00200C BYPASS: . . .00200E . . .

; If LEU, branch to BYPASS; Otherwise... continue

Before Instruction

After Instruction

PC 00 2000 PC 00 200CSR 0001 (C = 1) SR 0001 (C = 1)



Descriptions

5

BRA LT Branch if Signed Less Than


X X X X

Syntax: {label:} BRA LT, Expr


Operation: Condition = (N&&!OV)||(!N&&OV)If (Condition) (PC + 2) + 2 * Slit16 → PC NOP → Instruction Register



Description: If the logical expression ( (N&&!OV)||(!N&&OV) ) is true, then the program will branch relative to the next PC. The offset of the branch is the two’s complement number ‘2 * Slit16’, which supports branches up to 32K instructions forward or backward. The Slit16 value is resolved by the linker from the supplied label, absolute address or expression.



Words: 1


Example 1: 002000 HERE: BRA LT, BYPASS002002 NO_LT: . . .002004 . . .002006 . . .002008 . . .00200A GOTO THERE00200C BYPASS: . . .00200E . . .

; If LT, branch to BYPASS; Otherwise... continue

Before Instruction

After Instruction

PC 00 2000 PC 00 2002SR 0001 (C = 1) SR 0001 (C = 1)



BRA LTU Branch if Unsigned Less Than


X X X X

Syntax: {label:} BRA LTU, Expr


Operation: Condition = !CIf (Condition) (PC + 2) + 2 * Slit16 → PC NOP → Instruction Register



Description: If the Carry flag is ‘0’, then the program will branch relative to the next PC. The offset of the branch is the two’s complement number ‘2 * Slit16’, which supports branches up to 32K instructions forward or backward. The Slit16 value is resolved by the linker from the supplied label, absolute address or expression.



Note: This instruction is identical to the BRA NC, Expr (Branch if NotCarry) instruction and has the same encoding. It will reverseassemble as BRA NC, Slit16.

Words: 1


Example 1: 002000 HERE: BRA LTU, BYPASS002002 NO_LTU: . . .002004 . . .002006 . . .002008 . . .00200A GOTO THERE00200C BYPASS: . . .00200E . . .

; If LTU, branch to BYPASS; Otherwise... continue

Before Instruction

After Instruction

PC 00 2000 PC 00 2002SR 0001 (C = 1) SR 0001 (C = 1)



Descriptions

5

BRA N Branch if Negative


X X X X

Syntax: {label:} BRA N, Expr


Operation: Condition = NIf (Condition) (PC + 2) + 2 * Slit16 → PC NOP → Instruction Register.



Description: If the Negative flag is ‘1’, then the program will branch relative to the next PC. The offset of the branch is the two’s complement number ‘2 * Slit16’, which supports branches up to 32K instructions forward or backward. The Slit16 value is resolved by the linker from the supplied label, absolute address or expression.



Words: 1


Example 1: 002000 HERE: BRA N, BYPASS002002 NO_N: . . .002004 . . .002006 . . .002008 . . .00200A GOTO THERE00200C BYPASS: . . .00200E . . .

; If N, branch to BYPASS; Otherwise... continue

Before Instruction

After Instruction

PC 00 2000 PC 00 200CSR 0008 (N = 1) SR 0008 (N = 1)



BRA NC Branch if Not Carry


X X X X

Syntax: {label:} BRA NC, Expr


Operation: Condition = !CIf (Condition) (PC + 2) + 2 * Slit16 → PC NOP → Instruction Register



Description: If the Carry flag is ‘0’, then the program will branch relative to the next PC. The offset of the branch is the two’s complement number ‘2 * Slit16’, which supports branches up to 32K instructions forward or backward. The Slit16 value is resolved by the linker from the supplied label, absolute address or expression.



Words: 1


Example 1: 002000 HERE: BRA NC, BYPASS002002 NO_NC: . . .002004 . . .002006 . . .002008 . . .00200A GOTO THERE00200C BYPASS: . . .00200E . . .

; If NC, branch to BYPASS; Otherwise... continue

Before Instruction

After Instruction

PC 00 2000 PC 00 2002SR 0001 (C = 1) SR 0001 (C = 1)



Descriptions

5

BRA NN Branch if Not Negative


X X X X

Syntax: {label:} BRA NN, Expr


Operation: Condition = !NIf (Condition) (PC + 2) + 2 * Slit16 → PC NOP → Instruction Register



Description: If the Negative flag is ‘0’, then the program will branch relative to the next PC. The offset of the branch is the two’s complement number ‘2 * Slit16’, which supports branches up to 32K instructions forward or backward. The Slit16 value is resolved by the linker from the supplied label, absolute address or expression.



Words: 1


Example 1: 002000 HERE: BRA NN, BYPASS002002 NO_NN: . . .002004 . . .002006 . . .002008 . . .00200A GOTO THERE00200C BYPASS: . . .00200E . . .

; If NN, branch to BYPASS; Otherwise... continue

Before Instruction

After Instruction

PC 00 2000 PC 00 200CSR 0000 SR 0000



BRA NOV Branch if Not Overflow


X X X X

Syntax: {label:} BRA NOV, Expr


Operation: Condition = !OVIf (Condition) (PC + 2) + 2 * Slit16 → PC NOP → Instruction Register



Description: If the Overflow flag is ‘0’, then the program will branch relative to the next PC. The offset of the branch is the two’s complement number ‘2 * Slit16’, which supports branches up to 32K instructions forward or backward. The Slit16 value is resolved by the linker from the supplied label, absolute address or expression.



Words: 1


Example 1: 002000 HERE: BRA NOV, BYPASS002002 NO_NOV: . . .002004 . . .002006 . . .002008 . . .00200A GOTO THERE00200C BYPASS: . . .00200E . . .

; If NOV, branch to BYPASS; Otherwise... continue

Before Instruction

After Instruction

PC 00 2000 PC 00 200CSR 0008 (N = 1) SR 0008 (N = 1)



Descriptions

5

BRA NZ Branch if Not Zero


X X X X

Syntax: {label:} BRA NZ, Expr


Operation: Condition = !ZIf (Condition) (PC + 2) + 2 * Slit16 → PC NOP → Instruction Register



Description: If the Z flag is ‘0’, then the program will branch relative to the next PC. The offset of the branch is the two’s complement number ‘2 * Slit16’, which supports branches up to 32K instructions forward or backward. The Slit16 value is resolved by the linker from the supplied label, absolute address or expression.



Words: 1


Example 1: 002000 HERE: BRA NZ, BYPASS002002 NO_NZ: . . .002004 . . .002006 . . .002008 . . .00200A GOTO THERE00200C BYPASS: . . .00200E . . .

; If NZ, branch to BYPASS; Otherwise... continue

Before Instruction

After Instruction

PC 00 2000 PC 00 2002SR 0002 (Z = 1) SR 0002 (Z = 1)



BRA OA Branch if Overflow Accumulator A


X X

Syntax: {label:} BRA OA, Expr


Operation: Condition = OAIf (Condition) (PC + 2) + 2 * Slit16 → PC NOP → Instruction Register



Description: If the Overflow Accumulator A flag is ‘1’, then the program will branch relative to the next PC. The offset of the branch is the two’s complement number ‘2 * Slit16’, which supports branches up to 32K instructions forward or backward. The Slit16 value is resolved by the linker from the supplied label, absolute address or expression.



Note: The assembler will convert the specified label into the offset to be used.

Words: 1


Example 1: 002000 HERE: BRA OA, BYPASS002002 NO_OA: . . .002004 . . .002006 . . .002008 . . .00200A GOTO THERE00200C BYPASS: . . .00200E . . .

; If OA, branch to BYPASS; Otherwise... continue

Before Instruction

After Instruction

PC 00 2000 PC 00 200CSR 8800 (OA, OAB = 1) SR 8800 (OA, OAB = 1)



Descriptions

5

BRA OB Branch if Overflow Accumulator B


X X

Syntax: {label:} BRA OB, Expr


Operation: Condition = OBIf (Condition) (PC + 2) + 2 * Slit16 → PC NOP → Instruction Register



Description: If the Overflow Accumulator B flag is ‘1’, then the program will branch relative to the next PC. The offset of the branch is the two’s complement number ‘2 * Slit16’, which supports branches up to 32K instructions forward or backward. The Slit16 value is resolved by the linker from the supplied label, absolute address or expression.



Words: 1


Example 1: 002000 HERE: BRA OB, BYPASS002002 NO_OB: . . .002004 . . .002006 . . .002008 . . .00200A GOTO THERE00200C BYPASS: . . .00200E . . .

; If OB, branch to BYPASS; Otherwise... continue

Before Instruction

After Instruction

PC 00 2000 PC 00 2002SR 8800 (OA, OAB = 1) SR 8800 (OA, OAB = 1)



BRA OV Branch if Overflow


X X X X

Syntax: {label:} BRA OV, Expr


Operation: Condition = OVIf (Condition) (PC + 2) + 2 * Slit16 → PC NOP → Instruction Register



Description: If the Overflow flag is ‘1’, then the program will branch relative to the next PC. The offset of the branch is the two’s complement number ‘2 * Slit16’, which supports branches up to 32K instructions forward or backward. The Slit16 value is resolved by the linker from the supplied label, absolute address or expression.



Words: 1


Example 1: 002000 HERE: BRA OV, BYPASS002002 NO_OV . . .002004 . . .002006 . . .002008 . . .00200A GOTO THERE00200C BYPASS: . . .00200E . . .

; If OV, branch to BYPASS; Otherwise... continue

Before Instruction

After Instruction

PC 00 2000 PC 00 2002SR 0002 (Z = 1) SR 0002 (Z = 1)



Descriptions

5

BRA SA Branch if Saturation Accumulator A


X X

Syntax: {label:} BRA SA, Expr


Operation: Condition = SAIf (Condition) (PC + 2) + 2 * Slit16 → PC NOP → Instruction Register



Description: If the Saturation Accumulator A flag is ‘1’, then the program will branch relative to the next PC. The offset of the branch is the two’s complement number ‘2 * Slit16’, which supports branches up to 32K instructions for-ward or backward. The Slit16 value is resolved by the linker from the sup-plied label, absolute address or expression.



Words: 1


Example 1: 002000 HERE: BRA SA, BYPASS002002 NO_SA: . . .002004 . . .002006 . . .002008 . . .00200A GOTO THERE00200C BYPASS: . . .00200E . . .

; If SA, branch to BYPASS; Otherwise... continue

Before Instruction

After Instruction

PC 00 2000 PC 00 200CSR 2400 (SA, SAB = 1) SR 2400 (SA, SAB = 1)



BRA SB Branch if Saturation Accumulator B


X X

Syntax: {label:} BRA SB, Expr


Operation: Condition = SBif (Condition) (PC + 2) + 2 * Slit16→ PC NOP → Instruction Register



Description: If the Saturation Accumulator B flag is ‘1’, then the program will branch relative to the next PC. The offset of the branch is the two’s complement number ‘2 * Slit16’, which supports branches up to 32K instructions forward or backward. The Slit16 value is resolved by the linker from the supplied label, absolute address or expression.



Words: 1


Example 1: 002000 HERE: BRA SB, BYPASS002002 NO_SB: . . .002004 . . .002006 . . .002008 . . .00200A GOTO THERE00200C BYPASS: . . .00200E . . .

; If SB, branch to BYPASS; Otherwise... continue

Before Instruction

After Instruction

PC 00 2000 PC 00 2002SR 0000 SR 0000



Descriptions

5

BRA Z Branch if Zero


Syntax: {label:} BRA Z, Expr


Operation: Condition = Zif (Condition) (PC + 2) + 2 * Slit16 → PC NOP → Instruction Register


Description: If the Zero flag is ‘1’, then the program will branch relative to the next PC. The offset of the branch is the two’s complement number ‘2 * Slit16’, which supports branches up to 32K instructions forward or backward. The Slit16 value is resolved by the linker from the supplied label, absolute address or expression.



Words: 1Cycles: 1 (2 if branch taken)

Example 1: 002000 HERE: BRA Z, BYPASS002002 NO_Z: . . .002004 . . .002006 . . .002008 . . .00200A GOTO THERE00200C BYPASS: . . .00200E . . .

; If Z, branch to BYPASS; Otherwise... continue

Before Instruction

After Instruction

PC 00 2000 PC 00 200CSR 0002 (Z = 1) SR 0002 (Z = 1)



BSET Bit Set f


X X X X

Syntax: {label:} BSET{.B} f, #bit4

Operands: f ∈ [0 ... 8191] for byte operationf ∈ [0 ... 8190] (even only) for word operationbit4 ∈ [0 ... 7] for byte operationbit4 ∈ [0 ... 15] for word operation

Operation: 1 → f<bit4>



Description: Set the bit in the file register ‘f’ specified by ‘bit4’. Bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 7 for byte operations, bit 15 for word operations).

The ‘b’ bits select value bit4 of the bit position to be set.The ‘f’ bits select the address of the file register.




Words: 1

Cycles: 1

Example 1: BSET.B 0x601, #0x3 ; Set bit 3 in 0x601

Before Instruction

AfterInstruction

Data 0600 F234 Data 0600 FA34SR 0000 SR 0000

Example 2: BSET 0x444, #0xF ; Set bit 15 in 0x444

Before Instruction

AfterInstruction

Data 0444 5604 Data 0444 D604 SR 0000 SR 0000



Descriptions

5

BSET Bit Set in Ws


X X X X

Syntax: {label:} BSET{.B} Ws, #bit4

[Ws],

[Ws++],

[Ws--],

[++Ws],

[--Ws],


Operation: 1 → Ws<bit4>



Description: Set the bit in register Ws specified by ‘bit4’. Bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 7 for byte operations, bit 15 for word operations). Register direct or indirect addressing may be used for Ws.

The ‘b’ bits select value bit4 of the bit position to be cleared.The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘p’ bits select the source Address mode.The ‘s’ bits select the source/destination register.




Words: 1

Cycles: 1

Example 1: BSET.B W3, #0x7 ; Set bit 7 in W3

Before Instruction

AfterInstruction

W3 0026 W3 00A6SR 0000 SR 0000

Example 2: BSET [W4++], #0x0 ; Set bit 0 in [W4]; Post-increment W4

Before Instruction

AfterInstruction

W4 6700 W4 6702Data 6700 1734 Data 6700 1735

SR 0000 SR 0000



BSW Bit Write in Ws


X X X X

Syntax: {label:} BSW.C Ws, Wb

BSW.Z [Ws],

[Ws++],

[Ws--],

[++Ws],

[--Ws],

Operands: Ws ∈ [W0 ... W15]Wb ∈ [W0 ... W15]

Operation: For “.C” operation: C → Ws<(Wb)>For “.Z” operation (default): Z → Ws<(Wb)>


Encoding: 1010 1101 Zwww w000 0ppp ssss

Description: The (Wb) bit in register Ws is written with the value of the C or Z flag from the STATUS register. Bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 15) of the working register. Only the four Least Significant bits of Wb are used to determine the destination bit number. Register direct addressing must be used for Wb, and either register direct, or indirect addressing may be used for Ws.

The ‘Z’ bit selects the C or Z flag as source.The ‘w’ bits select the address of the bit select register.The ‘p’ bits select the source Address mode.The ‘s’ bits select the source register.

Note: This instruction only operates in Word mode. If no extension is provided, the “.Z” operation is assumed.

Words: 1

Cycles: 1

Example 1: BSW.C W2, W3 ; Set bit W3 in W2 to the value; of the C bit

Before Instruction

AfterInstruction

W2 F234 W2 7234W3 111F W3 111FSR 0002 (Z = 1, C = 0) SR 0002 (Z = 1, C = 0)



Descriptions

5

Example 2: BSW.Z W2, W3 ; Set bit W3 in W2 to the complement; of the Z bit

Before Instruction

AfterInstruction

W2 E235 W2 E234W3 0550 W3 0550SR 0002 (Z = 1, C = 0) SR 0002 (Z = 1, C = 0)

Example 3: BSW.C [++W0], W6 ; Set bit W6 in [W0++] to the value; of the C bit

Before Instruction

AfterInstruction

W0 1000 W0 1002W6 34A3 W6 34A3

Data 1002 2380 Data 1002 2388SR 0001 (Z = 0, C = 1) SR 0001 (Z = 0, C = 1)

Example 4: BSW [W1--], W5 ; Set bit W5 in [W1] to the; complement of the Z bit; Post-decrement W1

Before Instruction

AfterInstruction

W1 1000 W1 0FFEW5 888B W5 888B

Data 1000 C4DD Data 1000 CCDDSR 0001 (C = 1) SR 0001 (C = 1)



BTG Bit Toggle f


X X X X

Syntax: {label:} BTG{.B} f, #bit4


Operation: (f)<bit4> → (f)<bit4>



Description: Bit ‘bit4’ in file register ‘f’ is toggled (complemented). For the bit4 operand, bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 7 for byte operation, bit 15 for word operation) of the byte.

The ‘b’ bits select value bit4, the bit position to toggle.The ‘f’ bits select the address of the file register.




Words: 1

Cycles: 1

Example 1: BTG.B 0x1001, #0x4 ; Toggle bit 4 in 0x1001

Before Instruction

AfterInstruction

Data 1000 F234 Data 1000 E234SR 0000 SR 0000

Example 2: BTG 0x1660, #0x8 ; Toggle bit 8 in RAM660

Before Instruction

AfterInstruction

Data 1660 5606 Data 1660 5706 SR 0000 SR 0000



Descriptions

5

BTG Bit Toggle in Ws


X X X X

Syntax: {label:} BTG{.B} Ws, #bit4

[Ws],

[Ws++],

[Ws--],

[++Ws],

[--Ws],


Operation: (Ws)<bit4> → Ws<bit4>



Description: Bit ‘bit4’ in register Ws is toggled (complemented). For the bit4 operand, bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 7 for byte operations, bit 15 for word operations). Register direct or indirect addressing may be used for Ws.

The ‘b’ bits select value bit4, the bit position to test.The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘s’ bits select the source/destination register.The ‘p’ bits select the source Address mode.




Words: 1

Cycles: 1

Example 1: BTG W2, #0x0 ; Toggle bit 0 in W2

Before Instruction

AfterInstruction

W2 F234 W2 F235SR 0000 SR 0000

Example 2: BTG [W0++], #0x0 ; Toggle bit 0 in [W0]; Post-increment W0

Before Instruction

AfterInstruction

W0 2300 W0 2302Data 2300 5606 Data 2300 5607

SR 0000 SR 0000



BTSC Bit Test f, Skip if Clear


X X X X

Syntax: {label:} BTSC{.B} f, #bit4


Operation: Test (f)<bit4>, skip if clear



Description: Bit ‘bit4’ in the file register is tested. If the tested bit is ‘0’, the next instruction (fetched during the current instruction execution) is discarded and on the next cycle, a NOP is executed instead. If the tested bit is ‘1’, the next instruction is executed as normal. In either case, the contents of the file register are not changed. For the bit4 operand, bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 7 for byte operations, bit 15 for word operations).

The ‘b’ bits select value bit4, the bit position to test.The ‘f’ bits select the address of the file register.




Words: 1

Cycles: 1 (2 or 3)

Example 1: 002000 HERE: BTSC.B 0x1201, #2002002 GOTO BYPASS002004 . . .002006 . . .002008 BYPASS: . . .00200A . . .

; If bit 2 of 0x1201 is 0,; skip the GOTO

Before Instruction

After Instruction

PC 00 2000 PC 00 2002Data 1200 264F Data 1200 264F

SR 0000 SR 0000



Descriptions

5

Example 2: 002000 HERE: BTSC 0x804, #14002002 GOTO BYPASS002004 . . .002006 . . .002008 BYPASS: . . .00200A . . .


Before Instruction

After Instruction

PC 00 2000 PC 00 2004Data 0804 2647 Data 0804 2647

SR 0000 SR 0000



BTSC Bit Test Ws, Skip if Clear


X X X X

Syntax: {label:} BTSC Ws, #bit4

[Ws],

[Ws++],

[Ws--],

[++Ws],

[--Ws],

Operands: Ws ∈ [W0 ... W15]bit4 ∈ [0 ... 15]

Operation: Test (Ws)<bit4>, skip if clear


Encoding: 1010 0111 bbbb 0000 0ppp ssss

Description: Bit ‘bit4’ in Ws is tested. If the tested bit is ‘0’, the next instruction (fetched during the current instruction execution) is discarded and on the next cycle, a NOP is executed instead. If the tested bit is ‘1’, the next instruction is executed as normal. In either case, the contents of Ws are not changed. For the bit4 operand, bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 15) of the word. Either register direct or indirect addressing may be used for Ws.

The ‘b’ bits select value bit4, the bit position to test.The ‘p’ bits select the source Address mode.The ‘s’ bits select the source register.


Words: 1

Cycles: 1 (2 or 3 if the next instruction is skipped)

Example 1: 002000 HERE: BTSC W0, #0x0002002 GOTO BYPASS002004 . . .002006 . . .002008 BYPASS: . . .00200A . . .

; If bit 0 of W0 is 0,; skip the GOTO

Before Instruction

After Instruction

PC 00 2000 PC 00 2002W0 264F W0 264FSR 0000 SR 0000



Descriptions

5

Example 2: 002000 HERE: BTSC W6, #0xF002002 GOTO BYPASS002004 . . .002006 . . .002008 BYPASS: . . .00200A . . .


Before Instruction

After Instruction

PC 00 2000 PC 00 2004W6 264F W6 264FSR 0000 SR 0000

Example 3: 003400 HERE: BTSC [W6++], #0xC003402 GOTO BYPASS003404 . . .003406 . . .003408 BYPASS: . . .00340A . . .

; If bit 12 of [W6] is 0,; skip the GOTO; Post-increment W6

Before Instruction

After Instruction

PC 00 3400 PC 00 3402W6 1800 W6 1802

Data 1800 1000 Data 1800 1000SR 0000 SR 0000



BTSS Bit Test f, Skip if Set


X X X X

Syntax: {label:} BTSS{.B} f, #bit4


Operation: Test (f)<bit4>, skip if set



Description: Bit ‘bit4’ in the file register ‘f’ is tested. If the tested bit is ‘1’, the next instruction (fetched during the current instruction execution) is discarded and on the next cycle, a NOP is executed instead. If the tested bit is ‘0’, the next instruction is executed as normal. In either case, the contents of the file register are not changed. For the bit4 operand, bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 7 for byte operation, bit 15 for word operation).

The ‘b’ bits select value bit4, the bit position to test.The ‘f’ bits select the address of the file register.




Words: 1


Example 1: 007100 HERE: BTSS.B 0x1401, #0x1007102 CLR WREG007104 . . .

; If bit 1 of 0x1401 is 1,; don’t clear WREG

Before Instruction

After Instruction

PC 00 7100 PC 00 7104Data 1400 0280 Data 1400 0280

SR 0000 SR 0000

Example 2: 007100 HERE: BTSS 0x890, #0x9007102 GOTO BYPASS007104 . . .007106 BYPASS: . . .


Before Instruction

After Instruction

PC 00 7100 PC 00 7102Data 0890 00FE Data 0890 00FE

SR 0000 SR 0000



Descriptions

5

BTSS Bit Test Ws, Skip if Set


X X X X

Syntax: {label:} BTSS Ws, #bit4

[Ws],

[Ws++],

[Ws--],

[++Ws],

[--Ws],


Operation: Test (Ws)<bit4>, skip if set.


Encoding: 1010 0110 bbbb 0000 0ppp ssss

Description: Bit ‘bit4’ in Ws is tested. If the tested bit is ‘1’, the next instruction (fetched during the current instruction execution) is discarded and on the next cycle, a NOP is executed instead. If the tested bit is ‘0’, the next instruction is executed as normal. In either case, the contents of Ws are not changed. For the bit4 operand, bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 15) of the word. Either register direct or indirect addressing may be used for Ws.

The ‘b’ bits select the value bit4, the bit position to test.The ‘s’ bits select the source register.The ‘p’ bits select the source Address mode.


Words: 1


Example 1: 002000 HERE: BTSS W0, #0x0002002 GOTO BYPASS002004 . . .002006 . . .002008 BYPASS: . . .00200A . . .


Before Instruction

After Instruction

PC 00 2000 PC 00 2004W0 264F W0 264FSR 0000 SR 0000



Example 2: 002000 HERE: BTSS W6, #0xF002002 GOTO BYPASS002004 . . .002006 . . .002008 BYPASS: . . .00200A . . .


Before Instruction

After Instruction

PC 00 2000 PC 00 2002W6 264F W6 264FSR 0000 SR 0000

Example 3: 003400 HERE: BTSS [W6++], 0xC003402 GOTO BYPASS003404 . . .003406 . . .003408 BYPASS: . . .00340A . . .

; If bit 12 of [W6] is 1,; skip the GOTO; Post-increment W6

Before Instruction

After Instruction

PC 00 3400 PC 00 3404W6 1800 W6 1802

Data 1800 1000 Data 1800 1000SR 0000 SR 0000



Descriptions

5

BTST Bit Test f


X X X X

Syntax: {label:} BTST{.B} f, #bit4


Operation: (f)<bit4> → Z

Status Affected: Z


Description: Bit ‘bit4’ in file register ‘f’ is tested and the complement of the tested bit is stored to the Z flag in the STATUS register. The contents of the file register are not changed. For the bit4 operand, bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 7 for byte operation, bit 15 for word operation).

The ‘b’ bits select value bit4, the bit position to be tested.The ‘f’ bits select the address of the file register.




Words: 1

Cycles: 1

Example 1: BTST.B 0x1201, #0x3 ; Set Z = complement of ; bit 3 in 0x1201

Before Instruction

AfterInstruction

Data 1200 F7FF Data 1200 F7FFSR 0000 SR 0002 (Z = 1)

Example 2: BTST 0x1302, #0x7 ; Set Z = complement of; bit 7 in 0x1302

Before Instruction

AfterInstruction

Data 1302 F7FF Data 1302 F7FFSR 0002 (Z = 1) SR 0000



BTST Bit Test in Ws


X X X X

Syntax: {label:} BTST.C Ws, #bit4

BTST.Z [Ws],

[Ws++],

[Ws--],

[++Ws],

[--Ws],


Operation: For “.C” operation: (Ws)<bit4> → C For “.Z” operation (default): (Ws)<bit4> → Z

Status Affected: Z or C

Encoding: 1010 0011 bbbb Z000 0ppp ssss

Description: Bit ‘bit4’ in register Ws is tested. If the “.Z” option of the instruction is specified, the complement of the tested bit is stored to the Zero flag in the STATUS register. If the “.C” option of the instruction is specified, the value of the tested bit is stored to the Carry flag in the STATUS register. In either case, the contents of Ws are not changed.

For the bit4 operand, bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 15) of the word. Either register direct or indirect addressing may be used for Ws.The ‘b’ bits select value bit4, the bit position to test.The ‘Z’ bit selects the C or Z flag as destination.The ‘p’ bits select the source Address mode.The ‘s’ bits select the source register.

Note: This instruction only operates in Word mode. If no extension isprovided, the “.Z” operation is assumed.

Words: 1

Cycles: 1

Example 1: BTST.C [W0++], #0x3 ; Set C = bit 3 in [W0]; Post-increment W0

Before Instruction

AfterInstruction

W0 1200 W0 1202Data 1200 FFF7 Data 1200 FFF7

SR 0001 (C = 1) SR 0000

Example 2: BTST.Z W0, #0x7 ; Set Z = complement of bit 7 in W0

Before Instruction

AfterInstruction

W0 F234 W0 F234SR 0000 SR 0002 (Z = 1)



Descriptions

5

BTST Bit Test in Ws


X X X X

Syntax: {label:} BTST.C Ws, Wb

BTST.Z [Ws],

[Ws++],

[Ws--],

[++Ws],

[--Ws],


Operation: For “.C” operation: (Ws)<(Wb)> → C For “.Z” operation (default): (Ws)<(Wb)> → Z

Status Affected: Z or C

Encoding: 1010 0101 Zwww w000 0ppp ssss

Description: The (Wb) bit in register Ws is tested. If the “.C” option of the instruction is specified, the value of the tested bit is stored to the Carry flag in the STATUS register. If the “.Z” option of the instruction is specified, the complement of the tested bit is stored to the Zero flag in the STATUS register. In either case, the contents of Ws are not changed.

Only the four Least Significant bits of Wb are used to determine the bit number. Bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 15) of the working register. Register direct or indirect addressing may be used for Ws.

The ‘Z’ bit selects the C or Z flag as destination.The ‘w’ bits select the address of the bit select register.The ‘p’ bits select the source Address mode.The ‘s’ bits select the source register.

Note: This instruction only operates in Word mode. If no extension isprovided, the “.Z” operation is assumed.

Words: 1Cycles: 1

Example 1: BTST.C W2, W3 ; Set C = bit W3 of W2

Before Instruction

AfterInstruction

W2 F234 W2 F234W3 2368 W3 2368SR 0001 (C = 1) SR 0000



Example 2: BTST.Z [W0++], W1 ; Set Z = complement of ; bit W1 in [W0], ; Post-increment W0

Before Instruction

AfterInstruction

W0 1200 W0 1202W1 CCC0 W1 CCC0

Data 1200 6243 Data 1200 6243SR 0002 (Z = 1) SR 0000



Descriptions

5

BTSTS Bit Test/Set f


X X X X

Syntax: {label:} BTSTS{.B} f, #bit4


Operation: (f)<bit4> → Z1 → (f)<bit4>

Status Affected: Z


Description: Bit ‘bit4’ in file register ‘f’ is tested and the complement of the tested bit is stored to the Zero flag in the STATUS register. The tested bit is then set to ‘1’ in the file register. For the bit4 operand, bit numbering begins with the Least Significant bit (bit 0) and advances to the Most Significant bit (bit 7 for byte operations, bit 15 for word operations).

The ‘b’ bits select value bit4, the bit position to test/set.The ‘f’ bits select the address of the file register.




4: The file register ‘f’ must not be the CPU Status (SR) register.

Words: 1

Cycles: 1

Example 1: BTSTS.B 0x1201, #0x3 ; Set Z = complement of bit 3 in 0x1201, ; then set bit 3 of 0x1201 = 1

Before Instruction

AfterInstruction

Data 1200 F7FF Data 1200 FFFFSR 0000 SR 0002 (Z = 1)

Example 2: BTSTS 0x808, #15 ; Set Z = complement of bit 15 in 0x808,; then set bit 15 of 0x808 = 1

Before Instruction

AfterInstruction

RAM300 8050 RAM300 8050SR 0002 (Z = 1) SR 0000



BTSTS Bit Test/Set in Ws


Syntax: {label:} BTSTS.C Ws, #bit4BTSTS.Z [Ws],

[Ws++],[Ws--],[++Ws],[--Ws],


Operation: For “.C” operation: (Ws)<bit4> → C 1 → Ws<bit4>For “.Z” operation (default): (Ws)<bit4> → Z 1 → Ws<bit4>

Status Affected: Z or CEncoding: 1010 0100 bbbb Z000 0ppp ssss

Description: Bit ‘bit4’ in register Ws is tested. If the “.Z” option of the instruction is specified, the complement of the tested bit is stored to the Zero flag in the STATUS register. If the “.C” option of the instruction is specified, the value of the tested bit is stored to the Carry flag in the STATUS register. In both cases, the tested bit in Ws is set to ‘1’.

The ‘b’ bits select the value bit4, the bit position to test/set.The ‘Z’ bit selects the C or Z flag as destination.The ‘p’ bits select the source Address mode.The ‘s’ bits select the source register.

Note 1: This instruction only operates in Word mode. If no extension isprovided, the “.Z” operation is assumed.

2: If Ws is used as a pointer, it must not contain the address of theCPU Status (SR) register.

Words: 1Cycles: 1

Example 1: BTSTS.C [W0++], #0x3 ; Set C = bit 3 in [W0] ; Set bit 3 in [W0] = 1; Post-increment W0

Before Instruction

AfterInstruction

W0 1200 W0 1202Data 1200 FFF7 Data 1200 FFFF

SR 0001 (C = 1) SR 0000

Example 2: BTSTS.Z W0, #0x7 ; Set Z = complement of bit 7 ; in W0, and set bit 7 in W0 = 1

Before Instruction

AfterInstruction

W0 F234 W0 F2BCSR 0000 SR 0002 (Z = 1)


Instruction D

escriptions

5

CALL Call Subroutine


Syntax: {label:} CALL Expr

Operands: Expr may be a label or expression (but not a literal).Expr is resolved by the linker to a lit23, where lit23 ∈ [0 ... 8388606].

Operation: (PC) + 4 → PC(PC<15:0>) → (TOS)(W15) + 2 → W15(PC<23:16>) → (TOS)(W15) + 2 → W15lit23 → PC NOP → Instruction Register

Status Affected: NoneEncoding: 1st word 0000 0010 nnnn nnnn nnnn nnn0

2nd word 0000 0000 0000 0000 0nnn nnnn

Description: Direct subroutine call over the entire 4-Mbyte instruction program memory range. Before the CALL is made, the 24-bit return address (PC + 4) is PUSHed onto the stack. After the return address is stacked, the 23-bit value ‘lit23’ is loaded into the PC.

The ‘n’ bits form the target address.

Note: The linker will resolve the specified expression into the lit23 tobe used.

Words: 2Cycles: 2

Example 1: 026000 CALL _FIR026004 MOV W0, W1 . ... . ...026844 _FIR: MOV #0x400, W2026846 ...

; Call _FIR subroutine

; _FIR subroutine start

Before Instruction

After Instruction

PC 02 6000 PC 02 6844W15 A268 W15 A26C

Data A268 FFFF Data A268 6004Data A26A FFFF Data A26A 0002

SR 0000 SR 0000



Example 2: 072000 CALL _G66 ; call routine _G66072004 MOV W0, W1 . ...077A28 _G66: INC W6, [W7++] ; routine start077A2A ...077A2C

Before Instruction

After Instruction

PC 07 2000 PC 07 7A28W15 9004 W15 9008

Data 9004 FFFF Data 9004 2004Data 9006 FFFF Data 9006 0007

SR 0000 SR 0000


Instruction D

escriptions

5

CALL Call Indirect Subroutine


X X X X

Syntax: {label:} CALL Wn

Operands: Wn ∈ [W0 ... W15]Operation: (PC) + 2 → PC

(PC<15:0>) → TOS(W15) + 2 → W15(PC<23:16>) → TOS(W15) + 2 → W150 → PC<22:16>(Wn<15:1>) → PC<15:1>NOP → Instruction Register


Encoding: 0000 0001 0000 0000 0000 ssss

Description: Indirect subroutine call over the first 32K instructions of program memory. Before the CALL is made, the 24-bit return address (PC + 2) is PUSHed onto the stack. After the return address is stacked, Wn<15:1> is loaded into PC<15:1> and PC<22:16> is cleared. Since PC<0> is always ‘0’, Wn<0> is ignored.

The ‘s’ bits select the source register.Words: 1Cycles: 2

Example 1:

001002 CALL W0001004 ... . ...001600 _BOOT: MOV #0x400, W2001602 MOV #0x300, W6 . ...

; Call BOOT subroutine indirectly; using W0

; _BOOT starts here

Before Instruction

After Instruction

PC 00 1002 PC 00 1600W0 1600 W0 1600

W15 6F00 W15 6F04Data 6F00 FFFF Data 6F00 1004Data 6F02 FFFF Data 6F02 0000

SR 0000 SR 0000



Example 2: 004200 CALL W7004202 ... . ...005500 _TEST: INC W1, W2005502 DEC W1, W3 . ...

; Call TEST subroutine indirectly; using W7

; _TEST starts here;

Before Instruction

After Instruction

PC 00 4200 PC 00 5500W7 5500 W7 5500

W15 6F00 W15 6F04Data 6F00 FFFF Data 6F00 4202Data 6F02 FFFF Data 6F02 0000

SR 0000 SR 0000


Instruction D

escriptions

5

CLR Clear f or WREG


X X X X

Syntax: {label:} CLR{.B} f

WREG

Operands: f ∈ [0 ... 8191]

Operation: 0 → destination designated by D



Description: Clear the contents of a file register or the default working register WREG. If WREG is specified, the WREG is cleared. Otherwise, the specified file register ‘f’ is cleared.




Words: 1

Cycles: 1Example 1: CLR.B RAM200 ; Clear RAM200 (Byte mode)

Before Instruction

AfterInstruction

RAM200 8009 RAM200 8000SR 0000 SR 0000

Example 2: CLR WREG ; Clear WREG (Word mode)

Before Instruction

AfterInstruction

WREG 0600 WREG 0000SR 0000 SR 0000



CLR Clear Wd


X X X X

Syntax: {label:} CLR{.B} Wd

[Wd]

[Wd++]

[Wd--]

[++Wd]

[--Wd]

Operands: Wd ∈ [W0 ... W15]

Operation: 0 → Wd


Encoding: 1110 1011 0Bqq qddd d000 0000

Description: Clear the contents of register Wd. Either register direct or indirect addressing may be used for Wd.

The ‘B’ bit select byte or word operation (‘0’ for word, ‘1’ for byte).The ‘q’ bits select the destination Address mode.The ‘d’ bits select the destination register.

Note: The extension .B in the instruction denotes a byte operation rather than a word operation. You may use a .W extension to denote a word operation, but it is not required.

Words: 1

Cycles: 1

Example 1: CLR.B W2 ; Clear W2 (Byte mode)

Before Instruction

AfterInstruction

W2 3333 W2 3300SR 0000 SR 0000

Example 2: CLR [W0++] ; Clear [W0] ; Post-increment W0

Before Instruction

AfterInstruction

W0 2300 W0 2302Data 2300 5607 Data 2300 0000

SR 0000 SR 0000


Instruction D

escriptions

5

CLR Clear Accumulator, Prefetch Operands


X X

Syntax: {label:}

CLR Acc {,[Wx],Wxd} {,[Wy],Wyd} {,AWB}

{,[Wx] + = kx,Wxd} {,[Wy] + = ky,Wyd}

{,[Wx] – = kx,Wxd} {,[Wy] – = ky,Wyd}

{,[W9 + W12],Wxd} {,[W11 + W12],Wyd}

Operands: Acc ∈ [A,B]Wx ∈ [W8, W9]; kx ∈ [-6, -4, -2, 2, 4, 6]; Wxd ∈ [W4 ... W7] Wy ∈ [W10, W11]; ky ∈ [-6, -4, -2, 2, 4, 6]; Wyd ∈ [W4 ... W7]AWB ∈ [W13, [W13] + = 2]

Operation: 0 → Acc(A or B)([Wx]) → Wxd; (Wx) +/– kx → Wx([Wy]) → Wyd; (Wy) +/– ky → Wy(Acc(B or A)) rounded → AWB

Status Affected: OA, OB, SA, SB

Encoding: 1100 0011 A0xx yyii iijj jjaa

Description: Clear all 40 bits of the specified accumulator, optionally prefetch operands in preparation for a MAC type instruction and optionally store the non-specified accumulator results. This instruction clears the respec-tive overflow and saturate flags (either OA, SA or OB, SB).

Operands Wx, Wxd, Wy and Wyd specify optional prefetch operations, which support indirect and register offset addressing, as described in Section 4.14.1 “MAC Prefetches”. Operand AWB specifies the optional register direct or indirect store of the convergently rounded contents of the “other” accumulator, as described in Section 4.14.4 “MAC Write Back”.

The ‘A’ bit selects the other accumulator used for write back.The ‘x’ bits select the prefetch Wxd destination.The ‘y’ bits select the prefetch Wyd destination.The ‘i’ bits select the Wx prefetch operation.The ‘j’ bits select the Wy prefetch operation.The ‘a’ bits select the accumulator Write Back destination.

Words: 1

Cycles: 1



Example 1: CLR A, [W8]+=2, W4, W13 ; Clear ACCA; Load W4 with [W8], post-inc W8; Store ACCB to W13

Before Instruction

After Instruction

W4 F001 W4 1221W8 2000 W8 2002

W13 C623 W13 5420ACCA 00 0067 2345 ACCA 00 0000 0000ACCB 00 5420 3BDD ACCB 00 5420 3BDD

Data 2000 1221 Data 2000 1221SR 0000 SR 0000

Example 2:

CLR B, [W8]+=2, W6, [W10]+=2, W7, [W13]+=2 ; Clear ACCB; Load W6 with [W8]; Load W7 with [W10]; Save ACCA to [W13]; Post-inc W8,W10,W13

Before Instruction

After Instruction

W6 F001 W6 1221W7 C783 W7 FF80W8 2000 W8 2002

W10 3000 W10 3002W13 4000 W13 4002

ACCA 00 0067 2345 ACCA 00 0067 2345ACCB 00 5420 ABDD ACCB 00 0000 0000

Data 2000 1221 Data 2000 1221Data 3000 FF80 Data 3000 FF80Data 4000 FFC3 Data 4000 0067

SR 0000 SR 0000


Instruction D

escriptions

5

CLRWDT Clear Watchdog Timer


X X X X

Syntax: {label:} CLRWDT

Operands: None

Operation: 0 → WDT count register0 → WDT prescaler A count0 → WDT prescaler B count


Encoding: 1111 1110 0110 0000 0000 0000

Description: Clear the contents of the Watchdog Timer count register and the prescaler count registers. The Watchdog Prescaler A and Prescaler B settings, set by configuration fuses in the FWDT, are not changed.

Words: 1

Cycles: 1

Example 1: CLRWDT ; Clear Watchdog Timer

Before Instruction

AfterInstruction

SR 0000 SR 0000



COM Complement f


X X X X

Syntax: {label:} COM{.B} f {,WREG}

Operands: f ∈ [0 ... 8191]

Operation: (f) → destination designated by D



Description: Compute the 1’s complement of the contents of the file register and placethe result in the destination register. The optional WREG operanddetermines the destination register. If WREG is specified, the result isstored in WREG. If WREG is not specified, the result is stored in the fileregister.The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).The ‘f’ bits select the address of the file register.



Words: 1

Cycles: 1

Example 1: COM.b RAM200 ; COM RAM200 (Byte mode)

Before Instruction

AfterInstruction

RAM200 80FF RAM200 8000SR 0000 SR 0002 (Z)

Example 2: COM RAM400, WREG ; COM RAM400 and store to WREG ; (Word mode)

Before Instruction

AfterInstruction

WREG 1211 WREG F7DCRAM400 0823 RAM400 0823

SR 0000 SR 0008 (N = 1)


Instruction D

escriptions

5

COM Complement Ws


X X X X

Syntax: {label:} COM{.B} Ws, Wd

[Ws], [Wd]

[Ws++], [Wd++]

[Ws--], [Wd--]

[++Ws], [++Wd]

[--Ws], [--Wd]


Operation: (Ws) → Wd



Description: Compute the 1’s complement of the contents of the source register Ws and place the result in the destination register Wd. Either register direct or indirect addressing may be used for both Ws and Wd.



Words: 1

Cycles: 1

Example 1: COM.B [W0++], [W1++] ; COM [W0] and store to [W1] (Byte mode); Post-increment W0, W1

Before Instruction

AfterInstruction

W0 2301 W0 2302W1 2400 W1 2401

Data 2300 5607 Data 2300 5607 Data 2400 ABCD Data 2400 ABA9

SR 0000 SR 0008 (N = 1)

Example 2: COM W0, [W1++] ; COM W0 and store to [W1] (Word mode); Post-increment W1

Before Instruction

AfterInstruction

W0 D004 W0 D004W1 1000 W1 1002

Data 1000 ABA9 Data 1000 2FFB SR 0000 SR 0000



CP Compare f with WREG, Set Status Flags


X X X X

Syntax: {label:} CP{.B} f

Operands: f ∈ [0 ...8191]

Operation: (f) – (WREG)


Encoding: 1110 0011 0B0f ffff ffff ffff

Description: Compute (f) – (WREG) and update the STATUS register. This instruction is equivalent to the SUBWF instruction, but the result of the subtraction is not stored.

The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘f’ bits select the address of the file register.



Words: 1

Cycles: 1

Example 1: CP.B RAM400 ; Compare RAM400 with WREG (Byte mode)

Before Instruction

AfterInstruction

WREG 8823 WREG 8823RAM400 0823 RAM400 0823

SR 0000 SR 0002 (Z = 1)

Example 2: CP 0x1200 ; Compare (0x1200) with WREG (Word mode)

Before Instruction

AfterInstruction

WREG 2377 WREG 2377Data 1200 2277 Data 1200 2277

SR 0000 SR 0008 (N = 1)


Instruction D

escriptions

5

CP Compare Wb with lit5, Set Status Flags


X X X X

Syntax: {label:} CP{.B} Wb, #lit5

Operands: Wb ∈ [W0 ... W15]lit5 ∈ [0 ... 31]

Operation: (Wb) – lit5


Encoding: 1110 0001 0www wB00 011k kkkk

Description: Compute (Wb) – lit5, and update the STATUS register. This instruction is equivalent to the SUB instruction, but the result of the subtraction is not stored. Register direct addressing must be used for Wb.

The ‘w’ bits select the address of the Wb base register.The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘k’ bits provide the literal operand, a five-bit integer number.


Words: 1

Cycles: 1

Example 1: CP.B W4, #0x12 ; Compare W4 with 0x12 (Byte mode)

Before Instruction

AfterInstruction

W4 7711 W4 7711SR 0000 SR 0008 (N = 1)

Example 2: CP W4, #0x12 ; Compare W4 with 0x12 (Word mode)

Before Instruction

AfterInstruction

W4 7713 W4 7713SR 0000 SR 0000



CP Compare Wb with Ws, Set Status Flags


X X X X

Syntax: {label:} CP{.B} Wb, Ws

[Ws]

[Ws++]

[Ws--]

[++Ws]

[--Ws]

Operands: Wb ∈ [W0 ... W15]Ws ∈ [W0 ... W15]

Operation: (Wb) – (Ws)


Encoding: 1110 0001 0www wB00 0ppp ssss

Description: Compute (Wb) – (Ws), and update the STATUS register. This instruction is equivalent to the SUB instruction, but the result of the subtraction is not stored. Register direct addressing must be used for Wb. Register direct or indirect addressing may be used for Ws.

The ‘w’ bits select the address of the Wb source register.The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘p’ bits select the source Address mode.The ‘s’ bits select the address of the Ws source register.


Words: 1

Cycles: 1

Example 1: CP.B W0, [W1++] ; Compare [W1] with W0 (Byte mode) ; Post-increment W1

Before Instruction

AfterInstruction

W0 ABA9 W0 ABA9W1 2000 W1 2001

Data 2000 D004 Data 2000 D004 SR 0000 SR 0008 (N = 1)

Example 2: CP W5, W6 ; Compare W6 with W5 (Word mode)

Before Instruction

AfterInstruction

W5 2334 W5 2334W6 8001 W6 8001SR 0000 SR 000C (N, OV = 1)


Instruction D

escriptions

5

CP0 Compare f with 0x0, Set Status Flags


X X X X

Syntax: {label:} CP0{.B} f

Operands: f ∈ [0 ... 8191]

Operation: (f) – 0x0



Description: Compute (f) – 0x0 and update the STATUS register. The result of the subtraction is not stored.

The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte). The ‘f’ bits select the address of the file register.


Words: 1

Cycles: 1

Example 1: CP0.B RAM100 ; Compare RAM100 with 0x0 (Byte mode)

Before Instruction

AfterInstruction

RAM100 44C3 RAM100 44C3SR 0000 SR 0008 (N = 1)

Example 2: CP0 0x1FFE ; Compare (0x1FFE) with 0x0 (Word mode)

Before Instruction

AfterInstruction

Data 1FFE 0001 Data 1FFE 0001SR 0000 SR 0000



CP0 Compare Ws with 0x0, Set Status Flags


X X X X

Syntax: {label:} CP0{.B} Ws

[Ws]

[Ws++]

[Ws--]

[++Ws]

[--Ws]

Operands: Ws ∈ [W0 ... W15]

Operation: (Ws) – 0x0000


Encoding: 1110 0000 0000 0B00 0ppp ssss

Description: Compute (Ws) – 0x0000 and update the STATUS register. The result of the subtraction is not stored. Register direct or indirect addressing may be used for Ws.

The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘p’ bits select the source Address mode.The ‘s’ bits select the address of the Ws source register.


Words: 1

Cycles: 1

Example 1: CP0.B [W4--] ; Compare [W4] with 0 (Byte mode) ; Post-decrement W4

Before Instruction

AfterInstruction

W4 1001 W4 1000Data 1000 0034 Data 1000 0034

SR 0000 SR 0002 (Z = 1)

Example 2: CP0 [--W5] ; Compare [--W5] with 0 (Word mode)

Before Instruction

AfterInstruction

W5 2400 W5 23FEData 23FE 9000 Data 23FE 9000

SR 0000 SR 0008 (N = 1)


Instruction D

escriptions

5

CPB Compare f with WREG using Borrow, Set Status Flags


X X X X

Syntax: {label:} CPB{.B} f

Operands: f ∈ [0 ...8191]

Operation: (f) – (WREG) – (C)



Description: Compute (f) – (WREG) – (C), and update the STATUS register. This instruction is equivalent to the SUBB instruction, but the result of the subtraction is not stored.



2: The WREG is set to working register W0. 3: The Z flag is “sticky” for ADDC, CPB, SUBB and SUBBR. These


Words: 1

Cycles: 1

Example 1: CPB.B RAM400 ; Compare RAM400 with WREG using C (Byte mode)

Before Instruction

AfterInstruction

WREG 8823 WREG 8823RAM400 0823 RAM400 0823

SR 0000 SR 0008 (N = 1)

Example 2: CPB 0x1200 ; Compare (0x1200) with WREG using C (Word mode)

Before Instruction

AfterInstruction

WREG 2377 WREG 2377Data 1200 2377 Data 1200 2377

SR 0001 (C = 1) SR 0001 (C = 1)



CPB Compare Wb with lit5 using Borrow, Set Status Flags


Syntax: {label:} CPB{.B} Wb, #lit5

Operands: Wb ∈ [W0 ... W15]lit5 ∈ [0 ... 31]

Operation: (Wb) – lit5 – (C)Status Affected: DC, N, OV, Z, CEncoding: 1110 0001 1www wB00 011k kkkk

Description: Compute (Wb) – lit5 – (C), and update the STATUS register. This instruction is equivalent to the SUBB instruction, but the result of the subtraction is not stored. Register direct addressing must be used for Wb.

The ‘w’ bits select the address of the Wb source register.The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘k’ bits provide the literal operand, a five bit integer number.



Words: 1Cycles: 1

Example 1: CPB.B W4, #0x12 ; Compare W4 with 0x12 using C (Byte mode)

Before Instruction

AfterInstruction

W4 7711 W4 7711SR 0001 (C = 1) SR 0008 (N = 1)

Example 2: CPB.B W4, #0x12 ; Compare W4 with 0x12 using C (Byte mode)

Before Instruction

AfterInstruction

W4 7711 W4 7711SR 0000 SR 0008 (N = 1)

Example 3: CPB W12, #0x1F ; Compare W12 with 0x1F using C (Word mode)

Before Instruction

AfterInstruction

W12 0020 W12 0020SR 0002 (Z = 1) SR 0003 (Z, C = 1)

Example 4: CPB W12, #0x1F ; Compare W12 with 0x1F using C (Word mode)

Before Instruction

AfterInstruction

W12 0020 W12 0020SR 0003 (Z, C = 1) SR 0001 (C = 1)


Instruction D

escriptions

5

CPB Compare Ws with Wb using Borrow, Set Status Flags


X X X X

Syntax: {label:} CPB{.B} Wb, Ws

[Ws]

[Ws++]

[Ws--]

[++Ws]

[--Ws]

Operands: Wb ∈ [W0 ... W15]Ws ∈ [W0 ... W15]

Operation: (Wb) – (Ws) – (C)


Encoding: 1110 0001 1www wB00 0ppp ssss

Description: Compute (Wb) – (Ws) – (C), and update the STATUS register. This instruction is equivalent to the SUBB instruction, but the result of the subtraction is not stored. Register direct addressing must be used for Wb. Register direct or indirect addressing may be used for Ws.

The ‘w’ bits select the address of the Wb source register.The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘p’ bits select the source Address mode.The ‘s’ bits select the address of the Ws source register.



Words: 1

Cycles: 1

Example 1: CPB.B W0, [W1++] ; Compare [W1] with W0 using C (Byte mode); Post-increment W1

Before Instruction

AfterInstruction

W0 ABA9 W0 ABA9W1 1000 W1 1001

Data 1000 D0A9 Data 1000 D0A9 SR 0002 (Z = 1) SR 0008 (N = 1)



Example 2: CPB.B W0, [W1++] ; Compare [W1] with W0 using C (Byte mode); Post-increment W1

Before Instruction

AfterInstruction

W0 ABA9 W0 ABA9W1 1000 W1 1001

Data 1000 D0A9 Data 1000 D0A9 SR 0001 (C = 1) SR 0001 (C = 1)

Example 3: CPB W4, W5 ; Compare W5 with W4 using C (Word mode)

Before Instruction

AfterInstruction

W4 4000 W4 4000W5 3000 W5 3000SR 0001 (C = 1) SR 0001 (C = 1)


Instruction D

escriptions

5

CPSEQ Compare Wb with Wn, Skip if Equal (Wb = Wn)


X X X X

Syntax: {label:} CPSEQ{.B} Wb, Wn

Operands: Wb ∈ [W0 ... W15]Wn ∈ [W0 ... W15]

Operation: (Wb) – (Wn)Skip if (Wb) = (Wn)


Encoding: 1110 0111 1www wB00 0000 ssss

Description: Compare the contents of Wb with the contents of Wn by performing the subtraction (Wb) – (Wn), but do not store the result. If (Wb) = (Wn), the next instruction (fetched during the current instruction execution) is discarded and on the next cycle, a NOP is executed instead. If (Wb) ≠ (Wn), the next instruction is executed as normal.

The ‘w’ bits select the address of the Wb source register.The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘s’ bits select the address of the Ws source register.


Words: 1

Cycles: 1 (2 or 3 if skip taken)

Example 1: 002000 HERE:CPSEQ.BW0, W1; If W0 = W1 (Byte mode),002002GOTOBYPASS; skip the GOTO002004 . . .002006 . . .002008 BYPASS: . . .00200A . . .

Before Instruction

After Instruction

PC 00 2000 PC 00 2002W0 1001 W0 1001W1 1000 W1 1000SR 0000 SR 0000

Example 2: 018000 HERE: CPSEQ W4, W8; If W4 = W8 (Word mode),018002 CALL _FIR; skip the subroutine call018006 ...018008 ...

Before Instruction

After Instruction

PC 01 8000 PC 01 8006W4 3344 W4 3344W8 3344 W8 3344SR 0002 (Z = 1) SR 0002 (Z = 1)



CPSGT Signed Compare Wb with Wn, Skip if Greater Than (Wb > Wn)


X X X X

Syntax: {label:} CPSGT{.B} Wb, Wn


Operation: (Wb) – (Wn)Skip if (Wb) > (Wn)



Description: Compare the contents of Wb with the contents of Wn by performing the subtraction (Wb) – (Wn), but do not store the result. If (Wb) > (Wn), the next instruction (fetched during the current instruction execution) is discarded and on the next cycle, a NOP is executed instead. Otherwise, the next instruction is executed as normal.



Words: 1


Example 1: 002000 HERE: CPSGT.B W0, W1; If W0 > W1 (Byte mode),002002 GOTO BYPASS; skip the GOTO002006 . . .002008 . . .00200A BYPASS . . .00200C . . .

Before Instruction

After Instruction

PC 00 2000 PC 00 2006W0 00FF W0 00FFW1 26FE W1 26FESR 0009 (N, C = 1) SR 0009 (N, C = 1)

Example 2: 018000 HERE: CPSGT W4, W5; If W4 > W5 (Word mode),018002 CALL _FIR; skip the subroutine call018006 ...018008 ...

Before Instruction

After Instruction

PC 01 8000 PC 01 8002W4 2600 W4 2600W5 2600 W5 2600SR 0004 (OV = 1) SR 0004 (OV = 1)


Instruction D

escriptions

5

CPSLT Signed Compare Wb with Wn, Skip if Less Than (Wb < Wn)


X X X X

Syntax: {label:} CPSLT{.B} Wb, Wn


Operation: (Wb) – (Wn)Skip if (Wb) < (Wn)



Description: Compare the contents of Wb with the contents of Wn by performing the subtraction (Wb) – (Wn), but do not store the result. If (Wb) < (Wn), the next instruction (fetched during the current instruction execution) is discarded and on the next cycle, a NOP is executed instead. Otherwise, the next instruction is executed as normal.



Words: 1


Example 1: 002000 HERE: CPSLT.B W8, W9; If W8 < W9 (Byte mode),002002 GOTO BYPASS; skip the GOTO002006 . . .002008 . . .00200A BYPASS: . . .00200C . . .

Before Instruction

After Instruction

PC 00 2000 PC 00 2002W8 00FF W8 00FFW9 26FE W9 26FESR 0008 (N = 1) SR 0008 (N = 1)

Example 2: 018000 HERE: CPSLT W3, W6; If W3 < W6 (Word mode),018002 CALL _FIR; skip the subroutine call018006 . . .018008 . . .

Before Instruction

After Instruction

PC 01 8000 PC 01 8006W3 2600 W3 2600W6 3000 W6 3000SR 0000 SR 0000



CPSNE Signed Compare Wb with Wn, Skip if Not Equal (Wb ≠ Wn)


X X X X

Syntax: {label:} CPSNE{.B} Wb, Wn


Operation: (Wb) – (Wn)Skip if (Wb) ≠ (Wn)



Description: Compare the contents of Wb with the contents of Wn by performing the subtraction (Wb) – (Wn), but do not store the result. If (Wb) ≠ (Wn), the next instruction (fetched during the current instruction execution) is discarded and on the next cycle, a NOP is executed instead. Otherwise, the next instruction is executed as normal.



Words: 1


Example 1: 002000 HERE: CPSNE.B W2, W3 ; If W2 != W3 (Byte mode),002002 GOTO BYPASS ; skip the GOTO002006 . . .002008 . . .00200A BYPASS: . . .00200C . . .

Before Instruction

After Instruction

PC 00 2000 PC 00 2006W2 00FF W2 00FFW3 26FE W3 26FESR 0001 (C = 1) SR 0001 (C = 1)

Example 2: 018000 HERE: CPSNE W0, W8 ; If W0 != W8 (Word mode),018002 CALL _FIR ; skip the subroutine call018006 ...018008 ...

Before Instruction

After Instruction

PC 01 8000 PC 01 8002W0 3000 W0 3000W8 3000 W8 3000SR 0000 SR 0000


Instruction D

escriptions

5

DAW.B Decimal Adjust Wn


X X X X

Syntax: {label:} DAW.B Wn


Operation: If (Wn<3:0> > 9) or (DC = 1) (Wn<3:0>) + 6 → Wn<3:0>Else (Wn<3:0>) → Wn<3:0>

If (Wn<7:4> > 9) or (C = 1) (Wn<7:4>) + 6 → Wn<7:4>Else (Wn<7:4>) → Wn<7:4>

Status Affected: C

Encoding: 1111 1101 0100 0000 0000 ssss

Description: Adjust the Least Significant Byte in Wn to produce a binary coded decimal (BCD) result. The Most Significant Byte of Wn is not changed, and the Carry flag is used to indicate any decimal rollover. Register direct addressing must be used for Wn.

The ‘s’ bits select the source/destination register.

Note 1: This instruction is used to correct the data format after twopacked BCD bytes have been added.

2: This instruction operates in Byte mode only and the .Bextension must be included with the opcode.

Words: 1

Cycles: 1

Example 1: DAW.B W0 ; Decimal adjust W0

Before Instruction

AfterInstruction

W0 771A W0 7720SR 0002 (DC = 1) SR 0002 (DC = 1)

Example 2: DAW.B W3 ; Decimal adjust W3

Before Instruction

AfterInstruction

W3 77AA W3 7710SR 0000 SR 0001 (C = 1)



DEC Decrement f


X X X X

Syntax: {label:} DEC{.B} f {,WREG}

Operands: f ∈ [0 ... 8191]

Operation: (f) – 1 → destination designated by D



Description: Subtract one from the contents of the file register and place the result in thedestination register. The optional WREG operand determines thedestination register. If WREG is specified, the result is stored in WREG. IfWREG is not specified, the result is stored in the file register.




Words: 1

Cycles: 1

Example 1: DEC.B 0x200 ; Decrement (0x200) (Byte mode)

Before Instruction

AfterInstruction

Data 200 80FF Data 200 80FESR 0000 SR 0009 (N, C = 1)

Example 2: DEC RAM400, WREG ; Decrement RAM400 and store to WREG ; (Word mode)

Before Instruction

AfterInstruction

WREG 1211 WREG 0822RAM400 0823 RAM400 0823

SR 0000 SR 0000


Instruction D

escriptions

5

DEC Decrement Ws


X X X X

Syntax: {label:} DEC{.B} Ws, Wd

[Ws], [Wd]

[Ws++], [Wd++]

[Ws--], [Wd--]

[++Ws], [++Wd]

[--Ws], [--Wd]


Operation: (Ws) – 1 → Wd



Description: Subtract one from the contents of the source register Ws and place the result in the destination register Wd. Either register direct or indirect addressing may be used by Ws and Wd.



Words: 1

Cycles: 1

Example 1: DEC.B [W7++], [W8++] ; DEC [W7] and store to [W8] (Byte mode) ; Post-increment W7, W8

Before Instruction

AfterInstruction

W7 2301 W7 2302W8 2400 W8 2401

Data 2300 5607 Data 2300 5607 Data 2400 ABCD Data 2400 AB55

SR 0000 SR 0000

Example 2: DEC W5, [W6++] ; Decrement W5 and store to [W6] (Word mode) ; Post-increment W6

Before Instruction

AfterInstruction

W5 D004 W5 D004W6 2000 W6 2002

Data 2000 ABA9 Data 2000 D003 SR 0000 SR 0009 (N, C = 1)



DEC2 Decrement f by 2


X X X X

Syntax: {label:} DEC2{.B} f {,WREG}

Operands: f ∈ [0 ... 8191]

Operation: (f) – 2 → destination designated by D



Description: Subtract two from the contents of the file register and place the result in thedestination register. The optional WREG operand determines thedestination register. If WREG is specified, the result is stored in WREG. IfWREG is not specified, the result is stored in the file register.



Words: 1

Cycles: 1

Example 1: DEC2.B 0x200 ; Decrement (0x200) by 2 (Byte mode)

Before Instruction

AfterInstruction

Data 200 80FF Data 200 80FDSR 0000 SR 0009 (N, C = 1)

Example 2: DEC2 RAM400, WREG ; Decrement RAM400 by 2 and ; store to WREG (Word mode)

Before Instruction

AfterInstruction

WREG 1211 WREG 0821RAM400 0823 RAM400 0823

SR 0000 SR 0000


Instruction D

escriptions

5

DEC2 Decrement Ws by 2


Syntax: {label:} DEC2{.B} Ws, Wd[Ws], [Wd][Ws++], [Wd++][Ws--], [Wd--][++Ws], [++Wd][--Ws], [--Wd]


Operation: (Ws) – 2 → Wd Status Affected: DC, N, OV, Z, CEncoding: 1110 1001 1Bqq qddd dppp ssss

Description: Subtract two from the contents of the source register Ws and place the result in the destination register Wd. Either register direct or indirect addressing may be used by Ws and Wd.



Words: 1Cycles: 1

Example 1: DEC2.B [W7--], [W8--]; DEC [W7] by 2, store to [W8] (Byte mode); Post-decrement W7, W8

Before Instruction

AfterInstruction

W7 2301 W7 2300W8 2400 W8 23FF

Data 2300 0107 Data 2300 0107 Data 2400 ABCD Data 2400 ABFF

SR 0000 SR 0008 (N = 1)

Example 2: DEC2 W5, [W6++] ; DEC W5 by 2, store to [W6] (Word mode); Post-increment W6

Before Instruction

AfterInstruction

W5 D004 W5 D004W6 1000 W6 1002

Data 1000 ABA9 Data 1000 D002 SR 0000 SR 0009 (N, C = 1)



DISI Disable Interrupts Temporarily


X X X X

Syntax: {label:} DISI #lit14

Operands: lit14 ∈ [0 ... 16383]

Operation: lit14 → DISICNT1 → DISI Disable interrupts for (lit14 + 1) cycles


Encoding: 1111 1100 00kk kkkk kkkk kkkk

Description: Disable interrupts of priority 0 through priority 6 for (lit14 + 1) instruction cycles. Priority 0 through priority 6 interrupts are disabled starting in the cycle that DISI executes, and remain disabled for the next (lit 14) cycles. The lit14 value is written to the DISICNT register, and the DISI flag (INTCON2<14>) is set to ‘1’. This instruction can be used before executing time critical code, to limit the effects of interrupts.

Note: This instruction does not prevent priority 7 interrupts and trapsfrom running. See the specific device family reference manualfor details.

Words: 1

Cycles: 1

Example 1: 002000 HERE: DISI #100 ; Disable interrupts for 101 cycles002002 ; next 100 cycles protected by DISI002004 . . .

Before Instruction

After Instruction

PC 00 2000 PC 00 2002DISICNT 0000 DISICNT 0100

INTCON2 0000 INTCON2 4000 (DISI = 1)SR 0000 SR 0000


Instruction D

escriptions

5

DIV.S Signed Integer Divide


Syntax: {label:} DIV.S{W} Wm, WnDIV.SD Wm, Wn

Operands: Wm ∈ [W0 ... W15] for word operationWm ∈ [W0, W2, W4 ... W14] for double operationWn ∈ [W2 ... W15]

Operation: For word operation (default): Wm → W0 If (Wm<15> = 1): 0xFFFF → W1 Else: 0x0 → W1 W1:W0 / Wn → W0 Remainder → W1

For double operation (DIV.SD): Wm + 1:Wm → W1:W0 W1:W0 / Wn → W0 Remainder → W1

Status Affected: N, OV, Z, CEncoding: 1101 1000 0ttt tvvv vW00 ssss

Description: Iterative, signed integer divide, where the dividend is stored in Wm (for a 16-bit by 16-bit divide) or Wm + 1:Wm (for a 32-bit by 16-bit divide) and the divisor is stored in Wn. In the default word operation, Wm is first copied to W0 and sign-extended through W1 to perform the operation. In the double operation, Wm + 1:Wm is first copied to W1:W0. The 16-bit quotient of the divide operation is stored in W0, and the 16-bit remainder is stored in W1. This instruction must be executed 18 times using the REPEAT instruction (with an iteration count of 17) to generate the correct quotient and remainder. The N flag will be set if the remainder is negative and cleared otherwise. The OV flag will be set if the divide operation resulted in an overflow and cleared otherwise. The Z flag will be set if the remainder is ‘0’ and cleared otherwise. The C flag is used to implement the divide algorithm and its final value should not be used. The ‘t’ bits select the most significant word of the dividend for the double operation. These bits are clear for the word operation.The ‘v’ bits select the least significant word of the dividend.The ‘W’ bit selects the dividend size (‘0’ for 16-bit, ‘1’ for 32-bit).The ‘s’ bits select the divisor register.

Note 1: The extension .D in the instruction denotes a double word(32-bit) dividend rather than a word dividend. You may use a.W extension to denote a word operation, but it is not required.

2: Unexpected results will occur if the quotient can not berepresented in 16 bits. When this occurs for the doubleoperation (DIV.SD), the OV status bit will be set and thequotient and remainder should not be used. For the wordoperation (DIV.S), only one type of overflow may occur(0x8000/0xFFFF = + 32768 or 0x00008000), which allows theOV status bit to interpret the result.

3: Dividing by zero will initiate an arithmetic error trap during thefirst cycle of execution.

4: This instruction is interruptible on each instruction cycleboundary.



Words: 1Cycles: 18 (plus 1 for REPEAT execution)

Example 1: REPEAT #17 ; Execute DIV.S 18 timesDIV.S W3, W4 ; Divide W3 by W4 ; Store quotient to W0, remainder to W1

Before Instruction

AfterInstruction

W0 5555 W0 013BW1 1234 W1 0003W3 3000 W3 3000 W4 0027 W4 0027 SR 0000 SR 0000

Example 2: REPEAT #17 ; Execute DIV.SD 18 timesDIV.SD W0, W12 ; Divide W1:W0 by W12 ; Store quotient to W0, remainder to W1

Before Instruction

AfterInstruction

W0 2500 W0 FA6BW1 FF42 W1 EF00

W12 2200 W12 2200 SR 0000 SR 0008 (N = 1)


Instruction D

escriptions

5

DIV.U Unsigned Integer Divide


X X X X

Syntax: {label:} DIV.U{W} Wm, Wn

DIV.UD Wm, Wn

Operands: Wm ∈ [W0 ... W15] for word operationWm ∈ [W0, W2, W4 ... W14] for double operationWn ∈ [W2 ... W15]

Operation: For word operation (default): Wm → W0 0x0 → W1 W1:W0/Wn → W0 Remainder → W1

For double operation (DIV.UD): Wm + 1:Wm → W1:W0 W1:W0/Wns → W0 Remainder → W1

Status Affected: N, OV, Z, C

Encoding: 1101 1000 1ttt tvvv vW00 ssss

Description: Iterative, unsigned integer divide, where the dividend is stored in Wm (for a 16-bit by 16-bit divide), or Wm + 1:Wm (for a 32-bit by 16-bit divide) and the divisor is stored in Wn. In the word operation, Wm is first copied to W0 and W1 is cleared to perform the divide. In the double operation, Wm + 1:Wm is first copied to W1:W0. The 16-bit quotient of the divide operation is stored in W0, and the 16-bit remainder is stored in W1.This instruction must be executed 18 times using the REPEAT instruction (with an iteration count of 17) to generate the correct quotient and remainder. The N flag will always be cleared. The OV flag will be set if the divide operation resulted in an overflow and cleared otherwise. The Z flag will be set if the remainder is ‘0’ and cleared otherwise. The C flag is used to implement the divide algorithm and its final value should not be used.The ‘t’ bits select the most significant word of the dividend for the double operation. These bits are clear for the word operation.The ‘v’ bits select the least significant word of the dividend.The ‘W’ bit selects the dividend size (‘0’ for 16-bit, ‘1’ for 32-bit).The ‘s’ bits select the divisor register.

Note 1: The extension .D in the instruction denotes a double word(32-bit) dividend rather than a word dividend. You may use a .Wextension to denote a word operation, but it is not required.

2: Unexpected results will occur if the quotient can not berepresented in 16 bits. This may only occur for the doubleoperation (DIV.UD). When an overflow occurs, the OV statusbit will be set and the quotient and remainder should not beused.



Words: 1

Cycles: 18 (plus 1 for REPEAT execution)



Example 1: REPEAT #17 ; Execute DIV.U 18 timesDIV.U W2, W4 ; Divide W2 by W4 ; Store quotient to W0, remainder to W1

Before Instruction

AfterInstruction

W0 5555 W0 0040W1 1234 W1 0000W2 8000 W2 8000 W4 0200 W4 0200 SR 0000 SR 0002 (Z = 1)

Example 2: REPEAT #17 ; Execute DIV.UD 18 timesDIV.UD W10, W12 ; Divide W11:W10 by W12 ; Store quotient to W0, remainder to W1

Before Instruction

AfterInstruction

W0 5555 W0 01F2W1 1234 W1 0100

W10 2500 W10 2500 W11 0042 W11 0042 W12 2200 W12 2200

SR 0000 SR 0000


Instruction D

escriptions

5

DIVF Fractional Divide


X X

Syntax: {label:} DIVF Wm, Wn

Operands: Wm ∈ [W0 ... W15]Wn ∈ [W2 ... W15]

Operation: 0x0 → W0Wm → W1W1:W0/Wn → W0Remainder → W1

Status Affected: N, OV, Z, C

Encoding: 1101 1001 0ttt t000 0000 ssss

Description: Iterative, signed fractional 16-bit by 16-bit divide, where the dividend is stored in Wm and the divisor is stored in Wn. To perform the operation, W0 is first cleared and Wm is copied to W1. The 16-bit quotient of the divide operation is stored in W0, and the 16-bit remainder is stored in W1. The sign of the remainder will be the same as the sign of the dividend.

This instruction must be executed 18 times using the REPEAT instruction (with an iteration count of 17) to generate the correct quotient and remainder. The N flag will be set if the remainder is negative and cleared otherwise. The OV flag will be set if the divide operation resulted in an overflow and cleared otherwise. The Z flag will be set if the remainder is ‘0’ and cleared otherwise. The C flag is used to implement the divide algorithm and its final value should not be used.

The ‘t’ bits select the dividend register.The ‘s’ bits select the divisor register.

Note 1: For the fractional divide to be effective, Wm must be less thanWn. If Wm is greater than or equal to Wn, unexpected resultswill occur because the fractional result will be greater than orequal to 1.0. When this occurs, the OV status bit will be set andthe quotient and remainder should not be used.



Words: 1

Cycles: 18 (plus 1 for REPEAT execution)



Example 1: REPEAT #17 ; Execute DIVF 18 timesDIVF W8, W9 ; Divide W8 by W9 ; Store quotient to W0, remainder to W1

Before Instruction

AfterInstruction

W0 8000 W0 2000W1 1234 W1 0000W8 1000 W8 1000W9 4000 W9 4000 SR 0000 SR 0002 (Z = 1)


Before Instruction

AfterInstruction

W0 8000 W0 F000W1 1234 W1 0000W8 1000 W8 1000W9 8000 W9 8000 SR 0000 SR 0002 (Z = 1)


Before Instruction

AfterInstruction

W0 8002 W0 7FFEW1 8001 W1 8002SR 0000 SR 0008 (N = 1)


Instruction D

escriptions

5

DO Initialize Hardware Loop Literal


X X

Syntax: {label:} DO #lit14, Expr

Operands: lit14 ∈ [0 ... 16383]Expr may be an absolute address, label or expression.Expr is resolved by the linker to a Slit16, where Slit16 ∈ [-32768 ... +32767].

Operation: PUSH DO shadows (DCOUNT, DOEND, DOSTART)(lit14) → DCOUNT(PC) + 4 → PC(PC) → DOSTART(PC) + (2 * Slit16) → DOENDIncrement DL<2:0> (CORCON<10:8>)

Status Affected: DA


0000 0000 nnnn nnnn nnnn nnnn

Description: Initiate a no overhead hardware DO loop, which is executed (lit14 + 1) times. The DO loop begins at the address following the DO instruction, and ends at the address 2 * Slit16 instruction words away. The 14-bit count value (lit14) supports a maximum loop count value of 16384, and the 16-bit offset value (Slit16) supports offsets of 32K instruction words in both directions.When this instruction executes, DCOUNT, DOSTART and DOEND are first PUSHed into their respective shadow registers, and then updated with the new DO loop parameters specified by the instruction. The DO level count, DL<2:0> (CORCON<8:10>), is then incremented. After the DO loop completes execution, the PUSHed DCOUNT, DOSTART and DOEND registers are restored, and DL<2:0> is decremented.The ‘k’ bits specify the loop count.The ‘n’ bits are a signed literal that specifies the number of instructions offset from the PC to the last instruction executed in the loop.Special Features, Restrictions:The following features and restrictions apply to the DO instruction.1. Using a loop count of ‘0’ will result in the loop being executed one

time.2. Using a loop size of -2, -1 or 0 is invalid. Unexpected results may

occur if these offsets are used.3. The very last two instructions of the DO loop can NOT be:

• an instruction which changes program control flow• a DO or REPEAT instructionUnexpected results may occur if any of these instructions are used.

4. If a hard trap occurs in the second to last instruction or third to lastinstruction of a DO loop, the loop will not function properly. The hardtrap includes exceptions of priority level 13 through level 15,inclusive.

Note 1: The DO instruction is interruptible and supports 1 level ofhardware nesting. Nesting up to an additional 5 levels may beprovided in software by the user. See the specific device familyreference manual for details.

2: The linker will convert the specified expression into the offset tobe used.



Words: 2

Cycles: 2

Example 1: 002000 LOOP6: DO #5, END6; Initiate DO loop (6 reps)002004 ADD W1, W2, W3; First instruction in loop002006 . . .002008 . . .00200A END6: SUB W2, W3, W4; Last instruction in loop00200C . . .

Before Instruction

After Instruction

PC 00 2000 PC 00 2004DCOUNT 0000 DCOUNT 0005

DOSTART FF FFFF DOSTART 00 2004DOEND FF FFFF DOEND 00 200A

CORCON 0000 CORCON 0100 (DL = 1)SR 0001 (C = 1) SR 0201 (DA, C = 1)

Example 2: 01C000 LOOP12: DO #0x160, END12; Init DO loop (353 reps)01C004 DEC W1, W2; First instruction in loop01C006 . . .01C008 . . .01C00A . . .01C00C . . .01C00E . . .01C010 CALL _FIR88; Call the FIR88 subroutine01C014 END12: NOP; Last instruction in loop

; (Required NOP filler)

Before Instruction

After Instruction

PC 01 C000 PC 01 C004DCOUNT 0000 DCOUNT 0160

DOSTART FF FFFF DOSTART 01 C004DOEND FF FFFF DOEND 01 C014

CORCON 0000 CORCON 0100 (DL = 1)SR 0008 (N = 1) SR 0208 (DA, N = 1)


Instruction D

escriptions

5

DO Initialize Hardware Loop Wn


X X

Syntax: {label:} DO Wn, Expr

Operands: Wn ∈ [W0 ... W15]Expr may be an absolute address, label or expression.Expr is resolved by the linker to a Slit16, where Slit16 ∈ [-32768 ... +32767].

Operation: PUSH Shadows (DCOUNT, DOEND, DOSTART)(Wn) → DCOUNT(PC) + 4 → PC(PC) → DOSTART (PC) + (2 * Slit16) → DOENDIncrement DL<2:0> (CORCON<10:8>)

Status Affected: DA

0000 1000 1000 0000 0000 ssss


Description: Initiate a no overhead hardware DO loop, which is executed (Wn + 1) times. The DO loop begins at the address following the DO instruction, and ends at the address 2 * Slit16 instruction words away. The lower 14 bits of Wn support a maximum count value of 16384, and the 16-bit offset value (Slit16) supports offsets of 32K instruction words in both directions.

When this instruction executes, DCOUNT, DOSTART and DOEND are first PUSHed into their respective shadow registers, and then updated with the new DO loop parameters specified by the instruction. The DO level count, DL<2:0> (CORCON<8:10>), is then incremented. After the DO loop completes execution, the PUSHed DCOUNT, DOSTART and DOEND registers are restored, and DL<2:0> is decremented.

The ‘s’ bits specify the register Wn that contains the loop count.The ‘n’ bits are a signed literal that specifies the number of instructions offset from (PC + 4), which is the last instruction executed in the loop.

Special Features, Restrictions:The following features and restrictions apply to the DO instruction. 1. Using a loop count of ‘0’ will result in the loop being executed one

time.2. Using an offset of -2, -1 or 0 is invalid. Unexpected results may occur

if these offsets are used.3. The very last two instructions of the DO loop can NOT be:

• an instruction which changes program control flow• a DO or REPEAT instructionUnexpected results may occur if these last instructions are used.

Note 1: The DO instruction is interruptible and supports 1 level of nesting.Nesting up to an additional 5 levels may be provided in softwareby the user. See the specific device family reference manual fordetails.

2: The linker will convert the specified expression into the offset tobe used.

Words: 2

Cycles: 2



Example 1: 002000 LOOP6: DO W0, END6 ; Initiate DO loop (W0 reps)002004 ADD W1, W2, W3 ; First instruction in loop002006 . . .002008 . . .00200A . . .00200C REPEAT #600200E SUB W2, W3, W4 002010 END6: NOP ; Last instruction in loop ; (Required NOP filler)

Before Instruction

After Instruction

PC 00 2000 PC 00 2004W0 0012 W0 0012

DCOUNT 0000 DCOUNT 0012DOSTART FF FFFF DOSTART 00 2004

DOEND FF FFFF DOEND 00 2010CORCON 0000 CORCON 0100 (DL = 1)

SR 0000 SR 0080 (DA = 1)

Example 2: 002000 LOOPA: DO W7, ENDA ; Initiate DO loop (W7 reps)002004 SWAP W0 ; First instruction in loop002006 . . .002008 . . .00200A . . .002010 ENDA: MOV W1, [W2++] ; Last instruction in loop

Before Instruction

After Instruction

PC 00 2000 PC 00 2004W7 E00F W7 E00F

DCOUNT 0000 DCOUNT 200FDOSTART FF FFFF DOSTART 00 2004

DOEND FF FFFF DOEND 00 2010CORCON 0000 CORCON 0100 (DL = 1)

SR 0000 SR 0080 (DA = 1)


Instruction D

escriptions

5

ED Euclidean Distance (No Accumulate)


X X

Syntax: {label:} ED Wm * Wm, Acc, [Wx], [Wy], Wxd

[Wx] + = kx, [Wy] + = ky,

[Wx] – = kx, [Wy] – = ky,

[W9 + W12],

[W11 + W12],

Operands: Acc ∈ [A,B]Wm * Wm ∈ [W4 * W4, W5 * W5, W6 * W6, W7 * W7]Wx ∈ [W8, W9]; kx ∈ [-6, -4, -2, 2, 4, 6]Wy ∈ [W10, W11]; ky ∈ [-6, -4, -2, 2, 4, 6]Wxd ∈ [W4 ... W7]

Operation: (Wm) * (Wm) → Acc(A or B)([Wx] – [Wy]) → Wxd(Wx) + kx → Wx(Wy) + ky → Wy


Encoding: 1111 00mm A1xx 00ii iijj jj11

Description: Compute the square of Wm, and optionally compute the difference of the prefetch values specified by [Wx] and [Wy]. The results of Wm * Wm are sign-extended to 40 bits and stored in the specified accumulator. The results of [Wx] – [Wy] are stored in Wxd, which may be the same as Wm.

Operands Wx, Wxd and Wyd specify the prefetch operations which support indirect and register offset addressing as described in Section 4.14.1 “MAC Prefetches”.

The ‘m’ bits select the operand register Wm for the square.The ‘A’ bit selects the accumulator for the result.The ‘x’ bits select the prefetch difference Wxd destination.The ‘i’ bits select the Wx prefetch operation.The ‘j’ bits select the Wy prefetch operation.

Words: 1

Cycles: 1

Example 1: ED W4*W4, A, [W8]+=2, [W10]-=2, W4 ; Square W4 to ACCA; [W8]-[W10] to W4; Post-increment W8 ; Post-decrement W10

Before Instruction

After Instruction

W4 009A W4 0057W8 1100 W8 1102

W10 2300 W10 22FEACCA 00 3D0A 0000 ACCA 00 0000 5CA4

Data 1100 007F Data 1100 007FData 2300 0028 Data 2300 0028

SR 0000 SR 0000



Example 2: ED W5*W5, B, [W9]+=2, [W11+W12], W5 ; Square W5 to ACCB; [W9]-[W11+W12] to W5; Post-increment W9

Before Instruction

After Instruction

W5 43C2 W5 3F3FW9 1200 W9 1202

W11 2500 W11 2500W12 0008 W12 0008

ACCB 00 28E3 F14C ACCB 00 11EF 1F04Data 1200 6A7C Data 1200 6A7CData 2508 2B3D Data 2508 2B3D

SR 0000 SR 0000


Instruction D

escriptions

5

EDAC Euclidean Distance

Implemented in: PIC24F PIC24H dsPIC30F dsPIC33FX X

Syntax: {label:} EDAC Wm * Wm, Acc, [Wx], [Wy], Wxd[Wx] + = kx,

[Wy] + = ky,

[Wx] – = kx, [Wy] – = ky,[W9 + W12],

[W11 + W12],

Operands: Acc ∈ [A,B]Wm * Wm ∈ [W4 * W4, W5 * W5, W6 * W6, W7 * W7]Wx ∈ [W8, W9]; kx ∈ [-6, -4, -2, 2, 4, 6] Wy ∈ [W10, W11]; ky ∈ [-6, -4, -2, 2, 4, 6] Wxd ∈ [W4 ... W7]

Operation: (Acc(A or B)) + (Wm) * (Wm) → Acc(A or B)([Wx] – [Wy]) → Wxd(Wx) + kx → Wx(Wy) + ky → Wy

Status Affected: OA, OB, OAB, SA, SB, SABEncoding: 1111 00mm A1xx 00ii iijj jj10

Description: Compute the square of Wm, and also the difference of the prefetch values specified by [Wx] and [Wy]. The results of Wm * Wm are sign-extended to 40 bits and added to the specified accumulator. The results of [Wx] – [Wy] are stored in Wxd, which may be the same as Wm.

Operands Wx, Wxd and Wyd specify the prefetch operations which support indirect and register offset addressing as described in Section 4.14.1 “MAC Prefetches”.

The ‘m’ bits select the operand register Wm for the square.The ‘A’ bit selects the accumulator for the result. The ‘x’ bits select the prefetch difference Wxd destination.The ‘i’ bits select the Wx prefetch operation.The ‘j’ bits select the Wy prefetch operation.

Words: 1Cycles: 1

Example 1: EDAC W4*W4, A, [W8]+=2, [w10]-=2, W4 ; Square W4 and; add to ACCA; [W8]-[W10] to W4; Post-increment W8 ; Post-decrement W10

Before Instruction

After Instruction

W4 009A W4 0057W8 1100 W8 1102

W10 2300 W10 22FEACCA 00 3D0A 3D0A ACCA 00 3D0A 99AE

Data 1100 007F Data 1100 007FData 2300 0028 Data 2300 0028

SR 0000 SR 0000



Example 2: EDAC W5*W5, B, [w9]+=2, [W11+W12], W5 ; Square W5 and; add to ACCB; [W9]-[W11+W12] to W5; Post-increment W9

Before Instruction

After Instruction

W5 43C2 W5 3F3FW9 1200 W9 1202

W11 2500 W11 2500W12 0008 W12 0008

ACCB 00 28E3 F14C ACCB 00 3AD3 1050Data 1200 6A7C Data 1200 6A7CData 2508 2B3D Data 2508 2B3D

SR 0000 SR 0000


Instruction D

escriptions

5

EXCH Exchange Wns and Wnd


X X X X

Syntax: {label:} EXCH Wns, Wnd

Operands: Wns ∈ [W0 ... W15]Wnd ∈ [W0 ... W15]

Operation: (Wns) ↔ (Wnd)


Encoding: 1111 1101 0000 0ddd d000 ssss

Description: Exchange the word contents of two working registers. Register direct addressing must be used for Wns and Wnd.

The ‘d’ bits select the address of the first register.The ‘s’ bits select the address of the second register.

Note: This instruction only executes in Word mode.

Words: 1

Cycles: 1

Example 1: EXCH W1, W9 ; Exchange the contents of W1 and W9

BeforeInstruction

AfterInstruction

W1 55FF W1 A3A3W9 A3A3 W9 55FFSR 0000 SR 0000

Example 2: EXCH W4, W5 ; Exchange the contents of W4 and W5

BeforeInstruction

AfterInstruction

W4 ABCD W4 4321W5 4321 W5 ABCDSR 0000 SR 0000



FBCL Find First Bit Change from Left


X X X X

Syntax: {label:} FBCL Ws, Wnd

[Ws],

[Ws++],

[Ws--],

[++Ws],

[--Ws],

Operands: Ws ∈ [W0 ... W15]Wnd ∈ [W0 ... W15]

Operation: Max_Shift = 15Sign = (Ws) & 0x8000Temp = (Ws) << 1Shift = 0While ( (Shift < Max_Shift) && ( (Temp & 0x8000) == Sign) ) Temp = Temp << 1 Shift = Shift + 1-Shift → (Wnd)

Status Affected: C

Encoding: 1101 1111 0000 0ddd dppp ssss

Description: Find the first occurrence of a one (for a positive value), or zero (for a negative value), starting from the Most Significant bit after the sign bit of Ws and working towards the Least Significant bit of the word operand. The bit number result is sign-extended to 16 bits and placed in Wnd.

The next Most Significant bit after the sign bit is allocated bit number 0 and the Least Significant bit is allocated bit number -14. This bit ordering allows for the immediate use of Wd with the SFTAC instruction for scaling values up. If a bit change is not found, a result of -15 is returned and the C flag is set. When a bit change is found, the C flag is cleared.

The ‘d’ bits select the destination register.The ‘p’ bits select the source Address mode.The ‘s’ bits select the source register.


Words: 1

Cycles: 1

Example 1: FBCL W1, W9 ; Find 1st bit change from left in W1; and store result to W9

Before Instruction

After Instruction

W1 55FF W1 55FFW9 FFFF W9 0000SR 0000 SR 0000


Instruction D

escriptions

5

Example 2: FBCL W1, W9 ; Find 1st bit change from left in W1; and store result to W9

Before Instruction

After Instruction

W1 FFFF W1 FFFFW9 BBBB W9 FFF1SR 0000 SR 0001 (C = 1)

Example 3: FBCL [W1++], W9 ; Find 1st bit change from left in [W1] ; and store result to W9; Post-increment W1

Before Instruction

After Instruction

W1 2000 W1 2002W9 BBBB W9 FFF9

Data 2000 FF0A Data 2000 FF0ASR 0000 SR 0000



FF1L Find First One from Left


X X X X

Syntax: {label:} FF1L Ws, Wnd

[Ws],

[Ws++],

[Ws--],

[++Ws],

[--Ws],


Operation: Max_Shift = 17Temp = (Ws)Shift = 1While ( (Shift < Max_Shift) && !(Temp & 0x8000) ) Temp = Temp << 1 Shift = Shift + 1If (Shift == Max_Shift) 0 → (Wnd)Else Shift → (Wnd)

Status Affected: C


Description: Finds the first occurrence of a ‘1’ starting from the Most Significant bit of Ws and working towards the Least Significant bit of the word operand. The bit number result is zero-extended to 16 bits and placed in Wnd.

Bit numbering begins with the Most Significant bit (allocated number 1) and advances to the Least Significant bit (allocated number 16). A result of zero indicates a ‘1’ was not found, and the C flag will be set. If a ‘1’ is found, the C flag is cleared.



Words: 1

Cycles: 1

Example 1: FF1L W2, W5 ; Find the 1st one from the left in W2 ; and store result to W5

Before Instruction

After Instruction

W2 000A W2 000AW5 BBBB W5 000DSR 0000 SR 0000


Instruction D

escriptions

5

Example 2: FF1L [W2++], W5 ; Find the 1st one from the left in [W2] ; and store the result to W5; Post-increment W2

Before Instruction

After Instruction

W2 2000 W2 2002W5 BBBB W5 0000

Data 2000 0000 Data 2000 0000SR 0000 SR 0001 (C = 1)



FF1R Find First One from Right


X X X X

Syntax: {label:} FF1R Ws, Wnd

[Ws],

[Ws++],

[Ws--],

[++Ws],

[--Ws],


Operation: Max_Shift = 17Temp = (Ws)Shift = 1While ( (Shift < Max_Shift) && !(Temp & 0x1) ) Temp = Temp >> 1 Shift = Shift + 1If (Shift == Max_Shift) 0 → (Wnd)Else Shift → (Wnd)

Status Affected: C


Description: Finds the first occurrence of a ‘1’ starting from the Least Significant bit of Ws and working towards the Most Significant bit of the word operand. The bit number result is zero-extended to 16 bits and placed in Wnd.

Bit numbering begins with the Least Significant bit (allocated number 1) and advances to the Most Significant bit (allocated number 16). A result of zero indicates a ‘1’ was not found, and the C flag will be set. If a ‘1’ is found, the C flag is cleared.



Words: 1

Cycles: 1

Example 1: FF1R W1, W9 ; Find the 1st one from the right in W1 ; and store the result to W9

Before Instruction

After Instruction

W1 000A W1 000AW9 BBBB W9 0002SR 0000 SR 0000


Instruction D

escriptions

5

Example 2: FF1R [W1++], W9 ; Find the 1st one from the right in [W1] ; and store the result to W9; Post-increment W1

Before Instruction

After Instruction

W1 2000 W1 2002W9 BBBB W9 0010

Data 2000 8000 Data 2000 8000SR 0000 SR 0000



GOTO Unconditional Jump


X X X X

Syntax: {label:} GOTO Expr

Operands: Expr may be label or expression (but not a literal).Expr is resolved by the linker to a lit23, where lit23 ∈ [0 ... 8388606].

Operation: lit23 → PCNOP → Instruction Register


Encoding:

1st word 0000 0100 nnnn nnnn nnnn nnn0

2nd word 0000 0000 0000 0000 0nnn nnnn

Description: Unconditional jump to anywhere within the 4M instruction word program memory range. The PC is loaded with the 23-bit literal specified in the instruction. Since the PC must always reside on an even address boundary, lit23<0> is ignored.

The ‘n’ bits form the target address.

Note: The linker will resolve the specified expression into the lit23 to beused.

Words: 2

Cycles: 2

Example 1: 026000 GOTO _THERE026004 MOV W0, W1 . ... . ...027844 _THERE: MOV #0x400, W2027846 ...

; Jump to _THERE

; Code execution; resumes here

Before Instruction

After Instruction

PC 02 6000 PC 02 7844SR 0000 SR 0000

Example 2: 000100 _code: ... . ...026000 GOTO _code+2026004 ...

; start of code

; Jump to _code+2

Before Instruction

After Instruction

PC 02 6000 PC 00 0102SR 0000 SR 0000


Instruction D

escriptions

5

GOTO Unconditional Indirect Jump


X X X X

Syntax: {label:} GOTO Wn


Operation: 0 → PC<22:16>(Wn<15:1>) → PC<15:1>0 → PC<0>NOP → Instruction Register


Encoding: 0000 0001 0100 0000 0000 ssss

Description: Unconditional indirect jump within the first 32K words of program memory. Zero is loaded into PC<22:16> and the value specified in (Wn) is loaded into PC<15:1>. Since the PC must always reside on an even address boundary, Wn<0> is ignored.


Words: 1

Cycles: 2

Example 1: 006000 GOTO W4006002 MOV W0, W1 . ... . ...007844 _THERE: MOV #0x400, W2007846 ...

; Jump unconditionally; to 16-bit value in W4

; Code execution; resumes here

Before Instruction

After Instruction

W4 7844 W4 7844PC 00 6000 PC 00 7844SR 0000 SR 0000



INC Increment f


X X X X

Syntax: {label:} INC{.B} f {,WREG}

Operands: f ∈ [0 ... 8191]

Operation: (f) + 1 → destination designated by D



Description: Add one to the contents of the file register, and place the result in thedestination register. The optional WREG operand determines thedestination register. If WREG is specified, the result is stored in WREG. IfWREG is not specified, the result is stored in the file register.




Words: 1

Cycles: 1

Example 1: INC.B 0x1000 ; Increment 0x1000 (Byte mode)

Before Instruction

After Instruction

Data 1000 8FFF Data 1000 8F00SR 0000 SR 0101 (DC, C = 1)

Example 2: INC 0x1000, WREG ; Increment 0x1000 and store to WREG ; (Word mode)

Before Instruction

After Instruction

WREG ABCD WREG 9000Data 1000 8FFF Data 1000 8FFF

SR 0000 SR 0108 (DC, N = 1)


Instruction D

escriptions

5

INC Increment Ws


X X X X

Syntax: {label:} INC{.B} Ws, Wd

[Ws], [Wd]

[Ws++], [Wd++]

[Ws--], [Wd--]

[++Ws], [++Wd]

[--Ws], [--Wd]


Operation: (Ws) + 1 → Wd



Description: Add 1 to the contents of the source register Ws and place the result in the destination register Wd. Register direct or indirect addressing may be used for Ws and Wd.



Words: 1

Cycles: 1

Example 1: INC.B W1, [++W2] ; Pre-increment W2 ; Increment W1 and store to W2 ; (Byte mode)

Before Instruction

After Instruction

W1 FF7F W1 FF7FW2 2000 W2 2001

Data 2000 ABCD Data 2000 80CDSR 0000 SR 010C (DC, N, OV = 1)

Example 2: INC W1, W2 ; Increment W1 and store to W2 ; (Word mode)

Before Instruction

After Instruction

W1 FF7F W1 FF7FW2 2000 W2 FF80SR 0000 SR 0108 (DC, N = 1)



INC2 Increment f by 2


X X X X

Syntax: {label:} INC2{.B} f {,WREG}

Operands: f ∈ [0 ... 8191]




Description: Add 2 to the contents of the file register and place the result in the destination register. The optional WREG operand determines the destination register. If WREG is specified, the result is stored in WREG. If WREG is not specified, the result is stored in the file register.



Words: 1

Cycles: 1

Example 1: INC2.B 0x1000 ; Increment 0x1000 by 2 ; (Byte mode)

Before Instruction

After Instruction

Data 1000 8FFF Data 1000 8F01SR 0000 SR 0101 (DC, C = 1)

Example 2: INC2 0x1000, WREG ; Increment 0x1000 by 2 and store to WREG ; (Word mode)

Before Instruction

After Instruction

WREG ABCD WREG 9001Data 1000 8FFF Data 1000 8FFF

SR 0000 SR 0108 (DC, N = 1)


Instruction D

escriptions

5

INC2 Increment Ws by 2


X X X X

Syntax: {label:} INC2{.B} Ws, Wd

[Ws], [Wd]

[Ws++], [Wd++]

[Ws--], [Wd--]

[++Ws], [++Wd]

[--Ws], [--Wd]


Operation: (Ws) + 2 → Wd



Description: Add 2 to the contents of the source register Ws and place the result in the destination register Wd. Register direct or indirect addressing may be used for Ws and Wd.



Words: 1

Cycles: 1

Example 1: INC2.B W1, [++W2] ; Pre-increment W2 ; Increment by 2 and store to W1 ; (Byte mode)

Before Instruction

After Instruction

W1 FF7F W1 FF7FW2 2000 W2 2001

Data 2000 ABCD Data 2000 81CDSR 0000 SR 010C (DC, N, OV = 1)

Example 2: INC2 W1, W2 ; Increment W1 by 2 and store to W2 ; (word mode)

Before Instruction

After Instruction

W1 FF7F W1 FF7FW2 2000 W2 FF81SR 0000 SR 0108 (DC, N = 1)



IOR Inclusive OR f and WREG


X X X X

Syntax: {label:} IOR{.B} f {,WREG}

Operands: f ∈ [0 ... 8191]

Operation: (f).IOR.(WREG) → destination designated by D



Description: Compute the logical inclusive OR operation of the contents of the working register WREG and the contents of the file register and place the result in the destination register. The optional WREG operand determines the destination register. If WREG is specified, the result is stored in WREG. If WREG is not specified, the result is stored in the file register.




Words: 1

Cycles: 1

Example 1: IOR.B 0x1000 ; IOR WREG to (0x1000) (Byte mode) ; (Byte mode)

Before Instruction

After Instruction

WREG 1234 WREG 1234Data 1000 FF00 Data 1000 FF34

SR 0000 SR 0000

Example 2: IOR 0x1000, WREG ; IOR (0x1000) to WREG ; (Word mode)

Before Instruction

After Instruction

WREG 1234 WREG 1FBFData 1000 0FAB Data 1000 0FAB

SR 0008 (N = 1) SR 0000


Instruction D

escriptions

5

IOR Inclusive OR Literal and Wn


X X X X

Syntax: {label:} IOR{.B} #lit10, Wn


Operation: lit10.IOR.(Wn) → Wn



Description: Compute the logical inclusive OR operation of the 10-bit literal operand and the contents of the working register Wn and place the result back into the working register Wn.




Words: 1

Cycles: 1

Example 1: IOR.B #0xAA, W9 ; IOR 0xAA to W9 ; (Byte mode)

Before Instruction

After Instruction

W9 1234 W9 12BESR 0000 SR 0008 (N = 1)

Example 2: IOR #0x2AA, W4 ; IOR 0x2AA to W4 ; (Word mode)

Before Instruction

After Instruction

W4 A34D W4 A3EFSR 0000 SR 0008 (N = 1)



IOR Inclusive OR Wb and Short Literal


X X X X

Syntax: {label:} IOR{.B} Wb, #lit5, Wd

[Wd]

[Wd++]

[Wd--]

[++Wd]

[--Wd]


Operation: (Wb).IOR.lit5 → Wd



Description: Compute the logical inclusive OR operation of the contents of the base register Wb and the 5-bit literal operand and place the result in the destination register Wd. Register direct addressing must be used for Wb. Either register direct or indirect addressing may be used for Wd.



Words: 1

Cycles: 1

Example 1: IOR.B W1, #0x5, [W9++] ; IOR W1 and 0x5 (Byte mode) ; Store to [W9] ; Post-increment W9

Before Instruction

After Instruction

W1 AAAA W1 AAAAW9 2000 W9 2001

Data 2000 0000 Data 2000 00AFSR 0000 SR 0008 (N = 1)

Example 2: IOR W1, #0x0, W9 ; IOR W1 with 0x0 (Word mode) ; Store to W9

Before Instruction

After Instruction

W1 0000 W1 0000W9 A34D W9 0000SR 0000 SR 0002 (Z = 1)


Instruction D

escriptions

5

IOR Inclusive OR Wb and Ws


X X X X

Syntax: {label:} IOR{.B} Wb, Ws, Wd

[Ws], [Wd]

[Ws++], [Wd++]

[Ws--], [Wd--]

[++Ws], [++Wd]

[--Ws], [--Wd]


Operation: (Wb).IOR.(Ws) → Wd Status Affected: N, Z


Description: Compute the logical inclusive OR operation of the contents of the source register Ws and the contents of the base register Wb, and place the result in the destination register Wd. Register direct addressing must be used for Wb. Either register direct or indirect addressing may be used for Ws and Wd.



Words: 1Cycles: 1

Example 1: IOR.B W1, [W5++], [W9++] ; IOR W1 and [W5] (Byte mode) ; Store result to [W9] ; Post-increment W5 and W9

Before Instruction

After Instruction

W1 AAAA W1 AAAAW5 2000 W5 2001W9 2400 W9 2401

Data 2000 1155 Data 2000 1155Data 2400 0000 Data 2400 00FF

SR 0000 SR 0008 (N = 1)



Example 2: IOR W1, W5, W9 ; IOR W1 and W5 (Word mode) ; Store the result to W9

Before Instruction

After Instruction

W1 AAAA W1 AAAAW5 5555 W5 5555W9 A34D W9 FFFFSR 0000 SR 0008 (N = 1)


Instruction D

escriptions

5

LAC Load Accumulator


X X

Syntax: {label:} LAC Ws, {#Slit4,} Acc

[Ws],

[Ws++],

[Ws--],

[--Ws],

[++Ws],

[Ws+Wb],

Operands: Ws ∈ [W0 ... W15]Wb ∈ [W0 ... W15]Slit4 ∈ [-8 ... +7]Acc ∈ [A,B]

Operation: ShiftSlit4(Extend(Ws)) → Acc(A or B)


Encoding: 1100 1010 Awww wrrr rggg ssss

Description: Read the contents of the source register, optionally perform a signed 4-bit shift and store the result in the specified accumulator. The shift range is -8:7, where a negative operand indicates an arithmetic left shift and a positive operand indicates an arithmetic right shift. The data stored in the source register is assumed to be 1.15 fractional data and is automatically sign-extended (through bit 39) and zero-backfilled (bits [15:0]), prior to shifting.

The ‘A’ bit specifies the destination accumulator.The ‘w’ bits specify the offset register Wb.The ‘r’ bits encode the accumulator pre-shift.The ‘g’ bits select the source Address mode.The ‘s’ bits specify the source register Ws.

Note: If the operation moves more than sign-extension data into theupper Accumulator register (AccxU), or causes a saturation, theappropriate overflow and saturation bits will be set.

Words: 1Cycles: 1

Example 1: LAC [W4++], #-3, B ; Load ACCB with [W4] << 3 ; Contents of [W4] do not change ; Post increment W4 ; Assume saturation disabled ; (SATB = 0)

Before Instruction

After Instruction

W4 2000 W4 2002ACCB 00 5125 ABCD ACCB FF 9108 0000

Data 2000 1221 Data 2000 1221SR 0000 SR 4800 (OB, OAB = 1)



Example 2: LAC [--W2], #7, A ; Pre-decrement W2 ; Load ACCA with [W2] >> 7 ; Contents of [W2] do not change ; Assume saturation disabled ; (SATA = 0)

Before Instruction

After Instruction

W2 4002 W2 4000ACCA 00 5125 ABCD ACCA FF FF22 1000


SR 0000 SR 0000


Instruction D

escriptions

5

LNK Allocate Stack Frame


X X X X

Syntax: {label:} LNK #lit14

Operands: lit14 ∈ [0 ... 16382]

Operation: (W14) → (TOS)(W15) + 2 → W15(W15) → W14(W15) + lit14 → W15


Encoding: 1111 1010 00kk kkkk kkkk kkk0

Description: This instruction allocates a Stack Frame of size lit14 bytes for a subroutine calling sequence. The Stack Frame is allocated by PUSHing the contents of the Frame Pointer (W14) onto the stack, storing the updated Stack Pointer (W15) to the Frame Pointer and then incrementing the Stack Pointer by the unsigned 14-bit literal operand. This instruction supports a maximum Stack Frame of 16382 bytes.

The ‘k’ bits specify the size of the Stack Frame.

Note: Since the Stack Pointer can only reside on a word boundary,lit14 must be even.

Words: 1

Cycles: 1

Example 1: LNK #0xA0 ; Allocate a stack frame of 160 bytes

Before Instruction

After Instruction

W14 2000 W14 2002W15 2000 W15 20A2

Data 2000 0000 Data 2000 2000SR 0000 SR 0000



LSR Logical Shift Right f


Syntax: {label:} LSR{.B} f {,WREG}

Operands: f ∈ [0 ... 8191]Operation: For byte operation:

0 → Dest<7> (f<7:1>) → Dest<6:0> (f<0>) → CFor word operation: 0 → Dest<15> (f<15:1>) → Dest<14:0> (f<0>) → C

Status Affected: N, Z, CEncoding: 1101 0101 0BDf ffff ffff ffff

Description: Shift the contents of the file register one bit to the right and place the result in the destination register. The Least Significant bit of the file register is shifted into the Carry bit of the STATUS register. Zero is shifted into the Most Significant bit of the destination register.

The optional WREG operand determines the destination register. If WREG is specified, the result is stored in WREG. If WREG is not specified, the result is stored in the file register.



2: The WREG is set to working register W0. Words: 1Cycles: 1

C0

Example 1: LSR.B 0x600 ; Logically shift right (0x600) by one ; (Byte mode)

BeforeInstruction

AfterInstruction

Data 600 55FF Data 600 557FSR 0000 SR 0001 (C = 1)

Example 2: LSR 0x600, WREG ; Logically shift right (0x600) by one ; Store to WREG ; (Word mode)

BeforeInstruction

AfterInstruction

Data 600 55FF Data 600 55FFWREG 0000 WREG 2AFF

SR 0000 SR 0001 (C = 1)


Instruction D

escriptions

5

LSR Logical Shift Right Ws


X X X X

Syntax: {label:} LSR{.B} Ws, Wd

[Ws], [Wd]

[Ws++], [Wd++]

[Ws--], [Wd--]

[++Ws], [++Wd]

[--Ws], [--Wd]


Operation: For byte operation: 0 → Wd<7> (Ws<7:1>) → Wd<6:0> (Ws<0>) → C For word operation: 0 → Wd<15> (Ws<15:1>) → Wd<14:0> (Ws<0>) → C



Description: Shift the contents of the source register Ws one bit to the right, and place the result in the destination register Wd. The Least Significant bit of Ws is shifted into the Carry bit of the STATUS register. Zero is shifted into the Most Significant bit of Wd. Either register direct or indirect addressing may be used for Ws and Wd.



Words: 1

Cycles: 1

C0

Example 1: LSR.B W0, W1 ; LSR W0 (Byte mode) ; Store result to W1

Before Instruction

After Instruction

W0 FF03 W0 FF03W1 2378 W1 2301SR 0000 SR 0001 (C = 1)



Example 2: LSR W0, W1 ; LSR W0 (Word mode) ; Store the result to W1

Before Instruction

After Instruction

W0 8000 W0 8000W1 2378 W1 4000SR 0000 SR 0000


Instruction D

escriptions

5

LSR Logical Shift Right by Short Literal


X X X X

Syntax: {label:} LSR Wb, #lit4, Wnd

Operands: Wb ∈ [W0 ... W15]lit4 ∈ [0 ... 15]Wnd ∈ [W0 ... W15]

Operation: lit4<3:0> → Shift_Val0 → Wnd<15:15-Shift_Val + 1>Wb<15:Shift_Val> → Wnd<15-Shift_Val:0>



Description: Logical shift right the contents of the source register Wb by the 4-bit unsigned literal and store the result in the destination register Wnd. Direct addressing must be used for Wb and Wnd.

The ‘w’ bits select the address of the base register.The ‘d’ bits select the destination register.The ‘k’ bits provide the literal operand.


Words: 1

Cycles: 1

Example 1: LSR W4, #14, W5 ; LSR W4 by 14 ; Store result to W5

Before Instruction

After Instruction

W4 C800 W4 C800W5 1200 W5 0003SR 0000 SR 0000

Example 2: LSR W4, #1, W5 ; LSR W4 by 1 ; Store result to W5

Before Instruction

After Instruction

W4 0505 W4 0505W5 F000 W5 0282SR 0000 SR 0000



LSR Logical Shift Right by Wns


X X X X

Syntax: {label:} LSR Wb, Wns, Wnd


Operation: Wns<4:0> → Shift_Val0 → Wnd<15:15-Shift_Val + 1>Wb<15:Shift_Val> → Wnd<15 - Shift_Val:0>


Encoding: 1101 1110 0www wddd d000 ssss

Description: Logical shift right the contents of the source register Wb by the 5 Least Significant bits of Wns (only up to 15 positions) and store the result in the destination register Wnd. Direct addressing must be used for Wb and Wnd.

The ‘w’ bits select the address of the base register.The ‘d’ bits select the destination register.The ‘s’ bits select the source register.

Note 1: This instruction operates in Word mode only.2: If Wns is greater than 15, Wnd will be loaded with 0x0.

Words: 1

Cycles: 1

Example 1: LSR W0, W1, W2 ; LSR W0 by W1 ; Store result to W2

Before Instruction

After Instruction

W0 C00C W0 C00CW1 0001 W1 0001W2 2390 W2 6006SR 0000 SR 0000

Example 2: LSR W5, W4, W3 ; LSR W5 by W4 ; Store result to W3

Before Instruction

After Instruction

W3 DD43 W3 0000W4 000C W4 000CW5 0800 W5 0800SR 0000 SR 0002 (Z = 1)


Instruction D

escriptions

5

MAC Multiply and Accumulate


X X

Syntax: {label:} MAC Wm*Wn, Acc {,[Wx], Wxd} {,[Wy], Wyd} {,AWB}

{,[Wx] + = kx, Wxd} {,[Wy] + = ky, Wyd}

{,[Wx] – = kx, Wxd}

{,[Wy] – = ky, Wyd}

{,[W9 + W12], Wxd}

{,[W11 + W12], Wyd}

Operands: Wm * Wn ∈ [W4 * W5, W4 * W6, W4 * W7, W5 * W6, W5 * W7, W6 * W7]Acc ∈ [A,B]Wx ∈ [W8, W9]; kx ∈ [-6, -4, -2, 2, 4, 6]; Wxd ∈ [W4 ... W7]Wy ∈ [W10, W11]; ky ∈ [-6, -4, -2, 2, 4, 6]; Wyd ∈ [W4 ... W7]AWB ∈ [W13, [W13] + = 2]

Operation: (Acc(A or B)) + (Wm) * (Wn) → Acc(A or B)([Wx]) → Wxd; (Wx) + kx → Wx([Wy]) → Wyd; (Wy) + ky → Wy(Acc(B or A)) rounded → AWB


Encoding: 1100 0mmm A0xx yyii iijj jjaa

Description: Multiply the contents of two working registers, optionally prefetch operands in preparation for another MAC type instruction and optionally store the unspecified accumulator results. The 32-bit result of the signed multiply is sign-extended to 40 bits and added to the specified accumulator.

Operands Wx, Wxd, Wy and Wyd specify optional prefetch operations, which support indirect and register offset addressing, as described in Section 4.14.1 “MAC Prefetches”. Operand AWB specifies the optional store of the “other” accumulator, as described in Section 4.14.4 “MAC Write Back”.

The ‘m’ bits select the operand registers Wm and Wn for the multiply.The ‘A’ bit selects the accumulator for the result. The ‘x’ bits select the prefetch Wxd destination.The ‘y’ bits select the prefetch Wyd destination.The ‘i’ bits select the Wx prefetch operation.The ‘j’ bits select the Wy prefetch operation.The ‘a’ bits select the accumulator Write Back destination.

Note: The IF bit, CORCON<0>, determines if the multiply is fractional or an integer.

Words: 1

Cycles: 1



Example 1: MAC W4*W5, A, [W8]+=6, W4, [W10]+=2, W5 ; Multiply W4*W5 and add to ACCA ; Fetch [W8] to W4, Post-increment W8 by 6; Fetch [W10] to W5, Post-increment W10 by 2; CORCON = 0x00C0 (fractional multiply, normal saturation)

Before Instruction

After Instruction

W4 A022 W4 2567W5 B900 W5 909CW8 0A00 W8 0A06

W10 1800 W10 1802ACCA 00 1200 0000 ACCA 00 472D 2400

Data 0A00 2567 Data 0A00 2567Data 1800 909C Data 1800 909CCORCON 00C0 CORCON 00C0

SR 0000 SR 0000

Example 2: MAC W4*W5, A, [W8]-=2, W4, [W10]+=2, W5, W13; Multiply W4*W5 and add to ACCA; Fetch [W8] to W4, Post-decrement W8 by 2; Fetch [W10] to W5, Post-increment W10 by 2; Write Back ACCB to W13; CORCON = 0x00D0 (fractional multiply, super saturation)

Before Instruction

After Instruction

W4 1000 W4 5BBEW5 3000 W5 C967W8 0A00 W8 09FE

W10 1800 W10 1802W13 2000 W13 0001

ACCA 23 5000 2000 ACCA 23 5600 2000ACCB 00 0000 8F4C ACCB 00 0000 1F4C

Data 0A00 5BBE Data 0A00 5BBEData 1800 C967 Data 1800 C967CORCON 00D0 CORCON 00D0

SR 0000 SR 8800 (OA, OAB = 1)


Instruction D

escriptions

5

MAC Square and Accumulate


X X

Syntax: {label:} MAC Wm*Wm, Acc {,[Wx], Wxd} {,[Wy], Wyd}

{,[Wx] + = kx, Wxd} {,[Wy] + = ky, Wyd}

{,[Wx] – = kx, Wxd} {,[Wy] – = ky, Wyd}

{,[W9 + W12], Wxd} {,[W11 + W12], Wyd}

Operands: Wm * Wm ∈ [W4 * W4, W5 * W5, W6 * W6, W7 * W7]Acc ∈ [A,B]Wx ∈ [W8, W9]; kx ∈ [-6, -4, -2, 2, 4, 6]; Wxd ∈ [W4 ... W7]Wy ∈ [W10, W11]; ky ∈ [-6, -4, -2, 2, 4, 6]; Wyd ∈ [W4 ... W7]

Operation: (Acc(A or B)) + (Wm) * (Wm) → Acc(A or B)([Wx]) → Wxd; (Wx) + kx → Wx([Wy]) → Wyd; (Wy) + ky → Wy


Encoding: 1111 00mm A0xx yyii iijj jj00

Description: Square the contents of a working register, optionally prefetch operands in preparation for another MAC type instruction and optionally store the unspecified accumulator results. The 32-bit result of the signed multiply is sign-extended to 40 bits and added to the specified accumulator.

Operands Wx, Wxd, Wy and Wyd specify optional prefetch operations, which support indirect and register offset addressing, as described in Section 4.14.1 “MAC Prefetches”.

The ‘m’ bits select the operand register Wm for the square.The ‘A’ bit selects the accumulator for the result. The ‘x’ bits select the prefetch Wxd destination.The ‘y’ bits select the prefetch Wyd destination.The ‘i’ bits select the Wx prefetch operation.The ‘j’ bits select the Wy prefetch operation.

Note: The IF bit, CORCON<0>, determines if the multiply is fractionalor an integer.

Words: 1

Cycles: 1



Example 1: MAC W4*W4, B, [W9+W12], W4, [W10]-=2, W5 ; Square W4 and add to ACCB; Fetch [W9+W12] to W4; Fetch [W10] to W5, Post-decrement W10 by 2; CORCON = 0x00C0 (fractional multiply, normal saturation)

Before Instruction

After Instruction

W4 A022 W4 A230W5 B200 W5 650BW9 0C00 W9 0C00

W10 1900 W10 18FEW12 0020 W12 0020

ACCB 00 2000 0000 ACCB 00 67CD 0908Data 0C20 A230 Data 0C20 A230Data 1900 650B Data 1900 650BCORCON 00C0 CORCON 00C0

SR 0000 SR 0000

Example 2: MAC W7*W7, A, [W11]-=2, W7; Square W7 and add to ACCA ; Fetch [W11] to W7, Post-decrement W11 by 2; CORCON = 0x00D0 (fractional multiply, super saturation)

Before Instruction

After Instruction

W7 76AE W7 23FFW11 2000 W11 1FFE

ACCA FE 9834 4500 ACCA FF 063E 0188Data 2000 23FF Data 2000 23FFCORCON 00D0 CORCON 00D0

SR 0000 SR 8800 (OA, OAB = 1)


Instruction D

escriptions

5

MOV Move f to Destination


X X X X

Syntax: {label:} MOV{.B} f {,WREG}

Operands: f ∈ [0 ... 8191]

Operation: (f) → destination designated by D



Description: Move the contents of the specified file register to the destination register.The optional WREG operand determines the destination register. IfWREG is specified, the result is stored in WREG. If WREG is notspecified, the result is stored back to the file register and the only effect isto modify the STATUS register.



2: The WREG is set to working register W0.3: When moving word data from file register memory, the “MOV f

to Wnd” (page 5-147) instruction allows any working register(W0:W15) to be the destination register.

Words: 1

Cycles: 1

Example 1: MOV.B TMR0, WREG ; move (TMR0) to WREG (Byte mode)

Before Instruction

After Instruction

WREG (W0) 9080 WREG (W0) 9055TMR0 2355 TMR0 2355

SR 0000 SR 0000

Example 2: MOV 0x800 ; update SR based on (0x800) (Word mode)

Before Instruction

After Instruction

Data 0800 B29F Data 0800 B29FSR 0000 SR 0008 (N = 1)



MOV Move WREG to f


X X X X

Syntax: {label:} MOV{.B} WREG, f

Operands: f ∈ [0 ... 8191]

Operation: (WREG) → f



Description: Move the contents of the default working register WREG into the specified file register.


Note 1: The extension .B in the instruction denotes a byte move ratherthan a word move. You may use a .W extension to denote aword move, but it is not required.

2: The WREG is set to working register W0.3: When moving word data from the working register array to file

register memory, the “MOV Wns to f” (page 5-148) instructionallows any working register (W0:W15) to be the source regis-ter.

Words: 1

Cycles: 1

Example 1: MOV.B WREG, 0x801 ; move WREG to 0x801 (Byte mode)

Before Instruction

After Instruction

WREG (W0) 98F3 WREG (W0) 98F3Data 0800 4509 Data 0800 F309

SR 0000 SR 0008 (N = 1)

Example 2: MOV WREG, DISICNT ; move WREG to DISICNT

Before Instruction

After Instruction

WREG (W0) 00A0 WREG (W0) 00A0DISICNT 0000 DISICNT 00A0

SR 0000 SR 0000


Instruction D

escriptions

5

MOV Move f to Wnd


X X X X

Syntax: {label:} MOV f, Wnd

Operands: f ∈ [0 ... 65534]Wnd ∈ [W0 ... W15]

Operation: (f) → Wnd


Encoding: 1000 0fff ffff ffff ffff dddd

Description: Move the word contents of the specified file register to Wnd. The file register may reside anywhere in the 32K words of data memory, but must be word-aligned. Register direct addressing must be used for Wnd.

The ‘f’ bits select the address of the file register.The ‘d’ bits select the destination register.

Note 1: This instruction operates on word operands only.2: Since the file register address must be word-aligned, only the

upper 15 bits of the file register address are encoded (bit 0 isassumed to be ‘0’).

3: To move a byte of data from file register memory, the “MOV fto Destination” instruction (page 5-145) may be used.

Words: 1

Cycles: 1

Example 1: MOV CORCON, W12 ; move CORCON to W12

Before Instruction

After Instruction

W12 78FA W12 00F0CORCON 00F0 CORCON 00F0

SR 0000 SR 0000

Example 2: MOV 0x27FE, W3 ; move (0x27FE) to W3

Before Instruction

After Instruction

W3 0035 W3 ABCDData 27FE ABCD Data 27FE ABCD

SR 0000 SR 0000



MOV Move Wns to f


X X X X

Syntax: {label:} MOV Wns, f

Operands: f ∈ [0 ... 65534]Wns ∈ [W0 ... W15]

Operation: (Wns) → f


Encoding: 1000 1fff ffff ffff ffff ssss

Description: Move the word contents of the working register Wns to the specified file register. The file register may reside anywhere in the 32K words of data memory, but must be word-aligned. Register direct addressing must be used for Wn.

The ‘f’ bits select the address of the file register.The ‘s’ bits select the source register.

Note 1: This instruction operates on word operands only.2: Since the file register address must be word-aligned, only the

upper 15 bits of the file register address are encoded (bit 0 isassumed to be ‘0’).

3: To move a byte of data to file register memory, the “MOV WREGto f” instruction (page 5-146) may be used.

Words: 1

Cycles: 1

Example 1: MOV W4, XMDOSRT ; move W4 to XMODSRT

Before Instruction

After Instruction

W4 1200 W4 1200XMODSRT 1340 XMODSRT 1200

SR 0000 SR 0000

Example 2: MOV W8, 0x1222 ; move W8 to data address 0x1222

Before Instruction

After Instruction

W8 F200 W8 F200Data 1222 FD88 Data 1222 F200

SR 0000 SR 0000


Instruction D

escriptions

5

MOV.B Move 8-bit Literal to Wnd


X X X X

Syntax: {label:} MOV.B #lit8, Wnd

Operands: lit8 ∈ [0 ... 255] Wnd ∈ [W0 ... W15]

Operation: lit8 → Wnd


Encoding: 1011 0011 1100 kkkk kkkk dddd

Description: The unsigned 8-bit literal ‘k’ is loaded into the lower byte of Wnd. The upper byte of Wnd is not changed. Register direct addressing must be used for Wnd.

The ‘k’ bits specify the value of the literal.The ‘d’ bits select the address of the working register.

Note: This instruction operates in Byte mode and the .B extensionmust be provided.

Words: 1

Cycles: 1

Example 1: MOV.B #0x17, W5 ; load W5 with #0x17 (Byte mode)

Before Instruction

After Instruction

W5 7899 W5 7817SR 0000 SR 0000

Example 2: MOV.B #0xFE, W9 ; load W9 with #0xFE (Byte mode)

Before Instruction

After Instruction

W9 AB23 W9 ABFESR 0000 SR 0000



MOV Move 16-bit Literal to Wnd


X X X X

Syntax: {label:} MOV #lit16, Wnd

Operands: lit16 ∈ [-32768 ... 65535]Wnd ∈ [W0 ... W15]

Operation: lit16 → Wnd


Encoding: 0010 kkkk kkkk kkkk kkkk dddd

Description: The 16-bit literal ‘k’ is loaded into Wnd. Register direct addressing must be used for Wnd.

The ‘k’ bits specify the value of the literal.The ‘d’ bits select the address of the working register.

Note 1: This instruction operates only in Word mode.2: The literal may be specified as a signed value [-32768:32767],

or unsigned value [0:65535].

Words: 1

Cycles: 1

Example 1: MOV #0x4231, W13 ; load W13 with #0x4231

Before Instruction

After Instruction

W13 091B W13 4231SR 0000 SR 0000

Example 2: MOV #0x4, W2 ; load W2 with #0x4

Before Instruction

After Instruction

W2 B004 W2 0004SR 0000 SR 0000

Example 3: MOV #-1000, W8 ; load W8 with #-1000

Before Instruction

After Instruction

W8 23FF W8 FC18SR 0000 SR 0000


Instruction D

escriptions

5

MOV Move [Ws with offset] to Wnd


X X X X

Syntax: {label:} MOV{.B} [Ws + Slit10], Wnd

Operands: Ws ∈ [W0 ... W15]Slit10 ∈ [-512 ... 511] for byte operationSlit10 ∈ [-1024 ... 1022] (even only) for word operationWnd ∈ [W0 ... W15]

Operation: [Ws + Slit10] → Wnd


Encoding: 1001 0kkk kBkk kddd dkkk ssss

Description: The contents of [Ws + Slit10] are loaded into Wnd. In Word mode, the range of Slit10 is increased to [-1024 ... 1022] and Slit10 must be even to maintain word address alignment. Register indirect addressing must be used for the source, and direct addressing must be used for Wnd.

The ‘k’ bits specify the value of the literal.The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘d’ bits select the destination register.The ‘s’ bits select the source register.


2: In Byte mode, the range of Slit10 is not reduced as specified inSection 4.6 “Using 10-bit Literal Operands”, since the literalrepresents an address offset from Ws.

Words: 1

Cycles: 1

Example 1: MOV.B [W8+0x13], W10 ; load W10 with [W8+0x13] ; (Byte mode)

Before Instruction

After Instruction

W8 1008 W8 1008W10 4009 W10 4033

Data 101A 3312 Data 101A 3312SR 0000 SR 0000

Example 2: MOV [W4+0x3E8], W2 ; load W2 with [W4+0x3E8] ; (Word mode)

Before Instruction

After Instruction

W2 9088 W2 5634W4 0800 W4 0800

Data 0BE8 5634 Data 0BE8 5634SR 0000 SR 0000



MOV Move Wns to [Wd with offset]


X X X X

Syntax: {label:} MOV{.B} Wns, [Wd + Slit10]

Operands: Wns ∈ [W0 ... W15]Slit10 ∈ [-512 ... 511] in Byte modeSlit10 ∈ [-1024 ... 1022] (even only) in Word modeWd ∈ [W0 ... W15]

Operation: (Wns) → [Wd + Slit10]


Encoding: 1001 1kkk kBkk kddd dkkk ssss

Description: The contents of Wns are stored to [Wd + Slit10]. In Word mode, the range of Slit10 is increased to [-1024 ... 1022] and Slit10 must be even to maintain word address alignment. Register direct addressing must be used for Wns, and indirect addressing must be used for the destination.

The ‘k’ bits specify the value of the literal.The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘d’ bits select the destination register.The ‘s’ bits select the address of the destination register.


2: In Byte mode, the range of Slit10 is not reduced as specified inSection 4.6 “Using 10-bit Literal Operands”, since the literalrepresents an address offset from Wd.

Words: 1

Cycles: 1

Example 1: MOV.B W0, [W1+0x7] ; store W0 to [W1+0x7] ; (Byte mode)

Before Instruction

After Instruction

W0 9015 W0 9015W1 1800 W1 1800

Data 1806 2345 Data 1806 1545SR 0000 SR 0000

Example 2: MOV W11, [W1-0x400] ; store W11 to [W1-0x400] ; (Word mode)

Before Instruction

After Instruction

W1 1000 W1 1000W11 8813 W11 8813

Data 0C00 FFEA Data 0C00 8813SR 0000 SR 0000


Instruction D

escriptions

5

MOV Move Ws to Wd


X X X X

Syntax: {label:} MOV{.B} Ws, Wd

[Ws], [Wd]

[Ws++], [Wd++]

[Ws--], [Wd--]

[--Ws], [--Wd]

[++Ws], [++Wd]

[Ws + Wb], [Wd + Wb]

Operands: Ws ∈ [W0 ... W15]Wb ∈ [W0 ... W15]Wd ∈ [W0 ... W15]

Operation: (Ws) → Wd


Encoding: 0111 1www wBhh hddd dggg ssss

Description: Move the contents of the source register into the destination register. Either register direct or indirect addressing may be used for Ws and Wd.

The ‘w’ bits define the offset register Wb.The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘h’ bits select the destination Address mode.The ‘d’ bits select the destination register.The ‘g’ bits select the source Address mode.The ‘s’ bits select the source register.


2: When Register Offset Addressing mode is used for both thesource and destination, the offset must be the same becausethe ‘w’ encoding bits are shared by Ws and Wd.

3: The instruction “PUSH Ws” translates to MOV Ws, [W15++].4: The instruction “POP Wd” translates to MOV [--W15], Wd.

Words: 1

Cycles: 1

Example 1: MOV.B [W0--], W4 ; Move [W0] to W4 (Byte mode) ; Post-decrement W0

Before Instruction

After Instruction

W0 0A01 W0 0A00W4 2976 W4 2989

Data 0A00 8988 Data 0A00 8988SR 0000 SR 0000



Example 2: MOV [W6++], [W2+W3] ; Move [W6] to [W2+W3] (Word mode) ; Post-increment W6

Before Instruction

After Instruction

W2 0800 W2 0800W3 0040 W3 0040W6 1228 W6 122A


SR 0000 SR 0000


Instruction D

escriptions

5

MOV.D Double Word Move from Source to Wnd


X X X X

Syntax: {label:} MOV.D Wns, Wnd

[Ws],

[Ws++],

[Ws--],

[++Ws],

[--Ws],

Operands: Wns ∈ [W0, W2, W4 ... W14]Ws ∈ [W0 ... W15]Wnd ∈ [W0, W2, W4 ... W14]

Operation: For direct addressing of source: Wns → Wnd Wns + 1 → Wnd + 1For indirect addressing of source: See Description


Encoding: 1011 1110 0000 0ddd 0ppp ssss

Description: Move the double word specified by the source to a destination working register pair (Wnd:Wnd + 1). If register direct addressing is used for the source, the contents of two successive working registers (Wns:Wns + 1) are moved to Wnd:Wnd + 1. If indirect addressing is used for the source, Ws specifies the effective address for the least significant word of the double word. Any pre/post-increment or pre/post-decrement will adjust Ws by 4 bytes to accommodate for the double word.

The ‘d’ bits select the destination register. The ‘p’ bits select the source Address mode.The ‘s’ bits select the address of the first source register.

Note 1: This instruction only operates on double words. See Figure 4-3for information on how double words are aligned in memory.

2: Wnd must be an even working register.3: The instruction “POP.D Wnd” translates to MOV.D [--W15],

Wnd.

Words: 1

Cycles: 2

Example 1: MOV.D W2, W6 ; Move W2 to W6 (Double mode)

Before Instruction

After Instruction

W2 12FB W2 12FBW3 9877 W3 9877W6 9833 W6 12FBW7 FCC6 W7 9877SR 0000 SR 0000



Example 2: MOV.D [W7--], W4 ; Move [W7] to W4 (Double mode) ; Post-decrement W7

Before Instruction

After Instruction

W4 B012 W4 A319W5 FD89 W5 9927W7 0900 W7 08FC

Data 0900 A319 Data 0900 A319Data 0902 9927 Data 0902 9927

SR 0000 SR 0000


Instruction D

escriptions

5

MOVSAC Prefetch Operands and Store Accumulator


X X

Syntax: {label:} MOVSAC Acc {,[Wx], Wxd} {,[Wy], Wyd} {,AWB}

{,[Wx] + = kx, Wxd} {,[Wy] + = ky, Wyd}

{,[Wx] – = kx, Wxd} {,[Wy] – = ky, Wyd}

{,[W9 + W12], Wxd} {,[W11 + W12], Wyd}

Operands: Acc ∈ [A,B]Wx ∈ [W8, W9]; kx ∈ [-6, -4, -2, 2, 4, 6]; Wxd ∈ [W4 ... W7]Wy ∈ [W10, W11]; ky ∈ [-6, -4, -2, 2, 4, 6]; Wyd ∈ [W4 ... W7]AWB ∈ [W13, [W13] + = 2]

Operation: ([Wx]) → Wxd; (Wx) + kx → Wx([Wy]) → Wyd; (Wy) + ky → Wy(Acc(B or A)) rounded → AWB


Encoding: 1100 0111 A0xx yyii iijj jjaa

Description: Optionally prefetch operands in preparation for another MAC type instruction and optionally store the unspecified accumulator results. Even though an accumulator operation is not performed in this instruction, an accumulator must be specified to designate which accumulator to write back.

Operands Wx, Wxd, Wy and Wyd specify optional prefetch operations which support indirect and register offset addressing, as described in Section 4.14.1 “MAC Prefetches”. Operand AWB specifies the optional store of the “other” accumulator, as described in Section 4.14.4 “MAC Write Back”.

The ‘A’ bit selects the other accumulator used for write back.The ‘x’ bits select the prefetch Wxd destination.The ‘y’ bits select the prefetch Wyd destination.The ‘i’ bits select the Wx prefetch operation.The ‘j’ bits select the Wy prefetch operation.The ‘a’ bits select the accumulator Write Back destination.

Words: 1

Cycles: 1



Example 1: MOVSAC B, [W9], W6, [W11]+=4, W7, W13; Fetch [W9] to W6; Fetch [W11] to W7, Post-increment W11 by 4; Store ACCA to W13

Before Instruction

After Instruction

W6 A022 W6 7811W7 B200 W7 B2AFW9 0800 W9 0800

W11 1900 W11 1904W13 0020 W13 3290

ACCA 00 3290 5968 ACCA 00 3290 5968Data 0800 7811 Data 0800 7811Data 1900 B2AF Data 1900 B2AF

SR 0000 SR 0000

Example 2: MOVSAC A, [W9]-=2, W4, [W11+W12], W6, [W13]+=2; Fetch [W9] to W4, Post-decrement W9 by 2; Fetch [W11+W12] to W6; Store ACCB to [W13], Post-increment W13 by 2

Before Instruction

After Instruction

W4 76AE W4 BB00W6 2000 W6 52CEW9 1200 W9 11FE

W11 2000 W11 2000W12 0024 W12 0024W13 2300 W13 2302

ACCB 00 9834 4500 ACCB 00 9834 4500Data 1200 BB00 Data 1200 BB00Data 2024 52CE Data 2024 52CEData 2300 23FF Data 2300 9834

SR 0000 SR 0000


Instruction D

escriptions

5

MPY Multiply Wm by Wn to Accumulator


X X

Syntax: {label:} MPY Wm * Wn, Acc

{,[Wx], Wxd} {,[Wy], Wyd}

{,[Wx] + = kx, Wxd} {,[Wy] + = ky, Wyd}

{,[Wx] – = kx, Wxd} {,[Wy] – = ky, Wyd}

{,[W9 + W12], Wxd} {,[W11 + W12], Wyd}

Operands: Wm * Wn ∈ [W4 * W5, W4 * W6, W4 * W7, W5 * W6, W5 * W7, W6 * W7]Acc ∈ [A,B]Wx ∈ [W8, W9]; kx ∈ [-6, -4, -2, 2, 4, 6]; Wxd ∈ [W4 ... W7]Wy ∈ [W10, W11]; ky ∈ [-6, -4, -2, 2, 4, 6]; Wyd ∈ [W4 ... W7]AWB ∈ [W13], [W13] + = 2

Operation: (Wm) * (Wn) → Acc(A or B)([Wx]) → Wxd; (Wx) + kx → Wx([Wy]) → Wyd; (Wy) + ky → Wy


Encoding: 1100 0mmm A0xx yyii iijj jj11

Description: Multiply the contents of two working registers, optionally prefetch operands in preparation for another MAC type instruction and optionally store the unspecified accumulator results. The 32-bit result of the signed multiply is sign-extended to 40 bits and stored to the specified accumulator.

Operands Wx, Wxd, Wy and Wyd specify optional prefetch operations which support indirect and register offset addressing, as described in Section 4.14.1 “MAC Prefetches”.

The ‘m’ bits select the operand registers Wm and Wn for the multiply:The ‘A’ bit selects the accumulator for the result.The ‘x’ bits select the prefetch Wxd destination.The ‘y’ bits select the prefetch Wyd destination.The ‘i’ bits select the Wx prefetch operation.The ‘j’ bits select the Wy prefetch operation.


Words: 1

Cycles: 1



Example 1: MPY W4*W5, A, [W8]+=2, W6, [W10]-=2, W7; Multiply W4*W5 and store to ACCA; Fetch [W8] to W6, Post-increment W8 by 2; Fetch [W10] to W7, Post-decrement W10 by 2; CORCON = 0x0000 (fractional multiply, no saturation)

Before Instruction

After Instruction

W4 C000 W4 C000W5 9000 W5 9000W6 0800 W6 671FW7 B200 W7 E3DCW8 1780 W8 1782

W10 2400 W10 23FEACCA FF F780 2087 ACCA 00 3800 0000

Data 1780 671F Data 1780 671FData 2400 E3DC Data 2400 E3DCCORCON 0000 CORCON 0000

SR 0000 SR 0000

Example 2: MPY W6*W7, B, [W8]+=2, W4, [W10]-=2, W5; Multiply W6*W7 and store to ACCB; Fetch [W8] to W4, Post-increment W8 by 2 ; Fetch [W10] to W5, Post-decrement W10 by 2; CORCON = 0x0000 (fractional multiply, no saturation)

Before Instruction

After Instruction

W4 C000 W4 8FDCW5 9000 W5 0078W6 671F W6 671FW7 E3DC W7 E3DCW8 1782 W8 1784

W10 23FE W10 23FCACCB 00 9834 4500 ACCB FF E954 3748

Data 1782 8FDC Data 1782 8FDCData 23FE 0078 Data 23FE 0078CORCON 0000 CORCON 0000

SR 0000 SR 0000


Instruction D

escriptions

5

MPY Square to Accumulator


X X

Syntax: {label:} MPY Wm * Wm, Acc {,[Wx], Wxd} {,[Wy], Wyd}

{,[Wx] + = kx, Wxd} {,[Wy] + = ky, Wyd}

{,[Wx] – = kx, Wxd} {,[Wy] – = ky, Wyd}

{,[W9 + W12], Wxd} {,[W11 + W12], Wyd}

Operands: Wm * Wm ∈ [W4 * W4, W5 * W5, W6 * W6, W7 * W7]Acc ∈ [A,B]Wx ∈ [W8, W9]; kx ∈ [-6, -4, -2, 2, 4, 6]; Wxd ∈ [W4 ... W7]Wy ∈ [W10, W11]; ky ∈ [-6, -4, -2, 2, 4, 6]; Wyd ∈ [W4 ... W7]

Operation: (Wm) * (Wm) → Acc(A or B)([Wx]) → Wxd; (Wx) + kx → Wx([Wy]) → Wyd; (Wy) + ky → Wy


Encoding: 1111 00mm A0xx yyii iijj jj01

Description: Square the contents of a working register, optionally prefetch operands in preparation for another MAC type instruction and optionally store the unspecified accumulator results. The 32-bit result of the signed multiply is sign-extended to 40 bits and stored in the specified accumulator.

Operands Wx, Wxd, Wy and Wyd specify optional prefetch operations which support indirect and register offset addressing, as described in Section 4.14.1 “MAC Prefetches”.

The ‘m’ bits select the operand register Wm for the square.The ‘A’ bit selects the accumulator for the result.The ‘x’ bits select the prefetch Wxd destination.The ‘y’ bits select the prefetch Wyd destination.The ‘i’ bits select the Wx prefetch operation.The ‘j’ bits select the Wy prefetch operation.


Words: 1

Cycles: 1

Example 1: MPY W6*W6, A, [W9]+=2, W6; Square W6 and store to ACCA; Fetch [W9] to W6, Post-increment W9 by 2; CORCON = 0x0000 (fractional multiply, no saturation)

Before Instruction

After Instruction

W6 6500 W6 B865W9 0900 W9 0902

ACCA 00 7C80 0908 ACCA 00 4FB2 0000Data 0900 B865 Data 0900 B865CORCON 0000 CORCON 0000

SR 0000 SR 0000



Example 2: MPY W4*W4, B, [W9+W12], W4, [W10]+=2, W5; Square W4 and store to ACCB; Fetch [W9+W12] to W4; Fetch [W10] to W5, Post-increment W10 by 2; CORCON = 0x0000 (fractional multiply, no saturation)

Before Instruction

After Instruction

W4 E228 W4 8911W5 9000 W5 F678W9 1700 W9 1700

W10 1B00 W10 1B02W12 FF00 W12 FF00

ACCB 00 9834 4500 ACCB 00 06F5 4C80Data 1600 8911 Data 1600 8911Data 1B00 F678 Data 1B00 F678CORCON 0000 CORCON 0000

SR 0000 SR 0000


Instruction D

escriptions

5

MPY.N Multiply -Wm by Wn to Accumulator


X X

Syntax: {label:} MPY.N Wm * Wn, Acc {,[Wx], Wxd} {,[Wy], Wyd}

{,[Wx] + = kx, Wxd} {,[Wy] + = ky, Wyd}

{,[Wx] – = kx, Wxd} {,[Wy] – = ky, Wyd}

{,[W9 + W12], Wxd} {,[W11 + W12], Wyd}

Operands: Wm * Wn ∈ [W4 * W5; W4 * W6; W4 * W7; W5 * W6; W5 * W7; W6 * W7]Acc ∈ [A,B]Wx ∈ [W8, W9]; kx ∈ [-6, -4, -2, 2, 4, 6]; Wxd ∈ [W4 ... W7]Wy ∈ [W10, W11]; ky ∈ [-6, -4, -2, 2, 4, 6]; Wyd ∈ [W4 ... W7]

Operation: -(Wm) * (Wn) → Acc(A or B)([Wx]) → Wxd; (Wx) + kx → Wx([Wy]) → Wyd; (Wy) + ky → Wy

Status Affected: OA, OB, OAB

Encoding: 1100 0mmm A1xx yyii iijj jj11

Description: Multiply the contents of a working register by the negative of the contents of another working register, optionally prefetch operands in preparation for another MAC type instruction and optionally store the unspecified accumulator results. The 32-bit result of the signed multiply is sign-extended to 40 bits and stored to the specified accumulator.

The ‘m’ bits select the operand registers Wm and Wn for the multiply.The ‘A’ bit selects the accumulator for the result.The ‘x’ bits select the prefetch Wxd destination.The ‘y’ bits select the prefetch Wyd destination.The ‘i’ bits select the Wx prefetch operation.The ‘j’ bits select the Wy prefetch operation.

Note: The IF bit, CORCON<0>, determines if the multiply is fractionalor an integer.

Words: 1

Cycles: 1



Example 1: MPY.N W4*W5, A, [W8]+=2, W4, [W10]+=2, W5; Multiply W4*W5, negate the result and store to ACCA; Fetch [W8] to W4, Post-increment W8 by 2; Fetch [W10] to W5, Post-increment W10 by 2; CORCON = 0x0001 (integer multiply, no saturation)

Before Instruction

After Instruction

W4 3023 W4 0054W5 1290 W5 660AW8 0B00 W8 0B02

W10 2000 W10 2002ACCA 00 0000 2387 ACCA FF FC82 7650

Data 0B00 0054 Data 0B00 0054Data 2000 660A Data 2000 660ACORCON 0001 CORCON 0001

SR 0000 SR 0000

Example 2: MPY.N W4*W5, A, [W8]+=2, W4, [W10]+=2, W5; Multiply W4*W5, negate the result and store to ACCA; Fetch [W8] to W4, Post-increment W8 by 2 ; Fetch [W10] to W5, Post-increment W10 by 2; CORCON = 0x0000 (fractional multiply, no saturation)

Before Instruction

After Instruction

W4 3023 W4 0054W5 1290 W5 660AW8 0B00 W8 0B02

W10 2000 W10 2002ACCA 00 0000 2387 ACCA FF F904 ECA0

Data 0B00 0054 Data 0B00 0054Data 2000 660A Data 2000 660ACORCON 0000 CORCON 0000

SR 0000 SR 0000


Instruction D

escriptions

5

MSC Multiply and Subtract from Accumulator


X X

Syntax: {label:} MSC Wm * Wn, Acc {,[Wx], Wxd} {,[Wy], Wyd} {,AWB}

{,[Wx] + = kx, Wxd} {,[Wy] + = ky, Wyd}

{,[Wx] – = kx, Wxd} {,[Wy] – = ky, Wyd}

{,[W9 + W12], Wxd} {,[W11 + W12], Wyd}

Operands: Wm * Wn ∈ [W4 * W5, W4 * W6, W4 * W7, W5 * W6, W5 * W7, W6 * W7]Acc ∈ [A,B]Wx ∈ [W8, W9]; kx ∈ [-6, -4, -2, 2, 4, 6]; Wxd ∈ [W4 ... W7]Wy ∈ [W10, W11]; ky ∈ [-6, -4, -2, 2, 4, 6]; Wyd ∈ [W4 ... W7]AWB ∈ [W13, [W13] + = 2]

Operation: (Acc(A or B)) − (Wm) * (Wn) → Acc(A or B)([Wx]) → Wxd; (Wx) + kx → Wx([Wy]) → Wyd; (Wy) + ky → Wy(Acc(B or A)) rounded → AWB


Encoding: 1100 0mmm A1xx yyii iijj jjaa

Description: Multiply the contents of two working registers, optionally prefetch operands in preparation for another MAC type instruction and optionally store the unspecified accumulator results. The 32-bit result of the signed multiply is sign-extended to 40 bits and subtracted from the specified accumulator.

Operands Wx, Wxd, Wy and Wyd specify optional prefetch operations which support indirect and register offset addressing as described in Section 4.14.1 “MAC Prefetches”. Operand AWB specifies the optional store of the “other” accumulator as described in Section 4.14.4 “MAC Write Back”.

The ‘m’ bits select the operand registers Wm and Wn for the multiply.The ‘A’ bit selects the accumulator for the result.The ‘x’ bits select the prefetch Wxd destination.The ‘y’ bits select the prefetch Wyd destination.The ‘i’ bits select the Wx prefetch operation.The ‘j’ bits select the Wy prefetch operation.The ‘a’ bits select the accumulator Write Back destination.


Words: 1

Cycles: 1



Example 1: MSC W6*W7, A, [W8]-=4, W6, [W10]-=4, W7; Multiply W6*W7 and subtract the result from ACCA; Fetch [W8] to W6, Post-decrement W8 by 4; Fetch [W10] to W7, Post-decrement W10 by 4; CORCON = 0x0001 (integer multiply, no saturation)

Before Instruction

After Instruction

W6 9051 W6 D309W7 7230 W7 100BW8 0C00 W8 0BFC

W10 1C00 W10 1BFCACCA 00 0567 8000 ACCA 00 3738 5ED0

Data 0C00 D309 Data 0C00 D309Data 1C00 100B Data 1C00 100BCORCON 0001 CORCON 0001

SR 0000 SR 0000

Example 2: MSC W4*W5, B, [W11+W12], W5, W13; Multiply W4*W5 and subtract the result from ACCB; Fetch [W11+W12] to W5; Write Back ACCA to W13; CORCON = 0x0000 (fractional multiply, no saturation)

Before Instruction

After Instruction

W4 0500 W4 0500W5 2000 W5 3579

W11 1800 W11 1800W12 0800 W12 0800W13 6233 W13 3738

ACCA 00 3738 5ED0 ACCA 00 3738 5ED0ACCB 00 1000 0000 ACCB 00 0EC0 0000

Data 2000 3579 Data 2000 3579CORCON 0000 CORCON 0000

SR 0000 SR 0000


Instruction D

escriptions

5

MUL Integer Unsigned Multiply f and WREG


X X X X

Syntax: {label:} MUL{.B} f

Operands: f ∈ [0 ... 8191]

Operation: For byte operation: (WREG)<7:0> * (f)<7:0> → W2For word operation: (WREG) * (f) → W2:W3



Description: Multiply the default working register WREG with the specified file register and place the result in the W2:W3 register pair. Both operands and the result are interpreted as unsigned integers. If this instruction is executed in Byte mode, the 16-bit result is stored in W2. In Word mode, the most significant word of the 32-bit result is stored in W3, and the least significant word of the 32-bit result is stored in W2.



2: The WREG is set to working register W0. 3: The IF bit, CORCON<0>, has no effect on this operation.4: This is the only instruction, which provides for an 8-bit

multiply.

Words: 1

Cycles: 1

Example 1: MUL.B 0x800 ; Multiply (0x800)*WREG (Byte mode)

Before Instruction

After Instruction

WREG (W0) 9823 WREG (W0) 9823W2 FFFF W2 13B0W3 FFFF W3 FFFF

Data 0800 2690 Data 0800 2690SR 0000 SR 0000

Example 2: MUL TMR1 ; Multiply (TMR1)*WREG (Word mode)

Before Instruction

After Instruction

WREG (W0) F001 WREG (W0) F001W2 0000 W2 C287W3 0000 W3 2F5E

TMR1 3287 TMR1 3287SR 0000 SR 0000



MUL.SS Integer 16x16-bit Signed Multiply


X X X X

Syntax: {label:} MUL.SS Wb, Ws, Wnd

[Ws],

[Ws++],

[Ws--],

[++Ws],

[--Ws],

Operands: Wb ∈ [W0 ... W15]Ws ∈ [W0 ... W15] Wnd ∈ [W0, W2, W4 ... W12]

Operation: signed (Wb) * signed (Ws) → Wnd:Wnd + 1


Encoding: 1011 1001 1www wddd dppp ssss

Description: Multiply the contents of Wb with the contents of Ws, and store the 32-bit result in two successive working registers. The least significant word of the result is stored in Wnd (which must be an even numbered working register), and the most significant word of the result is stored in Wnd + 1. Both source operands and the result Wnd are interpreted as two’s complement signed integers. Register direct addressing must be used for Wb and Wnd. Register direct or register indirect addressing may be used for Ws.

The ‘w’ bits select the address of the base register.The ‘d’ bits select the address of the lower destination register.The ‘p’ bits select the source Address mode.The ‘s’ bits select the source register.

Note 1: This instruction operates in Word mode only.2: Since the product of the multiplication is 32 bits, Wnd must be

an even working register. See Figure 4-2 for information onhow double words are aligned in memory.

3: Wnd may not be W14, since W15<0> is fixed to zero. 4: The IF bit, CORCON<0>, has no effect on this operation.

Words: 1

Cycles: 1

Example 1: MUL.SS W0, W1, W12 ; Multiply W0*W1 ; Store the result to W12:W13

Before Instruction

After Instruction

W0 9823 W0 9823W1 67DC W1 67DC

W12 FFFF W12 D314W13 FFFF W13 D5DC

SR 0000 SR 0000


Instruction D

escriptions

5

Example 2: MUL.SS W2, [--W4], W0 ; Pre-decrement W4 ; Multiply W2*[W4] ; Store the result to W0:W1

Before Instruction

After Instruction

W0 FFFF W0 28F8W1 FFFF W1 0000W2 0045 W2 0045W4 27FE W4 27FC

Data 27FC 0098 Data 27FC 0098SR 0000 SR 0000



MUL.SU Integer 16x16-bit Signed-Unsigned Short Literal Multiply


X X X X

Syntax: {label:} MUL.SU Wb, #lit5, Wnd

Operands: Wb ∈ [W0 ... W15]lit5 ∈ [0 ... 31]Wnd ∈ [W0, W2, W4 ... W12]

Operation: signed (Wb) * unsigned lit5 → Wnd:Wnd + 1


Encoding: 1011 1001 0www wddd d11k kkkk

Description: Multiply the contents of Wb with the 5-bit literal, and store the 32-bit result in two successive working registers. The least significant word of the result is stored in Wnd (which must be an even numbered working register), and the most significant word of the result is stored in Wnd + 1. The Wb operand and the result Wnd are interpreted as a two’s complement signed integer. The literal is interpreted as an unsigned inte-ger. Register direct addressing must be used for Wb and Wnd.

The ‘w’ bits select the address of the base register.The ‘d’ bits select the address of the lower destination register.The ‘k’ bits define a 5-bit unsigned integer literal.




Words: 1

Cycles: 1

Example 1: MUL.SU W0, #0x1F, W2 ; Multiply W0 by literal 0x1F ; Store the result to W2:W3

Before Instruction

After Instruction

W0 C000 W0 C000W2 1234 W2 4000W3 C9BA W3 FFF8SR 0000 SR 0000


Instruction D

escriptions

5

Example 2: MUL.SU W2, #0x10, W0 ; Multiply W2 by literal 0x10 ; Store the result to W0:W1

Before Instruction

After Instruction

W0 ABCD W0 2400W1 89B3 W1 000FW2 F240 W2 F240SR 0000 SR 0000



MUL.SU Integer 16x16-bit Signed-Unsigned Multiply


X X X X

Syntax: {label:} MUL.SU Wb, Ws, Wnd

[Ws],

[Ws++],

[Ws--],

[++Ws],

[--Ws],


Operation: signed (Wb) * unsigned (Ws) → Wnd:Wnd + 1



Description: Multiply the contents of Wb with the contents of Ws, and store the 32-bit result in two successive working registers. The least significant word of the result is stored in Wnd (which must be an even numbered working register), and the most significant word of the result is stored in Wnd + 1. The Wb operand and the result Wnd are interpreted as a two’s complement signed integer. The Ws operand is interpreted as an unsigned integer. Register direct addressing must be used for Wb and Wnd. Register direct or register indirect addressing may be used for Ws.





Words: 1

Cycles: 1

Example 1: MUL.SU W8, [W9], W0 ; Multiply W8*[W9] ; Store the result to W0:W1

Before Instruction

After Instruction

W0 68DC W0 0000W1 AA40 W1 F100W8 F000 W8 F000W9 178C W9 178C

Data 178C F000 Data 178C F000SR 0000 SR 0000


Instruction D

escriptions

5

Example 2: MUL.SU W2, [++W3], W4 ; Pre-Increment W3 ; Multiply W2*[W3] ; Store the result to W4:W5

Before Instruction

After Instruction

W2 0040 W2 0040W3 0280 W3 0282W4 1819 W4 1A00W5 2021 W5 0000

Data 0282 0068 Data 0282 0068SR 0000 SR 0000



MUL.US Integer 16x16-bit Unsigned-Signed Multiply


X X X X

Syntax: {label:} MUL.US Wb, Ws, Wnd

[Ws],

[Ws++],

[Ws--],

[++Ws],

[--Ws],


Operation: unsigned (Wb) * signed (Ws) → Wnd:Wnd + 1



Description: Multiply the contents of Wb with the contents of Ws, and store the 32-bit result in two successive working registers. The least significant word of the result is stored in Wnd (which must be an even numbered working register), and the most significant word of the result is stored in Wnd + 1. The Wb operand is interpreted as an unsigned integer. The Ws operand and the result Wnd are interpreted as a two’s complement signed integer. Register direct addressing must be used for Wb and Wnd. Register direct or register indirect addressing may be used for Ws.





Words: 1

Cycles: 1

Example 1: MUL.US W0, [W1], W2 ; Multiply W0*[W1] (unsigned-signed) ; Store the result to W2:W3

Before Instruction

After Instruction

W0 C000 W0 C000W1 2300 W1 2300W2 00DA W2 0000W3 CC25 W3 F400

Data 2300 F000 Data 2300 F000SR 0000 SR 0000


Instruction D

escriptions

5

Example 2: MUL.US W6, [W5++], W10 ; Mult. W6*[W5] (unsigned-signed) ; Store the result to W10:W11 ; Post-Increment W5

Before Instruction

After Instruction

W5 0C00 W5 0C02W6 FFFF W6 FFFF

W10 0908 W10 8001W11 6EEB W11 7FFE

Data 0C00 7FFF Data 0C00 7FFFSR 0000 SR 0000



MUL.UU Integer 16x16-bit Unsigned Short Literal Multiply


X X X X

Syntax: {label:} MUL.UU Wb, #lit5, Wnd

Operands: Wb ∈ [W0 ... W15]lit5 ∈ [0 ... 31]Wnd ∈ [W0, W2, W4 ... W12]

Operation: unsigned (Wb) * unsigned lit5 → Wnd:Wnd + 1


Encoding: 1011 1000 0www wddd d11k kkkk

Description: Multiply the contents of Wb with the 5-bit literal, and store the 32-bit result in two successive working registers. The least significant word of the result is stored in Wnd (which must be an even numbered working register), and the most significant word of the result is stored in Wnd + 1. Both operands and the result are interpreted as unsigned integers. Register direct addressing must be used for Wb and Wnd.

The ‘w’ bits select the address of the base register.The ‘d’ bits select the address of the lower destination register.The ‘k’ bits define a 5-bit unsigned integer literal.




Words: 1

Cycles: 1

Example 1: MUL.UU W0, #0xF, W12 ; Multiply W0 by literal 0xF ; Store the result to W12:W13

Before Instruction

After Instruction

W0 2323 W0 2323W12 4512 W12 0F0DW13 7821 W13 0002

SR 0000 SR 0000

Example 2: MUL.UU W7, #0x1F, W0 ; Multiply W7 by literal 0x1F ; Store the result to W0:W1

Before Instruction

After Instruction

W0 780B W0 55C0W1 3805 W1 001DW7 F240 W7 F240SR 0000 SR 0000


Instruction D

escriptions

5

MUL.UU Integer 16x16-bit Unsigned Multiply


X X X X

Syntax: {label:} MUL.UU Wb, Ws, Wnd

[Ws],

[Ws++],

[Ws--],

[++Ws],

[--Ws],


Operation: unsigned (Wb) * unsigned (Ws) → Wnd:Wnd + 1



Description: Multiply the contents of Wb with the contents of Ws, and store the 32-bit result in two successive working registers. The least significant word of the result is stored in Wnd (which must be an even numbered working register), and the most significant word of the result is stored in Wnd + 1. Both source operands and the result are interpreted as unsigned integers. Register direct addressing must be used for Wb and Wnd. Register direct or indirect addressing may be used for Ws.





Words: 1

Cycles: 1

Example 1: MUL.UU W4, W0, W2 ; Multiply W4*W0 (unsigned-unsigned) ; Store the result to W2:W3

Before Instruction

After Instruction

W0 FFFF W0 FFFFW2 2300 W2 0001W3 00DA W3 FFFEW4 FFFF W4 FFFFSR 0000 SR 0000



Example 2: MUL.UU W0, [W1++], W4 ; Mult. W0*[W1] (unsigned-unsigned) ; Store the result to W4:W5 ; Post-Increment W1

Before Instruction

After Instruction

W0 1024 W0 1024W1 2300 W1 2302W4 9654 W4 6D34W5 BDBC W5 0D80

Data 2300 D625 Data 2300 D625SR 0000 SR 0000


Instruction D

escriptions

5

NEG Negate f


X X X X

Syntax: {label:} NEG{.B} f {,WREG}

Operands: f ∈ [0 ... 8191]




Description: Compute the two’s complement of the contents of the file register and place the result in the destination register. The optional WREG operand determines the destination register. If WREG is specified, the result is stored in WREG. If WREG is not specified, the result is stored in the file register.




Words: 1

Cycles: 1

Example 1: NEG.B 0x880, WREG ; Negate (0x880) (Byte mode) ; Store result to WREG

Before Instruction

After Instruction

WREG (W0) 9080 WREG (W0) 90ABData 0880 2355 Data 0880 2355

SR 0000 SR 0008 (N = 1)

Example 2: NEG 0x1200 ; Negate (0x1200) (Word mode)

Before Instruction

After Instruction

Data 1200 8923 Data 1200 76DDSR 0000 SR 0000



NEG Negate Ws


Syntax: {label:} NEG{.B} Ws, Wd[Ws], [Wd][Ws++], [Wd++][Ws--], [Wd--][++Ws], [++Wd][--Ws], [--Wd]


Operation: (Ws) + 1 → Wd Status Affected: DC, N, OV, Z, CEncoding: 1110 1010 0Bqq qddd dppp ssss

Description: Compute the two’s complement of the contents of the source register Ws and place the result in the destination register Wd. Either register direct or indirect addressing may be used for both Ws and Wd.



Words: 1Cycles: 1

Example 1: NEG.B W3, [W4++] ; Negate W3 and store to [W4] (Byte mode) ; Post-increment W4

Before Instruction

After Instruction

W3 7839 W3 7839W4 1005 W4 1006

Data 1004 2355 Data 1004 C755SR 0000 SR 0008 (N = 1)

Example 2: NEG [W2++], [--W4] ; Pre-decrement W4 (Word mode) ; Negate [W2] and store to [W4] ; Post-increment W2

Before Instruction

After Instruction

W2 0900 W2 0902W4 1002 W4 1000

Data 0900 870F Data 0900 870FData 1000 5105 Data 1000 78F1

SR 0000 SR 0000


Instruction D

escriptions

5

NEG Negate Accumulator


X X

Syntax: {label:} NEG Acc


Operation: If (Acc = A): -ACCA → ACCAElse: -ACCB → ACCB


Encoding: 1100 1011 A001 0000 0000 0000

Description: Compute the two’s complement of the contents of the specified accumulator. Regardless of the Saturation mode, this instruction operates on all 40 bits of the accumulator.

The ‘A’ bit specifies the selected accumulator.

Words: 1

Cycles: 1

Example 1: NEG A ; Negate ACCA ; Store result to ACCA ; CORCON = 0x0000 (no saturation)

Before Instruction

After Instruction

ACCA 00 3290 59C8 ACCA FF CD6F A638CORCON 0000 CORCON 0000

SR 0000 SR 0000

Example 2: NEG B ; Negate ACCB ; Store result to ACCB ; CORCON = 0x00C0 (normal saturation)

Before Instruction

After Instruction

ACCB FF F230 10DC ACCB 00 0DCF EF24CORCON 00C0 CORCON 00C0

SR 0000 SR 0000



NOP No Operation


X X X X

Syntax: {label:} NOP

Operands: None

Operation: No Operation


Encoding: 0000 0000 xxxx xxxx xxxx xxxx

Description: No Operation is performed.

The ‘x’ bits can take any value.

Words: 1

Cycles: 1

Example 1: NOP ; execute no operation

Before Instruction

After Instruction

PC 00 1092 PC 00 1094SR 0000 SR 0000

Example 2: NOP ; execute no operation

Before Instruction

After Instruction

PC 00 08AE PC 00 08B0SR 0000 SR 0000


Instruction D

escriptions

5

NOPR No Operation


X X X X

Syntax: {label:} NOPR

Operands: None

Operation: No Operation


Encoding: 1111 1111 xxxx xxxx xxxx xxxx

Description: No Operation is performed.

The ‘x’ bits can take any value.

Words: 1

Cycles: 1

Example 1: NOPR ; execute no operation

Before Instruction

After Instruction

PC 00 2430 PC 00 2432SR 0000 SR 0000

Example 2: NOPR ; execute no operation

Before Instruction

After Instruction

PC 00 1466 PC 00 1468SR 0000 SR 0000



POP Pop TOS to f


X X X X

Syntax: {label:} POP f

Operands: f ∈ [0 ... 65534]

Operation: (W15) – 2 → W15(TOS) → f


Encoding: 1111 1001 ffff ffff ffff fff0

Description: The Stack Pointer (W15) is pre-decremented by 2 and the Top-of-Stack (TOS) word is written to the specified file register, which may reside anywhere in the lower 32K words of data memory.

The ‘f’ bits select the address of the file register.

Note 1: This instruction operates in Word mode only.2: The file register address must be word-aligned.

Words: 1

Cycles: 1

Example 1: POP 0x1230 ; Pop TOS to 0x1230

Before Instruction

After Instruction

W15 1006 W15 1004Data 1004 A401 Data 1004 A401Data 1230 2355 Data 1230 A401

SR 0000 SR 0000

Example 2: POP 0x880 ; Pop TOS to 0x880

Before Instruction

After Instruction

W15 2000 W15 1FFEData 0880 E3E1 Data 0880 A090Data 1FFE A090 Data 1FFE A090

SR 0000 SR 0000


Instruction D

escriptions

5

POP Pop TOS to Wd


Syntax: {label:} POP Wd[Wd][Wd++][Wd--][--Wd][++Wd][Wd+Wb]

Operands: Wd ∈ [W0 ... W15]Wb ∈ [W0 ... W15]

Operation: (W15) – 2 → W15(TOS) → Wd

Status Affected: NoneEncoding: 0111 1www w0hh hddd d100 1111

Description: The Stack Pointer (W15) is pre-decremented by 2 and the Top-of-Stack (TOS) word is written to Wd. Either register direct or indirect addressing may be used for Wd.

The ‘w’ bits define the offset register Wb.The ‘h’ bits select the destination Address mode.The ‘d’ bits select the destination register.

Note 1: This instruction operates in Word mode only.2: This instruction is a specific version of the “MOV Ws, Wd”

instruction (MOV [--W15], Wd). It reverse assembles asMOV.

Words: 1Cycles: 1

Example 1: POP W4 ; Pop TOS to W4

Before Instruction

After Instruction

W4 EDA8 W4 C45AW15 1008 W15 1006

Data 1006 C45A Data 1006 C45ASR 0000 SR 0000

Example 2: POP [++W10] ; Pre-increment W10 ; Pop TOS to [W10]

Before Instruction

After Instruction

W10 0E02 W10 0E04W15 1766 W15 1764

Data 0E04 E3E1 Data 0E04 C7B5Data 1764 C7B5 Data 1764 C7B5

SR 0000 SR 0000



POP.D Double Pop TOS to Wnd:Wnd+1


X X X X

Syntax: {label:} POP.D Wnd

Operands: Wnd ∈ [W0, W2, W4, ... W14]

Operation: (W15) – 2 → W15(TOS) → Wnd + 1(W15) – 2 → W15(TOS) → Wnd


Encoding: 1011 1110 0000 0ddd 0100 1111

Description: A double word is POPped from the Top-of-Stack (TOS) and stored to Wnd:Wnd + 1. The most significant word is stored to Wnd + 1, and the least significant word is stored to Wnd. Since a double word is POPped, the Stack Pointer (W15) gets decremented by 4.

The ‘d’ bits select the address of the destination register pair.

Note 1: This instruction operates on double words. See Figure 4-3 forinformation on how double words are aligned in memory.

2: Wnd must be an even working register.3: This instruction is a specific version of the “MOV.D Ws, Wnd”

instruction (MOV.D [--W15], Wnd). It reverse assembles asMOV.D.

Words: 1

Cycles: 2

Example 1: POP.D W6 ; Double pop TOS to W6

Before Instruction

After Instruction

W6 07BB W6 3210W7 89AE W7 7654

W15 0850 W15 084CData 084C 3210 Data 084C 3210Data 084E 7654 Data 084E 7654

SR 0000 SR 0000

Example 2: POP.D W0 ; Double pop TOS to W0

Before Instruction

After Instruction

W0 673E W0 791CW1 DD23 W1 D400

W15 0BBC W15 0BB8Data 0BB8 791C Data 0BB8 791CData 0BBA D400 Data 0BBA D400

SR 0000 SR 0000


Instruction D

escriptions

5

POP.S Pop Shadow Registers


X X X X

Syntax: {label:} POP.S

Operands: None

Operation: POP shadow registers


Encoding: 1111 1110 1000 0000 0000 0000

Description: The values in the shadow registers are copied into their respective primary registers. The following registers are affected: W0-W3, and the C, Z, OV, N and DC STATUS register flags.

Note 1: The shadow registers are not directly accessible. They mayonly be accessed with PUSH.S and POP.S.

2: The shadow registers are only one-level deep.

Words: 1

Cycles: 1

Example 1: POP.S ; Pop the shadow registers ; (See PUSH.S Example 1 for contents of shadows)

Before Instruction

After Instruction

W0 07BB W0 0000W1 03FD W1 1000W2 9610 W2 2000W3 7249 W3 3000SR 00E0 (IPL = 7) SR 00E1 (IPL = 7, C = 1)

Note: After instruction execution, contents of shadow registers are NOT modified.



PUSH Push f to TOS


X X X X

Syntax: {label:} PUSH f

Operands: f ∈ [0 ... 65534]

Operation: (f) → (TOS)(W15) + 2 → W15


Encoding: 1111 1000 ffff ffff ffff fff0

Description: The contents of the specified file register are written to the Top-of-Stack (TOS) location and then the Stack Pointer (W15) is incremented by 2.The file register may reside anywhere in the lower 32K words of data memory.

The ‘f’ bits select the address of the file register.

Note 1: This instruction operates in Word mode only.2: The file register address must be word-aligned.

Words: 1

Cycles: 1

Example 1: PUSH 0x2004 ; Push (0x2004) to TOS

Before Instruction

After Instruction

W15 0B00 W15 0B02Data 0B00 791C Data 0B00 D400Data 2004 D400 Data 2004 D400

SR 0000 SR 0000

Example 2: PUSH 0xC0E ; Push (0xC0E) to TOS

Before Instruction

After Instruction

W15 0920 W15 0922Data 0920 0000 Data 0920 67AA

Data 0C0E 67AA Data 2004 67AASR 0000 SR 0000


Instruction D

escriptions

5

PUSH Push Ws to TOS


X X X X

Syntax: {label:} PUSH Ws

[Ws]

[Ws++]

[Ws--]

[--Ws]

[++Ws]

[Ws+Wb]


Operation: (Ws) → (TOS)(W15) + 2 → W15


Encoding: 0111 1www w001 1111 1ggg ssss

Description: The contents of Ws are written to the Top-of-Stack (TOS) location and then the Stack Pointer (W15) is incremented by 2.

The ‘w’ bits define the offset register Wb.The ‘g’ bits select the source Address mode.The ‘s’ bits select the source register.

Note 1: This instruction operates in Word mode only.2: This instruction is a specific version of the “MOV Ws, Wd”

instruction (MOV Ws, [W15++]). It reverse assembles asMOV.

Words: 1

Cycles: 1

Example 1: PUSH W2 ; Push W2 to TOS

Before Instruction

After Instruction

W2 6889 W2 6889W15 1566 W15 1568

Data 1566 0000 Data 1566 6889SR 0000 SR 0000

Example 2: PUSH [W5+W10] ; Push [W5+W10] to TOS

Before Instruction

After Instruction

W5 1200 W5 1200W10 0044 W10 0044W15 0806 W15 0808

Data 0806 216F Data 0806 B20AData 1244 B20A Data 1244 B20A

SR 0000 SR 0000



PUSH.D Double Push Wns:Wns+1 to TOS


X X X X

Syntax: {label:} PUSH.D Wns

Operands: Wns ∈ [W0, W2, W4 ... W14]

Operation: (Wns) → (TOS)(W15) + 2 → W15(Wns + 1) → (TOS)(W15) + 2 → W15


Encoding: 1011 1110 1001 1111 1000 sss0

Description: A double word (Wns:Wns + 1) is PUSHed to the Top-of-Stack (TOS). The least significant word (Wns) is PUSHed to the TOS first, and the most significant word (Wns + 1) is PUSHed to the TOS last. Since a double word is PUSHed, the Stack Pointer (W15) gets incremented by 4.

The ‘s’ bits select the address of the source register pair.

Note 1: This instruction operates on double words. See Figure 4-3 forinformation on how double words are aligned in memory.

2: Wns must be an even working register.3: This instruction is a specific version of the “MOV.D Wns, Wd”

instruction (MOV.D Wns, [W15++]). It reverse assembles asMOV.D.

Words: 1

Cycles: 2

Example 1: PUSH.D W6 ; Push W6:W7 to TOS

Before Instruction

After Instruction

W6 C451 W6 C451W7 3380 W7 3380

W15 1240 W15 1244Data 1240 B004 Data 1240 C451Data 1242 0891 Data 1242 3380

SR 0000 SR 0000

Example 2: PUSH.D W10 ; Push W10:W11 to TOS

Before Instruction

After Instruction

W10 80D3 W10 80D3W11 4550 W11 4550W15 0C08 W15 0C0C

Data 0C08 79B5 Data 0C08 80D3Data 0C0A 008E Data 0C0A 4550

SR 0000 SR 0000


Instruction D

escriptions

5

PUSH.S Push Shadow Registers


X X X X

Syntax: {label:} PUSH.S

Operands: None

Operation: PUSH shadow registers


Encoding: 1111 1110 1010 0000 0000 0000

Description: The contents of the primary registers are copied into their respective shadow registers. The following registers are shadowed: W0-W3, and the C, Z, OV, N and DC STATUS register flags.

Note 1: The shadow registers are not directly accessible. They mayonly be accessed with PUSH.S and POP.S.

2: The shadow registers are only one-level deep.

Words: 1

Cycles: 1

Example 1: PUSH.S ; Push primary registers into shadow registers

Before Instruction

After Instruction

W0 0000 W0 0000W1 1000 W1 1000W2 2000 W2 2000W3 3000 W3 3000SR 0001 (C = 1) SR 0001 (C = 1)

Note: After an instruction execution, contents of the shadow registers are updated.



PWRSAV Enter Power-Saving Mode


X X X X

Syntax: {label:} PWRSAV #lit1

Operands: lit1 ∈ [0,1]

Operation: 0 → WDT count register0 → WDT prescaler A count0 → WDT prescaler B count0 → WDTO (RCON<4>)0 → SLEEP (RCON<3>)0 → IDLE (RCON<2>)If (lit1 = 0): Enter Sleep modeElse: Enter Idle mode


Encoding: 1111 1110 0100 0000 0000 000k

Description: Place the processor into the specified Power Saving mode. If lit1 = ‘0’, Sleep mode is entered. In Sleep mode, the clock to the CPU and peripherals are shutdown. If an on-chip oscillator is being used, it is also shutdown. If lit1 = ‘1’, Idle mode is entered. In Idle mode, the clock to the CPU shuts down, but the clock source remains active and the peripherals continue to operate.

This instruction resets the Watchdog Timer Count register and the Prescaler Count registers. In addition, the WDTO, Sleep and Idle flags of the Reset System and Control (RCON) register are reset.

Note 1: The processor will exit from Idle or Sleep through an interrupt,processor Reset or Watchdog Time-out. See the specificdevice data sheet for details.

2: If awakened from Idle mode, Idle (RCON<2>) is set to ‘1’ andthe clock source is applied to the CPU.

3: If awakened from Sleep mode, Sleep (RCON<3>) is set to ‘1’and the clock source is started.

4: If awakened from a Watchdog Time-out, WDTO (RCON<4>)is set to ‘1’.

Words: 1

Cycles: 1

Example 1: PWRSAV #0 ; Enter SLEEP mode

Before Instruction

After Instruction

SR 0040 (IPL = 2) SR 0040 (IPL = 2)

Example 2: PWRSAV #1 ; Enter IDLE mode

Before Instruction

After Instruction

SR 0020 (IPL = 1) SR 0020 (IPL = 1)


Instruction D

escriptions

5

RCALL Relative Call


X X X X

Syntax: {label:} RCALL Expr

Operands: Expr may be an absolute address, label or expression.Expr is resolved by the linker to a Slit16, where Slit16 ∈ [-32768 ... 32767].

Operation: (PC) + 2 → PC(PC<15:0>) → (TOS)(W15) + 2 → W15(PC<22:16>) → (TOS)(W15) + 2 → W15(PC) + (2 * Slit16) → PCNOP → Instruction Register



Description: Relative subroutine call with a range of 32K program words forward or back from the current PC. Before the call is made, the return address (PC + 2) is PUSHed onto the stack. After the return address is stacked, the sign-extended 17-bit value (2 * Slit16) is added to the contents of the PC and the result is stored in the PC.

The ‘n’ bits are a signed literal that specifies the size of the relative call (in program words) from (PC + 2).

Note: When possible, this instruction should be used instead of CALL,since it only consumes one word of program memory.

Words: 1

Cycles: 2

Example 1: 012004 RCALL _Task1012006 ADD W0, W1, W2 . ... . ...012458 _Task1: SUB W0, W2, W301245A ...

; Call _Task1

; _Task1 subroutine

Before Instruction

After Instruction

PC 01 2004 PC 01 2458W15 0810 W15 0814

Data 0810 FFFF Data 0810 2006Data 0812 FFFF Data 0812 0001

SR 0000 SR 0000



Example 2: 00620E RCALL _Init006210 MOV W0, [W4++] . ... . ...007000 _Init: CLR W2007002 ...

; Call _Init

; _Init subroutine

Before Instruction

After Instruction

PC 00 620E PC 00 7000W15 0C50 W15 0C54

Data 0C50 FFFF Data 0C50 6210Data 0C52 FFFF Data 0C52 0000

SR 0000 SR 0000


Instruction D

escriptions

5

RCALL Computed Relative Call


X X X X

Syntax: {label:} RCALL Wn


Operation: (PC) + 2 → PC(PC<15:0>) → (TOS)(W15) + 2 → W15(PC<22:16>) → (TOS)(W15) + 2 → W15(PC) + (2 * (Wn)) → PCNOP → Instruction Register


Encoding: 0000 0001 0010 0000 0000 ssss

Description: Computed, relative subroutine call specified by the working register Wn. The range of the call is 32K program words forward or back from the current PC. Before the call is made, the return address (PC + 2) is PUSHed onto the stack. After the return address is stacked, the sign-extended 17-bit value (2 * (Wn)) is added to the contents of the PC and the result is stored in the PC. Register direct addressing must be used for Wn.


Words: 1

Cycles: 2

Example 1: 00FF8C EX1: INC W2, W300FF8E ... . ... . ...010008 01000A RCALL W601000C MOVE W4, [W10]

; Destination of RCALL

; RCALL with W6

Before Instruction

After Instruction

PC 01 000A PC 00 FF8CW6 FFC0 W6 FFC0

W15 1004 W15 1008Data 1004 98FF Data 1004 000CData 1006 2310 Data 1006 0001

SR 0000 SR 0000



Example 2: 000302 RCALL W2000304 FF1L W0, W1 . ... . ...000450 EX2: CLR W2000452 ...

; RCALL with W2

; Destination of RCALL

Before Instruction

After Instruction

PC 00 0302 PC 00 0450W2 00A6 W2 00A6

W15 1004 W15 1008Data 1004 32BB Data 1004 0304Data 1006 901A Data 1006 0000

SR 0000 SR 0000


Instruction D

escriptions

5

REPEAT Repeat Next Instruction ‘lit14+1’ Times


X X X X

Syntax: {label:} REPEAT #lit14

Operands: lit14 ∈ [0 ... 16383]

Operation: (lit14) → RCOUNT(PC) + 2 → PCEnable Code Looping

Status Affected: RA


Description: Repeat the instruction immediately following the REPEAT instruction (lit14 + 1) times. The repeated instruction (or target instruction) is held in the instruction register for all iterations and is only fetched once.When this instruction executes, the RCOUNT register is loaded with the repeat count value specified in the instruction. RCOUNT is decremented with each execution of the target instruction. When RCOUNT equals zero, the target instruction is executed one more time, and then normal instruction execution continues with the instruction following the target instruction.The ‘k’ bits are an unsigned literal that specifies the loop count.Special Features, Restrictions:1. When the repeat literal is ‘0’, REPEAT has the effect of a NOP and

the RA bit is not set.2. The target REPEAT instruction can NOT be:

• an instruction that changes program flow• a DO, DISI, LNK, MOV.D, PWRSAV, REPEAT or UNLK instruc-

tion• a 2-word instruction

Unexpected results may occur if these target instructions are used.

Note: The REPEAT and target instruction are interruptible.

Words: 1

Cycles: 1

Example 1: 000452 REPEAT #9 ; Execute ADD 10 times000454 ADD [W0++], W1, [W2++] ; Vector update

Before Instruction

After Instruction

PC 00 0452 PC 00 0454RCOUNT 0000 RCOUNT 0009

SR 0000 SR 0010 (RA = 1)

Example 2: 00089E REPEAT #0x3FF ; Execute CLR 1024 times0008A0 CLR [W6++] ; Clear the scratch space

Before Instruction

After Instruction

PC 00 089E PC 00 08A0RCOUNT 0000 RCOUNT 03FF

SR 0000 SR 0010 (RA = 1)



REPEAT Repeat Next Instruction Wn+1 Times


X X X X

Syntax: {label:} REPEAT Wn


Operation: (Wn<13:0>) → RCOUNT(PC) + 2 → PCEnable Code Looping

Status Affected: RA

Encoding: 0000 1001 1000 0000 0000 ssss

Description: Repeat the instruction immediately following the REPEAT instruction (Wn<13:0>) times. The instruction to be repeated (or target instruction) is held in the instruction register for all iterations and is only fetched once.

When this instruction executes, the RCOUNT register is loaded with the lower 14 bits of Wn. RCOUNT is decremented with each execution of the target instruction. When RCOUNT equals zero, the target instruction is executed one more time, and then normal instruction execution continues with the instruction following the target instruction.

The ‘s’ bits specify the Wn register that contains the repeat count.

Special Features, Restrictions:1. When (Wn) = 0, REPEAT has the effect of a NOP and the RA bit is

not set.2. The target REPEAT instruction can NOT be:

• an instruction that changes program flow• a DO, DISI, LNK, MOV.D, PWRSAV, REPEAT or ULNK instruc-

tion• a 2-word instruction

Unexpected results may occur if these target instructions are used.

Note: The REPEAT and target instruction are interruptible.

Words: 1

Cycles: 1

Example 1: 000A26 REPEAT W4 ; Execute COM (W4+1) times000A28 COM [W0++], [W2++] ; Vector complement

Before Instruction

After Instruction

PC 00 0A26 PC 00 0A28W4 0023 W4 0023

RCOUNT 0000 RCOUNT 0023SR 0000 SR 0010 (RA = 1)


Instruction D

escriptions

5

Example 2: 00089E REPEAT W10 ; Execute TBLRD (W10+1) times0008A0 TBLRDL [W2++], [W3++] ; Decrement (0x840)

Before Instruction

After Instruction

PC 00 089E PC 00 08A0W10 00FF W10 00FF

RCOUNT 0000 RCOUNT 00FFSR 0000 SR 0010 (RA = 1)



RESET Reset


X X X X

Syntax: {label:} RESET

Operands: None

Operation: Force all registers that are affected by a MCLR Reset to their Reset condition.1 → SWR (RCON<6>)0 → PC

Status Affected: OA, OB, OAB, SA, SB, SAB, DA, DC, IPL<2:0>, RA, N, OV, Z, C

Encoding: 1111 1110 0000 0000 0000 0000

Description: This instruction provides a way to execute a software Reset. All core and peripheral registers will take their power-on value. The PC will be set to ‘0’, the location of the RESET GOTO instruction. The SWR bit, RCON<6>, will be set to ‘1’ to indicate that the RESET instruction was executed.

Note: Refer to the specific device family reference manual for thepower-on value of all registers.

Words: 1

Cycles: 1


Instruction D

escriptions

5

Example 1: 00202A RESET ; Execute software RESET

Before Instruction

After Instruction

PC 00 202A PC 00 0000W0 8901 W0 0000W1 08BB W1 0000W2 B87A W2 0000W3 872F W3 0000W4 C98A W4 0000W5 AAD4 W5 0000W6 981E W6 0000W7 1809 W7 0000W8 C341 W8 0000W9 90F4 W9 0000

W10 F409 W10 0000W11 1700 W11 0000W12 1008 W12 0000W13 6556 W13 0000W14 231D W14 0000W15 1704 W15 0800

SPLIM 1800 SPLIM 0000TBLPAG 007F TBLPAG 0000PSVPAG 0001 PSVPAG 0000

CORCON 00F0 CORCON 0020 (SATDW = 1)RCON 0000 RCON 0040 (SWR = 1)

SR 0021 (IPL, C = 1) SR 0000



RETFIE Return from Interrupt


X X X X

Syntax: {label:} RETFIE

Operands: None

Operation: (W15) - 2 → W15(TOS<15:8>) → (SR<7:0>)(TOS<7>) → (IPL3, CORCON<3>)(TOS<6:0>) → (PC<22:16>)(W15) - 2 → W15(TOS<15:0>) → (PC<15:0>)NOP → Instruction Register

Status Affected: IPL<3:0>, RA, N, OV, Z, C

Encoding: 0000 0110 0100 0000 0000 0000

Description: Return from Interrupt Service Routine. The stack is POPped, which loads the low byte of the STATUS register, IPL<3> (CORCON<3>) and the Most Significant Byte of the PC. The stack is POPped again, which loads the lower 16 bits of the PC.

Note 1: Restoring IPL<3> and the low byte of the STATUS registerrestores the Interrupt Priority Level to the level before the exe-cution was processed.

2: Before RETFIE is executed, the appropriate interrupt flagmust be cleared in software to avoid recursive interrupts.

Words: 1

Cycles: 3 (2 if exception pending)

Example 1: 000A26 RETFIE ; Return from ISR

Before Instruction

After Instruction

PC 00 0A26 PC 01 0230W15 0834 W15 0830

Data 0830 0230 Data 0830 0230Data 0832 8101 Data 0832 8101CORCON 0001 CORCON 0001

SR 0000 SR 0081 (IPL = 4, C = 1)

Example 2: 008050 RETFIE ; Return from ISR

Before Instruction

After Instruction

PC 00 8050 PC 00 7008W15 0926 W15 0922

Data 0922 7008 Data 0922 7008Data 0924 0300 Data 0924 0300CORCON 0000 CORCON 0000

SR 0000 SR 0003 (Z, C = 1)


Instruction D

escriptions

5

RETLW Return with Literal in Wn


Syntax: {label:} RETLW{.B} #lit10, Wn


Operation: (W15) – 2 → W15(TOS) → (PC<22:16>)(W15) – 2 → W15(TOS) → (PC<15:0>)lit10 → Wn

Status Affected: NoneEncoding: 0000 0101 0Bkk kkkk kkkk dddd

Description: Return from subroutine with the specified, unsigned 10-bit literal stored in Wn. The software stack is POPped twice to restore the PC and the signed literal is stored in Wn. Since two POPs are made, the Stack Pointer (W15) is decremented by 4.

The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘k’ bits specify the value of the literal.The ‘d’ bits select the destination register.



Words: 1Cycles: 3 (2 if exception pending)

Example 1: 000440 RETLW.B #0xA, W0 ; Return with 0xA in W0

Before Instruction

After Instruction

PC 00 0440 PC 00 7006W0 9846 W0 980A

W15 1988 W15 1984Data 1984 7006 Data 1984 7006Data 1986 0000 Data 1986 0000

SR 0000 SR 0000

Example 2: 00050A RETLW #0x230, W2 ; Return with 0x230 in W2

Before Instruction

After Instruction

PC 00 050A PC 01 7008W2 0993 W2 0230

W15 1200 W15 11FCData 11FC 7008 Data 11FC 7008Data 11FE 0001 Data 11FE 0001

SR 0000 SR 0000



RETURN Return


X X X X

Syntax: {label:} RETURN

Operands: None

Operation: (W15) – 2 → W15(TOS) → (PC<22:16>)(W15) – 2 → W15(TOS) → (PC<15:0>)NOP → Instruction Register


Encoding: 0000 0110 0000 0000 0000 0000

Description: Return from subroutine. The software stack is POPped twice to restore the PC. Since two POPs are made, the Stack Pointer (W15) is decremented by 4.

Words: 1

Cycles: 3 (2 if exception pending)

Example 1: 001A06 RETURN ; Return from subroutine

Before Instruction

After Instruction

PC 00 1A06 PC 01 0004W15 1248 W15 1244


SR 0000 SR 0000

Example 2: 005404 RETURN ; Return from subroutine

Before Instruction

After Instruction

PC 00 5404 PC 00 0966W15 090A W15 0906


SR 0000 SR 0000


Instruction D

escriptions

5

RLC Rotate Left f through Carry


X X X X

Syntax: {label:} RLC{.B} f {,WREG}

Operands: f ∈ [0 ... 8191]

Operation: For byte operation: (C) → Dest<0> (f<6:0>) → Dest<7:1> (f<7>) → CFor word operation: (C) → Dest<0> (f<14:0>) → Dest<15:1> (f<15>) → C



Description: Rotate the contents of the file register f one bit to the left through the Carry flag and place the result in the destination register. The Carry flag of the STATUS Register is shifted into the Least Significant bit of the destination, and it is then overwritten with the Most Significant bit of Ws.


The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘D’ bit selects the destination (‘0’ for f, ‘1’ for WREG).The ‘f’ bits select the address of the file register.



Words: 1

Cycles: 1

C

Example 1: RLC.B 0x1233 ; Rotate Left w/ C (0x1233) (Byte mode)

Before Instruction

After Instruction

Data 1232 E807 Data 1232 D007SR 0000 SR 0009 (N, C = 1)

Example 2: RLC 0x820, WREG ; Rotate Left w/ C (0x820) (Word mode) ; Store result in WREG

Before Instruction

After Instruction

WREG (W0) 5601 WREG (W0) 42DDData 0820 216E Data 0820 216E

SR 0001 (C = 1) SR 0000 (C = 0)



RLC Rotate Left Ws through Carry


X X X X

Syntax: {label:} RLC{.B} Ws, Wd

[Ws], [Wd]

[Ws++], [Wd++]

[Ws--], [Wd--]

[++Ws], [++Wd]

[--Ws], [--Wd]


Operation: For byte operation: (C) → Wd<0> (Ws<6:0>) → Wd<7:1> (Ws<7>) → CFor word operation: (C) → Wd<0> (Ws<14:0>) → Wd<15:1> (Ws<15>) → C



Description: Rotate the contents of the source register Ws one bit to the left through the Carry flag and place the result in the destination register Wd. The Carry flag of the STATUS register is shifted into the Least Significant bit of Wd, and it is then overwritten with the Most Significant bit of Ws. Either register direct or indirect addressing may be used for Ws and Wd.



Words: 1

Cycles: 1

C

Example 1: RLC.B W0, W3 ; Rotate Left w/ C (W0) (Byte mode) ; Store the result in W3

Before Instruction

After Instruction

W0 9976 W0 9976W3 5879 W3 58EDSR 0001 (C = 1) SR 0009 (N = 1)


Instruction D

escriptions

5

Example 2: RLC [W2++], [W8] ; Rotate Left w/ C [W2] (Word mode) ; Post-increment W2 ; Store result in [W8]

Before Instruction

After Instruction

W2 2008 W2 200AW8 094E W8 094E

Data 094E 3689 Data 094E 8082Data 2008 C041 Data 2008 C041

SR 0001 (C = 1) SR 0009 (N, C = 1)



RLNC Rotate Left f without Carry


X X X X

Syntax: {label:} RLNC{.B} f {,WREG}

Operands: f ∈ [0 ... 8191]

Operation: For byte operation: (f<6:0>) → Dest<7:1> (f<7>) → Dest<0>For word operation: (f<14:0>) → Dest<15:1> (f<15>) → Dest<0>



Description: Rotate the contents of the file register f one bit to the left and place the result in the destination register. The Most Significant bit of f is stored in the Least Significant bit of the destination, and the Carry flag is not affected.





Words: 1

Cycles: 1

Example 1: RLNC.B 0x1233 ; Rotate Left (0x1233) (Byte mode)

Before Instruction

After Instruction

Data 1232 E807 Data 1233 D107SR 0000 SR 0008 (N = 1)

Example 2: RLNC 0x820, WREG ; Rotate Left (0x820) (Word mode) ; Store result in WREG

Before Instruction

After Instruction

WREG (W0) 5601 WREG (W0) 42DCData 0820 216E Data 0820 216E

SR 0001 (C = 1) SR 0000 (C = 0)


Instruction D

escriptions

5

RLNC Rotate Left Ws without Carry


X X X X

Syntax: {label:} RLNC{.B} Ws, Wd

[Ws], [Wd]

[Ws++], [Wd++]

[Ws--], [Wd--]

[++Ws], [++Wd]

[--Ws], [--Wd]


Operation: For byte operation: (Ws<6:0>) → Wd<7:1> (Ws<7>) → Wd<0>For word operation: (Ws<14:0>) → Wd<15:1> (Ws<15>) → Wd<0>



Description: Rotate the contents of the source register Ws one bit to the left and place the result in the destination register Wd. The Most Significant bit of Ws is stored in the Least Significant bit of Wd, and the Carry flag is not affected. Either register direct or indirect addressing may be used for Ws and Wd.

The ‘B’ bit selects byte or word operation (‘0’ for byte, ‘1’ for word).The ‘q’ bits select the destination Address mode.The ‘d’ bits select the destination register.The ‘p’ bits select the source Address mode.The ‘s’ bits select the source register.


Words: 1

Cycles: 1

Example 1: RLNC.B W0, W3 ; Rotate Left (W0) (Byte mode) ; Store the result in W3

Before Instruction

After Instruction

W0 9976 W0 9976W3 5879 W3 58ECSR 0001 (C = 1) SR 0009 (N, C = 1)



Example 2: RLNC [W2++], [W8] ; Rotate Left [W2] (Word mode) ; Post-increment W2 ; Store result in [W8]

Before Instruction

After Instruction

W2 2008 W2 200AW8 094E W8 094E

Data 094E 3689 Data 094E 8083Data 2008 C041 Data 2008 C041

SR 0001 (C = 1) SR 0009 (N, C = 1)


Instruction D

escriptions

5

RRC Rotate Right f through Carry


Syntax: {label:} RRC{.B} f {,WREG}

Operands: f ∈ [0 ... 8191]Operation: For byte operation:

(C) → Dest<7> (f<7:1>) → Dest<6:0> (f<0>) → CFor word operation: (C) → Dest<15> (f<15:1>) → Dest<14:0> (f<0>) → C

Status Affected: N, Z, CEncoding: 1101 0111 1BDf ffff ffff ffff

Description: Rotate the contents of the file register f one bit to the right through the Carry flag and place the result in the destination register. The Carry flag of the STATUS Register is shifted into the Most Significant bit of the destination, and it is then overwritten with the Least Significant bit of Ws.


The ‘B’ bit selects byte or word operation (‘0’ for byte, ‘1’ for word).The ‘D’ bit selects the destination (‘0’ for WREG, ‘1’ for file register).The ‘f’ bits select the address of the file register.


2: The WREG is set to working register W0.Words: 1Cycles: 1

C

Example 1: RRC.B 0x1233 ; Rotate Right w/ C (0x1233) (Byte mode)

Before Instruction

After Instruction

Data 1232 E807 Data 1232 7407SR 0000 SR 0000

Example 2: RRC 0x820, WREG ; Rotate Right w/ C (0x820) (Word mode) ; Store result in WREG

Before Instruction

After Instruction

WREG (W0) 5601 WREG (W0) 90B7Data 0820 216E Data 0820 216E

SR 0001 (C = 1) SR 0008 (N = 1)



RRC Rotate Right Ws through Carry


X X X X

Syntax: {label:} RRC{.B} Ws, Wd

[Ws], [Wd]

[Ws++], [Wd++]

[Ws--], [Wd--]

[++Ws], [++Wd]

[--Ws], [--Wd]


Operation: For byte operation: (C) → Wd<7> (Ws<7:1>) → Wd<6:0> (Ws<0>) → CFor word operation: (C) → Wd<15> (Ws<15:1>) → Wd<14:0> (Ws<0>) → C



Description: Rotate the contents of the source register Ws one bit to the right through the Carry flag and place the result in the destination register Wd. The Carry flag of the STATUS Register is shifted into the Most Significant bit of Wd, and it is then overwritten with the Least Significant bit of Ws. Either register direct or indirect addressing may be used for Ws and Wd.



Words: 1

Cycles: 1

C

Example 1: RRC.B W0, W3 ; Rotate Right w/ C (W0) (Byte mode) ; Store the result in W3

Before Instruction

After Instruction

W0 9976 W0 9976W3 5879 W3 58BBSR 0001 (C = 1) SR 0008 (N = 1)


Instruction D

escriptions

5

Example 2: RRC [W2++], [W8] ; Rotate Right w/ C [W2] (Word mode) ; Post-increment W2 ; Store result in [W8]

Before Instruction

After Instruction

W2 2008 W2 200AW8 094E W8 094E

Data 094E 3689 Data 094E E020Data 2008 C041 Data 2008 C041

SR 0001 (C = 1) SR 0009 (N, C = 1)



RRNC Rotate Right f without Carry


X X X X

Syntax: {label:} RRNC{.B} f {,WREG}

Operands: f ∈ [0 ... 8191]

Operation: For byte operation: (f<7:1>) → Dest<6:0> (f<0>) → Dest<7>For word operation: (f<15:1>) → Dest<14:0> (f<0>) → Dest<15>



Description: Rotate the contents of the file register f one bit to the right and place the result in the destination register. The Least Significant bit of f is stored in the Most Significant bit of the destination, and the Carry flag is not affected.





Words: 1

Cycles: 1

Example 1: RRNC.B 0x1233 ; Rotate Right (0x1233) (Byte mode)

Before Instruction

After Instruction

Data 1232 E807 Data 1232 7407SR 0000 SR 0000

Example 2: RRNC 0x820, WREG ; Rotate Right (0x820) (Word mode) ; Store result in WREG

Before Instruction

After Instruction

WREG (W0) 5601 WREG (W0) 10B7Data 0820 216E Data 0820 216E

SR 0001 (C = 1) SR 0001 (C = 1)


Instruction D

escriptions

5

RRNC Rotate Right Ws without Carry


X X X X

Syntax: {label:} RRNC{.B} Ws, Wd

[Ws], [Wd]

[Ws++], [Wd++]

[Ws--], [Wd--]

[++Ws], [++Wd]

[--Ws], [--Wd]


Operation: For byte operation: (Ws<7:1>) → Wd<6:0> (Ws<0>) → Wd<7>For word operation: (Ws<15:1>) → Wd<14:0> (Ws<0>) → Wd<15>



Description: Rotate the contents of the source register Ws one bit to the right and place the result in the destination register Wd. The Least Significant bit of Ws is stored in the Most Significant bit of Wd, and the Carry flag is not affected. Either register direct or indirect addressing may be used for Ws and Wd.



Words: 1

Cycles: 1

Example 1: RRNC.B W0, W3 ; Rotate Right (W0) (Byte mode) ; Store the result in W3

Before Instruction

After Instruction

W0 9976 W0 9976W3 5879 W3 583BSR 0001 (C = 1) SR 0001 (C = 1)



Example 2: RRNC [W2++], [W8] ; Rotate Right [W2] (Word mode) ; Post-increment W2 ; Store result in [W8]

Before Instruction

After Instruction

W2 2008 W2 200AW8 094E W8 094E

Data 094E 3689 Data 094E E020Data 2008 C041 Data 2008 C041

SR 0000 SR 0008 (N = 1)


Instruction D

escriptions

5

SAC Store Accumulator


X X

Syntax: {label:} SAC Acc, {#Slit4,} Wd

[Wd]

[Wd++]

[Wd--]

[--Wd]

[++Wd]

[Wd + Wb]

Operands: Acc ∈ [A,B] Slit4 ∈ [-8 ... +7]Wb, Wd ∈ [W0 ... W15]

Operation: ShiftSlit4(Acc) (optional)(Acc[31:16]) → Wd


Encoding: 1100 1100 Awww wrrr rhhh dddd

Description: Perform an optional, signed 4-bit shift of the specified accumulator, then store the shifted contents of ACCxH (Acc[31:16]) to Wd. The shift range is -8:7, where a negative operand indicates an arithmetic left shift and a positive operand indicates an arithmetic right shift. Either register direct or indirect addressing may be used for Wd.

The ‘A’ bit specifies the source accumulator. The ‘w’ bits specify the offset register Wb.The ‘r’ bits encode the optional accumulator pre-shift.The ‘h’ bits select the destination Address mode.The ‘d’ bits specify the destination register Wd.

Note 1: This instruction does not modify the contents of Acc.2: This instruction stores the truncated contents of Acc. The

instruction SAC.R may be used to store the rounded accumulator contents.

3: If Data Write saturation is enabled (SATDW, CORCON<5>, = 1), the value stored to Wd is subject to saturation after the optional shift is performed.

Words: 1

Cycles: 1

Example 1: SAC A, #4, W5 ; Right shift ACCA by 4 ; Store result to W5; CORCON = 0x0010 (SATDW = 1)

Before Instruction

After Instruction

W5 B900 W5 0120ACCA 00 120F FF00 ACCA 00 120F FF00

CORCON 0010 CORCON 0010SR 0000 SR 0000



Example 2: SAC B, #-4, [W5++] ; Left shift ACCB by 4 ; Store result to [W5], Post-increment W5; CORCON = 0x0010 (SATDW = 1)

Before Instruction

After Instruction

W5 2000 W5 2002ACCB FF C891 8F4C ACCB FF C891 1F4C

Data 2000 5BBE Data 2000 8000CORCON 0010 CORCON 0010

SR 0000 SR 0000


Instruction D

escriptions

5

SAC.R Store Rounded Accumulator


X X

Syntax: {label:} SAC.R Acc, {#Slit4,} Wd

[Wd]

[Wd++]

[Wd--]

[--Wd]

[++Wd]

[Wd + Wb]

Operands: Acc ∈ [A,B] Slit4 ∈ [-8 ... +7]Wb ∈ [W0 ... W15]Wd ∈ [W0 ... W15]

Operation: ShiftSlit4(Acc) (optional)Round(Acc)(Acc[31:16]) → Wd


Encoding: 1100 1101 Awww wrrr rhhh dddd

Description: Perform an optional, signed 4-bit shift of the specified accumulator, then store the rounded contents of ACCxH (Acc[31:16]) to Wd. The shift range is -8:7, where a negative operand indicates an arithmetic left shift and a positive operand indicates an arithmetic right shift. The Rounding mode (Conventional or Convergent) is set by the RND bit, CORCON<1>. Either register direct or indirect addressing may be used for Wd.

The ‘A’ bit specifies the source accumulator. The ‘w’ bits specify the offset register Wb.The ‘r’ bits encode the optional accumulator pre-shift.The ‘h’ bits select the destination Address mode.The ‘d’ bits specify the destination register Wd.

Note 1: This instruction does not modify the contents of the Acc.2: This instruction stores the rounded contents of Acc. The

instruction SAC may be used to store the truncated accumulator contents.

3: If Data Write saturation is enabled (SATDW, CORCON<5>, = 1), the value stored to Wd is subject to saturation after the optional shift is performed.

Words: 1

Cycles: 1



Example 1: SAC.R A, #4, W5 ; Right shift ACCA by 4 ; Store rounded result to W5; CORCON = 0x0010 (SATDW = 1)

Before Instruction

After Instruction

W5 B900 W5 0121ACCA 00 120F FF00 ACCA 00 120F FF00


Example 2: SAC.R B, #-4, [W5++]; Left shift ACCB by 4 ; Store rounded result to [W5], Post-increment W5; CORCON = 0x0010 (SATDW = 1)

Before Instruction

After Instruction

W5 2000 W5 2002ACCB FF F891 8F4C ACCB FF F891 8F4C

Data 2000 5BBE Data 2000 8919CORCON 0010 CORCON 0010

SR 0000 SR 0000


Instruction D

escriptions

5

SE Sign-Extend Ws


Syntax: {label:} SE Ws, Wnd[Ws],[Ws++],[Ws--],[++Ws],[--Ws],


Operation: Ws<7:0> → Wnd<7:0>If (Ws<7> = 1): 0xFF → Wnd<15:8>Else: 0 → Wnd<15:8>

Status Affected: N, Z, CEncoding: 1111 1011 0000 0ddd dppp ssss

Description: Sign-extend the byte in Ws and store the 16-bit result in Wnd. Either register direct or indirect addressing may be used for Ws, and register direct addressing must be used for Wnd. The C flag is set to the complement of the N flag.


Note 1: This operation converts a byte to a word, and it uses no .B or .W extension.

2: The source Ws is addressed as a byte operand, so any address modification is by ‘1’.

Words: 1Cycles: 1

Example 1: SE W3, W4 ; Sign-extend W3 and store to W4

Before Instruction

After Instruction

W3 7839 W3 7839W4 1005 W4 0039SR 0000 SR 0001 (C = 1)

Example 2: SE [W2++], W12 ; Sign-extend [W2] and store to W12 ; Post-increment W2

Before Instruction

After Instruction

W2 0900 W2 0901W12 1002 W12 FF8F

Data 0900 008F Data 0900 008FSR 0000 SR 0008 (N = 1)



SETM Set f or WREG


X X

Syntax: {label:} SETM{.B} f

WREG

Operands: f ∈ [0 ... 8191]

Operation: For byte operation: 0xFF → destination designated by DFor word operation: 0xFFFF → destination designated by D



Description: All the bits of the specified register are set to ‘1’. If WREG is specified, the bits of WREG are set. Otherwise, the bits of the specified file register are set.


Note 1: The extension .B in the instruction denotes a byte operation rather than a word operation. You may use a .W extension to denote a word operation, but it is not required.


Words: 1

Cycles: 1

Example 1: SETM.B 0x891 ; Set 0x891 (Byte mode)

Before Instruction

After Instruction

Data 0890 2739 Data 0890 FF39SR 0000 SR 0000

Example 2: SETM WREG ; Set WREG (Word mode)

Before Instruction

After Instruction

WREG (W0) 0900 WREG (W0) FFFFSR 0000 SR 0000


Instruction D

escriptions

5

SETM Set Ws


X X X X

Syntax: {label:} SETM{.B} Wd

[Wd]

[Wd++]

[Wd--]

[++Wd]

[--Wd]

Operands: Wd ∈ [W0 ... W15]

Operation: For byte operation: 0xFF → Wd for byte operationFor word operation: 0xFFFF → Wd for word operation


Encoding: 1110 1011 1Bqq qddd d000 0000

Description: All the bits of the specified register are set to ‘1’. Either register direct or indirect addressing may be used for Wd.

The ‘B’ bits selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘q’ bits select the destination Address mode.The ‘d’ bits select the destination register.


Words: 1

Cycles: 1

Example 1: SETM.B W13 ; Set W13 (Byte mode)

Before Instruction

After Instruction

W13 2739 W13 27FFSR 0000 SR 0000

Example 2: SETM [--W6] ; Pre-decrement W6 (Word mode) ; Set [W6]

Before Instruction

After Instruction

W6 1250 W6 124EData 124E 3CD9 Data 124E FFFF

SR 0000 SR 0000



SFTAC Arithmetic Shift Accumulator by Slit6


X X

Syntax: {label:} SFTAC Acc, #Slit6

Operands: Acc ∈ [A,B] Slit6 ∈ [-16 ... 16]

Operation: Shiftk(Acc) → Acc


Encoding: 1100 1000 A000 0000 01kk kkkk

Description: Arithmetic shift the 40-bit contents of the specified accumulator by the signed, 6-bit literal and store the result back into the accumulator. The shift range is -16:16, where a negative operand indicates a left shift and a positive operand indicates a right shift. Any bits which are shifted out of the accumulator are lost.

The ‘A’ bit selects the accumulator for the result.The ‘k’ bits determine the number of bits to be shifted.

Note 1: If saturation is enabled for the target accumulator (SATA, CORCON<7> or SATB, CORCON<6>), the value stored to the accumulator is subject to saturation.

2: If the shift amount is greater than 16 or less than -16, nomodification will be made to the accumulator, and anarithmetic trap will occur.

Words: 1

Cycles: 1

Example 1: SFTAC A, #12; Arithmetic right shift ACCA by 12; Store result to ACCA; CORCON = 0x0080 (SATA = 1)

Before Instruction

After Instruction

ACCA 00 120F FF00 ACCA 00 0001 20FFCORCON 0080 CORCON 0080

SR 0000 SR 0000

Example 2: SFTAC B, #-10; Arithmetic left shift ACCB by 10 ; Store result to ACCB; CORCON = 0x0040 (SATB = 1)

Before Instruction

After Instruction

ACCB FF FFF1 8F4C ACCB FF C63D 3000CORCON 0040 CORCON 0040

SR 0000 SR 0000


Instruction D

escriptions

5

SFTAC Arithmetic Shift Accumulator by Wb


X X

Syntax: {label:} SFTAC Acc, Wb

Operands: Acc ∈ [A,B] Wb ∈ [W0 ... W15]

Operation: Shift(Wb)(Acc) → Acc


Encoding: 1100 1000 A000 0000 0000 ssss

Description: Arithmetic shift the 40-bit contents of the specified accumulator and store the result back into the accumulator. The Least Significant 6 bits of Wb are used to specify the shift amount. The shift range is -16:16, where a negative value indicates a left shift and a positive value indicates a right shift. Any bits which are shifted out of the accumulator are lost.

The ‘A’ bit selects the accumulator for the source/destination.The ‘s’ bits select the address of the shift count register.

Note 1: If saturation is enabled for the target accumulator (SATA, CORCON<7> or SATB, CORCON<6>), the value stored to the accumulator is subject to saturation.

2: If the shift amount is greater than 16 or less than -16, nomodification will be made to the accumulator, and anarithmetic trap will occur.

Words: 1

Cycles: 1

Example 1: SFTAC A, W0; Arithmetic shift ACCA by (W0); Store result to ACCA; CORCON = 0x0000 (saturation disabled)

Before Instruction

After Instruction

W0 FFFC W0 FFFCACCA 00 320F AB09 ACCA 03 20FA B090

CORCON 0000 CORCON 0000SR 0000 SR 8800 (OA, OAB = 1)

Example 2: SFTAC B, W12; Arithmetic shift ACCB by (W12); Store result to ACCB; CORCON = 0x0040 (SATB = 1)

Before Instruction

After Instruction

W12 000F W12 000FACCB FF FFF1 8F4C ACCB FF FFFF FFE3




SL Shift Left f


X X X X

Syntax: {label:} SL{.B} f {,WREG}

Operands: f ∈ [0... 8191]

Operation: For byte operation: (f<7>) → (C) (f<6:0>) → Dest<7:1> 0 → Dest<0>For word operation: (f<15>) → (C) (f<14:0>) → Dest<15:1> 0 → Dest<0>



Description: Shift the contents of the file register one bit to the left and place the result in the destination register. The Most Significant bit of the file register is shifted into the Carry bit of the STATUS register, and zero is shifted into the Least Significant bit of the destination register.





Words: 1

Cycles: 1

C 0

Example 1: SL.B 0x909 ; Shift left (0x909) (Byte mode)

Before Instruction

After Instruction

Data 0908 9439 Data 0908 0839SR 0000 SR 0001 (C = 1)

Example 2: SL 0x1650, WREG ; Shift left (0x1650) (Word mode) ; Store result in WREG

Before Instruction

After Instruction

WREG (W0) 0900 WREG (W0) 80CAData 1650 4065 Data 1650 4065

SR 0000 SR 0008 (N = 1)


Instruction D

escriptions

5

SL Shift Left Ws


X X X X

Syntax: {label:} SL{.B} Ws, Wd

[Ws], [Wd]

[Ws++], [Wd++]

[Ws--], [Wd--]

[++Ws], [++Wd]

[--Ws], [--Wd]


Operation: For byte operation: (Ws<7>) → C (Ws<6:0>) → Wd<7:1> 0 → Wd<0>For word operation: (Ws<15>) → C (Ws<14:0>) → Wd<15:1> 0 → Wd<0>



Description: Shift the contents of the source register Ws one bit to the left and place the result in the destination register Wd. The Most Significant bit of Ws is shifted into the Carry bit of the STATUS register, and ‘0’ is shifted into the Least Significant bit of Wd. Either register direct or indirect addressing may be used for Ws and Wd.



Words: 1

Cycles: 1

C 0

Example 1: SL.B W3, W4 ; Shift left W3 (Byte mode) ; Store result to W4

Before Instruction

After Instruction

W3 78A9 W3 78A9W4 1005 W4 1052SR 0000 SR 0001 (C = 1)



Example 2: SL [W2++], [W12] ; Shift left [W2] (Word mode) ; Store result to [W12] ; Post-increment W2

Before Instruction

After Instruction

W2 0900 W2 0902W12 1002 W12 1002

Data 0900 800F Data 0900 800FData 1002 6722 Data 1002 001E

SR 0000 SR 0001 (C = 1)


Instruction D

escriptions

5

SL Shift Left by Short Literal


X X X X

Syntax: {label:} SL Wb, #lit4, Wnd

Operands: Wb ∈ [W0 ... W15]lit4 ∈ [0...15]Wnd ∈ [W0 ... W15]

Operation: lit4<3:0> → Shift_ValWnd<15:Shift_Val> = Wb<15-Shift_Val:0>Wd<Shift_Val – 1:0> = 0



Description: Shift left the contents of the source register Wb by the 4-bit unsigned literal and store the result in the destination register Wnd. Any bits shifted out of the source register are lost. Direct addressing must be used for Wb and Wnd.

The ‘w’ bits select the address of the base register.The ‘d’ bits select the destination register.The ‘k’ bits provide the literal operand, a five-bit integer number.


Words: 1

Cycles: 1

Example 1: SL W2, #4, W2 ; Shift left W2 by 4 ; Store result to W2

Before Instruction

After Instruction

W2 78A9 W2 8A90SR 0000 SR 0008 (N = 1)

Example 2: SL W3, #12, W8 ; Shift left W3 by 12 ; Store result to W8

Before Instruction

After Instruction

W3 0912 W3 0912W8 1002 W8 2000SR 0000 SR 0000



SL Shift Left by Wns


X X X X

Syntax: {label:} SL Wb, Wns, Wnd


Operation: Wns<4:0> → Shift_ValWnd<15:Shift_Val> = Wb<15 – Shift_Val:0>Wd<Shift_Val – 1:0> = 0


Encoding: 1101 1101 0www wddd d000 ssss

Description: Shift left the contents of the source register Wb by the 5 Least Significant bits of Wns (only up to 15 positions) and store the result in the destina-tion register Wnd. Any bits shifted out of the source register are lost. Register direct addressing must be used for Wb, Wns and Wnd.

The ‘w’ bits select the address of the base register.The ‘d’ bits select the destination register.The ‘s’ bits select the source register.

Note 1: This instruction operates in Word mode only.2: If Wns is greater than 15, Wnd will be loaded with 0x0.

Words: 1

Cycles: 1

Example 1: SL W0, W1, W2 ; Shift left W0 by W1<0:4> ; Store result to W2

Before Instruction

After Instruction

W0 09A4 W0 09A4W1 8903 W1 8903W2 78A9 W2 4D20SR 0000 SR 0000

Example 2: SL W4, W5, W6 ; Shift left W4 by W5<0:4> ; Store result to W6

Before Instruction

After Instruction

W4 A409 W4 A409W5 FF01 W5 FF01W6 0883 W6 4812SR 0000 SR 0000


Instruction D

escriptions

5

SUB Subtract WREG from f


X X X X

Syntax: {label:} SUB{.B} f {,WREG}

Operands: f ∈ [0 ... 8191]

Operation: (f) – (WREG) → destination designated by D



Description: Subtract the contents of the default working register WREG from the contents of the specified file register, and place the result in the destination register. The optional WREG operand determines the destination register. If WREG is specified, the result is stored in WREG. If WREG is not specified, the result is stored in the file register.




Words: 1

Cycles: 1

Example 1: SUB.B 0x1FFF ; Sub. WREG from (0x1FFF) (Byte mode) ; Store result to 0x1FFF

Before Instruction

After Instruction

WREG (W0) 7804 WREG (W0) 7804Data 1FFE 9439 Data 1FFE 9039

SR 0000 SR 0009 (N, C = 1)

Example 2: SUB 0xA04, WREG ; Sub. WREG from (0xA04) (Word mode) ; Store result to WREG

Before Instruction

After Instruction

WREG (W0) 6234 WREG (W0) E2EFData 0A04 4523 Data 0A04 4523

SR 0000 SR 0008 (N = 1)



SUB Subtract Literal from Wn


X X X X

Syntax: {label:} SUB{.B} #lit10, Wn


Operation: (Wn) – lit10 → Wn



Description: Subtract the 10-bit unsigned literal operand from the contents of the working register Wn, and store the result back in the working register Wn. Register direct addressing must be used for Wn.

The ‘B’ bit selects byte or word operation.The ‘k’ bits specify the literal operand.The ‘d’ bits select the address of the working register.


2: For byte operations, the literal must be specified as an unsigned value [0:255]. See Section 4.6 “Using 10-bit Literal Oper-ands” for information on using 10-bit literal operands in Byte mode.

Words: 1

Cycles: 1

Example 1: SUB.B #0x23, W0 ; Sub. 0x23 from W0 (Byte mode) ; Store result to W0

Before Instruction

After Instruction

W0 7804 W0 78E1SR 0000 SR 0008 (N = 1)

Example 2: SUB #0x108, W4 ; Sub. 0x108 from W4 (Word mode) ; Store result to W4

Before Instruction

After Instruction

W4 6234 W4 612CSR 0000 SR 0001 (C = 1)


Instruction D

escriptions

5

SUB Subtract Short Literal from Wb


Syntax: {label:} SUB{.B} Wb, #lit5, Wd[Wd][Wd++][Wd--][++Wd][--Wd]


Operation: (Wb) – lit5 → Wd Status Affected: DC, N, OV, Z, CEncoding: 0101 0www wBqq qddd d11k kkkk

Description: Subtract the 5-bit unsigned literal operand from the contents of the base register Wb, and place the result in the destination register Wd. Register direct addressing must be used for Wb. Register direct or indirect addressing must be used for Wd.



Words: 1Cycles: 1

Example 1: SUB.B W4, #0x10, W5 ; Sub. 0x10 from W4 (Byte mode) ; Store result to W5

Before Instruction

After Instruction

W4 1782 W4 1782W5 7804 W5 7872SR 0000 SR 0005 (OV, C = 1)

Example 2: SUB W0, #0x8, [W2++] ; Sub. 0x8 from W0 (Word mode) ; Store result to [W2] ; Post-increment W2

Before Instruction

After Instruction

W0 F230 W0 F230W2 2004 W2 2006

Data 2004 A557 Data 2004 F228SR 0000 SR 0009 (N, C = 1)



SUB Subtract Ws from Wb


X X X X

Syntax: {label:} SUB{.B} Wb, Ws, Wd

[Ws], [Wd]

[Ws++], [Wd++]

[Ws--], [Wd--]

[++Ws], [++Wd]

[--Ws], [--Wd]


Operation: (Wb) – (Ws) → Wd



Description: Subtract the contents of the source register Ws from the contents of the base register Wb and place the result in the destination register Wd. Register direct addressing must be used for Wb. Either register direct or indirect addressing may be used for Ws and Wd.



Words: 1

Cycles: 1

Example 1: SUB.B W0, W1, W0 ; Sub. W1 from W0 (Byte mode) ; Store result to W0

Before Instruction

After Instruction

W0 1732 W0 17EEW1 7844 W1 7844SR 0000 SR 0108 (DC, N = 1)


Instruction D

escriptions

5

Example 2: SUB W7, [W8++], [W9++] ; Sub. [W8] from W7 (Word mode) ; Store result to [W9] ; Post-increment W8 ; Post-increment W9

Before Instruction

After Instruction

W7 2450 W7 2450W8 1808 W8 180AW9 2020 W9 2022

Data 1808 92E4 Data 1808 92E4Data 2020 A557 Data 2020 916C

SR 0000 SR 010C (DC, N, OV = 1)



SUB Subtract Accumulators


X X

Syntax: {label:} SUB Acc


Operation: If (Acc = A): ACCA – ACCB → ACCAElse: ACCB – ACCA → ACCB


Encoding: 1100 1011 A011 0000 0000 0000

Description: Subtract the contents of the unspecified accumulator from the contents of Acc, and store the result back into Acc. This instruction performs a 40-bit subtraction.

The ‘A’ bit specifies the destination accumulator.

Words: 1

Cycles: 1

Example 1: SUB A ; Subtract ACCB from ACCA ; Store the result to ACCA ; CORCON = 0x0000 (no saturation)

Before Instruction

After Instruction

ACCA 76 120F 098A ACCA 52 1EFC 4D73ACCB 23 F312 BC17 ACCB 23 F312 BC17

CORCON 0000 CORCON 0000SR 0000 SR 1100 (OA, OB = 1)

Example 2: SUB B ; Subtract ACCA from ACCB ; Store the result to ACCB ; CORCON = 0x0040 (SATB = 1)

Before Instruction

After Instruction

ACCA FF 9022 2EE1 ACCA FF 9022 2EE1ACCB 00 2456 8F4C ACCB 00 7FFF FFFF

CORCON 0040 CORCON 0040SR 0000 SR 1400 (SB, SAB = 1)


Instruction D

escriptions

5

SUBB Subtract WREG and Carry bit from f


X X X X

Syntax: {label:} SUBB{.B} f {,WREG}

Operands: f ∈ [0 ... 8191]

Operation: (f) – (WREG) – (C) → destination designated by D



Description: Subtract the contents of the default working register WREG and the Borrow flag (Carry flag inverse, C) from the contents of the specified file register and place the result in the destination register. The optional WREG operand determines the destination register. If WREG is specified, the result is stored in WREG. If WREG is not specified, the result is stored in the file register



2: The WREG is set to working register W0.3: The Z flag is “sticky” for ADDC, CPB, SUBB and SUBBR. These


Words: 1

Cycles: 1

Example 1: SUBB.B 0x1FFF ; Sub. WREG and C from (0x1FFF) (Byte mode) ; Store result to 0x1FFF

Before Instruction

After Instruction

WREG (W0) 7804 WREG (W0) 7804Data 1FFE 9439 Data 1FFE 8F39

SR 0000 SR 0008 (N = 1)

Example 2: SUBB 0xA04, WREG ; Sub. WREG and C from (0xA04) (Word mode) ; Store result to WREG

Before Instruction

After Instruction

WREG (W0) 6234 WREG (W0) 0000Data 0A04 6235 Data 0A04 6235

SR 0000 SR 0001 (C = 1)



SUBB Subtract Wn from Literal with Borrow


X X X X

Syntax: {label:} SUBB{.B} #lit10, Wn


Operation: (Wn) – lit10 – (C) → Wn



Description: Subtract the unsigned 10-bit literal operand and the Borrow flag (Carry flag inverse, C) from the contents of the working register Wn, and store the result back in the working register Wn. Register direct addressing must be used for Wn.


Note 1: The extension .B in the instruction denotes a byte operation rather than a word operation. You may use a .w extension to denote a word operation, but it is not required.

2: For byte operations, the literal must be specified as an unsigned value [0:255]. See Section 4.6 “Using 10-bit Literal Operands” for information on using 10-bit literal operands in Byte mode.

3: The Z flag is “sticky” for ADDC, CPB, SUBB and SUBBR. These instructions can only clear Z.

Words: 1

Cycles: 1

Example 1: SUBB.B #0x23, W0 ; Sub. 0x23 and C from W0 (Byte mode) ; Store result to W0

Before Instruction

After Instruction

W0 7804 W0 78E0SR 0000 SR 0108 (DC, N = 1)

Example 2: SUBB #0x108, W4 ; Sub. 0x108 and C from W4 (Word mode) ; Store result to W4

Before Instruction

After Instruction

W4 6234 W4 612CSR 0001 (C = 1) SR 0001 (C = 1)


Instruction D

escriptions

5

SUBB Subtract Short Literal from Wb with Borrow


X X X X

Syntax: {label:} SUBB{.B} Wb, #lit5, Wd

[Wd]

[Wd++]

[Wd--]

[++Wd]

[--Wd]


Operation: (Wb) – lit5 – (C) → Wd



Description: Subtract the 5-bit unsigned literal operand and the Borrow flag (Carry flag inverse, C) from the contents of the base register Wb and place the result in the destination register Wd. Register direct addressing must be used for Wb. Either register direct or indirect addressing may be used for Wd.




Words: 1

Cycles: 1

Example 1: SUBB.B W4, #0x10, W5 ; Sub. 0x10 and C from W4 (Byte mode) ; Store result to W5

Before Instruction

After Instruction

W4 1782 W4 1782W5 7804 W5 7871SR 0000 SR 0005 (OV, C = 1)



Example 2: SUBB W0, #0x8, [W2++] ; Sub. 0x8 and C from W0 (Word mode) ; Store result to [W2] ; Post-increment W2

Before Instruction

After Instruction

W0 0009 W0 0009W2 2004 W2 2006

Data 2004 A557 Data 2004 0000SR 0020 (Z = 1) SR 0103 (DC, Z, C = 1)


Instruction D

escriptions

5

SUBB Subtract Ws from Wb with Borrow


X X X X

Syntax: {label:} SUBB{.B} Wb, Ws, Wd

[Ws], [Wd]

[Ws++], [Wd++]

[Ws--], [Wd--]

[++Ws], [++Wd]

[--Ws], [--Wd]


Operation: (Wb) – (Ws) – (C) → Wd



Description: Subtract the contents of the source register Ws and the Borrow flag (Carry flag inverse, C) from the contents of the base register Wb, and place the result in the destination register Wd. Register direct addressing must be used for Wb. Register direct or indirect addressing may be used for Ws and Wd.




Words: 1

Cycles: 1

Example 1: SUBB.B W0, W1, W0 ; Sub. W1 and C from W0 (Byte mode) ; Store result to W0

Before Instruction

After Instruction

W0 1732 W0 17EDW1 7844 W1 7844SR 0000 SR 0108 (DC, N = 1)



Example 2: SUBB W7,[W8++],[W9++] ; Sub. [W8] and C from W7 (Word mode) ; Store result to [W9] ; Post-increment W8 ; Post-increment W9

Before Instruction

After Instruction

W7 2450 W7 2450W8 1808 W8 180AW9 2022 W9 2024

Data 1808 92E4 Data 1808 92E4Data 2022 A557 Data 2022 916C

SR 0000 SR 010C (DC, N, OV = 1)


Instruction D

escriptions

5

SUBBR Subtract f from WREG with Borrow


X X X X

Syntax: {label:} SUBBR{.B} f {,WREG}

Operands: f ∈ [0 ... 8191]

Operation: (WREG) – (f) – (C) → destination designated by D



Description: Subtract the contents of the specified file register f and the Borrow flag (Carry flag inverse, C) from the contents of WREG, and place the result in the destination register. The optional WREG operand determines the destination register. If WREG is specified, the result is stored in WREG. If WREG is not specified, the result is stored in the file register.



2: The WREG is set to working register W0.3: The Z flag is “sticky” for ADDC, CPB, SUBB and SUBBR. These


Words: 1

Cycles: 1

Example 1: SUBBR.B 0x803 ; Sub. (0x803) and C from WREG (Byte mode) ; Store result to 0x803

Before Instruction

After Instruction

WREG (W0) 7804 WREG (W0) 7804Data 0802 9439 Data 0802 6F39

SR 0002 (Z = 1) SR 0000

Example 2: SUBBR 0xA04, WREG ; Sub. (0xA04) and C from WREG (Word mode) ; Store result to WREG

Before Instruction

After Instruction

WREG (W0) 6234 WREG (W0) FFFEData 0A04 6235 Data 0A04 6235

SR 0000 SR 0008 (N = 1)



SUBBR Subtract Wb from Short Literal with Borrow


X X X X

Syntax: {label:} SUBBR{.B} Wb, #lit5, Wd

[Wd]

[Wd++]

[Wd--]

[++Wd]

[--Wd]


Operation: lit5 – (Wb) – (C) → Wd



Description: Subtract the contents of the base register Wb and the Borrow flag (Carry flag inverse, C) from the 5-bit unsigned literal and place the result in the destination register Wd. Register direct addressing must be used for Wb. Register direct or indirect addressing must be used for Wd.




Words: 1

Cycles: 1

Example 1: SUBBR.B W0, #0x10, W1 ; Sub. W0 and C from 0x10 (Byte mode) ; Store result to W1

Before Instruction

After Instruction

W0 F310 W0 F310W1 786A W1 7800SR 0003 (Z, C = 1) SR 0103 (DC, Z, C = 1)


Instruction D

escriptions

5

Example 2: SUBBR W0, #0x8, [W2++] ; Sub. W0 and C from 0x8 (Word mode) ; Store result to [W2] ; Post-increment W2

Before Instruction

After Instruction

W0 0009 W0 0009W2 2004 W2 2006

Data 2004 A557 Data 2004 FFFESR 0020 (Z = 1) SR 0108 (DC, N = 1)



SUBBR Subtract Wb from Ws with Borrow


X X X X

Syntax: {label:} SUBBR{.B} Wb, Ws, Wd

[Ws], [Wd]

[Ws++], [Wd++]

[Ws--], [Wd--]

[++Ws], [++Wd]

[--Ws], [--Wd]


Operation: (Ws) – (Wb) – (C) → Wd



Description: Subtract the contents of the base register Wb and the Borrow flag (Carry flag inverse, C) from the contents of the source register Ws and place the result in the destination register Wd. Register direct addressing must be used for Wb. Register direct or indirect addressing may be used for Ws and Wd.




Words: 1

Cycles: 1

Example 1: SUBBR.B W0, W1, W0 ; Sub. W0 and C from W1 (Byte mode) ; Store result to W0

Before Instruction

After Instruction

W0 1732 W0 1711W1 7844 W1 7844SR 0000 SR 0001 (C = 1)


Instruction D

escriptions

5

Example 2: SUBBR W7,[W8++],[W9++] ; Sub. W7 and C from [W8] (Word mode) ; Store result to [W9] ; Post-increment W8 ; Post-increment W9

Before Instruction

After Instruction

W7 2450 W7 2450W8 1808 W8 180AW9 2022 W9 2024

Data 1808 92E4 Data 1808 92E4Data 2022 A557 Data 2022 6E93

SR 0000 SR 0005 (OV, C = 1)



SUBR Subtract f from WREG


X X X X

Syntax: {label:} SUBR{.B} f {,WREG}

Operands: f ∈ [0 ... 8191]

Operation: (WREG) – (f) → destination designated by D



Description: Subtract the contents of the specified file register from the contents of the default working register WREG, and place the result in the destination register. The optional WREG operand determines the destination register. If WREG is specified, the result is stored in WREG. If WREG is not specified, the result is stored in the file register




Words: 1

Cycles: 1

Example 1: SUBR.B 0x1FFF ; Sub. (0x1FFF) from WREG (Byte mode) ; Store result to 0x1FFF

Before Instruction

After Instruction


SR 0000 SR 0000

Example 2: SUBR 0xA04, WREG ; Sub. (0xA04) from WREG (Word mode) ; Store result to WREG

Before Instruction

After Instruction

WREG (W0) 6234 WREG (W0) FFFFData 0A04 6235 Data 0A04 6235

SR 0000 SR 0008 (N = 1)


Instruction D

escriptions

5

SUBR Subtract Wb from Short Literal


Syntax: {label:} SUBR{.B} Wb, #lit5 Wd[Wd][Wd++][Wd--][++Wd][--Wd]


Operation: lit5 – (Wb) → Wd Status Affected: DC, N, OV, Z, CEncoding: 0001 0www wBqq qddd d11k kkkk

Description: Subtract the contents of the base register Wb from the unsigned 5-bit literal operand, and place the result in the destination register Wd. Register direct addressing must be used for Wb. Either register direct or indirect addressing may be used for Wd.



Words: 1Cycles: 1

Example 1: SUBR.B W0, #0x10, W1 ; Sub. W0 from 0x10 (Byte mode) ; Store result to W1

Before Instruction

After Instruction

W0 F310 W0 F310W1 786A W1 7800SR 0000 SR 0103 (DC, Z, C = 1)

Example 2: SUBR W0, #0x8, [W2++] ; Sub. W0 from 0x8 (Word mode) ; Store result to [W2] ; Post-increment W2

Before Instruction

After Instruction

W0 0009 W0 0009W2 2004 W2 2006

Data 2004 A557 Data 2004 FFFFSR 0000 SR 0108 (DC, N = 1)



SUBR Subtract Wb from Ws


X X X X

Syntax: {label:} SUBR{.B} Wb, Ws, Wd

[Ws], [Wd]

[Ws++], [Wd++]

[Ws--], [Wd--]

[++Ws], [++Wd]

[--Ws], [--Wd]


Operation: (Ws) – (Wb) → Wd



Description: Subtract the contents of the base register Wb from the contents of the source register Ws and place the result in the destination register Wd. Register direct addressing must be used for Wb. Either register direct or indirect addressing may be used for Ws and Wd.



Words: 1

Cycles: 1

Example 1: SUBR.B W0, W1, W0 ; Sub. W0 from W1 (Byte mode) ; Store result to W0

Before Instruction

After Instruction

W0 1732 W0 1712W1 7844 W1 7844SR 0000 SR 0001 (C = 1)


Instruction D

escriptions

5

Example 2: SUBR W7, [W8++], [W9++] ; Sub. W7 from [W8] (Word mode) ; Store result to [W9] ; Post-increment W8 ; Post-increment W9

Before Instruction

After Instruction

W7 2450 W7 2450W8 1808 W8 180AW9 2022 W9 2024

Data 1808 92E4 Data 1808 92E4Data 2022 A557 Data 2022 6E94

SR 0000 SR 0005 (OV, C = 1)



SWAP Byte or Nibble Swap Wn


X X X X

Syntax: {label:} SWAP{.B} Wn


Operation: For byte operation: (Wn)<7:4> ↔ (Wn)<3:0> For word operation: (Wn)<15:8> ↔ (Wn)<7:0>


Encoding: 1111 1101 1B00 0000 0000 ssss

Description: Swap the contents of the working register Wn. In Word mode, the two bytes of Wn are swapped. In Byte mode, the two nibbles of the Least Significant Byte of Wn are swapped, and the Most Significant Byte of Wn is unchanged. Register direct addressing must be used for Wn.

The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘s’ bits select the address of the working register.


Words: 1

Cycles: 1

Example 1: SWAP.B W0 ; Nibble swap (W0)

Before Instruction

After Instruction

W0 AB87 W0 AB78SR 0000 SR 0000

Example 2: SWAP W0 ; Byte swap (W0)

Before Instruction

After Instruction

W0 8095 W0 9580SR 0000 SR 0000


Instruction D

escriptions

5

TBLRDH Table Read High


X X X X

Syntax: {label:} TBLRDH{.B} [Ws], Wd

[Ws++], [Wd]

[Ws--], [Wd++]

[++Ws], [Wd--]

[--Ws], [++Wd]

[--Wd]


Operation: For byte operation: If (LSB(Ws) = 1) 0 → Wd Else Program Mem [(TBLPAG),(Ws)] <23:16> → WdFor word operation: Program Mem [(TBLPAG),(Ws)] <23:16> → Wd <7:0> 0 → Wd <15:8>



Description: Read the contents of the most significant word of program memory and store it to the destination register Wd. The target word address of program memory is formed by concatenating the 8-bit Table Pointer register, TBLPAG<7:0>, with the effective address specified by Ws. Indirect addressing must be used for Ws, and either register direct or indirect addressing may be used for Wd.

In Word mode, zero is stored to the Most Significant Byte of the destination register (due to non-existent program memory) and the third program memory byte (PM<23:16>) at the specified program memory address is stored to the Least Significant Byte of the destination register.

In Byte mode, the source address depends on the contents of Ws. If Ws is not word-aligned, zero is stored to the destination register (due to non-existent program memory). If Ws is word-aligned, the third program memory byte (PM<23:16>) at the specified program memory address is stored to the destination register.


Note: The extension .B in the instruction denotes a byte move ratherthan a word move. You may use a .W extension to denote aword move, but it is not required.

Words: 1

Cycles: 2



Example 1: TBLRDH.B [W0], [W1++] ; Read PM (TBLPAG:[W0]) (Byte mode) ; Store to [W1] ; Post-increment W1

Before Instruction

After Instruction

W0 0812 W0 0812W1 0F71 W1 0F72

Data 0F70 0944 Data 0F70 EF44Program 01 0812 EF 2042 Program 01 0812 EF 2042

TBLPAG 0001 TBLPAG 0001SR 0000 SR 0000

Example 2: TBLRDH [W6++], W8 ; Read PM (TBLPAG:[W6]) (Word mode) ; Store to W8 ; Post-increment W6

Before Instruction

After Instruction

W6 3406 W6 3408W8 65B1 W8 0029

Program 00 3406 29 2E40 Program 00 3406 29 2E40TBLPAG 0000 TBLPAG 0000

SR 0000 SR 0000


Instruction D

escriptions

5

TBLRDL Table Read Low


X X X X

Syntax: {label:} TBLRDL{.B} [Ws], Wd

[Ws++], [Wd]

[Ws--], [Wd++]

[++Ws], [Wd--]

[--Ws], [++Wd]

[--Wd]


Operation: For byte operation: If (LSB(Ws) = 1) Program Mem [(TBLPAG),(Ws)] <15:8> → Wd Else Program Mem [(TBLPAG),(Ws)] <7:0> → WdFor word operation: Program Mem [(TBLPAG),(Ws)] <15:0> → Wd



Description: Read the contents of the least significant word of program memory and store it to the destination register Wd. The target word address of program memory is formed by concatenating the 8-bit Table Pointer register, TBLPAG<7:0>, with the effective address specified by Ws. Indirect addressing must be used for Ws, and either register direct or indirect addressing may be used for Wd.

In Word mode, the lower 2 bytes of program memory are stored to the destination register. In Byte mode, the source address depends on the contents of Ws. If Ws is not word-aligned, the second byte of the program memory word (PM<15:7>) is stored to the destination register. If Ws is word-aligned, the first byte of the program memory word (PM<7:0>) is stored to the destination register.

The ‘B’ bit selects byte or word operation (‘0’ for word mode, ‘1’ for byte).The ‘q’ bits select the destination Address mode.The ‘d’ bits select the destination register.The ‘p’ bits select the source Address mode.The ‘s’ bits select the source register.

Note: The extension .B in the instruction denotes a byte move ratherthan a word move. You may use a .W extension to denote aword move, but it is not required.

Words: 1

Cycles: 2



Example 1: TBLRDL.B [W0++], W1 ; Read PM (TBLPAG:[W0]) (Byte mode) ; Store to W1 ; Post-increment W0

Before Instruction

After Instruction

W0 0813 W0 0814W1 0F71 W1 0F20

Data 0F70 0944 Data 0F70 EF44Program 01 0812 EF 2042 Program 01 0812 EF 2042


Example 2: TBLRDL [W6], [W8++] ; Read PM (TBLPAG:[W6]) (Word mode) ; Store to W8 ; Post-increment W8

Before Instruction

After Instruction

W6 3406 W6 3408W8 1202 W8 1204

Data 1202 658B Data 1202 2E40Program 00 3406 29 2E40 Program 00 3406 29 2E40



Instruction D

escriptions

5

TBLWTH Table Write High


X X X X

Syntax: {label:} TBLWTH{.B} Ws, [Wd]

[Ws], [Wd++]

[Ws++], [Wd--]

[Ws--], [++Wd]

[++Ws], [--Wd]

[--Ws],


Operation: For byte operation: If (LSB(Wd) = 1) NOP Else (Ws) → Program Mem [(TBLPAG),(Wd)]<23:16>For word operation: (Ws)<7:0> → Program Mem [(TBLPAG),(Wd)] <23:16>



Description: Store the contents of the working source register Ws to the most significant word of program memory. The destination word address of program mem-ory is formed by concatenating the 8-bit Table Pointer register, TBLPAG<7:0>, with the effective address specified by Wd. Either direct or indirect addressing may be used for Ws, and indirect addressing must be used for Wd.

Since program memory is 24 bits wide, this instruction can only write to the upper byte of program memory (PM<23:16>). This may be performed using a Wd that is word-aligned in Byte mode or Word mode. If Byte mode is used with a Wd that is not word-aligned, no operation is performed.


Note: The extension .B in the instruction denotes a byte move ratherthan a word move. You may use a .W extension to denote a wordmove, but it is not required.

Words: 1

Cycles: 2



Example 1: TBLWTH.B [W0++], [W1] ; Write [W0]... (Byte mode) ; to PM Latch High (TBLPAG:[W1]) ; Post-increment W0

Before Instruction

After Instruction

W0 0812 W0 0812W1 0F70 W1 0F70

Data 0812 0944 Data 0812 EF44Program 01 0F70 EF 2042 Program 01 0F70 44 2042


Note: Only the Program Latch is written to. The contents of program memoryare not updated until the Flash memory is programmed using theprocedure described in the specific device family reference manual.

Example 2: TBLWTH W6, [W8++] ; Write W6... (Word mode) ; to PM Latch High (TBLPAG:[W8]) ; Post-increment W8

Before Instruction

After Instruction

W6 0026 W6 0026W8 0870 W8 0872

Program 00 0870 22 3551 Program 00 0870 26 3551TBLPAG 0000 TBLPAG 0000

SR 0000 SR 0000



Instruction D

escriptions

5

TBLWTL Table Write Low


X X X X

Syntax: {label:} TBLWTL{.B} Ws, [Wd]

[Ws], [Wd++]

[Ws++], [Wd--]

[Ws--], [++Wd]

[++Ws], [--Wd]

[--Ws],


Operation: For byte operation: If (LSB(Wd)=1) (Ws) → Program Mem [(TBLPAG),(Wd)] <15:8> Else (Ws) → Program Mem [(TBLPAG),(Wd)] <7:0>For word operation: (Ws) → Program Mem [(TBLPAG),(Wd)] <15:0>



Description: Store the contents of the working source register Ws to the least significant word of program memory. The destination word address of program memory is formed by concatenating the 8-bit Table Pointer register, TBLPAG<7:0>, with the effective address specified by Wd. Either direct or indirect addressing may be used for Ws, and indirect addressing must be used for Wd.

In Word mode, Ws is stored to the lower 2 bytes of program memory. In Byte mode, the Least Significant bit of Wd determines the destination byte. If Wd is not word-aligned, Ws is stored to the second byte of program memory (PM<15:8>). If Wd is word-aligned, Ws is stored to the first byte of program memory (PM<7:0>).


Note: The extension .B in the instruction denotes a byte move ratherthan a word move. You may use a .W extension to denote a wordmove, but it is not required.

Words: 1

Cycles: 2



Example 1: TBLWTL.B W0, [W1++] ; Write W0... (Byte mode) ; to PM Latch Low (TBLPAG:[W1]) ; Post-increment W1

Before Instruction

After Instruction

W0 6628 W0 6628W1 1225 W1 1226

Program 00 1224 78 0080 Program 01 1224 78 2880TBLPAG 0000 TBLPAG 0000

SR 0000 SR 0000


Example 2: TBLWTL [W6], [W8] ; Write [W6]... (Word mode) ; to PM Latch Low (TBLPAG:[W8]) ; Post-increment W8

Before Instruction

After Instruction

W6 1600 W6 1600W8 7208 W8 7208

Data 1600 0130 Data 1600 0130Program 01 7208 09 0002 Program 01 7208 09 0130




Instruction D

escriptions

5

ULNK De-allocate Stack Frame


X X X X

Syntax: {label:} ULNK

Operands: None

Operation: W14 → W15(W15) – 2 → W15(TOS) → W14


Encoding: 1111 1010 1000 0000 0000 0000

Description: This instruction de-allocates a Stack Frame for a subroutine calling sequence. The Stack Frame is de-allocated by setting the Stack Pointer (W15) equal to the Frame Pointer (W14), and then POPping the stack to reset the Frame Pointer (W14).

Words: 1

Cycles: 1

Example 1: ULNK ; Unlink the stack frame

Before Instruction

After Instruction

W14 2002 W14 2000W15 20A2 W15 2000

Data 2000 2000 Data 2000 2000SR 0000 SR 0000

Example 2: ULNK ; Unlink the stack frame

Before Instruction

After Instruction

W14 0802 W14 0800W15 0812 W15 0800

Data 0800 0800 Data 0800 0800SR 0000 SR 0000



XOR Exclusive OR f and WREG


X X X X

Syntax: {label:} XOR{.B} f {,WREG}

Operands: f ∈ [0 ... 8191]

Operation: (f).XOR.(WREG) → destination designated by D



Description: Compute the logical exclusive OR operation of the contents of the default working register WREG and the contents of the specified file register and place the result in the destination register. The optional WREG operand determines the destination register. If WREG is specified, the result is stored in WREG. If WREG is not specified, the result is stored in the file register.




Words: 1

Cycles: 1

Example 1: XOR.B 0x1FFF ; XOR (0x1FFF) and WREG (Byte mode) ; Store result to 0x1FFF

Before Instruction

After Instruction


SR 0000 SR 0008 (N = 1)

Example 2: XOR 0xA04, WREG ; XOR (0xA04) and WREG (Word mode) ; Store result to WREG

Before Instruction

After Instruction

WREG (W0) 6234 WREG (W0) C267Data 0A04 A053 Data 0A04 A053

SR 0000 SR 0008 (N = 1)


Instruction D

escriptions

5

XOR Exclusive OR Literal and Wn


X X X X

Syntax: {label:} XOR{.B} #lit10, Wn


Operation: lit10.XOR.(Wn) → Wn



Description: Compute the logical exclusive OR operation of the unsigned 10-bit literal operand and the contents of the working register Wn and store the result back in the working register Wn. Register direct addressing must be used for Wn.



2: For byte operations, the literal must be specified as an unsignedvalue [0:255]. See Section 4.6 “Using 10-bit Literal Oper-ands” for information on using 10-bit literal operands in Bytemode.

Words: 1

Cycles: 1

Example 1: XOR.B #0x23, W0 ; XOR 0x23 and W0 (Byte mode) ; Store result to W0

Before Instruction

After Instruction

W0 7804 W0 7827SR 0000 SR 0000

Example 2: XOR #0x108, W4 ; XOR 0x108 and W4 (Word mode) ; Store result to W4

Before Instruction

After Instruction

W4 6134 W4 603CSR 0000 SR 0000



XOR Exclusive OR Wb and Short Literal


X X X X

Syntax: {label:} XOR{.B} Wb, #lit5, Wd

[Wd]

[Wd++]

[Wd--]

[++Wd]

[--Wd]


Operation: (Wb).XOR.lit5 → Wd



Description: Compute the logical exclusive OR operation of the contents of the base register Wb and the unsigned 5-bit literal operand and place the result in the destination register Wd. Register direct addressing must be used for Wb. Either register direct or indirect addressing may be used for Wd.

The ‘w’ bits select the address of the base register.The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte).The ‘q’ bits select the destination Address mode.The ‘d’ bits select the destination register.The ‘k’ bits provide the literal operand, a 5-bit integer number.


Words: 1

Cycles: 1

Example 1: XOR.B W4, #0x16, W5 ; XOR W4 and 0x14 (Byte mode) ; Store result to W5

Before Instruction

After Instruction

W4 C822 W4 C822W5 1200 W5 1234SR 0000 SR 0000

Example 2: XOR W2, #0x1F, [W8++] ; XOR W2 by 0x1F (Word mode) ; Store result to [W8] ; Post-increment W8

Before Instruction

After Instruction

W2 8505 W2 8505W8 1004 W8 1006

Data 1004 6628 Data 1004 851ASR 0000 SR 0008 (N = 1)


Instruction D

escriptions

5

XOR Exclusive OR Wb and Ws


X X X X

Syntax: {label:} XOR{.B} Wb, Ws, Wd

[Ws], [Wd]

[Ws++], [Wd++]

[Ws--], [Wd--]

[++Ws], [++Wd]

[--Ws], [--Wd]


Operation: (Wb).XOR.(Ws) → Wd



Description: Compute the logical exclusive OR operation of the contents of the source register Ws and the contents of the base register Wb, and place the result in the destination register Wd. Register direct addressing must be used for Wb. Either register direct or indirect addressing may be used for Ws and Wd.

The ‘w’ bits select the address of the base register.The ‘B’ bit selects byte or word operation (‘0’ for word, ‘1’ for byte). The ‘q’ bits select the destination Address mode.The ‘d’ bits select the destination register.The ‘p’ bits select the source Address mode.The ‘s’ bits select the source register.


Words: 1

Cycles: 1

Example 1: XOR.B W1, [W5++], [W9++] ; XOR W1 and [W5] (Byte mode) ; Store result to [W9] ; Post-increment W5 and W9

Before Instruction

After Instruction

W1 AAAA W1 AAAAW5 2000 W5 2001W9 2600 W9 2601

Data 2000 115A Data 2000 115AData 2600 0000 Data 2600 00F0

SR 0000 SR 0008 (N = 1)



Example 2: XOR W1, W5, W9 ; XOR W1 and W5 (Word mode) ; Store the result to W9

Before Instruction

After Instruction

W1 FEDC W1 FEDCW5 1234 W5 1234W9 A34D W9 ECE8SR 0000 SR 0008 (N = 1)


Instruction D

escriptions

5

ZE Zero-Extend Wn


Syntax: {label:} ZE Ws, Wnd[Ws],[Ws++],[Ws--],[++Ws],[--Ws],


Operation: Ws<7:0> → Wnd<7:0>0 → Wnd<15:8>

Status Affected: N, Z, CEncoding: 1111 1011 10qq qddd dppp ssss

Description: Zero-extend the Least Significant Byte in source working register Ws to a 16-bit value and store the result in the destination working register Wnd. Either register direct or indirect addressing may be used for Ws, and register direct addressing must be used for Wnd. The N flag is cleared and the C flag is set, because the zero-extended word is always positive.

The ‘q’ bits select the destination Address mode.The ‘d’ bits select the destination register.The ‘p’ bits select the source Address mode.The ‘s’ bits select the source register.

Note 1: This operation converts a byte to a word, and it uses no .B or .W extension.

2: The source Ws is addressed as a byte operand, so anyaddress modification is by ‘1’.

Words: 1Cycles: 1

Example 1: ZE W3, W4 ; zero-extend W3 ; Store result to W4

Before Instruction

After Instruction

W3 7839 W3 7839W4 1005 W4 0039SR 0000 SR 0001 (C = 1)

Example 2: ZE [W2++], W12 ; Zero-extend [W2] ; Store to W12 ; Post-increment W2

Before Instruction

After Instruction

W2 0900 W2 0901W12 1002 W12 008F

Data 0900 268F Data 0900 268FSR 0000 SR 0001 (C = 1)



NOTES:


Reference

6

Section 6. Reference


6.1 Instruction Bit Map ........................................................................................................ 3586.2 Instruction Set Summary Table ..................................................................................... 3606.3 Revision History ............................................................................................................ 367



6.1 INSTRUCTION BIT MAPInstruction encoding for the 16-bit MCU and DSC family devices is summarized in Table 6-1. Thistable contains the encoding for the Most Significant Byte (MSB) of each instruction. The firstcolumn in the table represents bits 23:20 of the opcode, and the first row of the table representsbits 19:16 of the opcode. The first byte of the opcode is formed by taking the first column bit valueand appending the first row bit value. For instance, the MSB of the PUSH instruction (last row,ninth column) is encoded with 11111000b (0xF8).

Note: The complete opcode for each instruction may be determined by the instructiondescriptions in Section 5. “Instruction Descriptions”, using Table 5-1 throughTable 5-12.


© 2009 M

icrochip Technology Inc.D

S70157D

-page 359


Reference 6

Ta

011 1100 1101 1110 1111

Opc

ode<

23:2

0>

— BRA(1)

(OA)BRA(1)

(OB)BRA(1)

(SA)BRA(1)

(SB)

UBBR

RANN)

BRA(GT)

BRA(GE)

BRA(GTU)

—

ADDC

SUBB

XOR

MOV

TST BTSTS BSW BTSS BTSC

LWTHLWTL

MUL SUBSUBB

MOV.D MOV

D(1)

G(1)

B(1)

SAC(1) SAC.R(1) — FF1L(1)

FF1R(1)

— — SL ASRLSR

FBCL

LRETM

INCINC2

DECDEC2

COMNEG

CLRSETM

SEZE

DISI DAWEXCHSWAP

CLRWDTPWRSAV

POP.SPUSH.SRESET

NOPR

No

ble 6-1: Instruction EncodingOpcode<19:16>

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1

0000 NOP BRACALLGOTORCALL

CALL — GOTO RETLW RETFIERETURN

RCALL DO(1) REPEAT —

0001 SUBR S0010 MOV0011 BRA

(OV)BRA (C)

BRA(Z)

BRA(N)

BRA(LE)

BRA(LT)

BRA(LEU)

BRA BRA (NOV) BRA(NC)

BRA(NZ)

B(

0100 ADD0101 SUB0110 AND0111 IOR1000 MOV1001 MOV1010 BSET BCLR BTG BTST BTSTS BTST BTSS BTSC BSET BCLR BTG B1011 ADD

ADDCSUB

SUBBANDXOR

IORMOV

ADDADDC

SUBSUBB

ANDXOR

IORMOV

MUL.USMUL.UU

MUL.SSMUL.SU

TBLRDHTBLRDL

TBTB

1100 MAC(1)

MPY(1)

MPY.N(1)

MSC(1)

CLRAC(1) MAC(1)

MPY(1)

MPY.N(1)

MSC(1)

MOVSAC(1) SFTAC(1) ADD(1) LAC(1) ADNESU

1101 SL ASRLSR

RLCRLNC

RRC RRNC

SL ASRLSR

RLC RLNC

RRC RRNC

DIV.SDIV.U

DIVF(2) —

1110 CP0 CPCPB

CP0 CPCPB

— — CPSGTCPSLT

CPSEQCPSNE

INCINC2

DECDEC2

COMNEG

CS

1111 ED(1)

EDAC(1)

MAC(1)

MPY(1)

— — — — PUSH POP LNKULNK

te 1: This instruction is only available in dsPIC30F and dsPIC33F family devices.

16-bit MC

U and D

SC Program

mer’s R

eference Manual

DS

70157D-page 360

© 2009 M

icrochip Technology Inc.

is table contains an alphabetized listing of the execution time (in instruction cycles), affected-2 identifies the symbols that are used in the

(2) SAB(1,2) DC N OV Z C Page Number

— 5-89

— 5-90

— 5-91

— 5-93

— — — — — 5-95

— — — — — 5-96

— 5-98

— 5-99

— 5-100

— 5-102

— — — — 5-104

— — — — 5-105

— — — — 5-106

— — — — 5-107

— — — 5-109

— — — 5-111

— — — — 5-113

— — — — 5-114

— — — — — — 5-115— — — — — — 5-116— — — — — — 5-117— — — — — — 5-118— — — — — — 5-119— — — — — — 5-121— — — — — — 5-122— — — — — — 5-123— — — — — — 5-124

6.2 INSTRUCTION SET SUMMARY TABLEThe complete 16-bit MCU and DSC device instruction set is summarized in Table 6-2. Thinstruction set. It includes instruction assembly syntax, description, size (in 24-bit words),status bits and the page number in which the detailed description can be found. Table 1Instruction Set Summary Table.

Table 6-2: Instruction Set Summary TableAssembly Syntax

Mnemonic, Operands Description Words Cycles OA(2) OB(2) SA(1,2) SB(1,2) OAB

ADD f {,WREG} Destination = f + WREG 1 1 — — — — —

ADD #lit10,Wn Wn = lit10 + Wn 1 1 — — — — —

ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 — — — — —

ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 — — — — —

ADD Acc(2) Add accumulators 1 1

ADD Ws,#Slit4,Acc 16-bit signed add to accumulator 1 1

ADDC f {,WREG} Destination = f + WREG + (C) 1 1 — — — — —

ADDC #lit10,Wn Wn = lit10 + Wn + (C) 1 1 — — — — —

ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 — — — — —

ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 — — — — —

AND f {,WREG} Destination = f .AND. WREG 1 1 — — — — —

AND #lit10,Wn Wn = lit10 .AND. Wn 1 1 — — — — —

AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 — — — — —

AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 — — — — —

ASR f {,WREG} Destination = arithmetic right shift f 1 1 — — — — —

ASR Ws,Wd Wd = arithmetic right shift Ws 1 1 — — — — —

ASR Wb,#lit4,Wnd Wnd = arithmetic right shift Wb by lit4 1 1 — — — — —

ASR Wb,Wns,Wnd Wnd = arithmetic right shift Wb by Wns 1 1 — — — — —

BCLR f,#bit4 Bit clear f 1 1 — — — — —BCLR Ws,#bit4 Bit clear Ws 1 1 — — — — —BRA Expr Branch unconditionally 1 2 — — — — —BRA Wn Computed branch 1 2 — — — — —BRA C,Expr Branch if Carry 1 1 (2) — — — — —BRA GE,Expr Branch if greater than or equal 1 1 (2) — — — — —BRA GEU,Expr Branch if Carry 1 1 (2) — — — — —BRA GT,Expr Branch if greater than 1 1 (2) — — — — —BRA GTU,Expr Branch if unsigned greater than 1 1 (2) — — — — —Legend: set or cleared; may be cleared, but never set; may be set, but never cleared; ‘1’ always set; ‘0’ always cleared; — unchangedNote 1: SA, SB and SAB are only modified if the corresponding saturation is enabled, otherwise unchanged.

2: This instruction/operand is only available in dsPIC30F and dsPIC33F devices.

© 2009 M


S70157D

-page 361


Reference 6

BR — — — — — — 5-125BR — — — — — — 5-126BR — — — — — — 5-127BR — — — — — — 5-128BR — — — — — — 5-129BR — — — — — — 5-130BR — — — — — — 5-131BR — — — — — — 5-132BR — — — — — — 5-133BR — — — — — — 5-134BR — — — — — — 5-135BR — — — — — — 5-136BR — — — — — — 5-137BR — — — — — — 5-138BR — — — — — — 5-139BS — — — — — — 5-140BS — — — — — — 5-141BS — — — — — — 5-142BS — — — — — — 5-142BT — — — — — — 5-144BT — — — — — — 5-145BT — — — — — — 5-146

BT — — — — — — 5-148

BT — — — — — — 5-150

BT — — — — — — 5-151

BT — — — — — 5-153

BT — — — — — 5-154

BT — — — — — 5-154

BT — — — — — 5-155

BT — — — — — 5-155

BT — — — — — 5-157

BT — — — — — 5-158

Ta

AB(1,2) DC N OV Z C Page Number

LeNo

A LE,Expr Branch if less than or equal 1 1 (2) — — — — —A LEU,Expr Branch if unsigned less than or equal 1 1 (2) — — — — —A LT,Expr Branch if less than 1 1 (2) — — — — —A LTU,Expr Branch if not Carry 1 1 (2) — — — — —A N,Expr Branch if Negative 1 1 (2) — — — — —A NC,Expr Branch if not Carry 1 1 (2) — — — — —A NN,Expr Branch if not Negative 1 1 (2) — — — — —A NOV,Expr Branch if not Overflow 1 1 (2) — — — — —A NZ,Expr Branch if not Zero 1 1 (2) — — — — —A OA,Expr(2) Branch if Accumulator A overflow 1 1 (2) — — — — —A OB,Expr(2) Branch if Accumulator B overflow 1 1 (2) — — — — —A OV,Expr Branch if Overflow 1 1 (2) — — — — —A SA,Expr(2) Branch if Accumulator A saturated 1 1 (2) — — — — —A SB,Expr(2) Branch if Accumulator B saturated 1 1 (2) — — — — —A Z,Expr Branch if Zero 1 1 (2) — — — — —ET f,#bit4 Bit set f 1 1 — — — — —ET Ws,#bit4 Bit set Ws 1 1 — — — — —W.C Ws,Wb Write C bit to Ws<Wb> 1 1 — — — — —W.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 — — — — —G f,#bit4 Bit toggle f 1 1 — — — — —G Ws,#bit4 Bit toggle Ws 1 1 — — — — —SC f,#bit4 Bit test f, skip if clear 1 1

(2 or 3)— — — — —

SC Ws,#bit4 Bit test Ws, skip if clear 1 1(2 or 3)

— — — — —

SS f,#bit4 Bit test f, skip if set 1 1(2 or 3)

— — — — —

SS Ws,#bit4 Bit test Ws, skip if set 1 1(2 or 3)

— — — — —

ST f,#bit4 Bit test f 1 1 — — — — —

ST.C Ws,#bit4 Bit test Ws to C 1 1 — — — — —

ST.Z Ws,#bit4 Bit test Ws to Z 1 1 — — — — —

ST.C Ws,Wb Bit test Ws<Wb> to C 1 1 — — — — —

ST.Z Ws,Wb Bit test Ws<Wb> to Z 1 1 — — — — —

STS f,#bit4 Bit test then set f 1 1 — — — — —

STS.C Ws,#bit4 Bit test Ws to C then set 1 1 — — — — —

ble 6-2: Instruction Set Summary Table (Continued)Assembly Syntax

Mnemonic, Operands Description Words Cycles OA(2) OB(2) SA(1,2) SB(1,2) OAB(2) S

gend: set or cleared; may be cleared, but never set; may be set, but never cleared; ‘1’ always set; ‘0’ always cleared; — unchangedte 1: SA, SB and SAB are only modified if the corresponding saturation is enabled, otherwise unchanged.


16-bit MC

U and D

SC Program

mer’s R

eference Manual

DS

70157D-page 362

© 2009 M


— — — — — 5-158

— — — — — — 5-159— — — — — — 5-161— — — — — — 5-163— — — — — — 5-163— — — — — — 5-1640 — — — — — 5-165— — — — — — 5-167— — — — 5-168

— — — — 5-169

— 5-170

— 5-171

— 5-172

— 1 1 5-173

— 1 1 5-174

— 5-175

— 5-176

— 5-177

— — — — — — 5-179

— — — — — — 5-180

— — — — — — 5-181

— — — — — — 5-182

— — — — — 5-183

— 5-184

— 5-185

— 5-186

— 5-187

— — — — — — 5-188— — 5-189

— — 5-189


BTSTS.Z Ws,#bit4 Bit test Ws to Z then set 1 1 — — — — —

CALL Expr Call subroutine 2 2 — — — — —CALL Wn Call indirect subroutine 1 2 — — — — —CLR f f = 0x0000 1 1 — — — — —CLR WREG WREG = 0x0000 1 1 — — — — —CLR Wd Wd = 0 1 1 — — — — —CLR Acc,Wx,Wxd,Wy,Wyd,AWB(2) Clear accumulator 1 1 0 0 0 0 0CLRWDT Clear Watchdog Timer 1 1 — — — — —COM f {,WREG} Destination = f 1 1 — — — — —

COM Ws,Wd Wd = Ws 1 1 — — — — —

CP f Compare (f – WREG) 1 1 — — — — —

CP Wb,#lit5 Compare (Wb – lit5) 1 1 — — — — —

CP Wb,Ws Compare (Wb – Ws) 1 1 — — — — —

CP0 f Compare (f – 0x0000) 1 1 — — — — —

CP0 Ws Compare (Ws – 0x0000) 1 1 — — — — —

CPB f Compare with borrow (f – WREG – C) 1 1 — — — — —

CPB Wb,#lit5 Compare with borrow (Wb – lit5 – C) 1 1 — — — — —

CPB Wb,Ws Compare with borrow (Wb – Ws – C) 1 1 — — — — —

CPSEQ Wb, Wn Compare (Wb with Wn), skip if = 1 1(2 or 3)

— — — — —

CPSGT Wb, Wn Signed Compare (Wb with Wn), skip if > 1 1(2 or 3)

— — — — —

CPSLT Wb, Wn Signed Compare (Wb with Wn), skip if < 1 1(2 or 3)

— — — — —

CPSNE Wb, Wn Signed Compare (Wb with Wn), skip if ≠ 1 1(2 or 3)

— — — — —

DAW.B Wn Wn = decimal adjust Wn 1 1 — — — — —

DEC f {,WREG} Destination = f – 1 1 1 — — — — —

DEC Ws,Wd Wd = Ws – 1 1 1 — — — — —

DEC2 f {,WREG} Destination = f – 2 1 1 — — — — —

DEC2 Ws,Wd Wd = Ws – 2 1 1 — — — — —

DISI #lit14 Disable interrupts for lit14 instruction cycles 1 1 — — — — —DIV.S Wm, Wn Signed 16/16-bit integer divide 1 18 — — — — —

DIV.SD Wm, Wn Signed 32/16-bit integer divide 1 18 — — — — —

Table 6-2: Instruction Set Summary Table (Continued)Assembly Syntax


Legend: set or cleared; may be cleared, but never set; may be set, but never cleared; ‘1’ always set; ‘0’ always cleared; — unchangedNote 1: SA, SB and SAB are only modified if the corresponding saturation is enabled, otherwise unchanged.


© 2009 M


S70157D

-page 363


Reference 6

DI — — 0 0 5-191

DI — — 0 5-191

DI — — 5-193

DO — — — — — — 5-195DO — — — — — — 5-197ED — — — — — 5-199

ED — — — — — 5-201

EX — — — — — — 5-203FB — — — — — 5-204

FF — — — — — 5-206

FF — — — — — 5-208

GO — — — — — — 5-210GO — — — — — — 5-211IN — 5-212

IN — 5-213

IN — 5-214

IN — 5-215

IO — — — — 5-216

IO — — — — 5-217

IO — — — — 5-218

IO — — — — 5-219

LA — — — — — 5-221

LN — — — — — — 5-223LS — — 0 — 5-224

LS — — 0 — 5-225

LS — — — — 5-227

LS — — — — 5-228

MA — — — — — 5-229

MA — — — — — 5-231

MO — — — — 5-233

MO — — — — — — 5-234MO — — — — — — 5-235

Ta


LeNo

V.U Wm, Wn Unsigned 16/16-bit integer divide 1 18 — — — — —

V.UD Wm, Wn Unsigned 32/16-bit integer divide 1 18 — — — — —

VF Wm, Wn(2) Signed 16/16-bit fractional divide 1 18 — — — — —

#lit14, Expr(2) Do code to PC + Expr, (lit14 + 1) times 2 2 — — — — —Wn, Expr(2) Do code to PC + Expr, (Wn + 1) times 2 2 — — — — —Wm*Wm,Acc,Wx,Wy,Wxd(2) Euclidean distance (no accumulate) 1 1

AC Wm*Wm,Acc,Wx,Wy,Wxd(2) Euclidean distance 1 1

CH Wns,Wnd Swap Wns and Wnd 1 1 — — — — —CL Ws,Wnd Find bit change from left (MSb) side 1 1 — — — — —

1L Ws,Wnd Find first one from left (MSb) side 1 1 — — — — —

1R Ws,Wnd Find first one from right (LSb) side 1 1 — — — — —

TO Expr Go to address 2 2 — — — — —TO Wn Go to address indirectly 1 2 — — — — —C f {,WREG} Destination = f + 1 1 1 — — — — —

C Ws,Wd Wd = Ws + 1 1 1 — — — — —

C2 f {,WREG} Destination = f + 2 1 1 — — — — —

C2 Ws,Wd Wd = Ws + 2 1 1 — — — — —

R f {,WREG} Destination = f .IOR. WREG 1 1 — — — — —

R #lit10,Wn Wn = lit10 .IOR. Wn 1 1 — — — — —

R Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 — — — — —

R Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 — — — — —

C Ws,#Slit4, Acc(2) Load accumulator 1 1

K #lit14 Link Frame Pointer 1 1 — — — — —R f {,WREG} Destination = logical right shift f 1 1 — — — — —

R Ws,Wd Wd = logical right shift Ws 1 1 — — — — —

R Wb,#lit4,Wnd Wnd = logical right shift Wb by lit4 1 1 — — — — —

R Wb,Wns,Wnd Wnd = logical right shift Wb by Wns 1 1 — — — — —

C Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB(2) Multiply and accumulate 1 1

C Wm*Wm,Acc,Wx,Wxd,Wy,Wyd(2) Square and accumulate 1 1

V f {,WREG} Move f to destination 1 1 — — — — —

V WREG,f Move WREG to f 1 1 — — — — —V f,Wnd Move f to Wnd 1 1 — — — — —





16-bit MC

U and D

SC Program

mer’s R

eference Manual

DS

70157D-page 364

© 2009 M


— — — — — — 5-236— — — — — — 5-237— — — — — — 5-238— — — — — — 5-239— — — — — — 5-240— — — — — — 5-241— — — — — — 5-243— — — — — — 5-243— — — — — — 5-245

— — — — — 5-247

— — — — — 5-249

— — — — — — 5-251— — — — — 5-253

— — — — — — 5-255— — — — — — 5-256— — — — — — 5-258— — — — — — 5-260— — — — — — 5-262— — — — — — 5-264— — — — — — 5-265— 5-267

— 5-268

— — — — — 5-269

— — — — — — 5-270— — — — — — 5-271— — — — — — 5-272— — — — — — 5-273— — — — — — 5-274— 5-275

— — — — — — 5-276— — — — — — 5-277— — — — — — 5-278— — — — — — 5-279— — — — — — 5-280— — — — — — 5-281


MOV Wns,f Move Wns to f 1 1 — — — — —MOV.B #lit8,Wnd Move 8-bit unsigned literal to Wnd 1 1 — — — — —MOV #lit16,Wnd Move 16-bit literal to Wnd 1 1 — — — — —MOV [Ws+Slit10],Wnd Move [Ws + Slit10] to Wnd 1 1 — — — — —MOV Wns,[Wd+Slit10] Move Wns to [Wd + Slit10] 1 1 — — — — —MOV Ws,Wd Move Ws to Wd 1 1 — — — — —MOV.D Wns,Wnd Move double Wns to Wnd:Wnd + 1 1 2 — — — — —MOV.D Wns,Wnd Move double Wns:Wns + 1 to Wnd 1 2 — — — — —MOVSAC Acc,Wx,Wxd,Wy,Wyd,AWB(2) Move [Wx] to Wxd, and [Wy] to Wyd 1 1 — — — — —MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd(2) Multiply Wn by Wm to accumulator 1 1

MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd(2) Square to accumulator 1 1

MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd(2) -(Multiply Wn by Wm) to accumulator 1 1 0 0 — — 0MSC Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB(2) Multiply and subtract from accumulator 1 1

MUL f W3:W2 = f * WREG 1 1 — — — — —MUL.SS Wb,Ws,Wnd {Wnd + 1,Wnd} = signed(Wb) * signed(Ws) 1 1 — — — — —MUL.SU Wb,#lit5,Wnd {Wnd + 1,Wnd} = signed(Wb) * unsigned(lit5) 1 1 — — — — —MUL.SU Wb,Ws,Wnd {Wnd + 1,Wnd} = signed(Wb) * unsigned(Ws) 1 1 — — — — —MUL.US Wb,Ws,Wnd {Wnd + 1,Wnd} = unsigned(Wb) * signed(Ws) 1 1 — — — — —MUL.UU Wb,#lit5,Wnd {Wnd + 1,Wnd} = unsigned(Wb) * unsigned(lit5) 1 1 — — — — —MUL.UU Wb,Ws,Wnd {Wnd + 1,Wnd} = unsigned(Wb) * unsigned(Ws) 1 1 — — — — —NEG f {,WREG} Destination = f + 1 1 1 — — — — —

NEG Ws,Wd Wd = Ws + 1 1 1 — — — — —

NEG Acc(2) Negate accumulator 1 1

NOP No operation 1 1 — — — — —NOPR No operation 1 1 — — — — —POP f POP TOS to f 1 1 — — — — —POP Wd POP TOS to Wd 1 1 — — — — —POP.D Wnd POP double from TOS to Wnd:Wnd + 1 1 2 — — — — —POP.S POP shadow registers 1 1 — — — — —

PUSH f PUSH f to TOS 1 1 — — — — —PUSH Ws PUSH Ws to TOS 1 1 — — — — —PUSH.D Wns PUSH double Wns:Wns + 1 to TOS 1 2 — — — — —PUSH.S PUSH shadow registers 1 1 — — — — —PWRSAV #lit1 Enter Power-saving mode 1 1 — — — — —RCALL Expr Relative call 1 2 — — — — —





© 2009 M


S70157D

-page 365


Reference 6

RC — — — — — — 5-283RE — — — — — — 5-285RE — — — — — — 5-286RE — — — — — — 5-288RE — — 5-290

RE — — — — — — 5-291RE — — — — — — 5-292RL — — — 5-293

RL — — — 5-294

RL — — — — 5-296

RL — — — — 5-297

RR — — — 5-299

RR — — — 5-300

RR — — — — 5-302

RR — — — — 5-303

SA — — — — — — 5-305SA — — — — — — 5-307SE — — — 5-309

SE — — — — — — 5-310SE — — — — — — 5-310SE — — — — — — 5-311SF — — — — — 5-312

SF — — — — — 5-313

SL — — — 5-314

SL — — — 5-315

SL — — — — 5-317

SL — — — — 5-318

SU — 5-319

SU — 5-320

SU — 5-321

SU — 5-322

SU — — — — — 5-324

Ta


LeNo

ALL Wn Computed call 1 2 — — — — —PEAT #lit14 Repeat next instruction (lit14 + 1) times 1 1 — — — — —PEAT Wn Repeat next instruction (Wn + 1) times 1 1 — — — — —SET Software device Reset 1 1 — — — — —TFIE Return from interrupt enable 1 3 (2) — — — — —

TLW #lit10,Wn Return with lit10 in Wn 1 3 (2) — — — — —TURN Return from subroutine 1 3 (2) — — — — —C f {,WREG} Destination = rotate left through Carry f 1 1 — — — — —

C Ws,Wd Wd = rotate left through Carry Ws 1 1 — — — — —

NC f {,WREG} Destination = rotate left (no Carry) f 1 1 — — — — —

NC Ws,Wd Wd = rotate left (no Carry) Ws 1 1 — — — — —

C f {,WREG} Destination = rotate right through Carry f 1 1 — — — — —

C Ws,Wd Wd = rotate right through Carry Ws 1 1 — — — — —

NC f {,WREG} Destination = rotate right (no Carry) f 1 1 — — — — —

NC Ws,Wd Wd = rotate right (no Carry) Ws 1 1 — — — — —

C Acc,#Slit4,Wd(2) Store accumulator 1 1 — — — — —C.R Acc,#Slit4,Wd(2) Store rounded Accumulator 1 1 — — — — —

Ws,Wd Wd = sign-extended Ws 1 1 — — — — —

TM f f = 0xFFFF 1 1 — — — — —TM WREG WREG = 0xFFFF 1 1 — — — — —TM Ws Ws = 0xFFFF 1 1 — — — — —TAC Acc,#Slit6(2) Arithmetic shift accumulator by Slit6 1 1

TAC Acc,Wb(2) Arithmetic shift accumulator by (Wb) 1 1

f {,WREG} Destination = arithmetic left shift f 1 1 — — — — —

Ws,Wd Wd = arithmetic left shift Ws 1 1 — — — — —

Wb,#lit4,Wnd Wnd = left shift Wb by lit4 1 1 — — — — —

Wb,Wns,Wnd Wnd = left shift Wb by Wns 1 1 — — — — —

B f {,WREG} Destination = f – WREG 1 1 — — — — —

B #lit10,Wn Wn = Wn – lit10 1 1 — — — — —

B Wb,#lit5,Wd Wd = Wb – lit5 1 1 — — — — —

B Wb,Ws,Wd Wd = Wb – Ws 1 1 — — — — —

B Acc(2) Subtract accumulators 1 1





16-bit MC

U and D

SC Program

mer’s R

eference Manual

DS

70157D-page 366

© 2009 M


— 5-325

— 5-326

— 5-327

— 5-329

— 5-331

— 5-332

— 5-334

— 5-336

— 5-337

— 5-338

— — — — — — 5-340— — — — — — 5-341— — — — — — 5-343— — — — — — 5-345— — — — — — 5-347— — — — — — 5-349— — — — 5-350

— — — — 5-351

— — — — 5-352

— — — — 5-353

— — 0 — 1 5-355


SUBB f {,WREG} Destination = f – WREG – (C) 1 1 — — — — —

SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 — — — — —

SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 — — — — —

SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 — — — — —

SUBBR f {,WREG} Destination = WREG – f – (C) 1 1 — — — — —

SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 — — — — —

SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 — — — — —

SUBR f {,WREG} Destination = WREG – f 1 1 — — — — —

SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 — — — — —

SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 — — — — —

SWAP Wn Wn = byte or nibble swap Wn 1 1 — — — — —TBLRDH Ws,Wd Read high program word to Wd 1 2 — — — — —TBLRDL Ws,Wd Read low program word to Wd 1 2 — — — — —TBLWTH Ws,Wd Write Ws to high program word 1 2 — — — — —TBLWTL Ws,Wd Write Ws to low program word 1 2 — — — — —ULNK Unlink Frame Pointer 1 1 — — — — —XOR f {,WREG} Destination = f .XOR. WREG 1 1 — — — — —

XOR #lit10,Wn Wn = lit10 .XOR. Wn 1 1 — — — — —

XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 — — — — —

XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 — — — — —

ZE Ws,Wnd Wnd = zero-extended Ws 1 1 — — — — —





Section 6. ReferenceR

eference

6
6.3 REVISION HISTORY
Revision A This is the initial released version of this document.

Revision B This revision incorporates all known errata at the time of this document update.

Revision C (February 2008)This revision includes the following corrections and updates:

• Instruction Updates:- Updated BRA Instruction (see “BRA”)- Updated DIVF Instruction (see “DIVF”)- Updated DO Instruction (see “DO”)- Updated SUB instruction (see “SUB”)

Revision D (November 2009)This revision includes the following corrections and updates:

• Document renamed from dsPIC30F/33F Programmer’s Reference Manual to 16-bit MCU and DSC Programmer’s Reference Manual

• Document has been completely redesigned to accommodate all current 16-bit families: dsPIC30F, dsPIC33F, PIC24F and PIC24H



NOTES:


IndexIndex

INDEXAAccumulator A, Accumulator B ........................................... 18Accumulator Access ........................................................... 73Accumulator Usage............................................................. 72Addressing Modes for Wd Destination Register ................. 85Addressing Modes for Ws Source Register ........................ 85Assigned Working Register Usage ..................................... 67

BByte Operations .................................................................. 54

CCode Examples

’Z’ Status bit Operation for 32-bit Addition .................. 66Base MAC Syntax....................................................... 75File Register Addressing............................................. 43File Register Addressing and WREG.......................... 43Frame Pointer Usage.................................................. 63Illegal Word Move Operations..................................... 58Immediate Addressing ................................................ 49Indirect Addressing with Effective Address Update .... 45Indirect Addressing with Register Offset..................... 46Legal Word Move Operations ..................................... 57MAC Accumulator WB Syntax .................................... 77MAC Prefetch Syntax.................................................. 76Move with Literal Offset Instructions ........................... 46MSC Instruction with Two Prefetches and Accumulator

Write Back .......................................................... 77Normalizing with FBCL ............................................... 81Register Direct Addressing ......................................... 44Sample Byte Math Operations .................................... 55Sample Byte Move Operations ................................... 54Scaling with FBCL....................................................... 80Stack Pointer Usage ................................................... 61Unsigned f and WREG Multiply (Legacy MULWF Instruc-

tion)..................................................................... 69Using 10-bit Literals for Byte Operands ...................... 59Using the Default Working Register WREG................ 68

Conditional Branch Instructions .......................................... 65Core Control Register ......................................................... 21

DData Addressing Mode Tree ............................................... 49Data Addressing Modes...................................................... 42DCOUNT Register .............................................................. 19Default Working Register (WREG) ............................... 17, 68Development Support ........................................................... 6DOEND Register................................................................. 19DOSTART Register ............................................................ 19DSP Accumulator Instructions ............................................ 78DSP Data Formats.............................................................. 70DSP MAC Indirect Addressing Modes ................................ 47DSP MAC Instructions ........................................................ 74dsPIC30F/33F Overview..................................................... 12

FFile Register Addressing..................................................... 42

IImmediate Addressing ........................................................ 48

Operands in the Instruction Set .................................. 48Implied DSP Operands ....................................................... 67

Implied Frame and Stack Pointer ....................................... 67Instruction Bit Map............................................................ 358Instruction Description Example ......................................... 88Instruction Descriptions ...................................................... 89

ADD (16-bit Signed Add to Accumulator) ................... 96ADD (Add Accumulators) ........................................... 95ADD (Add f to WREG) ................................................ 89ADD (Add Literal to Wn) ............................................. 90ADD (Add Wb to Short Literal) ................................... 91ADD (Add Wb to Ws).................................................. 93ADDC (Add f to WREG with Carry) ............................ 98ADDC (Add Literal to Wn with Carry) ......................... 99ADDC (Add Wb to Short Literal with Carry).............. 100ADDC (Add Wb to Ws with Carry)............................ 102AND (AND f and WREG).......................................... 104AND (AND Literal and Wd)....................................... 105AND (AND Wb and Short Literal) ............................. 106AND (AND Wb and Ws) ........................................... 107ASR (Arithmetic Shift Right by Short Literal) ............ 113ASR (Arithmetic Shift Right by Wns) ........................ 114ASR (Arithmetic Shift Right f) ................................... 109ASR (Arithmetic Shift Right Ws) ............................... 111BCLR (Bit Clear in Ws)............................................. 116BCLR.B (Bit Clear f) ................................................. 115BRA (Branch Unconditionally) .................................. 117BRA (Computed Branch).......................................... 118BRA C (Branch if Carry) ........................................... 119BRA GE (Branch if Signed Greater Than or Equal) . 121BRA GEU (Branch if Unsigned Greater Than or Equal).

122BRA GT (Branch if Signed Greater Than) ................ 123BRA GTU (Branch if Unsigned Greater Than) ......... 124BRA LE (Branch if Signed Less Than or Equal)....... 125BRA LEU (Branch if Unsigned Less Than or Equal) 126BRA LT (Branch if Signed Less Than) ..................... 127BRA LTU (Branch if Not Carry) ................................ 130BRA LTU (Branch if Unsigned Less Than)............... 128BRA N (Branch if Negative)...................................... 129BRA NN (Branch if Not Negative)............................. 131BRA NOV (Branch if Not Overflow) .......................... 132BRA NZ (Branch if Not Zero).................................... 133BRA OA (Branch if Overflow Accumulator A)........... 134BRA OB (Branch if Overflow Accumulator B)........... 135BRA OV (Branch if Overflow) ................................... 136BRA SA (Branch if Saturation Accumulator A) ......... 137BRA SB (Branch if Saturation Accumulator B) ......... 138BRA Z (Branch if Zero) ............................................. 139BSET (Bit Set f) ........................................................ 140BSET (Bit Set in Ws) ................................................ 141BSW (Bit Write in Ws) .............................................. 142BTG (Bit Toggle f)..................................................... 144BTG (Bit Toggle in Ws)............................................. 145BTSC (Bit Test f, Skip if Clear) ................................. 146BTSC (Bit Test Ws, Skip if Clear)............................. 148BTSS (Bit Test f, Skip if Set) .................................... 150BTSS (Bit Test Ws, Skip if Set) ................................ 151BTST (Bit Test f)....................................................... 153BTST (Bit Test in Ws)....................................... 154, 155BTSTS (Bit Test/Set f) .............................................. 157BTSTS (Bit Test/Set in Ws) ...................................... 158CALL (Call Indirect Subroutine)................................ 161CALL (Call Subroutine)............................................. 159CLR (Clear Accumulator, Prefetch Operands) ......... 165CLR (Clear f or WREG) ............................................ 163CLR (Clear Wd) ........................................................ 164



CLRWDT (Clear Watchdog Timer) ........................... 167COM (Complement f) ................................................ 168COM (Complement Ws)............................................ 169CP (Compare f with WREG, Set Status Flags) ......... 170CP (Compare Wb with lit5, Set Status Flags) ........... 171CP (Compare Wb with Ws, Set Status Flags) .......... 172CP0 (Compare f with 0x0, Set Status Flags) ............ 173CP0 (Compare Ws with 0x0, Set Status Flags) ........ 174CPB (Compare f with WREG using Borrow, Set Status

Flags) ................................................................ 175CPB (Compare Wb with lit5 using Borrow, Set Status

Flags) ................................................................ 176CPB (Compare Ws with Wb using Borrow, Set Status

Flags) ................................................................ 177CPSEQ (Compare Wb with Wn, Skip if Equal) ......... 179CPSGT (Signed Compare Wb with Wn, Skip if Greater

Than)................................................................. 180CPSLT (Signed Compare Wb with Wn, Skip if Less

Than)................................................................. 181CPSNE (Signed Compare Wb with Wn, Skip if Not

Equal)................................................................ 182DAW.B (Decimal Adjust Wn) .................................... 183DEC (Decrement f) ................................................... 184DEC (Decrement Ws) ............................................... 185DEC2 (Decrement f by 2).......................................... 186DEC2 (Decrement Ws by 2) ..................................... 187DISI (Disable Interrupts Temporarily) ....................... 188DIV.S (Signed Integer Divide) ................................... 189DIV.U (Unsigned Integer Divide)............................... 191DIVF (Fractional Divide)............................................ 193DO (Initialize Hardware Loop Literal) ........................ 195DO (Initialize Hardware Loop Wn) ............................ 197ED (Euclidean Distance, No Accumulate) ................ 199EDAC (Euclidean Distance) ...................................... 201EXCH (Exchange Wns and Wnd) ............................. 203FBCL (Find First Bit Change from Left) .................... 204FF1L (Find First One from Left) ................................ 206FF1R (Find First One from Right) ............................. 208GOTO (Unconditional Indirect Jump)........................ 211GOTO (Unconditional Jump) .................................... 210INC (Increment f) ...................................................... 212INC (Increment Ws) .................................................. 213INC2 (Increment f by 2)............................................. 214INC2 (Increment Ws by 2) ........................................ 215IOR (Inclusive OR f and WREG)............................... 216IOR (Inclusive OR Literal and Wn)............................ 217IOR (Inclusive OR Wb and Short Literal) .................. 218IOR (Inclusive OR Wb and Ws) ................................ 219LAC (Load Accumulator)........................................... 221LNK (Allocate Stack Frame) ..................................... 223LSR (Logical Shift Right by Short Literal) ................. 227LSR (Logical Shift Right by Wns).............................. 228LSR (Logical Shift Right f)......................................... 224LSR (Logical Shift Right Ws) .................................... 225MAC (Multiply and Accumulate)................................ 229MAC (Square and Accumulate) ................................ 231MOV (Move 16-bit Literal to Wn) .............................. 238MOV (Move f to Destination)..................................... 233MOV (Move f to Wnd) ............................................... 235MOV (Move Wns to [Wd with offset]) ........................ 240MOV (Move Wns to f) ............................................... 236MOV (Move WREG to f) ........................................... 234MOV (Move Ws to Wd) ............................................. 241MOV (Move Ws with offset to Wnd) .......................... 239MOV.B (Move 8-bit Literal to Wnd) ........................... 237MOV.D (Double-Word Move from Source to Wnd) ... 243

MOVSAC (Prefetch Operands and Store Accumulator) .245

MPY (Multiply Wm by Wn to Accumulator)............... 247MPY (Square to Accumulator) .................................. 249MPY.N (Multiply -Wm by Wn to Accumulator) .......... 251MSC (Multiply and Subtract from Accumulator)........ 253MUL (Integer Unsigned Multiply f and WREG)......... 255MUL.SS (Integer 16x16-bit Signed Multiply)............. 256MUL.SU (Integer 16x16-bit Signed-Unsigned Multiply) ..

260MUL.SU (Integer 16x16-bit Signed-Unsigned Short Liter-

al Multiply) ........................................................ 258MUL.US (Integer 16x16-bit Unsigned-Signed Multiply) ..

262MUL.UU (Integer 16x16-bit Unsigned Multiply) ........ 265MUL.UU (Integer 16x16-bit Unsigned Short Literal Multi-

ply).................................................................... 264NEG (Negate Accumulator) ...................................... 269NEG (Negate f) ......................................................... 267NEG (Negate Ws)..................................................... 268NOP (No Operation) ................................................. 270NOPR (No Operation)............................................... 271POP (Pop TOS to f) .................................................. 272POP (Pop TOS to Wd).............................................. 273POP.D (Double Pop TOS to Wnd/

Wnd+1) ............................................................. 274POP.S (Pop Shadow Registers)............................... 275PUSH (Push f to TOS).............................................. 276PUSH (Push Ws to TOS).......................................... 277PUSH.D (Double Push Wns/

Wns+1 to TOS)................................................. 278PUSH.S (Push Shadow Registers)........................... 279PWRSAV (Enter Power Saving Mode) ..................... 280RCALL (Computed Relative Call) ............................. 283RCALL (Relative Call)............................................... 281REPEAT (Repeat Next Instruction ’lit14’ Times) ...... 285REPEAT (Repeat Next Instruction Wn Times) ......... 286RESET (Reset) ......................................................... 288RETFIE (Return from Interrupt) ................................ 290RETLW (Return with Literal in Wn)........................... 291RETURN (Return)..................................................... 292RLC (Rotate Left f through Carry)............................. 293RLC (Rotate Left Ws through Carry) ........................ 294RLNC (Rotate Left f without Carry)........................... 296RLNC (Rotate Left Ws without Carry)....................... 297RRC (Rotate Right f through Carry).......................... 299RRC (Rotate Right Ws through Carry) ..................... 300RRNC (Rotate Right f without Carry)........................ 302RRNC (Rotate Right Ws without Carry).................... 303SAC (Store Accumulator) ......................................... 305SAC.R (Store Rounded Accumulator) ...................... 307SE (Sign-Extend Ws)................................................ 309SETM (Set f or WREG)............................................. 310SETM (Set Ws)......................................................... 311SFTAC (Arithmetic Shift Accumulator by Slit5)......... 312SFTAC (Arithmetic Shift Accumulator by Wb) .......... 313SL (Shift Left by Short Literal)................................... 317SL (Shift Left by Wns)............................................... 318SL (Shift Left f).......................................................... 314SL (Shift Left Ws)...................................................... 315SUB (Subtract Accumulators)................................... 324SUB (Subtract Literal from Wn) ................................ 320SUB (Subtract Short Literal from Wb)....................... 321SUB (Subtract WREG from f) ................................... 319SUB (Subtract Ws from Wb)..................................... 322SUBB (Subtract Short Literal from Wb with Borrow) 327SUBB (Subtract Wn from Literal with Borrow) .......... 326


IndexIndex

SUBB (Subtract WREG and Carry bit from f) ........... 325SUBB (Subtract Ws from Wb with Borrow)............... 329SUBBR (Subtract f from WREG with Borrow)........... 331SUBBR (Subtract Wb from Short Literal with Borrow) ....

332SUBBR (Subtract Wb from Ws with Borrow) ............ 334SUBR (Subtract f from WREG)................................. 336SUBR (Subtract Wb from Short Literal) .................... 337SUBR (Subtract Wb from Ws) .................................. 338SWAP (Byte or Nibble Swap Wn) ............................. 340TBLRDH (Table Read High) ..................................... 341TBLRDL (Table Read Low)....................................... 343TBLWTH (Table Write High) ..................................... 345TBLWTL (Table Write Low) ...................................... 347ULNK (De-allocate Stack Frame) ............................. 349XOR (Exclusive OR f and WREG) ............................ 350XOR (Exclusive OR Literal and Wn) ......................... 351XOR (Exclusive OR Wb and Short Literal) ............... 352XOR (Exclusive OR Wb and Ws).............................. 353ZE (Zero-Extend Wn)................................................ 355

Instruction Encoding Field Descriptors Introduction............ 84Instruction Set Overview ..................................................... 30

Bit Instructions ............................................................ 36Compare/Skip Instructions.......................................... 37Control Instructions ..................................................... 39DSP Instructions ......................................................... 39dsPIC30F/33F Instruction Groups .............................. 30Logic Instructions ........................................................ 34Math Instructions......................................................... 32Move Instructions........................................................ 32Program Flow Instructions .......................................... 38Rotate/Shift Instructions.............................................. 35Shadow/Stack Instructions.......................................... 39

Instruction Set Summary Table......................................... 360Instruction Set Symbols ........................................................ 8

(text).............................................................................. 8[text] .............................................................................. 8{ }................................................................................... 8{label:} ........................................................................... 8#text .............................................................................. 8<n:m>............................................................................ 8Acc ................................................................................ 8AWB.............................................................................. 8bit4 ................................................................................ 8Expr............................................................................... 8f ..................................................................................... 8lit1 ................................................................................. 8lit10 ............................................................................... 8lit14 ............................................................................... 8lit16 ............................................................................... 8lit23 ............................................................................... 8lit4 ................................................................................. 8lit5 ................................................................................. 8lit8 ................................................................................. 8Slit10 ............................................................................. 8Slit16 ............................................................................. 8Slit4 ............................................................................... 8Slit5 ............................................................................... 8TOS............................................................................... 8Wb................................................................................. 8Wd................................................................................. 8Wm, Wn ........................................................................ 8Wm*Wm........................................................................ 8Wm*Wn......................................................................... 8Wn................................................................................. 8Wnd............................................................................... 8Wns............................................................................... 8

WREG .......................................................................... 8Ws ................................................................................ 8Wx ................................................................................ 8Wxd .............................................................................. 8Wy ................................................................................ 8Wyd .............................................................................. 8

Instruction Stalls ................................................................. 52DO/REPEAT Loops .................................................... 53Exceptions .................................................................. 53Instructions that Change Program Flow ..................... 53PSV ............................................................................ 53RAW Dependency Detection...................................... 52

Instruction Symbols ............................................................ 84Integer and Fractional Data ................................................ 70

Representation ........................................................... 71Interrupt Priority Level......................................................... 21Introduction........................................................................... 6

MMAC

Operations .................................................................. 75Prefetch Register Updates ......................................... 74Prefetches .................................................................. 74Syntax......................................................................... 75Write Back .................................................................. 75

MAC Accumulator Write Back Selection............................. 87MAC or MPY Source Operands (Different Working Register)

87MAC or MPY Source Operands (Same Working Register) 87Manual Objective.................................................................. 6Modulo and Bit-Reversed Addressing Modes .................... 47Multi-Cycle Instructions....................................................... 31Multi-Word Instructions ....................................................... 31

NNormalizing the Accumulator with the FBCL Instruction..... 81

OOffset Addressing Modes for Wd Destination Register (with

Register Offset) .......................................................... 85Offset Addressing Modes for Ws Source Register (with Reg-

ister Offset) ................................................................. 85

PPIC® Microcontroller Compatibility ..................................... 68PRODH

PRODL Register Pair ................................................. 68Program Addressing Modes ............................................... 51

Methods of Modifying Flow......................................... 51Program Counter ................................................................ 18Programmer’s Model .......................................................... 14

Diagram ...................................................................... 15Register Descriptions ................................................. 16

PSVPAG Register............................................................... 18



RRCOUNT Register .............................................................. 19Register Direct Addressing ................................................. 43Register Indirect Addressing ............................................... 44

Modes ......................................................................... 44Register Indirect Addressing and the Instruction Set .......... 47Registers

CORCON (Core Control) Register ........................ 26, 27SR (CPU Status) ......................................................... 23SR (Status) Register ................................................... 24

Related Documents............................................................... 9

SScaling Data with the FBCL Instruction............................... 79

Scaling Examples ....................................................... 79Shadow Registers ............................................................... 22

Automatic Usage......................................................... 22Software Stack Frame Pointer ...................................... 18, 62

Example ...................................................................... 63Overflow...................................................................... 64Underflow.................................................................... 64

Software Stack Pointer.................................................. 18, 60Example ...................................................................... 61

Stack Pointer Limit Register (SPLIM).................................. 18Status Register.................................................................... 19

DSP ALU Status Bits .................................................. 20Loop Status Bits.......................................................... 20MCU ALU Status Bits.................................................. 19

Style and Symbol Conventions ............................................. 7Document Conventions................................................. 7

TTBLPAG Register ............................................................... 18Third Party Documentation ................................................... 9

UUsing 10-bit Literal Operands ............................................. 59

10-bit Literal Coding.................................................... 59

WWord Move Operations....................................................... 56

Data Alignment in Memory ......................................... 56Working Register Array....................................................... 17

XX Data Space Prefetch Destination .................................... 86X Data Space Prefetch Operation ...................................... 86

YY Data Space Prefetch Destination .................................... 87Y Data Space Prefetch Operation ...................................... 86

ZZ Status Bit ......................................................................... 66


IndexIndex

NOTES:



AMERICASCorporate Office2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 480-792-7200 Fax: 480-792-7277Technical Support: http://support.microchip.comWeb Address: www.microchip.comAtlantaDuluth, GA Tel: 678-957-9614 Fax: 678-957-1455BostonWestborough, MA Tel: 774-760-0087 Fax: 774-760-0088ChicagoItasca, IL Tel: 630-285-0071 Fax: 630-285-0075ClevelandIndependence, OH Tel: 216-447-0464 Fax: 216-447-0643DallasAddison, TX Tel: 972-818-7423 Fax: 972-818-2924DetroitFarmington Hills, MI Tel: 248-538-2250Fax: 248-538-2260KokomoKokomo, IN Tel: 765-864-8360Fax: 765-864-8387Los AngelesMission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608Santa ClaraSanta Clara, CA Tel: 408-961-6444Fax: 408-961-6445TorontoMississauga, Ontario, CanadaTel: 905-673-0699 Fax: 905-673-6509

ASIA/PACIFICAsia Pacific OfficeSuites 3707-14, 37th FloorTower 6, The GatewayHarbour City, KowloonHong KongTel: 852-2401-1200Fax: 852-2401-3431Australia - SydneyTel: 61-2-9868-6733Fax: 61-2-9868-6755China - BeijingTel: 86-10-8528-2100 Fax: 86-10-8528-2104China - ChengduTel: 86-28-8665-5511Fax: 86-28-8665-7889China - Hong Kong SARTel: 852-2401-1200 Fax: 852-2401-3431China - NanjingTel: 86-25-8473-2460Fax: 86-25-8473-2470China - QingdaoTel: 86-532-8502-7355Fax: 86-532-8502-7205China - ShanghaiTel: 86-21-5407-5533 Fax: 86-21-5407-5066China - ShenyangTel: 86-24-2334-2829Fax: 86-24-2334-2393China - ShenzhenTel: 86-755-8203-2660 Fax: 86-755-8203-1760China - WuhanTel: 86-27-5980-5300Fax: 86-27-5980-5118China - XiamenTel: 86-592-2388138 Fax: 86-592-2388130China - XianTel: 86-29-8833-7252Fax: 86-29-8833-7256China - ZhuhaiTel: 86-756-3210040 Fax: 86-756-3210049

ASIA/PACIFICIndia - BangaloreTel: 91-80-3090-4444 Fax: 91-80-3090-4080India - New DelhiTel: 91-11-4160-8631Fax: 91-11-4160-8632India - PuneTel: 91-20-2566-1512Fax: 91-20-2566-1513Japan - YokohamaTel: 81-45-471- 6166 Fax: 81-45-471-6122Korea - DaeguTel: 82-53-744-4301Fax: 82-53-744-4302Korea - SeoulTel: 82-2-554-7200Fax: 82-2-558-5932 or 82-2-558-5934Malaysia - Kuala LumpurTel: 60-3-6201-9857Fax: 60-3-6201-9859Malaysia - PenangTel: 60-4-227-8870Fax: 60-4-227-4068Philippines - ManilaTel: 63-2-634-9065Fax: 63-2-634-9069SingaporeTel: 65-6334-8870Fax: 65-6334-8850Taiwan - Hsin ChuTel: 886-3-6578-300Fax: 886-3-6578-370Taiwan - KaohsiungTel: 886-7-536-4818Fax: 886-7-536-4803Taiwan - TaipeiTel: 886-2-2500-6610 Fax: 886-2-2508-0102Thailand - BangkokTel: 66-2-694-1351Fax: 66-2-694-1350

EUROPEAustria - WelsTel: 43-7242-2244-39Fax: 43-7242-2244-393Denmark - CopenhagenTel: 45-4450-2828 Fax: 45-4485-2829France - ParisTel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79Germany - MunichTel: 49-89-627-144-0 Fax: 49-89-627-144-44Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781Netherlands - DrunenTel: 31-416-690399 Fax: 31-416-690340Spain - MadridTel: 34-91-708-08-90Fax: 34-91-708-08-91UK - WokinghamTel: 44-118-921-5869Fax: 44-118-921-5820

Worldwide Sales and Service

03/26/09

http://support.microchip.com


Reference 1

Documents

Transcript of Reference 1