I

High

I

High Substrate

Mirror

In

I

Low

I

Low

Mirror

Out

Mirror

Common

1 2

1 2

8 7 6 5

1 2 3 4

100µA 100µA

Product

Folder

Order

Now

Technical

Documents

Tools &

Software

Support &Community

ReferenceDesign

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

REF200SBVS020C –SEPTEMBER 2000–REVISED FEBRUARY 2020

REF200 Dual Current Source and Current Sink

1

1 Features1• Completely floating: no power supply or ground

connections• High accuracy: 100 µA ±0.5%• Low temperature coefficient: ±25 ppm/°C• Wide voltage compliance: 2.5 V to 40 V• Includes current mirror

2 Applications• Sensor excitation• Biasing circuitry• Offsetting current loops• Low voltage references• Charge-pump circuitry• Hybrid microcircuits

3 DescriptionThe REF200 combines three circuit building-blockson a single monolithic chip: two 100-µA currentsources and a current mirror. The sections aredielectrically isolated, making them completelyindependent. Also, because the current sources aretwo-terminal devices, they can be used equally wellas current sinks. The performance of each section isindividually measured and laser-trimmed to achievehigh accuracy at low cost.

The sections can be pin-strapped for currents of 50µA, 100 µA, 200 µA, 300 µA, or 400 µA. Externalcircuitry can obtain virtually any current. These andmany other circuit techniques are shown in theApplication Information section of this data sheet.

The REF200 is available in an SOIC package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)REF200 SOIC (8) 3.91 mm × 4.90 mm

(1) For all available packages, see the package addendum at theend of the data sheet.

Functional Block Diagram

2

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Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Pin Configuration and Functions ......................... 36 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 46.2 ESD Ratings ............................................................ 46.3 Recommended Operating Conditions....................... 46.4 Electrical Characteristics........................................... 46.5 Typical Characteristics .............................................. 5

7 Detailed Description .............................................. 77.1 Overview ................................................................... 77.2 Functional Block Diagram ......................................... 77.3 Feature Description................................................... 77.4 Device Functional Modes.......................................... 8

8 Application and Implementation .......................... 98.1 Application Information.............................................. 98.2 Typical Application ................................................... 98.3 System Examples ................................................... 12

9 Power Supply Recommendations ...................... 2510 Layout................................................................... 25

10.1 Layout Guidelines ................................................. 2510.2 Layout Example .................................................... 25

11 Device and Documentation Support ................. 2611.1 Documentation Support ....................................... 2611.2 Receiving Notification of Documentation Updates 2611.3 Support Resources ............................................... 2611.4 Trademarks ........................................................... 2611.5 Electrostatic Discharge Caution............................ 2611.6 Glossary ................................................................ 26

12 Mechanical, Packaging, and OrderableInformation ........................................................... 26

4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (July 2015) to Revision C Page

• Changed storage temperature................................................................................................................................................ 4

Changes from Revision A (August 2013) to Revision B Page

• Changed multiple instances of "mA" in data sheet back to "µA" (typo) ................................................................................. 1

Changes from Original (September 2000) to Revision A Page

• Added ESD Ratings and Recommended Operating Conditions tables, and Feature Description, Device FunctionalModes, Application and Implementation, Power Supply Recommendations, Layout, Device and DocumentationSupport, and Mechanical, Packaging, and Orderable Information sections........................................................................... 1

I

I

Substrate

Mirror Input

Low

Low

Mirror Common

Mirror Output

1

2

3

4

8

7

6

5

1

2

High

High

1

2

I

I

3

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5 Pin Configuration and Functions

D Package8-Pin SOICTop View

Pin FunctionsPIN

DESCRIPTIONNAME NO.I1 Low 1 Current source 1 low terminalI2 Low 2 Current source 2 low terminalMirror Common 3 Current mirror common terminalMirror Output 4 Current mirror output terminalMirror Input 5 Current mirror input terminalSubstrate 6 Substrate (Usually connected to most negative potential in the system)I2 High 7 Current source 2 high terminalI1 High 8 Current source 1 high terminal

4

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNITApplied voltage –6 40 VReverse current –350 µAVoltage between any two sections ±80 VOperating temperature –40 85 °C

Tstg Storage temperature –55 150 °C

(1) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing withless than 250-V CDM is possible with the necessary precautions.

6.2 ESD RatingsVALUE UNIT

V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (1) ±750 V

6.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNITVCOMP Compliance voltage 2.5 40 VTA Specified temperature range –25 85 °C

6.4 Electrical Characteristicsat TA = 25°C, VS = 15 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITCURRENT SOURCES

Current accuracy ±0.25% ±1%Current match ±0.25% ±1%Temperature drift Specified temperature range 25 ppm/°C

Output impedance2.5 V to 40 V 20 100

MΩ3.5 V to 30 V 200 500

NoiseBW = 0.1 Hz to 10 Hz 1 nAp-pf = 10 kHz 20 pA/√Hz

Voltage compliance (1%) TMIN to TMAX See Typical CharacteristicsCapacitance 10 pF

CURRENT MIRROR – I = 100 µA unless otherwise notedGain 0.995 1 1.005Temperature drift 25 ppm/°CImpedance (output) 2 V to 40 V 40 100 MΩ

Nonlinearity I = 0 µA to 250 µA 0.05%Input voltage 1.4 VOutput compliance voltage See Typical CharacteristicsFrequency response (–3 dB) Transfer 5 MHz

1000

900

800

700

600

500

400

300

200

100

Re

ve

rse

Cu

rre

nt

(µA

)

0

0 –2 –4 –6 –8 –10 –12

Reverse Voltage (V)

Reverse Voltage

Circuit Model

12kW 7V

5kW

Safe Reverse Current

Safe Reverse Voltage

101

100.8

100.6

100.4

100.2

100

99.8

99.6

99.4

99.2

Curr

ent (µ

A)

99

0 5 10 15 20 25 30 35 40

Voltage (V)

0

100.5

100.4

100.3

100.2

100.1

100

99.9

99.8

99.7

99.6

99.5

Voltage (V)

1 2 3 4 5

Curr

ent (µ

A)

–55°C

25°C

125°C

100.1

100

99.9

99.8

99.7

99.6

99.5

–25–50 25 7550 1251000

Temperature (°C)

Curr

ent (µ

A)

85°CDrift specified by

“box method”

(See text)

600

500

400

300

200

100

0

50 10

Temperature Drift (ppm/°C)

Quantit

y (

Units

)

Distribution of three

production lots —

1284 Current Sources.

2015 25 3530 40 5045 55 6560

2 5

117

30 15 6 0 1 1

501

454

8666

5

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6.5 Typical Characteristicsat TA = 25°C, VS = 15 V (unless otherwise noted)

Figure 1. Current Source Typical Drift vs Temperature Figure 2. Current Source Temperature Drift Distribution

Figure 3. Current Source Output Current vs Voltage Figure 4. Current Source Output Current vs Voltage

Figure 5. Current Source Current Noise (0.1 Hz to 10 Hz) Figure 6. Current Source Reverse Current vs ReverseVoltage

Inp

ut

Vo

lta

ge

(V

)

0

1µA 10µA 100µA 1mA 10mA

Current

4

3

2

1

Input Voltage

Output

Compliance

Voltage

5

4

3

2

1

0

–1

–2

–3

–4

Err

or

(%)

–5

10µA 100µA 1mA

Mirror Current (A)

V =

1.25V

V = 1V

V = 1.5V

O

O

O

0

0.1

0.08

0.06

0.04

0.02

0

–0.02

–0.04

–0.06

–0.08

–0.01

Current (µA)

50 100 150 200 250

No

nlin

ea

rity

(%

of

25

0µ

A)

Data from Three

Representative Units

(Least-square fit)

6

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Typical Characteristics (continued)at TA = 25°C, VS = 15 V (unless otherwise noted)

Figure 7. Mirror Gain Error vs Current Figure 8. Mirror Transfer Nonlinearity

Figure 9. Mirror Input Voltage and Output Compliance Voltage vs Current

I

High

I

High Substrate

Mirror

In

I

Low

I

Low

Mirror

Out

Mirror

Common

1 2

1 2

8 7 6 5

1 2 3 4

100µA 100µA

7

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7 Detailed Description

7.1 OverviewThe REF200 device combines three circuit building-blocks on a single monolithic chip—two 100-µA currentsources and a current mirror. The sections are dielectrically isolated, making them completely independent. Also,because the current sources are two terminal devices, they can be used equally well as current sinks. Theperformance of each section is individually measured and laser-trimmed to achieve high accuracy at low cost.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Temperature DriftDrift performance is specified by the box method, as illustrated in Figure 1. The upper and lower currentextremes measured over temperature define the top and bottom of the box. The sides are determined by thespecified temperature range of the device. The drift of the unit is the slope of the diagonal, typically 25 ppm/°Cfrom –25°C to +85°C.

(Substrate)

Current

Source

(1 of 2)

4kΩ

8X

8,7

5kΩ

1kΩ

1,2

6

3

5 4

1kΩ

12kΩ

Current

Mirror

8

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7.4 Device Functional ModesThe three circuit sections of the REF200 are electrically isolated from one another, using a dielectrically-isolatedfabrication process. A substrate connection is provided (pin 6), which is isolated from all circuitry. This pin shouldbe connected to a defined circuit potential to assure rated DC performance. The preferred connection is to themost negative constant potential in the system. In most analog systems, this would be –VS. For best acperformance, leave pin 6 open and leave unused sections unconnected. Figure 10 shows the simplified circuitdiagram of the REF200.

Figure 10. Simplified Circuit Diagram

100µA

REF200

+5V

100µA

3 WireRTD

+5V

RT

D

R3 78.7

INA326

Vout

R2

69

8k

C2

22

0p

R1

2k R1

R2

+

±

9

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8 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

8.1 Application InformationApplications for the REF200 are limitless. Application Bulletin AB-165 (SBOA046) shows additional REF200circuits as well as other related current source techniques. In this section, a collection of circuits are shown toillustrate some techniques.

If the current sources are subjected to reverse voltage, a protection diode may be required. A reverse voltagecircuit model of the REF200 is shown in Figure 6. If reverse voltage is limited to less than 6 V or reverse currentis limited to less than 350 µA, then no protection circuitry is required. A parallel diode (see (a) in Figure 17)protects the device by limiting the reverse voltage across the current source to approximately 0.7 V. In someapplications, a series diode may be preferable (see (b) in Figure 17), because it allows no reverse current. Thisconfiguration, however, reduces the compliance voltage range by one diode drop.

8.2 Typical ApplicationFigure 11 shows the schematic of a circuit that translates RTD resistance to a voltage level convenient for anADC input. The REF200 precision current reference provides excitation and an instrumentation amplifier scalesthe signal. The design also uses a 3-wire RTD configuration to minimize errors due to wiring resistance.

Figure 11. RTD Resistance to Voltage Converter Schematic

100µA

REF200

+5V

100µA

3 WireRTD

+5V

RT

D

R3 78.7

INA326

VOUT

R2

69

8k

C2

22

0p

R1

2k R1

R1

80.3@-50C

8.03mV+

+

160µ V0.111V

G = 2(R2/R1)- 7.87mV +

+

200µA

- - -

10

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Typical Application (continued)8.2.1 Design RequirementsThe design requirements are as follows:• Supply Voltage: 5 V• RTD temperature range: –50°C to +125°C• RTD resistance range 80.3 Ω to 147.9 Ω• Output: 0.1 V to 4.9 V

The design goals and performance are summarized in Table 1. Figure 15 depicts the measured transfer functionof the design.

Table 1. Comparison of Design Goals, Calculations, Simulation, and Measured PerformanceVOUT RTD GOAL CALCULATED SIMULATED MEASURED

VOUT maximum scale 80.3 Ω 0.1 V 0.112 V 0.117 V 0.11 3 VVOUT minimum scale 142.9 Ω 4.9 V 4.83 V 4.82 V 4.862 V

8.2.2 Detailed Design ProcedureFigure 12 and Figure 13 shows the schematic of the RTD amplifier for minimum and maximum output conditions.This circuit was designed for a –50°C to 150°C RTD temperature range. At –50°C the RTD resistance is 80.3 Ωand the voltage across it is 8.03 mV (VRTD = (100 μA) (80.3 Ω), see Figure 2). Notice that R3 develops a voltagedrop that opposes the RTD drop. The drop across R3 is used to shift amplifiers input differential voltage to aminimum level. The output is the differential input multiplied by the gain (Vout = 698 ∙ 160 μV = 0.111 V). At150°C, the RTD resistance is 148 Ω and the voltage across it is 14. 8 mV (VRTD = (100 μA × 148 Ω ). Thisproduces a differential input of 6.93 mV and an output voltage of 4.84 V (VOUT = 698 ∙ 6.93 mV = 4.84 V , seeFigure 13). For more detailed design procedures and results, refer to the reference guide, RTD to VoltageReference Design Using Instrumentation Amplifier and Current Reference (TIDU969).

Figure 12. RTD Amplifier with Minimum Output Condition

100µA

REF200

+5V

100µA +5V

RT

D

R3 78.7

INA326

VOUT

R2

69

8k

C2

22

0p

R1

2k R1

R1148@

150C14.8mV

+

4.84V

+2mV-

+

-

PCB

3 WireRTD

Large Lead R

300m

10

-1mV+

-14.8mV

+

-10

- 1mV+

10

100µA

REF200

+5V

100µA

3 WireRTD

+5V

RT

D

R3 78.7

INA326

VOUT

R2

69

8k

C2

22

0p

R1

2k R1

R1

148@ 150C 14.8mV

+

+

6.93mV4.84V

G = 2(R2/R1)- 7.87mV +

200µA

+

- - -

11

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Figure 13. RTD Amplifier with Maximum Output Condition

8.2.2.1 Lead Resistance Cancelation (3-Wire RTD)Figure 14 shows the 3-wire RTD configuration can be used to cancel lead resistance. The resistance in eachlead must be equal to cancel the error. Also, the two current sources in the REF200 must be equal. Notice thatthe voltage developed on the two top leads of the RTD are equal and opposite polarity so that the amplifiersinput is only from the RTD voltage. In this example, the RTD drop is 14.8 mV and the leads each have 1 mV.Notice that the 1 mV drops cancel. Finally, notice that the voltage on the 3rd lead (2 mV) creates a small shift inthe common mode voltage. In some applications, a larger resistor is intentionally added to shift the common-mode voltage. However, the INA326 has a rail-to-rail common mode range, so it can accept common-modevoltages near ground.

Figure 14. 3-Wire RTD Configuration Cancels Lead Resistance

–VS

+VS

100µA

IOUT

100µA

50µA45

3

In Out

Com

Mirror

100µA

Bidirectional

Current Source

D4 D2

D D31

D2

D1100µA

100µA

NOTE: All diodes = 1N4148.

Bidirectional

Current Source

(a) (b) (c) (d)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

80 90 100 110 120 130 140 150

Vo

ut (

V)

RTD Resistance C001

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

80 100 120 140 160

Outp

ut

Err

or

(%)

RTD Resistance ()

Error (0

Error (10

C002

12

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8.2.3 Application Curves

Figure 15. RTD to Vout Transfer Function Figure 16. Measured Error vs RTD Resistance

8.3 System Examples

Figure 17. Reverse Voltage Protection

Figure 18. 50-µA Current Source

101

100

99

0 10 20 30 40 50 60 70 80

Applied Voltage (V)

Provides 2X Higher Compliance Voltage

SERIES-CONNECTED CURRENT SOURCES

CURRENT vs APPLIED VOLTAGE

Curr

ent (µ

A)

100µA

100µA

High

Low100µA/200µA

45

3

In Out

Com

Mirror

SCompliance to –V + 1.5V

+VS

100µA100µA

S–V

(b)

50 µA

100 µA

45

3

In Out

Com

Mirror

–VS

100 kΩ

50 µA

100 µA

45

3

In Out

Com

Mirror

(c)

Compliance to

–V + 5.1 VS

+VS

–VS

5.1 V

1N4689

27 kΩ

0.01 µF

100 µA

45

3

In Out

Com

Mirror

(a)

–VS

Compliance to

–V + 5 VS

+VS

100 µA50 µA

Compliance to

Ground

300µA

100µA

45

3

In Out

Com

Mirror

100µA

Compliance = 4V

(b)

400µA

100µA

45

3

In Out

Com

Mirror

100µA

Compliance = 4V

(c)(a)

200µA

100µA 100µA

13

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System Examples (continued)

Figure 19. 200-µA, 300-µA, and 400-µA Floating Current Sources

Figure 20. 50-µA Current Sinks

Figure 21. Improved Low-Voltage Compliance Figure 22. 100-µA Current Source—80-V Compliance

100µA

100µA

± ±

40kΩ

40kΩ 0.01µF

0.01µF

1N41481N4148

1N41481N4148

(e) Bidirectional 200µA

cascoded current source.

100µA

100µA40kΩ

40kΩ 0.01µF

0.01µF

(d) Floating 200µA cascoded

current source.

100µA

Load

–VS

+VS

(a) Compliance approximate

to Gnd. HV compliance

limited by FET breakdown.

100µA

Load

+VS

(b) Compliance to +V – 5V.

High

Low

100µA

–VS

33kΩ0.01µF

S

100µA

Load

+VS

(c)

–VS

27kΩ

5.1V

1N4689

NOTES: (1) FET cascoded current sources offer improved output impedance and high frequency operation. Circuit in (b)

also provides improved PSRR. (2) For current sinks (Circuits (a) and (b) only), invert circuits and use “N” channel JFETS.

14

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System Examples (continued)

Figure 23. FET Cascode Circuits

To

Other

Amps

Op Amp

V

R

+V

NOTE: (1) For N Op Amps, use Potentiometer Resistance = N • 100 .Ω

100µA

51Ω

51Ω

S

IN

B

OUT

AR

V

–V

Using Standard Potentiometer

S

V = V (–R /R )

Offset Adjustment Range = ±5mVOUT IN B A

To

Other

Amps

Op Amp

V

R

+V

100µA

S

IN

B

OUT

AR

V

–V

Using Bourns Op Amp Trimpot

S

V = –V (R /R )

Offset Adjustment Range = ±5mVOUT IN B A

(1)

100Ω

Bourns Trimpot®

(1)

®

2k Linear

100µA

Ω

100µA

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System Examples (continued)

Figure 24. Operational Amplifier Offset Adjustment Circuits

R

100 µA

Reference

–V

100 µA

S

R2

0.01 µF

R

(N • R )2

1

I = N • 100 µAOUT

(1)

R

(N • R )2

1

I = N • 100 µAOUT

(1)

100 µA

0.01 µF

R2

+VS

+V

100 µA

S

OPA602

0.01 µF NR

I = (N +1) 100 µAO

R0.01 µF NR

I = (N +1) 100 µAO

R

100 µA

OPA602

0.01 µF NR

I = (N +1) 100 µAO

10 pF

(a) (b)

(d)(c)

(e)

–VS

OPA602

R NR IOUT

1 kΩ 4 kΩ 500 Aμ

1 kΩ 9 kΩ 1 mA

100 kΩ 9.9 kΩ 10 mA

EXAMPLES

FEATURES:

(1) Zero volts shunt compliance.

(2) Adjustable only to values above

reference value.

NOTE:

Current source/sink swing to the

Load Return rail is limited only

by the op amp's input common

mode range and output swing

capability. Voltage drop across R

can be tailored for any amplifier to

allow swing to zero volts from rail.

NOTE: (1) OPA602 or OPA128

EXAMPLES

R R I1 2 OUT

100 Ω 10 MΩ 1 nA

10 kΩ 1 MΩ 1 Aμ

10 kΩ 1 kΩ 1 mA

Use OPA128

I = 100 A (N + 1). Compliance » 3.5 VO

μ

with 0.1 V across R. Max I limited by FET.O

For I = 1 A, R = 0.1 , NR = 1 k .O

Ω Ω

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System Examples (continued)

Figure 25. Adjustable Current Sources

1N41481N4148

1N41481N4148

Bidirectional

Current Source1/2

REF200

OPA602

R

C

Triangle Output

Square Output

2 Vp-p

2 Vp-p

10 kΩ

Frequency = 1/4RC (Hz)

Frequency = 25/C (Hz)

(C is in µF and R = 10 k )Ω

7

V = Gain • 200 µA • RTDΔOUT

A B

O

C

I

–VS

+VS

RTDCable Shield

200-µA

Reference

Current

200-µA

Compensation

Current

REF200

1

ROFFSET

INA110

Instrumentation Amplifier

2 3 4

8 6 5

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System Examples (continued)

Figure 26. RTD Excitation With Three-Wire Lead Resistance Compensation

Figure 27. Precision Triangle Waveform Generator

–15 V

100 µA

0.1 µF

Siliconix

J109

50kΩ

IOUTFor current source,

invert circuitry and

use P-Channel FET.

100 N

1/4 OPA404

100 µA + Bridge (1)

VIN = 10 V: 100% Duty Cycle

12 Vp-p

Duty Cycle Out

C

V IN

100 µA + Bridge (1)

1/4 OPA404

1/4

OPA404

60 k VIN = 0 V: 50% Duty Cycle

VIN = ±10 V: 0% Duty Cycle

¦10 V VIN 10 V

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System Examples (continued)

(1) See Figure 27.

Figure 28. Precision Duty-Cycle Modulator

Figure 29. Low Noise Current Sink

27 kΩ

In OutMirror

Com

20 kΩ0.01 µF

0.01 µF

100 µA

100 µA

High

300 µA

2N5116

2N4340

5 4

3

300 µA

Low

(a) Regulation (15 V to 30 V = 0.00003%/V (10 GW)

In OutMirror

Com

20 kΩ0.01 µF

100 µA

High

400 µA

2N5116

2N4340

5 4

3

400 µA

Low

(a) Regulation (15 V to 30 V = 0.000025%/V (10 GW)

100 µA

–15 V

100 µA

0.1 µF

Siliconix

J109

50 kΩ

IOUT

For current source,

invert circuitry and

use P-Channel FET.

50 kΩ0.1 µF

100 µA

19

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System Examples (continued)

Figure 30. Low Noise Current Sink With Compliance Below Ground

Figure 31. Floating 300-µA and 400-µA Cascoded Current Sources

Compliance4 V to 30 V

High

25 mA

100 Ω

100 Aμ

+VS

40.2 Ω10 kΩ

Low

–VS

NOTE: Each amplifier 1/4 LM324Op amp power supplies are derivedwithin the circuitry, and this quiescentcurrent is included in the 25 mA.

100 Ω

100 Ω

100 Ω

10 kΩ

10 kΩ

OPA602

C

100 µA

–VS

+VS

V = –VI

100 µA

VI

V Rate Limit = 100 µA/CO

Diodes: 1N4148

or PWS740-3

Diode Bridge for

reduced V .OS

O

20

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System Examples (continued)

Figure 32. Rate Limiter

Figure 33. 25-mA Floating Current Source

–10 –5 +5 +10

–10

–5

+5

+10

OPA602

100 µA

1N4148

1N4148

R

(50 kΩ)

VI

R

(50 kΩ)

+15 V

10 pF

VO

OPA602

1N4148

1N4148

R

(50 kΩ)

VI

R

(50 kΩ)

10 pF

VO

100 µA

–15 V

–10 –5 +5 +10

–10

–5

+5

+10

For V > –5 V: V = 0

For V < –5 V: V = –V – 5 V

(Dead to 100 µA • R)

O

O

I

I I

For V < 5 V: V = 0

For V > 5 V: V = 5 V – V

(Dead to –100 µA • R)

O

O

I

I I

OV

OV

VI

VI

21

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System Examples (continued)

Figure 34. Dead-Band Circuit

100 µA

1 Ω

+V

V = 100 µV

S

O

OPA602

100 µA

1N4148

1N4148

R

(50 kΩ)

R

(50 kΩ)

+15 V

10 pF

OPA602

1N4148

1N4148

R

(50 kΩ)

VI

R

(50 kΩ)

10 pF

100 µA

–15 V

–10 –5 +5 +10

–10

–5

+5

+10

For V > 5 V: V = V – 5 V

For V < –5 V: V = V + 5 V

(Dead to ±100 µA • R)

O

O

I

I I

OV

VI

I

OPA602

VO

10 kΩ

10 kΩ

10 kΩ

22

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System Examples (continued)

Figure 35. Double Dead-Band Circuit

Figure 36. Low-Voltage Reference

R

(50 kΩ)

OPA121

100 µF

VO

OPA121

V I

100 µA

1 kΩ

1N4148

V = V (V < 5 V)

V = 5 V (V > 5 V)

(V = 100 µA • R)

O

O

I I

I

LIMIT

–10 –5 +5 +10

–10

–5

+5

+10OV

VI

+7.5 V (R = 75 kΩ)

+5 V (R = 50 kΩ)

+2.5 V (R = 25 kΩ)

100 µA

with bridge(1)

OPA121

100 µF

VO

OPA121

V I

R

(50 k )Ω

1 kΩ

V = V (–5 V < V < 5 V)

V = 5 V (V > 5 V)

V = –5 V (V < –5 V)

(Bound = 100 µA • R)

O

O

O

I I

I

I

–10 –5 +5 +10

–10

–5

+5

+10OV

VI

+7.5 V (R = 75 k )Ω

+5 V (R = 50 k )Ω

+2.5 V (R = 25 k )Ω

–2.5 V (R = 25 k )Ω

+5 V (R = 50 k )Ω

+7.5 V (R = 75 k )Ω

100 µA

10 kΩ

+V

V = 1 V

S

OOPA602

0.01 µF

23

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System Examples (continued)

Figure 37. Voltage Reference

(1) See Figure 17.

Figure 38. Bipolar Limiting Circuit

Figure 39. Limiting Circuit

100µA

V = +In – (–In)

100µA

O

–VS

INA105

+VS

–InPMI

MAT03+In

1/2OPA1013

1/2OPA1013

V

V

CENTER

O

I

W–V , +V = 100µA • RW

W–V W+V

V

5V

The

Window

0

1kΩ

–VS

VOCENTERV

VI

100µA

100µA

0.01µF

R(3)

(2)

(1)

0.01µF(1)

R(3)

+5V

1/2LM393

1/2LM393

NOTES: (1) Capacitors optional to reduce noise and switching time.(2) Programs center of threshold voltage. (3) Programs window voltage.

+VS

(2)

24

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System Examples (continued)

Figure 40. Window Comparator

Figure 41. Instrumentation Amplifier With Compliance to –VS

REF200

VSUPPLY GND

C

R

R

R

To RTD

To INA

25

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9 Power Supply RecommendationsThe REF200 device has completely floating current sources and current mirror. The REF200 device has a widecompliance voltage range from 2.5 V to 40 V.

10 Layout

10.1 Layout GuidelinesFigure 42 illustrates an example of a printed-circuit-board (PCB) layout for a data acquisition system using theREF2030. Some key considerations are:

• Minimize trace lengths in the current source and current mirror paths to reduce impedance.• Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup.• Place the external components as close to the device as possible. This configuration prevents parasitic errors

(such as the Seebeck effect) from occurring.• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when absolutely necessary.

10.2 Layout Example

Figure 42. Example Layout of REF200 in a RTD Measurement System

26

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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation• RTD to Voltage Reference Design Using Instrumentation Amplifier and Current Reference, TIDU969• Implementation and Applications of Current Sources and Current Receivers, SBOA046

11.2 Receiving Notification of Documentation UpdatesTo receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperright corner, click on Alert me to register and receive a weekly digest of any product information that haschanged. For change details, review the revision history included in any revised document.

11.3 Support ResourcesTI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straightfrom the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and donot necessarily reflect TI's views; see TI's Terms of Use.

11.4 TrademarksE2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

11.6 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

REF200AU ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-3-260C-168 HR -25 to 85 REF200U

REF200AU/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -25 to 85 REF200U

REF200AU/2K5E4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -25 to 85 REF200U

REF200AUE4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-3-260C-168 HR -25 to 85 REF200U

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

REF200AU/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Oct-2020

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

REF200AU/2K5 SOIC D 8 2500 853.0 449.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 16-Oct-2020

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

C

.228-.244 TYP[5.80-6.19]

.069 MAX[1.75]

6X .050[1.27]

8X .012-.020 [0.31-0.51]

2X.150[3.81]

.005-.010 TYP[0.13-0.25]

0 - 8 .004-.010[0.11-0.25]

.010[0.25]

.016-.050[0.41-1.27]

4X (0 -15 )

A

.189-.197[4.81-5.00]

NOTE 3

B .150-.157[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)[1.04]

SOIC - 1.75 mm max heightD0008ASMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash.5. Reference JEDEC registration MS-012, variation AA.

18

.010 [0.25] C A B

54

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL ATYPICAL

SCALE 2.800

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX[0.07]ALL AROUND

.0028 MIN[0.07]ALL AROUND

(.213)[5.4]

6X (.050 )[1.27]

8X (.061 )[1.55]

8X (.024)[0.6]

(R.002 ) TYP[0.05]

SOIC - 1.75 mm max heightD0008ASMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METALSOLDER MASKOPENING

NON SOLDER MASKDEFINED

SOLDER MASK DETAILS

EXPOSEDMETAL

OPENINGSOLDER MASK METAL UNDER

SOLDER MASK

SOLDER MASKDEFINED

EXPOSEDMETAL

LAND PATTERN EXAMPLEEXPOSED METAL SHOWN

SCALE:8X

SYMM

1

45

8

SEEDETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )[1.55]

8X (.024)[0.6]

6X (.050 )[1.27]

(.213)[5.4]

(R.002 ) TYP[0.05]

SOIC - 1.75 mm max heightD0008ASMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLEBASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

SYMM

1

45

8

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.

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