Reducing Synchronization Overhead in Test Data Compression Environments

Paul Theo Gonciari

Bashir Al-Hashimi

Electronic Systems Design

Group

University of

Southampton, UK

Nicola Nicolici

Electrical and Computer

Engineering

McMaster University,

Canada

Overview

• TDCE and synchronization issues – Generic on-chip decoder – Synchronization overhead in TDCE

• Previous solutions– Tailoring the compression method– Interleaving architecture

• Proposed solutions– Tailoring the compressed test set– Distribution architecture

• Experimental results

• Conclusions

Test data compression• Exponential increase in volume of test data (ITRS)

• 60% of ATE upgrade caused by memory (EETimes)

• SolutionsBuilt-in self-test (BIST)Test data reduction– Useless – UMA [Gonciari et. al, VTS02]– Useful – test data compression

• TDCE [Gonciari et. al, DATE02]

On-ChipDecoderATE

SOC CUT

uncompressedcompressed

Generic on-chip decoder

• Serial decoder– PG and CI can not work independently– Implicit communication between PG and CI

• Parallel decoder– PG and CI can work independently– Explicit communication between PG and CI

sync data

T Ddata

sour

ce

T E

chip clock

data out

scan clk

data in

code identifier

pattern generator

Synchronization overhead - Serial decoder

• De-serialization unit

• Multiple ATE channels and FIFO-like structure

• Synchronization channels necessary

CUT

ATE SOC

outbit in

de-s

er u

nit

serial dec

SOCsync

ATE

Head

FIFO

Synchronization overhead - Parallel decoder

• NO De-serialization unit

• Single ATE channel and FIFO-like structure

• Synchronization channels necessary

CUTparallel dec

FIFOATE SOC

SOC

ATE

Hea

d

sync

Previous solution – Serial decoder

• Interleaving architecture [Chandra et. al, TCAD01]– Single channel FIFO-like structure– Synchronization channels– Interleaving FSM– Changes serial-decoders to ease the control– Does not exploit frequency ratio

CUT

CUT

CUT

serial dec

serial dec

serial dec

serial dec

CUT

dem

ultip

lexe

r

FSM

FIFOATE SOC

ATE

Hea

d

syncSOC

Previous solution – Parallel decoder

• Tailoring the compression method [Jas et. al, VTS99]

– Decoder dependent on frequency ratio– Imposes ATE restrictions– Changes the on-chip decoder– NO FIFO-like structure needed– NO interleaving FSM

Proposed core level solution

• Tailoring the compressed test set– Applicable when FIFO-like structures are needed– Insert dummy bits– FIFO-like structure is eliminated– NO changes to on-chip decoders– Decoder independent of the frequency ratio

tcmp= 000 001 1stop 1stop 1 011 1 010

t’cmp= 000 001 1D 1D 1 011 1 010

Proposed system level solution

Distribution architecture

en(k

-1)

prog

reg

k:1 mux

clk

log

2k:k

deco

der

en0

data out

scan clk

Syncelem (k-1)dec (k-1)

ATE sync

data out

scan clk

Syncelem 0 0

dec clk

ATE sync

FSM clk

data in

FSM clk

log 2kbit cnt

CUT

CUTdec

SOC

Distribution architecture

• Composite test set– Tailor compressed test sets– Simple merge procedure

T C 000 1 1 1 011 1 1 1 010 1 011 1 010000 001 1

t 000 001 1D 1D 1 011 1 010

1

0

t 000 1D 1 011 1D 1 010

• NO changes to on-chip decoders

• Easy design integration for TDC system test

• Applicable to any parallel decoder

• Applicable to LFSR architectures when reseeding

• IEEE 1149.1 compatible solution for SOC TDC test

• Reduces trade-off

cmp vs. set – s38417 (

0

50000

100000

150000

200000

250000

300000

4 8 16

Group size

Clo

ck

cy

cle

s

cmp [Jas VTS99] set [core level solution]

cmp vs. set – s38417 (

0

20000

40000

60000

80000

100000

120000

140000

160000

4 8 16

Group size

Clo

ck c

ycle

s

cmp [Jas VTS99] set [core level solution]

cmp vs. set vs. distr – S1

0

50000

100000

150000

200000

250000

300000

350000

400000

450000

500000

Frequency ratio

Clo

ck c

ycl

es

cmp [Jas VTS99] set [core level solution] distr [system level solution]

inter vs. distr – S2

0

100000

200000

300000

400000

500000

600000

Frequency ratio

Clo

ck c

ycl

es

inter [Chandra TCAD01] distr [system level solution]

Conclusions

• Synchronization overhead in TDCE

• Proposed two solutions– Core level solution

• Tailor the compressed test set

– System level solution• Distribution architecture

• IEEE 1149.1 compatible solution for SOC TDC test

• Future work– Integrate TDC in system level design flow

Example – VIHC [Gonciari DATE02]

• Core level solution

= 26 bits = 16 bits t tinit cmphm = 4

t cmp

t init 1 01 0000 0000 0000 0001 0000 001

10111001000 1 1 010

tcmp= 000 001 1stop 1stop 1 011 1 010

t’cmp= 000 001 1D 1D 1 011 1 010