Reducing Interpolant Circuit Size by Ad-Hoc Logic Synthesis and … · 3 Motivations & related...
Transcript of Reducing Interpolant Circuit Size by Ad-Hoc Logic Synthesis and … · 3 Motivations & related...
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Reducing Interpolant Circuit Size by Ad-Hoc Logic Synthesis and SAT-Based Weakening
Gianpiero Cabodi
Paolo Camurati Paolo Pasini
Marco Palena Danilo Vendraminetto
Politecnico di Torino
Torino, Italy
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Outline l Motivations & background
l Craig interpolation in MC => Size bottleneck (>105 gates) l Highly redundant circuits, missing ad hoc reduction
l Contribution l Ad HOC (fast) logic synthesis (based on known
techniques) l SAT-based Weakening (and strenthening) with high
compaction potential (strength/time for size)
l Experimental results & Conclusions
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Motivations & related works l Interpolation (ITP) still a major engine in UMC
portfolio [McMillan CAV’03] l Other ITP usages
l Formula/constraint synthesis in predicate abstr. l Scalability problem
l ITPs are large and highly redundant l Previous efforts [Marques-Silva CHARME’05, D’Silva et al.
VMCAI’08, Cabodi et al. FMSD’15, Rollini et al LPAR’13 (PeRIPLO)] l Proof reduction l Interpolant compaction
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Rk,bwd
F
Background: Craig Interpolant for IMG in Unbounded MC
From T T T T
To
T
To+
Unrollk
4
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Interpolant: set view
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∧ A(x,y) B(y,z) ∩
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Interpolant: set view
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∧ A(x,y) B(y,z)
I(y)
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Craig Interpolant from refutation proof
A B
CNF clauses
UNSAT problem (A∧B = 0)
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Craig Interpolant from refutation proof
A B
Resolution graph
Null clause
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Craig Interpolant from refutation proof
A B
Resolution graph
Null clause
Unsatisfiable core
resolution (A ∨ p) (¬p ∨ B)
(A ∨ B)
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Craig Interpolant from refutation proof
A B
Resolution graph
Null clause
AND-OR circuit
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I(Y) = Interpolant (A(X,Y),B(Y,Z))
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Craig Interpolant from refutation proof
A B
Resolution graph
Null clause
AND-OR circuit
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I(Y) = Interpolant (A(X,Y),B(Y,Z))
A gate for each resolution node
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Redundancy / Compaction |Interpolant| = O(|proof|) highly redundant => compaction
l Reduce proof l Recycle-pivots, local transformations, proof restructure
l Combinational logic synthesis l BDD/SAT-sweeping l Rewriting l Refactoring
l Ad hoc logic synthesis l Logic synthesis using proof graph l ITE-based decompose & compact
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Contributions
l AD-hoc logic synthesis (rewrite/refactor) l Implemented/tuned for interpolants l Interpolant strength unchanged l Trade-off speed for optimality
l Compaction by strenghtening/weakening l Gate Level Abstraction l Proof (core) based l Expensive (SAT needed) l Trade-off strength for size 13
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Circuit graph decomposition
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y1
yN
I 1
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Circuit graph decomposition
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1
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Circuit graph decomposition
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1
Macrogates
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Circuit graph decomposition
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1
Macrogates
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Circuit graph decomposition
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1
Cluster
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Circuit graph decomposition
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1
Cut
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Circuit graph decomposition
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1
Dominators
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d dominates n
Circuit graph decomposition
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1 dn
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Rewrite: direct ODC removal
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a f
y1
yN
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Rewrite: direct ODC removal
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1
a
g
F(Y,a) = a∧g(Y,a) = a∧g(Y,1)
f
y1
yN
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Rewrite: direct ODC removal
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a f
y1
yN
1
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Algorithm
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DirectOdcSimplify()
forall clusters CL
find node v ∈ cut(CL) with fanout(v) >1 in CL
take u,t ∈ fanout(v) ∩ CL
if (domG(t) dominates u)
u <= constant // u is redundant
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Rewrite: transitive ODC
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a f
y1
yN
a
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Rewrite: transitive ODC
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1 f
y1
yN
a
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Refactor: search sharable term
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a b c d c
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Refactor: search sharable term
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a b c d c
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Refactor: search sharable term
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a c b d c
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Refactor: search sharable term
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a b d c
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Algorithm
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MacrogateRefactor()
forall macrogates G
forall nodes v ∈ cut(G)
find AND(u,v) ∉ G such that u ∈ cut(G)
refactor G using AND(u,v)
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Experimental results
l Implementation on PdTrav tool l HWMCC ’07 to ‘15
l ITPs stored on files from MC runs l Picked 87 instances l experiments also on ITPs from PeRIPLO
(Sharygina’s group, Lugano)
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• Benchmark set (87 ITPs) • Size range: 4·105 – 8,5 ·106 gates • Average size: 2 ·106 gates
• Experimental set-up • Time limit: 900 seconds • Memory limit: 8 GB
Completed Benchmarks
Average compaction rate
Average execution time
Balance 87 61.31 % 25.27 s
ITP Simplify 68 83.06 % 421.06 s
No Direct ODC 68 80.83 % 505.89 s
No Refactoring 86 69.28 % 84.80 s
No Transitive ODC 72 80.93 % 310.46 s
ABC 31 94.96 % 568.98 s
Logic synthesis
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Cumulative size
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Cumulative time
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ITP weakening by SAT GLA
l GLA: Gate Level Abstraction l used here to abstract combinational circuit
l SAT-based abstraction (PBA) l SAT(I∧B) => UNSAT CORE => abstract
l Given cut var, monotonicity => existential quantification by constant substitution
l NNF encoding l monotone w.r.t. all circuit nodes except Pis.
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Interpolant weakening
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∧ I(y) B(y,z)
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Interpolant weakening
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I(y) B(y,z)
IW(y)
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Interpolant weakening
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I(y) B(y,z) 1 ∧
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Interpolant weakening
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I(y) B(y,z) 1 ∧
UNSAT => CORE
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Interpolant weakening
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I(y) B(y,z) 1 ∧
N out of CORE
N
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Interpolant weakening
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I(y) B(y,z) 1 ∧
ABSTRACT
N
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Interpolant weakening
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I(y,N)
B(y,z) 1 ∧
EXTRA VARIABLE
N
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Existential quantification
NNF encoding NNF circuit monotone w.r.t. internal nodes Quantification by constant substitution
∃NI(Y,N) = I(Y,1) 1. I(Y) => INNF(Y) 2. SAT(INNF(Y) ∧ B(Y,Z)) 3. INNF => (uns. core, abstract, inject 1) => INNF,weak
4. INNF,weak => Iweak
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Interpolant strengthening
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∧ ¬I(y) A(x,y)
Strengthening by weakening complement of interpolant w.r.t. A
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• Benchmark set (87 circuits) • Size range: 4·105 – 8,5 ·106 gates • Average size: 2 ·106 gates
• Experimental set-up • Time limit: 3600 seconds • Memory limit: 8 GB
Completed Benchmarks
Average compaction rate
Average execution time
A 72 82.24 % 902.33 s
AB 63 97.99 % 1495.78 s
ABAB 57 99.59 % 1649.79 s
B 68 97.53 % 1324.51 s
BA 67 98.03 % 1371.30 s
BABA 60 99.56 % 1470.84 s
SAT-based weakening
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Cumulative size
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Cumulative time
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Conclusions
l Contributions: l Adapting logic synthesis for fast/scalable ITP
compaction l More expensive SAT-based compaction
(weakening/strengthening) l Evaluation
l Fast synthesis always used l Expensive weakening/strengthening
l Avoid memory explosion (or time not critical) l Strength may impact on quality of result
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Thank you!
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