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Reconfigurable CORDIC-Based Low-Power DCT Architecture

Based on Data Priority

Abstract:

This paper presents a low-power coordinate rotation digital computer (CORDIC)-based

reconfigurable discrete cosine transform (DCT) architecture. The main idea of this paper is

based on the interesting fact that all the computations in DCT are not equally important in

generating the frequency domain outputs. Considering the importance difference in the DCT

coefficients, the number of CORDIC iterations can be dynamically changed to efficiently tradeoff

image quality for power consumption. Thus, the computational energy can be significantly

reduced without seriously compromising the image quality. The proposed CORDIC-based 2-D

DCT architecture is implemented using 0.13m CMOS process, and the experimental results

show that our reconfigurable DCT achieves power savings ranging from 22.9% to 52.2% over

the CORDIC-based Loffler DCT at the cost of minor image quality degradations.

Objective:

Design energy efficient CORDIC based reconfigurable DCT without affecting the image

quality.

Existing:

Many previous research works focused on reducing the hardware complexity of DCT

such as distribute arithmetic (DA)-based DCT and multiple constant multiplications (MCM)-

based approach. Although bit-serial DA-based approach offers a regular and simple DCT

architecture, large hardware area is needed for bit-parallel operations because of additional

ROMs and control logics.

The low-power CORDIC-based DCT architecture was proposed the data correlations

between neighboring pixels are efficiently used to skip the internal CORDIC iterations.

Approximation technique or incorporating compensation steps into the quantization is

also exploited to reduce the power consumption of CORDIC-based DCT architecture.

Most of the previous research works are mainly focused on reducing the number

of arithmetic units; the inherent data priorities in DCT coefficients, however, have not

been exploited in the CORDIC-based DCT

Proposed:

In this work low-power CORDIC-based DCT architecture is proposed, where the

important differences among the DCT coefficients are efficiently exploited to achieve the power

savings minimum image quality degradation.

To apply the priority-based data processing, look ahead CORDIC architectures are

adopted to overcome the inherent data-dependencies in the conventional CORDIC architecture.

Thus, the number of CORDIC iterations is dynamically controlled considering the

importance of DCT coefficients by which considerable power savings is achieved.

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Block Diagram:

Advantages:

1. Low power

2. Low design complexity

Applications:

1. Multimedia(Image and video processing)

2. DSP

Tools Utilized:

1.

Modelsim6.3f2. Xilinxs 8.1

3. Matlab 2010a