Reconfigurable Communications Processor
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Reconfigurable Communications Processor
Principal Investigator: Chris Papachristou
Task Number: NAG3-2578
Electrical Engineering & Computer Science
Case Western Reserve University
Cleveland, Ohio 44106
September 17 – 19, 2002
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A novel reconfigurable communications processor
for high data rate agile communications
Features
- Reconfigurability & adaptability,
- Low power, system-on-chip technology,
- Real time, robust performance,
- Fault tolerance,
- Self-healing.
Platform: autonomous sensor or unit
being a typical node in space
Reconfigurable Communications Processor Project Overview
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Reconfigurable Communications Processor
Concept: The Big Picture
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Reconfigurable Communications Processor
Background
Ability of a device to change its internal structure, functionality, and behavior, either on command, or autonomously.
Reconfigurability Classes
Static Configuration: performed while device is off line.
Dynamic Configuration: device is on-line, "on the fly".
Self Reconfiguration: performed autonomously by device.
Evolution type: Self Reconfiguration with adaptation such as replication and growth, "bio-inspired". ...
Reconfigurability
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Reconfigurable Communications Processor
Enterprise Relevance
Space Science Enterprise
Self Configurable communication nodes employed in proximity wireless networking are very important in Science Enerprise.
Specific application: Software Radio-based communications.
Earth Science Enterprise
Configurable communication nodes employed in access networking can be very useful in Earth Science Enterprise. Specific application: Sensor Web networks.
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Reconfigurable Communications Processor
Impact on NASA Communications
Access Networking :
Static and Dynamic configuration useful process to quickly modify the behavior of processing node
Proximity wireless Networking :
Dynamic and Self Configuration is important for slower autonomous adaptation
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Reconfigurable Communications Processor Technology Assessment
Advantages over competing FPGA and DSP processors:
Flexibility: ability for self-reconfiguration
Granularity: ability to scale for variable bit-length operations
Cost: simpler upgrading of protocols, algorithms, code schemes
Fault Tolerance: ability for self repair and self healing from SEUs
Low Power: efficient energy consumption through configuration
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Reconfigurable Communications Processor
Enhancements to NASA Technology
Communication Requirements in Missions
• Rapid adaptation of onboard systems to changing environments
• Dynamic communications links: - self adaptable bandwidth to meet changing throughput requirements - self managing channel capacity
• Passive communication to reduce power
• Communication Protocol adaptation: - adapt to changing communication protocols for each situation
Reconfigurable Hardware: enabling technology to meet these requirements.
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Reconfigurable Communications Processor
Sensor Web: Scenario
Communication Tradeoffs
Bandwidth = Buffer / Latency
Data Rate,
Protocol,
Error Bit Rate.
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Reconfigurable Communications Processor
Approach
Architecture: reconfigurable at four Layers:
Layer 4: the Adaptation Manager.
Layer 3: the Real-Time Operating System RTOS.
Layer 2: the Embedded Processors and Memory.
Layer 1: the Reconfigurable Hardware Fabric.
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Reconfigurable Communications Processor
Architecture: Non Traditional Reconfigurable
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Reconfigurable Communications Processor
Reconfiguration : Occurs at several levels:
(a) Selection of application modules by the Adaptation Manager.
(b) Mapping of modules into the hardware fabric or the embedded processors, depending on performance requirements.
(c) Configuration of the hardware fabric and the embedded processor to meet performance and data delivery requirements.
The reconfigurable hardware is essential for mapping of wireless communications algorithms such as : IR filtering, multichannel CDMA, complex encoding, advanced imaging.
Strategy
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Reconfigurable Communications Processor
Self Adaptation - Dynamic Configuration
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Reconfigurable Communications Processor
Reconfigurable Fabric
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Reconfigurable Communications Processor
Reconfigurable Tile
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Reconfigurable Communications Processor
Architecture Mapper Software A tool inputing an algorithm flow graph and generating an architecture resource netlist
Binding Configuration SoftwareA tool inputing an architecture resource graph and generating connectivity within HW fabric
Results on several benchmarksVHDL synthesis algorithms, including scheduling, resource allocation, config. mapping.
Simulator of hardware FabricVHDL models of the HW fabric,behavioral and structural models.
Results
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Reconfigurable Communications Processor
Configuration Tools
Binding Configurator
Algorithm Data Flow
Arch Resource Netlist
Connectivity Bindings
Architecture Mapper Synthesis tools
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Reconfigurable Communications Processor
Configuration Tools (Cont.)
Synthesis: Data Flow transormation of the application into a resource graph.
Binding: allocation of resources into configurable modules, This involves functional, local memories and interconnect modules.
Configuration Core: compact description of the mapping -- in space and time
Key idea: Pre-Load the configuration matrix into Double Buffered FIFOs to employ mapping.
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Reconfigurable Communications Processor
Core Switch Matrix
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Reconfigurable Communications Processor
Double Buffer Configuration Switch Cell
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Reconfigurable Communications Processor
Results on Some Benches
Application AllocatedMemories
OperatorUnits
Size of 2 CoreMatrices
Deq 5 5 (10X10) and (5X5)
Bandpass Filter 9 9 (18X18) and (9X9)
Cosine Filter 11 11 (22X22) and (11X11)
Elliptical Filter 8 8 (16X16) and (8X8)
Arfilter 9 9 (18X18) and (9X9)
Wave Filter 6 6 (12X12) and (6X6)
DCT 12 12 (24X24) and (12X12)
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Reconfigurable Communications Processor
Collaborations
Good collaboration and synergism has been established with NASA Glenn researchers. We have also collaborative relations with industry such as CISCO, Conexant, Broadcom. These collaborations will address difficulties and optimize opportunities.
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Reconfigurable Communications Processor
Proof of Concept
For proof of concept, we will employ advanced FPGA boards from Xilinx and Altera, as well as CAD tools that we have obtained from commercial vendors.
We will develop an advanced prototyping environment based on these tools and software.
We will implement by emulation our proposed reconfigurable hardware on these boards, without actual chip design. Emulation and prototyping is quite feasible.